From 860a139ba0c8de593d293600f0f7734fe4bfa7c0 Mon Sep 17 00:00:00 2001 From: ziggurat29 Date: Sat, 26 Mar 2016 11:58:30 -0500 Subject: [PATCH 1/3] trivial; update stm32l4 readme indicating things recently completed --- arch/arm/src/stm32l4/README.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/src/stm32l4/README.txt b/arch/arm/src/stm32l4/README.txt index c0bb2bb14dc..4e3951b39bc 100644 --- a/arch/arm/src/stm32l4/README.txt +++ b/arch/arm/src/stm32l4/README.txt @@ -36,7 +36,7 @@ Timers : TODO PM : TODO, PWR registers defined FSMC : TODO AES : TODO -RNG : TODO +RNG : works CRC : TODO (configurable polynomial) WWDG : TODO IWDG : TODO @@ -55,6 +55,6 @@ OPAMP : TODO (Analog operational amplifier) COMP : TODO (Analog comparators) DFSDM : TODO (Digital Filter and Sigma-Delta Modulator) LCD : TODO (Segment LCD controller) -SAIPLL : TODO (PLL For Digital Audio interfaces) +SAIPLL : works (PLL For Digital Audio interfaces, and other things) SAI : TODO (Digital Audio interfaces, I2S, SPDIF, etc) From cc53b25dbd3b640f0f00387bdee626cfd136d0b0 Mon Sep 17 00:00:00 2001 From: ziggurat29 Date: Sun, 27 Mar 2016 10:48:02 -0500 Subject: [PATCH 2/3] fix typos in names of some LSE-related constants --- arch/arm/src/stm32l4/chip/stm32l4x6xx_rcc.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/src/stm32l4/chip/stm32l4x6xx_rcc.h b/arch/arm/src/stm32l4/chip/stm32l4x6xx_rcc.h index 117f8f30adc..134ee2844cd 100644 --- a/arch/arm/src/stm32l4/chip/stm32l4x6xx_rcc.h +++ b/arch/arm/src/stm32l4/chip/stm32l4x6xx_rcc.h @@ -714,11 +714,11 @@ #define RCC_BDCR_LSEBYP (1 << 2) /* Bit 2: External Low Speed oscillator Bypass */ #define RCC_BDCR_LSEDRV_SHIFT (3) /* Bits 3-4: LSE oscillator drive capability */ -#define RCC_BDCR_LSEDRV_MASK (3 << DCC_BDCR_LSEDRV_SHIFT) -# define RCC_BDCR_LSEDRV_LOWER (0 << DCC_BDCR_LSEDRV_SHIFT) /* 00: Lower driving capability */ -# define RCC_BDCR_LSEDRV_MIDLOW (1 << DCC_BDCR_LSEDRV_SHIFT) /* 01: Medium Low driving capability */ -# define RCC_BDCR_LSEDRV_MIDHI (2 << DCC_BDCR_LSEDRV_SHIFT) /* 10: Medium High driving capability*/ -# define RCC_BDCR_LSEDRV_HIGER (3 << DCC_BDCR_LSEDRV_SHIFT) /* 11: Higher driving capability */ +#define RCC_BDCR_LSEDRV_MASK (3 << RCC_BDCR_LSEDRV_SHIFT) +# define RCC_BDCR_LSEDRV_LOWER (0 << RCC_BDCR_LSEDRV_SHIFT) /* 00: Lower driving capability */ +# define RCC_BDCR_LSEDRV_MIDLOW (1 << RCC_BDCR_LSEDRV_SHIFT) /* 01: Medium Low driving capability */ +# define RCC_BDCR_LSEDRV_MIDHI (2 << RCC_BDCR_LSEDRV_SHIFT) /* 10: Medium High driving capability*/ +# define RCC_BDCR_LSEDRV_HIGER (3 << RCC_BDCR_LSEDRV_SHIFT) /* 11: Higher driving capability */ #define RCC_BDCR_LSECSSON (1 << 5) /* Bit 5: CSS on LSE enable */ #define RCC_BDCR_LSECSSD (1 << 6) /* Bit 6: CSS on LSE failure Detection */ From 5bd7b7b54c52dba3f1e3c77966fdd9a19ad60eed Mon Sep 17 00:00:00 2001 From: ziggurat29 Date: Sun, 27 Mar 2016 12:07:47 -0500 Subject: [PATCH 3/3] add support for LSE oscillator configuration; requires also initial support of PWR control block --- arch/arm/src/stm32l4/Make.defs | 2 +- arch/arm/src/stm32l4/stm32l4_lse.c | 108 +++++++++++++++ arch/arm/src/stm32l4/stm32l4_pwr.c | 174 +++++++++++++++++++++++++ arch/arm/src/stm32l4/stm32l4_pwr.h | 111 ++++++++++++++++ arch/arm/src/stm32l4/stm32l4x6xx_rcc.c | 26 +++- 5 files changed, 416 insertions(+), 5 deletions(-) create mode 100644 arch/arm/src/stm32l4/stm32l4_lse.c create mode 100644 arch/arm/src/stm32l4/stm32l4_pwr.c diff --git a/arch/arm/src/stm32l4/Make.defs b/arch/arm/src/stm32l4/Make.defs index 3990bab7011..9319db11faf 100644 --- a/arch/arm/src/stm32l4/Make.defs +++ b/arch/arm/src/stm32l4/Make.defs @@ -115,7 +115,7 @@ CHIP_ASRCS = CHIP_CSRCS = stm32l4_allocateheap.c stm32l4_exti_gpio.c stm32l4_gpio.c CHIP_CSRCS += stm32l4_idle.c stm32l4_irq.c stm32l4_lowputc.c stm32l4_rcc.c CHIP_CSRCS += stm32l4_serial.c stm32l4_start.c stm32l4_waste.c -CHIP_CSRCS += stm32l4_spi.c stm32l4_i2c.c +CHIP_CSRCS += stm32l4_spi.c stm32l4_i2c.c stm32l4_lse.c stm32l4_pwr.c ifneq ($(CONFIG_SCHED_TICKLESS),y) CHIP_CSRCS += stm32l4_timerisr.c diff --git a/arch/arm/src/stm32l4/stm32l4_lse.c b/arch/arm/src/stm32l4/stm32l4_lse.c new file mode 100644 index 00000000000..3cd028b2836 --- /dev/null +++ b/arch/arm/src/stm32l4/stm32l4_lse.c @@ -0,0 +1,108 @@ +/**************************************************************************** + * arch/arm/src/stm32l4/stm32l4_lse.c + * + * Copyright (C) 2009, 2011, 2015 Gregory Nutt. All rights reserved. + * Author: dev@ziggurat29.com + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "up_arch.h" + +#include "stm32l4_pwr.h" +#include "stm32l4_rcc.h" +#include "stm32l4_waste.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32l4_rcc_enablelse + * + * Description: + * Enable the External Low-Speed (LSE) oscillator. + * + * Todo: + * Check for LSE good timeout and return with -1, + * + ****************************************************************************/ + +void stm32l4_rcc_enablelse(void) +{ + bool bkpenabled; + uint32_t regval; + + /* The LSE is in the RTC domain and write access is denied to this domain + * after reset, you have to enable write access using DBP bit in the PWR CR + * register before to configuring the LSE. + */ + + bkpenabled = stm32l4_pwr_enablebkp(true); + + /* Enable the External Low-Speed (LSE) oscillator by setting the LSEON bit + * the RCC BDCR register. + */ + + regval = getreg32(STM32L4_RCC_BDCR); + regval |= RCC_BDCR_LSEON|RCC_BDCR_LSEDRV_MIDHI; + putreg32(regval,STM32L4_RCC_BDCR); + + /* Wait for the LSE clock to be ready */ + + while (((regval = getreg32(STM32L4_RCC_BDCR)) & RCC_BDCR_LSERDY) == 0) + { + up_waste(); + } + + /* Disable backup domain access if it was disabled on entry */ + + if (!bkpenabled) + { + (void)stm32l4_pwr_enablebkp(false); + } +} diff --git a/arch/arm/src/stm32l4/stm32l4_pwr.c b/arch/arm/src/stm32l4/stm32l4_pwr.c new file mode 100644 index 00000000000..d17c9d6fba8 --- /dev/null +++ b/arch/arm/src/stm32l4/stm32l4_pwr.c @@ -0,0 +1,174 @@ +/************************************************************************************ + * arch/arm/src/stm32l4/stm32l4_pwr.c + * + * Copyright (C) 2011 Uros Platise. All rights reserved. + * Copyright (C) 2013, 2015 Gregory Nutt. All rights reserved. + * Authors: Uros Platise + * Gregory Nutt + * dev@ziggurat29.com + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include + +#include +#include +#include + +#include "up_arch.h" +#include "stm32l4_pwr.h" +#include "stm32l4_rcc.h" + + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +static inline uint16_t stm32l4_pwr_getreg(uint8_t offset) +{ + return (uint16_t)getreg32(STM32L4_PWR_BASE + (uint32_t)offset); +} + +static inline void stm32l4_pwr_putreg(uint8_t offset, uint16_t value) +{ + putreg32((uint32_t)value, STM32L4_PWR_BASE + (uint32_t)offset); +} + +static inline void stm32l4_pwr_modifyreg(uint8_t offset, uint16_t clearbits, uint16_t setbits) +{ + modifyreg32(STM32L4_PWR_BASE + (uint32_t)offset, (uint32_t)clearbits, (uint32_t)setbits); +} + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: enableclk + * + * Description: + * Enable/disable the clock to the power control peripheral. Enabling must be done + * after the APB1 clock is validly configured, and prior to using any functionality + * controlled by the PWR block (i.e. much of anything else provided by this module). + * + * Input Parameters: + * enable - True: enable the clock to the Power control (PWR) block. + * + * Returned Value: + * True: the PWR block was previously enabled. + * + ************************************************************************************/ + +bool stm32l4_pwr_enableclk(bool enable) +{ + uint32_t regval; + bool wasenabled; + + regval = getreg32(STM32L4_RCC_APB1ENR1); + wasenabled = ((regval & RCC_APB1ENR1_PWREN) != 0); + + /* Power interface clock enable. + */ + + if (wasenabled && !enable) + { + /* Disable power interface clock */ + + regval &= ~RCC_APB1ENR1_PWREN; + putreg32(STM32L4_RCC_APB1ENR1, regval); + } + else if (!wasenabled && enable) + { + /* Enable power interface clock */ + + regval |= RCC_APB1ENR1_PWREN; + putreg32(STM32L4_RCC_APB1ENR1, regval); + } + + return wasenabled; +} + +/************************************************************************************ + * Name: stm32l4_pwr_enablebkp + * + * Description: + * Enables access to the backup domain (RTC registers, RTC backup data registers + * and backup SRAM). + * + * Input Parameters: + * writable - True: enable ability to write to backup domain registers + * + * Returned Value: + * True: The backup domain was previously writable. + * + ************************************************************************************/ + +bool stm32l4_pwr_enablebkp(bool writable) +{ + uint16_t regval; + bool waswritable; + + /* Get the current state of the STM32 PWR control register */ + + regval = stm32l4_pwr_getreg(STM32L4_PWR_CR1_OFFSET); + waswritable = ((regval & PWR_CR1_DBP) != 0); + + /* Enable or disable the ability to write */ + + if (waswritable && !writable) + { + /* Disable backup domain access */ + + regval &= ~PWR_CR1_DBP; + stm32l4_pwr_putreg(STM32L4_PWR_CR1_OFFSET, regval); + } + else if (!waswritable && writable) + { + /* Enable backup domain access */ + + regval |= PWR_CR1_DBP; + stm32l4_pwr_putreg(STM32L4_PWR_CR1_OFFSET, regval); + + /* Enable does not happen right away */ + + up_udelay(4); + } + + return waswritable; +} diff --git a/arch/arm/src/stm32l4/stm32l4_pwr.h b/arch/arm/src/stm32l4/stm32l4_pwr.h index e69de29bb2d..b22eebb06c0 100644 --- a/arch/arm/src/stm32l4/stm32l4_pwr.h +++ b/arch/arm/src/stm32l4/stm32l4_pwr.h @@ -0,0 +1,111 @@ +/************************************************************************************ + * arch/arm/src/stm32l4/stm32l4_pwr.h + * + * Copyright (C) 2009, 2013, 2015 Gregory Nutt. All rights reserved. + * Author: dev@ziggurat29.com + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_PWR_H +#define __ARCH_ARM_SRC_STM32L4_STM32L4_PWR_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include + +#include "chip.h" +#include "chip/stm32l4_pwr.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: enableclk + * + * Description: + * Enable/disable the clock to the power control peripheral. Enabling must be done + * after the APB1 clock is validly configured, and prior to using any functionality + * controlled by the PWR block (i.e. much of anything else provided by this module). + * + * Input Parameters: + * enable - True: enable the clock to the Power control (PWR) block. + * + * Returned Value: + * True: the PWR block was previously enabled. + * + ************************************************************************************/ + +bool stm32l4_pwr_enableclk(bool enable); + + +/************************************************************************************ + * Name: stm32l4_pwr_enablebkp + * + * Description: + * Enables access to the backup domain (RTC registers, RTC backup data registers + * and backup SRAM). + * + * Input Parameters: + * writable - True: enable ability to write to backup domain registers + * + * Returned Value: + * True: The backup domain was previously writable. + * + ************************************************************************************/ + +bool stm32l4_pwr_enablebkp(bool writable); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_PWR_H */ diff --git a/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c b/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c index 4e5dbf367e1..e3901207272 100644 --- a/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c @@ -621,14 +621,17 @@ static void stm32l4_stdclockconfig(void) { #warning todo: regulator voltage according to clock freq #if 0 - /* Select regulator voltage output Scale 1 mode to support system - * frequencies up to 168 MHz. + /* ensure Power control is enabled before modifying it */ - + regval = getreg32(STM32L4_RCC_APB1ENR); regval |= RCC_APB1ENR_PWREN; putreg32(regval, STM32L4_RCC_APB1ENR); + /* Select regulator voltage output Scale 1 mode to support system + * frequencies up to 168 MHz. + */ + regval = getreg32(STM32L4_PWR_CR); regval &= ~PWR_CR_VOS_MASK; regval |= PWR_CR_VOS_SCALE_1; @@ -808,11 +811,26 @@ static void stm32l4_stdclockconfig(void) stm32l4_rcc_enablelsi(); #endif -#if defined(CONFIG_RTC_LSECLOCK) +#if defined(STM32L4_USE_LSE) /* Low speed external clock source LSE * * TODO: There is another case where the LSE needs to * be enabled: if the MCO1 pin selects LSE as source. + * XXX and other cases, like automatic trimming of MSI for USB use + */ + + /* ensure Power control is enabled since it is indirectly required + * to alter the LSE parameters. + */ + stm32l4_pwr_enableclk(true); + + /* XXX other LSE settings must be made before turning on the oscillator + * and we need to ensure it is first off before doing so. + */ + + /* turn on the LSE oscillator + * XXX this will almost surely get moved since we also want to use + * this for automatically trimming MSI, etc. */ stm32l4_rcc_enablelse();