From 2a434fe1fafcd9c5e3394728992c2698824242ed Mon Sep 17 00:00:00 2001 From: Masayuki Ishikawa Date: Mon, 28 Feb 2022 13:58:16 +0900 Subject: [PATCH] arch: imx6: Add the pgheap for imx6 Summary: - This commit adds the pgheap for imx6 Impact: - None Testing: - Tested with sabre-6quad:netknsh (not merged yet) Signed-off-by: Masayuki Ishikawa --- arch/arm/src/imx6/Kconfig | 26 ++++++++ arch/arm/src/imx6/Make.defs | 4 ++ arch/arm/src/imx6/imx_pgalloc.c | 104 ++++++++++++++++++++++++++++++++ 3 files changed, 134 insertions(+) create mode 100644 arch/arm/src/imx6/imx_pgalloc.c diff --git a/arch/arm/src/imx6/Kconfig b/arch/arm/src/imx6/Kconfig index 91c78e77d77..5dd9163f9eb 100644 --- a/arch/arm/src/imx6/Kconfig +++ b/arch/arm/src/imx6/Kconfig @@ -197,4 +197,30 @@ config IMX6_BOOT_SRAM endchoice # i.MX6 Boot Configuration +config IMX6_DDRCS_PGHEAP + bool "Include DDR-SDRAM in page cache" + default y + depends on IMX6_BOOT_SDRAM && ARCH_ADDRENV + ---help--- + Include a portion of DDR-SDRAM memory in the page cache. + +if IMX6_DDRCS_PGHEAP + +config IMX6_DDRCS_PGHEAP_OFFSET + hex "DDR-SDRAM heap offset" + default 0x0 + ---help--- + Preserve this number of bytes at the beginning of SDRAM. The + portion of DRAM beginning at this offset from the DDRCS base will + be added to the heap. + +config IMX6_DDRCS_PGHEAP_SIZE + int "DDR-SDRAM heap size" + default 0 + ---help--- + Add the region of DDR-SDRAM beginning at IMX6_DDRCS_PGHEAP_OFFSET + and of size IMX6_DDRCS_PGHEAP_SIZE to the heap. + +endif # IMX6_DDRCS_PGHEAP + endif # ARCH_CHIP_IMX6 diff --git a/arch/arm/src/imx6/Make.defs b/arch/arm/src/imx6/Make.defs index 851c0c7b138..60c0e40106e 100644 --- a/arch/arm/src/imx6/Make.defs +++ b/arch/arm/src/imx6/Make.defs @@ -149,3 +149,7 @@ endif ifeq ($(CONFIG_IMX6_ENET),y) CHIP_CSRCS += imx_enet.c endif + +ifeq ($(CONFIG_MM_PGALLOC),y) +CHIP_CSRCS += imx_pgalloc.c +endif diff --git a/arch/arm/src/imx6/imx_pgalloc.c b/arch/arm/src/imx6/imx_pgalloc.c new file mode 100644 index 00000000000..393661989dd --- /dev/null +++ b/arch/arm/src/imx6/imx_pgalloc.c @@ -0,0 +1,104 @@ +/**************************************************************************** + * arch/arm/src/imx6/imx_pgalloc.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "mmu.h" + +#ifdef CONFIG_MM_PGALLOC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Currently, page cache memory must be allocated in DRAM. There are other + * possibilities, but the logic in this file will have to extended in order + * handle any other possibility. + */ + +#ifndef CONFIG_ARCH_PGPOOL_MAPPING +# error CONFIG_ARCH_PGPOOL_MAPPING must be selected +#endif + +#ifndef CONFIG_IMX6_DDRCS_PGHEAP +# error CONFIG_IMX6_DDRCS_PGHEAP must be selected +#endif + +#ifndef CONFIG_IMX6_DDRCS_PGHEAP_OFFSET +# error CONFIG_IMX6_DDRCS_PGHEAP_OFFSET must be specified +#endif + +#if (CONFIG_IMX6_DDRCS_PGHEAP_OFFSET & MM_PGMASK) != 0 +# warning CONFIG_IMX6_DDRCS_PGHEAP_OFFSET is not aligned to a page boundary +#endif + +#ifndef CONFIG_IMX6_DDRCS_PGHEAP_SIZE +# error CONFIG_IMX6_DDRCS_PGHEAP_SIZE must be specified +#endif + +#if (CONFIG_IMX6_DDRCS_PGHEAP_SIZE & MM_PGMASK) != 0 +# warning CONFIG_IMX6_DDRCS_PGHEAP_SIZE is not aligned to a page boundary +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_allocate_pgheap + * + * Description: + * If there is a page allocator in the configuration, then this function + * must be provided by the platform-specific code. The OS initialization + * logic will call this function early in the initialization sequence to + * get the page heap information needed to configure the page allocator. + * + * Input parameters: + * heap_start - A double pointer to the start address of the pgheap + * heap_size - A pointer to the size of the pgheap + * + * Returned Value: + * None + * + ****************************************************************************/ + +void up_allocate_pgheap(FAR void **heap_start, size_t *heap_size) +{ + DEBUGASSERT(heap_start && heap_size); + + *heap_start = (FAR void *)((uintptr_t)IMX_MMDCDDR_PSECTION + + CONFIG_IMX6_DDRCS_PGHEAP_OFFSET); + *heap_size = CONFIG_IMX6_DDRCS_PGHEAP_SIZE; +} + +#endif /* CONFIG_MM_PGALLOC */