Mirrors_Framework/nuttx
1
0
Fork 0
mirror of https://github.com/apache/nuttx.git synced 2026-05-29 04:19:37 +08:00
Code Issues Actions 1 Packages Projects Releases Wiki Activity

Kinetis:Add OSC_DIV to the kinetis_osc header

Browse Source
This commit is contained in:
David Sidrane
2017-05-05 07:16:11 -06:00
committed by Gregory Nutt
parent f73e2aab8d
commit 29ef635e89
1 changed files with 12 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/src/kinetis/chip/kinetis_osc.h
+12 -1
View File
@@ -1,7 +1,7 @@
/******************************************************************************************** /********************************************************************************************
* arch/arm/src/kinetis/chip/kinetis_osc.h * arch/arm/src/kinetis/chip/kinetis_osc.h
* *
* Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. * Copyright (C) 2011, 2016-2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org> * Author: Gregory Nutt <gnutt@nuttx.org>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
@@ -51,10 +51,12 @@
/* Register Offsets *************************************************************************/ /* Register Offsets *************************************************************************/
#define KINETIS_OSC_CR_OFFSET 0x0000 /* OSC Control Register */ #define KINETIS_OSC_CR_OFFSET 0x0000 /* OSC Control Register */
#define KINETIS_OSC_DIV_OFFSET 0x0002 /* OSC CLock divider register */
/* Register Addresses ***********************************************************************/ /* Register Addresses ***********************************************************************/
#define KINETIS_OSC_CR (KINETIS_OSC_BASE+KINETIS_OSC_CR_OFFSET) #define KINETIS_OSC_CR (KINETIS_OSC_BASE+KINETIS_OSC_CR_OFFSET)
#define KINETIS_OSC_DIV (KINETIS_OSC_BASE+KINETIS_OSC_DIV_OFFSET)
/* Register Bit Definitions *****************************************************************/ /* Register Bit Definitions *****************************************************************/
@@ -69,6 +71,15 @@
#define OSC_CR_SC8P (1 << 1) /* Bit 1: Oscillator 8 pF Capacitor Load Configure */ #define OSC_CR_SC8P (1 << 1) /* Bit 1: Oscillator 8 pF Capacitor Load Configure */
#define OSC_CR_SC16P (1 << 0) /* Bit 0: Oscillator 16 pF Capacitor Load Configure */ #define OSC_CR_SC16P (1 << 0) /* Bit 0: Oscillator 16 pF Capacitor Load Configure */
/* OSC Control Register (8-bit) */
/* Bits 0-5: Reserved */
#define OSC_DIV_ERPS_SHIFT 6 /* Bits 6-7: ERCLK prescaler */
#define OSC_DIV_ERPS_MASK (3 << OSC_DIV_ERPS_SHIFT)
# define OSC_DIV_ERPS_DIV1 (0 << OSC_DIV_ERPS_SHIFT) /* The divisor ratio is 1 */
# define OSC_DIV_ERPS_DIV2 (1 << OSC_DIV_ERPS_SHIFT) /* The divisor ratio is 2 */
# define OSC_DIV_ERPS_DIV3 (2 << OSC_DIV_ERPS_SHIFT) /* The divisor ratio is 4 */
# define OSC_DIV_ERPS_DIV8 (3 << OSC_DIV_ERPS_SHIFT) /* The divisor ratio is 8 */
/******************************************************************************************** /********************************************************************************************
* Public Types * Public Types
********************************************************************************************/ ********************************************************************************************/