Merge remote-tracking branch 'origin/master' into esp32

arch/Kconfig

@@ -52,6 +52,13 @@ config ARCH_RENESAS
 	---help---
 		Renesas architectures (SH and M16C).
 
+config ARCH_RISCV
+	bool "RISC-V"
+	select ARCH_HAVE_INTERRUPTSTACK
+	select ARCH_HAVE_CUSTOMOPT
+	---help---
+		RISC-V 32 and 64-bit RV32 / RV64 architectures.
+
 config ARCH_SIM
 	bool "Simulation"
 	select ARCH_HAVE_MULTICPU
@@ -94,6 +101,7 @@ config ARCH
 	default "mips"    if ARCH_MIPS
 	default "rgmp"    if ARCH_RGMP
 	default "renesas" if ARCH_RENESAS
+	default "risc-v"  if ARCH_RISCV
 	default "sim"     if ARCH_SIM
 	default "x86"     if ARCH_X86
 	default "xtensa"  if ARCH_XTENSA
@@ -106,6 +114,7 @@ source arch/hc/Kconfig
 source arch/mips/Kconfig
 source arch/rgmp/Kconfig
 source arch/renesas/Kconfig
+source arch/risc-v/Kconfig
 source arch/sim/Kconfig
 source arch/x86/Kconfig
 source arch/xtensa/Kconfig
@@ -547,6 +556,7 @@ config ARCH_USBDUMP
 config ENDIAN_BIG
 	bool "Big Endian Architecture"
 	default n
+	depends on !ARCH_RISCV
 	---help---
 		Select if architecture operates using big-endian byte ordering.
 

arch/README.txt

@@ -233,6 +233,15 @@ arch/rgmp
     See http://rgmp.sourceforge.net/wiki/index.php/Main_Page for further
     information about RGMP.
 
+arch/risc-v
+    This directory is dedicated to ports to the RISC-V family.
+
+    Architecture Support
+      arch/risc-v/include/rv32im
+
+    MCU support
+      arch/risc-v/include/nr5m100
+
 arch/x86 - Intel x86 architectures
     This directory holds related, 32- and 64-bit architectures from Intel.
     At present, this includes the following subdirectories:

arch/arm/src/kinetis/Make.defs

@@ -90,7 +90,7 @@ CHIP_ASRCS  =
 CHIP_CSRCS  = kinetis_allocateheap.c kinetis_clockconfig.c
 CHIP_CSRCS += kinetis_clrpend.c kinetis_idle.c kinetis_irq.c
 CHIP_CSRCS += kinetis_lowputc.c kinetis_pin.c kinetis_pingpio.c
-CHIP_CSRCS += kinetis_serial.c kinetis_start.c kinetis_wdog.c
+CHIP_CSRCS += kinetis_serial.c kinetis_start.c kinetis_uid.c kinetis_wdog.c
 CHIP_CSRCS += kinetis_cfmconfig.c
 
 # Configuration-dependent Kinetis files

arch/arm/src/kinetis/kinetis_uid.c

@@ -0,0 +1,70 @@
+/****************************************************************************
+ * arch/arm/src/kinetis/kinetis_uid.c
+ *
+ *   Copyright (C) 2016 Neil Hancock. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <chip/kinetis_k64memorymap.h>
+#include <chip/kinetis_sim.h>
+#include "kinetis_uid.h"
+
+#ifdef CONFIG_BOARDCTL_UNIQUEID
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: kinetis_get_uniqueid
+ ****************************************************************************/
+
+void kinetis_get_uniqueid(uint8_t *uniqueid)
+{
+  uint32_t *unique_u32;
+  int i;
+
+  unique_u32 = (uint32_t *)uniqueid;
+
+  /* Copy into buffer LS first, which in the Kinetis is the highest memory */
+
+  for (i = 0; i < (KINETIS_UID_SIZE / sizeof(uint32_t)); i++)
+    {
+      unique_u32[i] = *((uint32_t*)(KINETIS_SIM_UIDL) - i);
+    }
+}
+
+#endif /* CONFIG_BOARDCTL_UNIQUEID */

arch/arm/src/kinetis/kinetis_uid.h

@@ -0,0 +1,56 @@
+/****************************************************************************
+ * arch/arm/src/kinetis/kinetis_uid.h
+ *
+ *   Copyright (C) 2016 Neil Hancock. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_KINETIS_UID_H
+#define __ARCH_ARM_SRC_KINETIS_UID_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <stdint.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define KINETIS_UID_SIZE 16
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+void kinetis_get_uniqueid(uint8_t *uniqueid);
+
+#endif /* __ARCH_ARM_SRC_KINETIS_UID_H */

arch/arm/src/stm32/stm32_serial.c

@@ -1189,18 +1189,27 @@ static int up_dma_nextrx(struct up_dev_s *priv)
 static void up_set_format(struct uart_dev_s *dev)
 {
   struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)
+  uint32_t usartdiv8;
+#else
+  uint32_t usartdiv32;
+  uint32_t mantissa;
+  uint32_t fraction;
+#endif
   uint32_t regval;
+  uint32_t brr;
+
+  /* Load CR1 */
+
+  regval = up_serialin(priv, STM32_USART_CR1_OFFSET);
 
 #if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)
   /* This first implementation is for U[S]ARTs that support oversampling
    * by 8 in additional to the standard oversampling by 16.
-   */
+   * With baud rate of fCK / Divider for oversampling by 16.
-
+   * and baud rate of  2 * fCK / Divider for oversampling by 8
-  uint32_t usartdiv8;
+   *
-  uint32_t cr1;
+   * In case of oversampling by 8, the equation is:
-  uint32_t brr;
-
-  /* In case of oversampling by 8, the equation is:
    *
    *   baud      = 2 * fCK / usartdiv8
    *   usartdiv8 = 2 * fCK / baud
@@ -1214,11 +1223,10 @@ static void up_set_format(struct uart_dev_s *dev)
    *   baud       = fCK / usartdiv16
    *   usartdiv16 = fCK / baud
    *              = 2 * usartdiv8
+   *
+   * Use oversamply by 8 only if the divisor is small.  But what is small?
    */
 
-  /* Use oversamply by 8 only if the divisor is small.  But what is small? */
-
-  cr1 = up_serialin(priv, STM32_USART_CR1_OFFSET);
   if (usartdiv8 > 100)
     {
       /* Use usartdiv16 */
@@ -1227,7 +1235,7 @@ static void up_set_format(struct uart_dev_s *dev)
 
       /* Clear oversampling by 8 to enable oversampling by 16 */
 
-      cr1 &= ~USART_CR1_OVER8;
+      regval &= ~USART_CR1_OVER8;
     }
   else
     {
@@ -1239,24 +1247,14 @@ static void up_set_format(struct uart_dev_s *dev)
 
       /* Set oversampling by 8 */
 
-      cr1 |= USART_CR1_OVER8;
+      regval |= USART_CR1_OVER8;
     }
 
-   up_serialout(priv, STM32_USART_CR1_OFFSET, cr1);
-   up_serialout(priv, STM32_USART_BRR_OFFSET, brr);
-
 #else
-
   /* This second implementation is for U[S]ARTs that support fractional
    * dividers.
-   */
+   *
-
+   * Configure the USART Baud Rate.  The baud rate for the receiver and
-  uint32_t usartdiv32;
-  uint32_t mantissa;
-  uint32_t fraction;
-  uint32_t brr;
-
-  /* Configure the USART Baud Rate.  The baud rate for the receiver and
    * transmitter (Rx and Tx) are both set to the same value as programmed
    * in the Mantissa and Fraction values of USARTDIV.
    *
@@ -1277,18 +1275,50 @@ static void up_set_format(struct uart_dev_s *dev)
   /* The mantissa part is then */
 
   mantissa   = usartdiv32 >> 5;
-  brr        = mantissa << USART_BRR_MANT_SHIFT;
 
   /* The fractional remainder (with rounding) */
 
   fraction   = (usartdiv32 - (mantissa << 5) + 1) >> 1;
-  brr       |= fraction << USART_BRR_FRAC_SHIFT;
+
-  up_serialout(priv, STM32_USART_BRR_OFFSET, brr);
+#if defined(CONFIG_STM32_STM32F40XX)
+  /* The F4 supports 8 X in oversampling additional to the
+   * standard oversampling by 16.
+   *
+   * With baud rate of fCK / (16 * Divider) for oversampling by 16.
+   * and baud rate of  fCK /  (8 * Divider) for oversampling by 8
+   */
+
+  /* Check if 8x oversampling is necessary */
+
+  if (mantissa == 0)
+    {
+      regval |= USART_CR1_OVER8;
+
+      /* Rescale the mantissa */
+
+      mantissa = usartdiv32 >> 4;
+
+      /* The fractional remainder (with rounding) */
+
+      fraction = (usartdiv32 - (mantissa << 4) + 1) >> 1;
+    }
+  else
+    {
+      /* Use 16x Oversampling */
+
+      regval &= ~USART_CR1_OVER8;
+    }
 #endif
 
+  brr  = mantissa << USART_BRR_MANT_SHIFT;
+  brr |= fraction << USART_BRR_FRAC_SHIFT;
+#endif
+
+  up_serialout(priv, STM32_USART_CR1_OFFSET, regval);
+  up_serialout(priv, STM32_USART_BRR_OFFSET, brr);
+
   /* Configure parity mode */
 
-  regval  = up_serialin(priv, STM32_USART_CR1_OFFSET);
   regval &= ~(USART_CR1_PCE | USART_CR1_PS | USART_CR1_M);
 
   if (priv->parity == 1)       /* Odd parity */
@@ -1334,7 +1364,8 @@ static void up_set_format(struct uart_dev_s *dev)
   regval  = up_serialin(priv, STM32_USART_CR3_OFFSET);
   regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE);
 
-#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32_FLOWCONTROL_BROKEN)
+#if defined(CONFIG_SERIAL_IFLOWCONTROL) && \
+   !defined(CONFIG_STM32_FLOWCONTROL_BROKEN)
   if (priv->iflow && (priv->rts_gpio != 0))
     {
       regval |= USART_CR3_RTSE;

arch/arm/src/stm32l4/Kconfig

@@ -731,6 +731,13 @@ config STM32L4_TIM1_CH1OUT
 	---help---
 		Enables channel 1 output.
 
+config STM32L4_TIM1_CH1NOUT
+	bool "TIM1 Channel 1 Complementary Output"
+	default n
+	depends on STM32L4_TIM1_CH1OUT
+	---help---
+		Enables channel 1 complementary output.
+
 endif # STM32L4_TIM1_CHANNEL1
 
 config STM32L4_TIM1_CHANNEL2
@@ -754,6 +761,13 @@ config STM32L4_TIM1_CH2OUT
 	---help---
 		Enables channel 2 output.
 
+config STM32L4_TIM1_CH2NOUT
+	bool "TIM1 Channel 2 Complemenrary Output"
+	default n
+	depends on STM32L4_TIM1_CH2OUT
+	---help---
+		Enables channel 2 complementary output.
+
 endif # STM32L4_TIM1_CHANNEL2
 
 config STM32L4_TIM1_CHANNEL3
@@ -777,6 +791,13 @@ config STM32L4_TIM1_CH3OUT
 	---help---
 		Enables channel 3 output.
 
+config STM32L4_TIM1_CH3NOUT
+	bool "TIM1 Channel 3 Complementary Output"
+	default n
+	depends on STM32L4_TIM1_CH3OUT
+	---help---
+		Enables channel 3 complementary output.
+
 endif # STM32L4_TIM1_CHANNEL3
 
 config STM32L4_TIM1_CHANNEL4
@@ -1426,6 +1447,13 @@ config STM32L4_TIM8_CH1OUT
 	---help---
 		Enables channel 1 output.
 
+config STM32L4_TIM8_CH1NOUT
+	bool "TIM8 Channel 1 Complementary Output"
+	default n
+	depends on STM32L4_TIM8_CH1OUT
+	---help---
+		Enables channel 1 complementary output.
+
 endif # STM32L4_TIM8_CHANNEL1
 
 config STM32L4_TIM8_CHANNEL2
@@ -1449,6 +1477,13 @@ config STM32L4_TIM8_CH2OUT
 	---help---
 		Enables channel 2 output.
 
+config STM32L4_TIM8_CH2NOUT
+	bool "TIM8 Channel 2 Complementary Output"
+	default n
+	depends on STM32L4_TIM8_CH2OUT
+	---help---
+		Enables channel 2 complementary output.
+
 endif # STM32L4_TIM8_CHANNEL2
 
 config STM32L4_TIM8_CHANNEL3
@@ -1472,6 +1507,13 @@ config STM32L4_TIM8_CH3OUT
 	---help---
 		Enables channel 3 output.
 
+config STM32L4_TIM8_CH3NOUT
+	bool "TIM8 Channel 3 Complementary Output"
+	default n
+	depends on STM32L4_TIM8_CH3OUT
+	---help---
+		Enables channel 3 complementary output.
+
 endif # STM32L4_TIM8_CHANNEL3
 
 config STM32L4_TIM8_CHANNEL4
@@ -1557,6 +1599,13 @@ config STM32L4_TIM15_CH1OUT
 	---help---
 		Enables channel 1 output.
 
+config STM32L4_TIM15_CH1NOUT
+	bool "TIM15 Channel 1 Complementary Output"
+	default n
+	depends on STM32L4_TIM15_CH1OUT
+	---help---
+		Enables channel 1 complementary output.
+
 endif # STM32L4_TIM15_CHANNEL1
 
 config STM32L4_TIM15_CHANNEL2
@@ -1642,6 +1691,13 @@ config STM32L4_TIM16_CH1OUT
 	---help---
 		Enables channel 1 output.
 
+config STM32L4_TIM16_CH1NOUT
+	bool "TIM16 Channel 1 Complementary Output"
+	default n
+	depends on STM32L4_TIM16_CH1OUT
+	---help---
+		Enables channel 1 complementary output.
+
 endif # STM32L4_TIM16_CHANNEL1
 
 endif # STM32L4_PWM_MULTICHAN
@@ -1704,6 +1760,13 @@ config STM32L4_TIM17_CH1OUT
 	---help---
 		Enables channel 1 output.
 
+config STM32L4_TIM17_CH1NOUT
+	bool "TIM17 Channel 1 Complementary Output"
+	default n
+	depends on STM32L4_TIM17_CH1OUT
+	---help---
+		Enables channel 1 complementary output.
+
 endif # STM32L4_TIM17_CHANNEL1
 
 endif # STM32L4_PWM_MULTICHAN

arch/arm/src/stm32l4/stm32l4_pwm.c

@@ -128,6 +128,7 @@ struct stm32l4_pwmchan_s
   uint8_t channel;                     /* Timer output channel: {1,..4} */
   uint32_t pincfg;                     /* Output pin configuration */
   enum stm32l4_chanmode_e mode;
+  uint32_t npincfg;                    /* Complementary output pin configuration (only TIM1/8 CH1-3)*/
 };
 
 /* This structure represents the state of one PWM timer */
@@ -229,6 +230,7 @@ static struct stm32l4_pwmtimer_s g_pwm1dev =
       .channel = 1,
       .pincfg  = PWM_TIM1_CH1CFG,
       .mode    = CONFIG_STM32L4_TIM1_CH1MODE,
+      .npincfg = PWM_TIM1_CH1NCFG,
     },
 #endif
 #ifdef CONFIG_STM32L4_TIM1_CHANNEL2
@@ -236,6 +238,7 @@ static struct stm32l4_pwmtimer_s g_pwm1dev =
       .channel = 2,
       .pincfg  = PWM_TIM1_CH2CFG,
       .mode    = CONFIG_STM32L4_TIM1_CH2MODE,
+      .npincfg = PWM_TIM1_CH2NCFG,
     },
 #endif
 #ifdef CONFIG_STM32L4_TIM1_CHANNEL3
@@ -243,6 +246,7 @@ static struct stm32l4_pwmtimer_s g_pwm1dev =
       .channel = 3,
       .pincfg  = PWM_TIM1_CH3CFG,
       .mode    = CONFIG_STM32L4_TIM1_CH3MODE,
+      .npincfg = PWM_TIM1_CH3NCFG,
     },
 #endif
 #ifdef CONFIG_STM32L4_TIM1_CHANNEL4
@@ -250,6 +254,7 @@ static struct stm32l4_pwmtimer_s g_pwm1dev =
       .channel = 4,
       .pincfg  = PWM_TIM1_CH4CFG,
       .mode    = CONFIG_STM32L4_TIM1_CH4MODE,
+      .npincfg = 0,
     },
 #endif
   },
@@ -275,6 +280,7 @@ static struct stm32l4_pwmtimer_s g_pwm2dev =
       .channel = 1,
       .pincfg  = PWM_TIM2_CH1CFG,
       .mode    = CONFIG_STM32L4_TIM2_CH1MODE,
+      .npincfg = 0,
     },
 #endif
 #ifdef CONFIG_STM32L4_TIM2_CHANNEL2
@@ -282,6 +288,7 @@ static struct stm32l4_pwmtimer_s g_pwm2dev =
       .channel = 2,
       .pincfg  = PWM_TIM2_CH2CFG,
       .mode    = CONFIG_STM32L4_TIM2_CH2MODE,
+      .npincfg = 0,
     },
 #endif
 #ifdef CONFIG_STM32L4_TIM2_CHANNEL3
@@ -289,6 +296,7 @@ static struct stm32l4_pwmtimer_s g_pwm2dev =
       .channel = 3,
       .pincfg  = PWM_TIM2_CH3CFG,
       .mode    = CONFIG_STM32L4_TIM2_CH3MODE,
+      .npincfg = 0,
     },
 #endif
 #ifdef CONFIG_STM32L4_TIM2_CHANNEL4
@@ -296,6 +304,7 @@ static struct stm32l4_pwmtimer_s g_pwm2dev =
       .channel = 4,
       .pincfg  = PWM_TIM2_CH4CFG,
       .mode    = CONFIG_STM32L4_TIM2_CH4MODE,
+      .npincfg = 0,
     },
 #endif
   },
@@ -321,6 +330,7 @@ static struct stm32l4_pwmtimer_s g_pwm3dev =
       .channel = 1,
       .pincfg  = PWM_TIM3_CH1CFG,
       .mode    = CONFIG_STM32L4_TIM3_CH1MODE,
+      .npincfg = 0,
     },
 #endif
 #ifdef CONFIG_STM32L4_TIM3_CHANNEL2
@@ -328,6 +338,7 @@ static struct stm32l4_pwmtimer_s g_pwm3dev =
       .channel = 2,
       .pincfg  = PWM_TIM3_CH2CFG,
       .mode    = CONFIG_STM32L4_TIM3_CH2MODE,
+      .npincfg = 0,
     },
 #endif
 #ifdef CONFIG_STM32L4_TIM3_CHANNEL3
@@ -335,6 +346,7 @@ static struct stm32l4_pwmtimer_s g_pwm3dev =
       .channel = 3,
       .pincfg  = PWM_TIM3_CH3CFG,
       .mode    = CONFIG_STM32L4_TIM3_CH3MODE,
+      .npincfg = 0,
     },
 #endif
 #ifdef CONFIG_STM32L4_TIM3_CHANNEL4
@@ -342,6 +354,7 @@ static struct stm32l4_pwmtimer_s g_pwm3dev =
       .channel = 4,
       .pincfg  = PWM_TIM3_CH4CFG,
       .mode    = CONFIG_STM32L4_TIM3_CH4MODE,
+      .npincfg = 0,
     },
 #endif
   },
@@ -367,6 +380,7 @@ static struct stm32l4_pwmtimer_s g_pwm4dev =
       .channel = 1,
       .pincfg  = PWM_TIM4_CH1CFG,
       .mode    = CONFIG_STM32L4_TIM4_CH1MODE,
+      .npincfg = 0,
     },
 #endif
 #ifdef CONFIG_STM32L4_TIM4_CHANNEL2
@@ -374,6 +388,7 @@ static struct stm32l4_pwmtimer_s g_pwm4dev =
       .channel = 2,
       .pincfg  = PWM_TIM4_CH2CFG,
       .mode    = CONFIG_STM32L4_TIM4_CH2MODE,
+      .npincfg = 0,
     },
 #endif
 #ifdef CONFIG_STM32L4_TIM4_CHANNEL3
@@ -381,6 +396,7 @@ static struct stm32l4_pwmtimer_s g_pwm4dev =
       .channel = 3,
       .pincfg  = PWM_TIM4_CH3CFG,
       .mode    = CONFIG_STM32L4_TIM4_CH3MODE,
+      .npincfg = 0,
     },
 #endif
 #ifdef CONFIG_STM32L4_TIM4_CHANNEL4
@@ -388,6 +404,7 @@ static struct stm32l4_pwmtimer_s g_pwm4dev =
       .channel = 4,
       .pincfg  = PWM_TIM4_CH4CFG,
       .mode    = CONFIG_STM32L4_TIM4_CH4MODE,
+      .npincfg = 0,
     },
 #endif
   },
@@ -413,6 +430,7 @@ static struct stm32l4_pwmtimer_s g_pwm5dev =
       .channel = 1,
       .pincfg  = PWM_TIM5_CH1CFG,
       .mode    = CONFIG_STM32L4_TIM5_CH1MODE,
+      .npincfg = 0,
     },
 #endif
 #ifdef CONFIG_STM32L4_TIM5_CHANNEL2
@@ -420,6 +438,7 @@ static struct stm32l4_pwmtimer_s g_pwm5dev =
       .channel = 2,
       .pincfg  = PWM_TIM5_CH2CFG,
       .mode    = CONFIG_STM32L4_TIM5_CH2MODE,
+      .npincfg = 0,
     },
 #endif
 #ifdef CONFIG_STM32L4_TIM5_CHANNEL3
@@ -427,6 +446,7 @@ static struct stm32l4_pwmtimer_s g_pwm5dev =
       .channel = 3,
       .pincfg  = PWM_TIM5_CH3CFG,
       .mode    = CONFIG_STM32L4_TIM5_CH3MODE,
+      .npincfg = 0,
     },
 #endif
 #ifdef CONFIG_STM32L4_TIM5_CHANNEL4
@@ -434,6 +454,7 @@ static struct stm32l4_pwmtimer_s g_pwm5dev =
       .channel = 4,
       .pincfg  = PWM_TIM5_CH4CFG,
       .mode    = CONFIG_STM32L4_TIM5_CH4MODE,
+      .npincfg = 0,
     },
 #endif
   },
@@ -459,6 +480,7 @@ static struct stm32l4_pwmtimer_s g_pwm8dev =
       .channel = 1,
       .pincfg  = PWM_TIM8_CH1CFG,
       .mode    = CONFIG_STM32L4_TIM8_CH1MODE,
+      .npincfg = PWM_TIM8_CH1NCFG,
     },
 #endif
 #ifdef CONFIG_STM32L4_TIM8_CHANNEL2
@@ -466,6 +488,7 @@ static struct stm32l4_pwmtimer_s g_pwm8dev =
       .channel = 2,
       .pincfg  = PWM_TIM8_CH2CFG,
       .mode    = CONFIG_STM32L4_TIM8_CH2MODE,
+      .npincfg = PWM_TIM8_CH2NCFG,
     },
 #endif
 #ifdef CONFIG_STM32L4_TIM8_CHANNEL3
@@ -473,6 +496,7 @@ static struct stm32l4_pwmtimer_s g_pwm8dev =
       .channel = 3,
       .pincfg  = PWM_TIM8_CH3CFG,
       .mode    = CONFIG_STM32L4_TIM8_CH3MODE,
+      .npincfg = PWM_TIM8_CH3NCFG,
     },
 #endif
 #ifdef CONFIG_STM32L4_TIM8_CHANNEL4
@@ -480,6 +504,7 @@ static struct stm32l4_pwmtimer_s g_pwm8dev =
       .channel = 4,
       .pincfg  = PWM_TIM8_CH4CFG,
       .mode    = CONFIG_STM32L4_TIM8_CH4MODE,
+      .npincfg = 0,
     },
 #endif
   },
@@ -505,6 +530,7 @@ static struct stm32l4_pwmtimer_s g_pwm15dev =
       .channel = 1,
       .pincfg  = PWM_TIM15_CH1CFG,
       .mode    = CONFIG_STM32L4_TIM15_CH1MODE,
+      .npincfg = PWM_TIM15_CH1NCFG,
     },
 #endif
 #ifdef CONFIG_STM32L4_TIM15_CHANNEL2
@@ -512,6 +538,7 @@ static struct stm32l4_pwmtimer_s g_pwm15dev =
       .channel = 2,
       .pincfg  = PWM_TIM15_CH2CFG,
       .mode    = CONFIG_STM32L4_TIM15_CH2MODE,
+      .npincfg = 0,
     },
 #endif
   },
@@ -537,6 +564,7 @@ static struct stm32l4_pwmtimer_s g_pwm16dev =
       .channel = 1,
       .pincfg  = PWM_TIM16_CH1CFG,
       .mode    = CONFIG_STM32L4_TIM16_CH1MODE,
+      .npincfg = PWM_TIM16_CH1NCFG,
     },
 #endif
   },
@@ -562,6 +590,7 @@ static struct stm32l4_pwmtimer_s g_pwm17dev =
       .channel = 1,
       .pincfg  = PWM_TIM17_CH1CFG,
       .mode    = CONFIG_STM32L4_TIM17_CH1MODE,
+      .npincfg = PWM_TIM17_CH1NCFG,
     },
 #endif
   },
@@ -737,6 +766,7 @@ static int stm32l4pwm_timer(FAR struct stm32l4_pwmtimer_s *priv,
   /* New timer register bit settings */
 
   uint16_t ccenable;
+  uint16_t ccnenable;
   uint32_t ocmode1;
   uint32_t ocmode2;
 
@@ -967,6 +997,7 @@ static int stm32l4pwm_timer(FAR struct stm32l4_pwmtimer_s *priv,
   /* Handle channel specific setup */
 
   ccenable  = 0;
+  ccnenable = 0;
   ocmode1   = 0;
   ocmode2   = 0;
 
@@ -976,6 +1007,7 @@ static int stm32l4pwm_timer(FAR struct stm32l4_pwmtimer_s *priv,
     {
       ub16_t                duty;
       uint32_t              chanmode;
+      uint32_t              compout; /* Complementary output config */
       bool                  ocmbit = false;
       uint8_t               channel;
 #ifdef CONFIG_PWM_MULTICHAN
@@ -1001,6 +1033,7 @@ static int stm32l4pwm_timer(FAR struct stm32l4_pwmtimer_s *priv,
           if (priv->channels[j].channel == channel)
             {
               mode = priv->channels[j].mode;
+              compout = priv->channels[j].npincfg;
               break;
             }
         }
@@ -1014,6 +1047,7 @@ static int stm32l4pwm_timer(FAR struct stm32l4_pwmtimer_s *priv,
       duty = info->duty;
       channel = priv->channels[0].channel;
       mode = priv->channels[0].mode;
+      compout = priv->channels[0].npincfg;
 #endif
 
       /* Duty cycle:
@@ -1068,6 +1102,13 @@ static int stm32l4pwm_timer(FAR struct stm32l4_pwmtimer_s *priv,
 
               ccenable |= ATIM_CCER_CC1E;
 
+              /* Conditionnaly enable the complementary output */
+
+              if (compout)
+                {
+                  ccnenable |= ATIM_CCER_CC1NE;
+                }
+
               /* Set the CCMR1 mode values (leave CCMR2 zero) */
 
               ocmode1  |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC1S_SHIFT) |
@@ -1091,6 +1132,13 @@ static int stm32l4pwm_timer(FAR struct stm32l4_pwmtimer_s *priv,
 
               ccenable |= ATIM_CCER_CC2E;
 
+              /* Conditionnaly enable the complementary output */
+
+              if (compout)
+                {
+                  ccnenable |= ATIM_CCER_CC2NE;
+                }
+
               /* Set the CCMR1 mode values (leave CCMR2 zero) */
 
               ocmode1  |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC2S_SHIFT) |
@@ -1114,6 +1162,13 @@ static int stm32l4pwm_timer(FAR struct stm32l4_pwmtimer_s *priv,
 
               ccenable |= ATIM_CCER_CC3E;
 
+              /* Conditionnaly enable the complementary output */
+
+              if (compout)
+                {
+                  ccnenable |= ATIM_CCER_CC3NE;
+                }
+
               /* Set the CCMR2 mode values (leave CCMR1 zero) */
 
               ocmode2  |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR2_CC3S_SHIFT) |
@@ -1206,7 +1261,9 @@ static int stm32l4pwm_timer(FAR struct stm32l4_pwmtimer_s *priv,
        */
 
       ccer &= ~(ATIM_CCER_CC1NE | ATIM_CCER_CC1NP | ATIM_CCER_CC2NE | ATIM_CCER_CC2NP |
-                ATIM_CCER_CC3NE | ATIM_CCER_CC3NP | ATIM_CCER_CC4NP);
+                ATIM_CCER_CC3NE | ATIM_CCER_CC3NP);
+
+      ccer |= ccnenable;
 
       /* Reset the output compare and output compare N IDLE State */
 
@@ -1223,9 +1280,22 @@ static int stm32l4pwm_timer(FAR struct stm32l4_pwmtimer_s *priv,
       stm32l4pwm_putreg(priv, STM32L4_ATIM_BDTR_OFFSET, bdtr);
     }
   else
+#if defined(CONFIG_STM32L4_TIM15_PWM) || defined(CONFIG_STM32L4_TIM15_PWM) || defined(CONFIG_STM32L4_TIM15_PWM)
+  if (priv->timtype == TIMTYPE_COUNTUP16)
+    {
+
+      /* Reset output N polarity level, output N state, output compare state,
+       * output compare N idle state.
+       */
+
+      ccer &= ~(ATIM_CCER_CC1NE | ATIM_CCER_CC1NP);
+      ccer |= ccnenable;
+    }
+  else
+#endif
 #endif
     {
-      ccer &= ~(GTIM_CCER_CC1NP | GTIM_CCER_CC2NP | GTIM_CCER_CC3NP | ATIM_CCER_CC4NP);
+      ccer &= ~(GTIM_CCER_CC1NP | GTIM_CCER_CC2NP | GTIM_CCER_CC3NP); /* Not sure why? */
     }
 
   /* Save the modified register values */
@@ -1646,14 +1716,24 @@ static int stm32l4pwm_setup(FAR struct pwm_lowerhalf_s *dev)
   for (i = 0; i < PWM_NCHANNELS; i++)
     {
       pincfg = priv->channels[i].pincfg;
-      if (pincfg == 0)
+      if (pincfg != 0)
         {
-          continue;
-        }
-
           pwminfo("pincfg: %08x\n", pincfg);
 
           stm32l4_configgpio(pincfg);
+        }
+
+
+      /* Enable complementary channel if available */
+
+      pincfg = priv->channels[i].npincfg;
+      if (pincfg != 0)
+        {
+          pwminfo("npincfg: %08x\n", pincfg);
+
+          stm32l4_configgpio(pincfg);
+        }
+
       pwm_dumpgpio(pincfg, "PWM setup");
     }
 
@@ -1697,20 +1777,29 @@ static int stm32l4pwm_shutdown(FAR struct pwm_lowerhalf_s *dev)
   for (i = 0; i < PWM_NCHANNELS; i++)
     {
       pincfg = priv->channels[i].pincfg;
-      if (pincfg == 0)
+      if (pincfg != 0)
         {
-          continue;
-        }
-
           pwminfo("pincfg: %08x\n", pincfg);
 
           pincfg &= (GPIO_PORT_MASK | GPIO_PIN_MASK);
-
           pincfg |= GPIO_INPUT | GPIO_FLOAT;
 
           stm32l4_configgpio(pincfg);
         }
 
+      pincfg = priv->channels[i].npincfg;
+      if (pincfg != 0)
+        {
+          pwminfo("npincfg: %08x\n", pincfg);
+
+          pincfg &= (GPIO_PORT_MASK | GPIO_PIN_MASK);
+          pincfg |= GPIO_INPUT | GPIO_FLOAT;
+
+          stm32l4_configgpio(pincfg);
+        }
+
+    }
+
   return OK;
 }
 

arch/arm/src/stm32l4/stm32l4_pwm.h

@@ -114,6 +114,11 @@
 #  else
 #    define PWM_TIM1_CH1CFG 0
 #  endif
+#  ifdef CONFIG_STM32L4_TIM1_CH1NOUT
+#    define PWM_TIM1_CH1NCFG GPIO_TIM1_CH1NOUT
+#  else
+#    define PWM_TIM1_CH1NCFG 0
+#  endif
 #  define PWM_TIM1_CHANNEL1 1
 #else
 #  define PWM_TIM1_CHANNEL1 0
@@ -124,6 +129,11 @@
 #  else
 #    define PWM_TIM1_CH2CFG 0
 #  endif
+#  ifdef CONFIG_STM32L4_TIM1_CH2NOUT
+#    define PWM_TIM1_CH2NCFG GPIO_TIM1_CH2NOUT
+#  else
+#    define PWM_TIM1_CH2NCFG 0
+#  endif
 #  define PWM_TIM1_CHANNEL2 1
 #else
 #  define PWM_TIM1_CHANNEL2 0
@@ -134,6 +144,11 @@
 #  else
 #    define PWM_TIM1_CH3CFG 0
 #  endif
+#  ifdef CONFIG_STM32L4_TIM1_CH3NOUT
+#    define PWM_TIM1_CH3NCFG GPIO_TIM1_CH3NOUT
+#  else
+#    define PWM_TIM1_CH3NCFG 0
+#  endif
 #  define PWM_TIM1_CHANNEL3 1
 #else
 #  define PWM_TIM1_CHANNEL3 0
@@ -329,6 +344,11 @@
 #  else
 #    define PWM_TIM8_CH1CFG 0
 #  endif
+#  ifdef CONFIG_STM32L4_TIM8_CH1OUT
+#    define PWM_TIM8_CH1NCFG GPIO_TIM8_CH1NOUT
+#  else
+#    define PWM_TIM8_CH1NCFG 0
+#  endif
 #  define PWM_TIM8_CHANNEL1 1
 #else
 #  define PWM_TIM8_CHANNEL1 0
@@ -339,6 +359,11 @@
 #  else
 #    define PWM_TIM8_CH2CFG 0
 #  endif
+#  ifdef CONFIG_STM32L4_TIM8_CH2NOUT
+#    define PWM_TIM8_CH2NCFG GPIO_TIM8_CH2NOUT
+#  else
+#    define PWM_TIM8_CH2NCFG 0
+#  endif
 #  define PWM_TIM8_CHANNEL2 1
 #else
 #  define PWM_TIM8_CHANNEL2 0
@@ -349,6 +374,11 @@
 #  else
 #    define PWM_TIM8_CH3CFG 0
 #  endif
+#  ifdef CONFIG_STM32L4_TIM8_CH3NOUT
+#    define PWM_TIM8_CH3NCFG GPIO_TIM8_CH3NOUT
+#  else
+#    define PWM_TIM8_CH3NCFG 0
+#  endif
 #  define PWM_TIM8_CHANNEL3 1
 #else
 #  define PWM_TIM8_CHANNEL3 0
@@ -372,6 +402,11 @@
 #  else
 #    define PWM_TIM15_CH1CFG 0
 #  endif
+#  ifdef CONFIG_STM32L4_TIM15_CH1NOUT
+#    define PWM_TIM15_CH1NCFG GPIO_TIM15_CH1NOUT
+#  else
+#    define PWM_TIM15_CH1NCFG 0
+#  endif
 #  define PWM_TIM15_CHANNEL1 1
 #else
 #  define PWM_TIM15_CHANNEL1 0
@@ -394,6 +429,11 @@
 #  else
 #    define PWM_TIM16_CH1CFG 0
 #  endif
+#  ifdef CONFIG_STM32L4_TIM16_CH1NOUT
+#    define PWM_TIM16_CH1NCFG GPIO_TIM16_CH1NOUT
+#  else
+#    define PWM_TIM16_CH1NCFG 0
+#  endif
 #  define PWM_TIM16_CHANNEL1 1
 #else
 #  define PWM_TIM16_CHANNEL1 0
@@ -406,6 +446,11 @@
 #  else
 #    define PWM_TIM17_CH1CFG 0
 #  endif
+#  ifdef CONFIG_STM32L4_TIM17_CH1NOUT
+#    define PWM_TIM17_CH1NCFG GPIO_TIM17_CH1NOUT
+#  else
+#    define PWM_TIM17_CH1NCFG 0
+#  endif
 #  define PWM_TIM17_CHANNEL1 1
 #else
 #  define PWM_TIM17_CHANNEL1 0
@@ -422,7 +467,7 @@
                       PWM_MAX(PWM_TIM8_NCHANNELS, \
                       PWM_MAX(PWM_TIM15_NCHANNELS, \
                       PWM_MAX(PWM_TIM16_NCHANNELS, \
-                              PWM_TIM17_NCHANNELS))))))))))))))
+                              PWM_TIM17_NCHANNELS))))))))
 
 #else
 

arch/risc-v/Kconfig

@@ -0,0 +1,55 @@
+#
+# For a description of the syntax of this configuration file,
+# see the file kconfig-language.txt in the NuttX tools repository.
+#
+
+if ARCH_RISCV
+comment "RISC-V Options"
+
+choice
+	prompt "RISC-V chip selection"
+	default ARCH_CHIP_NR5M100
+
+config ARCH_CHIP_NR5M100
+	bool "NEXT NanoRisc5 M100"
+	select ARCH_RV32IM
+	default ARCH_CHIP_NR5
+	---help---
+		NEXT RISC-V NR5Mxx architectures (RISC-V RV32IM cores).
+
+endchoice
+
+config ARCH_RV32I
+	bool
+	default n
+
+config ARCH_RV32IM
+	bool
+	default n
+
+config ARCH_FAMILY
+	string
+	default "rv32im"	if ARCH_RM32IM
+
+config ARCH_CHIP
+	string
+	default "nr5m100"	if ARCH_CHIP_NR5M100
+
+config NR5_MPU
+	bool "MPU support"
+	default n
+	depends on ARCH_HAVE_MPU
+	select ARCH_USE_MPU
+	---help---
+		Build in support for the RISC-V Memory Protection Unit (MPU).
+		Check your chip specifications first; not all RISC-V architectures
+		support the MPU.
+
+if ARCH_RV32IM
+source arch/risc-v/src/rv32im/Kconfig
+endif
+if ARCH_CHIP_NR5M100
+source arch/risc-v/src/nr5m100/Kconfig
+endif
+
+endif

arch/risc-v/include/arch.h

@@ -0,0 +1,119 @@
+/****************************************************************************
+ * arch/risc-v/include/arch.h
+ *
+ *   Copyright (C) 2016 Ken Pettit. All rights reserved.
+ *   Author: Ken Pettit <pettitkd@gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directed but, rather,
+ * only indirectly through nuttx/arch.h
+ */
+
+#ifndef __ARCH_RISCV_INCLUDE_ARCH_H
+#define __ARCH_RISCV_INCLUDE_ARCH_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+#  include <stdint.h>
+#endif
+
+#ifdef CONFIG_ARCH_RV32IM
+#  include "rv32im/csr.h"
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Macros to get the core and vendor ID, HART, arch and ISA codes, etc.
+ */
+#ifdef CONFIG_RV32IM_SYSTEM_CSRRS_SUPPORT 
+
+uint32_t up_getmisa(void);
+uint32_t up_getarchid(void);
+uint32_t up_getimpid(void);
+uint32_t up_getvendorid(void);
+uint32_t up_gethartid(void);
+
+#else
+
+#define up_getmisa() 0
+#define up_getarchid() 0
+#define up_getimpid() 0
+#define up_getvendorid() 0
+#define up_gethartid() 0
+
+#endif
+
+/****************************************************************************
+ * Inline functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Variables
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#ifdef CONFIG_RV32IM_HW_MULDIV 
+uint32_t up_hard_mul(uint32_t a, uint32_t b);
+uint32_t up_hard_mulh(uint32_t a, uint32_t b);
+uint32_t up_hard_mulhsu(uint32_t a, uint32_t b);
+uint32_t up_hard_mulhu(uint32_t a, uint32_t b);
+uint32_t up_hard_div(uint32_t a, uint32_t b);
+uint32_t up_hard_rem(uint32_t a, uint32_t b);
+uint32_t up_hard_divu(uint32_t a, uint32_t b);
+uint32_t up_hard_remu(uint32_t a, uint32_t b);
+uint32_t time_hard_mul(uint32_t a, uint32_t b, uint32_t *t);
+#endif
+
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C" {
+#else
+#define EXTERN extern
+#endif
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ARCH_RISCV_INCLUDE_ARCH_H */
+

arch/risc-v/include/irq.h

@@ -0,0 +1,79 @@
+/****************************************************************************
+ * arch/risc-v/include/irq.h
+ *
+ *   Copyright (C) 2016 Ken Pettit. All rights reserved.
+ *   Author: Ken Pettit <pettitkd@gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directed but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_RISCV_INCLUDE_IRQ_H
+#define __ARCH_RISCV_INCLUDE_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/* Include chip-specific IRQ definitions (including IRQ numbers) */
+
+#include <stdint.h>
+#include <nuttx/irq.h>
+#include <arch/chip/irq.h>
+
+/* Include RISC-V architecture-specific IRQ definitions */
+
+#if defined(CONFIG_ARCH_RV32IM) || defined(CONFIG_ARCH_RV32I)
+#  include <arch/rv32im/irq.h>
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+typedef uint32_t  irqstate_t;
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Variables
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+irqstate_t  irqsave(void);
+
+void irqrestore(irqstate_t);
+
+#endif /* __ARCH_RISCV_INCLUDE_IRQ_H */
+

arch/risc-v/include/limits.h

@@ -0,0 +1,90 @@
+/****************************************************************************
+ * arch/risc-v/include/limits.h
+ *
+ *   Copyright (C) 2007-2009, 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_INCLUDE_LIMITS_H
+#define __ARCH_RISCV_INCLUDE_LIMITS_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define CHAR_BIT    8
+#define SCHAR_MIN  (-SCHAR_MAX - 1)
+#define SCHAR_MAX   127
+#define UCHAR_MAX   255
+
+/* These could be different on machines where char is unsigned */
+
+#ifdef __CHAR_UNSIGNED__
+#define CHAR_MIN    0
+#define CHAR_MAX    UCHAR_MAX
+#else
+#define CHAR_MIN    SCHAR_MIN
+#define CHAR_MAX    SCHAR_MAX
+#endif
+
+#define SHRT_MIN    (-SHRT_MAX - 1)
+#define SHRT_MAX    32767
+#define USHRT_MAX   65535U
+
+#define INT_MIN     (-INT_MAX - 1)
+#define INT_MAX     2147483647
+#define UINT_MAX    4294967295U
+
+/* These change on 32-bit and 64-bit platforms */
+
+#if defined(CONFIG_ARCH_32IM) || defined(CONFIG_ARCH_32I)
+
+#define LONG_MIN    (-LONG_MAX - 1)
+#define LONG_MAX    2147483647L
+#define ULONG_MAX   4294967295UL
+
+#define LLONG_MIN   (-LLONG_MAX - 1)
+#define LLONG_MAX   9223372036854775807LL
+#define ULLONG_MAX  18446744073709551615ULL
+
+/* A pointer is 4 bytes */
+
+#define PTR_MIN     (-PTR_MAX - 1)
+#define PTR_MAX     2147483647
+#define UPTR_MAX    4294967295U
+
+#endif /* defined(CONFIG_ARCH_32IM) || defined(CONFIG_ARCH_32I) */
+
+#endif /* __ARCH_RISCV_INCLUDE_LIMITS_H */

arch/risc-v/include/nr5m100/chip.h

@@ -0,0 +1,61 @@
+/****************************************************************************
+ * arch/risc-v/include/nr5m100/chip.h
+ *
+ *   Copyright (C) 2016 Ken Pettit. All rights reserved.
+ *   Author: Ken Pettit <pettitkd@gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directed but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_RISCV_INCLUDE_NR5M100_CHIP_H
+#define __ARCH_RISCV_INCLUDE_NR5M100_CHIP_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Variables
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#endif /* __ARCH_RISCV_INCLUDE_NR5M100_CHIP_H */
+

arch/risc-v/include/nr5m100/irq.h

@@ -0,0 +1,73 @@
+/****************************************************************************
+ * arch/risc-v/include/nr5m100/irq.h
+ * include/arch/nr5m100/irq.h
+ *
+ *   Copyright (C) 2016 Ken Pettit. All rights reserved.
+ *   Author: Ken Pettit <pettitkd@gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_INCLUDE_NR5M100_IRQ_H
+#define __ARCH_RISCV_INCLUDE_NR5M100_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#if defined(CONFIG_NR5_NR5M1XX)
+#  include <arch/chip/nr5m1xx_irq.h>
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define  NR5_IRQ_TRAP      0
+
+#define  EPIC_STATUS_PRI_MASK       0x001C
+#define  EPIC_STATUS_INT_PRI_MASK   0x01C0
+#define  EPIC_STATUS_INT_PRI1       0x0040
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Variables
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+void up_enable_irq(int irq);
+
+irqstate_t up_irq_save(void);
+void up_irq_restore(irqstate_t irqstate);
+
+#endif /* __ARCH_RISCV_INCLUDE_NR5M100_IRQ_H */
+

arch/risc-v/include/nr5m100/nr5m1xx_irq.h

@@ -0,0 +1,71 @@
+/****************************************************************************
+ * arch/risc-v/include/nr5m100/nr5m1xx_irq.h
+ * include/arch/nr5m100/nr5m1xx_irq.h
+ *
+ *   Copyright (C) 2016 Ken Pettit. All rights reserved.
+ *   Author: Ken Pettit <pettitkd@gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_INCLUDE_NR5M100_NR5M1XX_IRQ_H
+#define __ARCH_RISCV_INCLUDE_NR5M100_NR5M1XX_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define  NR5_IRQ_SYSTICK     1
+#define  NR5_IRQ_TIMER       2
+#define  NR5_IRQ_SOFTWARE    3
+#define  NR5_IRQ_DEBUG       4
+#define  NR5_IRQ_UART1_RX    5
+#define  NR5_IRQ_UART1_TX    6
+#define  NR5_IRQ_TIMER1_A    7
+#define  NR5_IRQ_TIMER1_B    8
+#define  NR5_IRQ_TIMER2_A    9
+#define  NR5_IRQ_TIMER2_B    10
+
+#define  NR_IRQS             11
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Variables
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#endif /* __ARCH_RISCV_INCLUDE_NR5M100_NR5M1XX_IRQ_H */
+

arch/risc-v/include/rv32im/csr.h

@@ -0,0 +1,100 @@
+/****************************************************************************
+ * arch/risc-v/include/rv32im/csr.h
+ *
+ *   Copyright (C) 2016 Ken Pettit. All rights reserved.
+ *   Author: Ken Pettit <pettitkd@gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directed but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_RISCV_INCLUDE_RV32IM_CSR_H
+#define __ARCH_RISCV_INCLUDE_RV32IM_CSR_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Machine Information Registers */
+
+#define CSR_MISA          0xF10
+#define CSR_MVENDORID     0xF11
+#define CSR_MARCHID       0xF12
+#define CSR_MIMPID        0xF13
+#define CSR_MHARTID       0xF14
+
+/* Machine Trap Registers */
+
+#define CSR_MSTATUS       0x300
+#define CSR_MTDELEG       0x302
+#define CSR_MIE           0x304
+#define CSR_MTVEC         0x305
+#define CSR_MIVEC         0x30f
+
+/* Machine Trap Handling */
+
+#define CSR_MSCRATCH      0x340
+#define CSR_MEPC          0x341
+#define CSR_MCAUSE        0x342
+#define CSR_MBADADDR      0x343
+#define CSR_MIP           0x344
+
+/* Machine Timers and Counters */
+
+#define CSR_CYCLE         0xF00
+#define CSR_TIME          0xF01
+#define CSR_INSTRET       0xF02
+#define CSR_CYCLEH        0xF80
+#define CSR_TIMEH         0xF81
+#define CSR_INSTRETH      0xF82
+
+/* Debug interface CSRs */
+
+#define CSR_DCSR          0x7B0
+#define CSR_DPC           0x7B1
+#define CSR_DSCRATCH      0x7B2
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Variables
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#endif /* __ARCH_RISCV_INCLUDE_RV32IM_CSR_H */
+

arch/risc-v/include/rv32im/irq.h

@@ -0,0 +1,347 @@
+/****************************************************************************
+ * arch/risc-v/include/rv32im/irq.h
+ *
+ *   Copyright (C) 2011, 2013, 2015 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ *   Modified for RISC-V:
+ *
+ *   Copyright (C) 2016 Ken Pettit. All rights reserved.
+ *   Author: Ken Pettit <pettitkd@gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directed but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_RISCV_INCLUDE_RV32IM_IRQ_H
+#define __ARCH_RISCV_INCLUDE_RV32IM_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <arch/types.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+/* Configuration ************************************************************/
+
+/* If this is a kernel build, how many nested system calls should we support? */
+
+#ifndef CONFIG_SYS_NNEST
+#  define CONFIG_SYS_NNEST 2
+#endif
+
+/* Processor PC */
+#define REG_EPC_NDX         0
+
+/* General pupose registers */
+/* $0: Zero register does not need to be saved */
+/* $1: ra (return address) */
+
+#define REG_X1_NDX          1
+
+/* $2: Stack POinter
+ * $3: Global Pointer
+ * $4: Thread Pointer
+ */
+
+#define REG_X2_NDX          2
+#define REG_X3_NDX          3
+#define REG_X4_NDX          4
+
+/* $5-$7 = t0-t3: Temporary registers */
+
+#define REG_X5_NDX          5
+#define REG_X6_NDX          6
+#define REG_X7_NDX          7
+
+/* $8: s0 / fp Frame pointer */
+
+#define REG_X8_NDX          8
+
+/* $89 s1 Saved register */
+
+#define REG_X9_NDX          9
+
+/* $10-$17 = a0-a7: Argument registers */
+
+#define REG_X10_NDX         10
+#define REG_X11_NDX         11
+#define REG_X12_NDX         12
+#define REG_X13_NDX         13
+#define REG_X14_NDX         14
+#define REG_X15_NDX         15
+#define REG_X16_NDX         16
+#define REG_X17_NDX         17
+
+/* $18-$27 = s2-s11: Saved registers */
+
+#define REG_X18_NDX         18
+#define REG_X19_NDX         19
+#define REG_X20_NDX         20
+#define REG_X21_NDX         21
+#define REG_X22_NDX         22
+#define REG_X23_NDX         23
+#define REG_X24_NDX         24
+#define REG_X25_NDX         25
+#define REG_X26_NDX         26
+#define REG_X27_NDX         27
+
+/* $28-31 = t3-t6: Temporary (Volatile) registers */
+
+#define REG_X28_NDX         28
+#define REG_X29_NDX         29
+#define REG_X30_NDX         30
+#define REG_X31_NDX         31
+
+/* Interrupt Context register */
+
+#define REG_INT_CTX_NDX     32
+
+#define XCPTCONTEXT_REGS    33
+#define XCPTCONTEXT_SIZE    (4 * XCPTCONTEXT_REGS)
+
+/* In assembly language, values have to be referenced as byte address
+ * offsets.  But in C, it is more convenient to reference registers as
+ * register save table offsets.
+ */
+
+#ifdef __ASSEMBLY__
+#  define REG_EPC           (4*REG_EPC_NDX)
+#  define REG_X1            (4*REG_X1_NDX)
+#  define REG_X2            (4*REG_X2_NDX)
+#  define REG_X3            (4*REG_X3_NDX)
+#  define REG_X4            (4*REG_X4_NDX)
+#  define REG_X5            (4*REG_X5_NDX)
+#  define REG_X6            (4*REG_X6_NDX)
+#  define REG_X7            (4*REG_X7_NDX)
+#  define REG_X8            (4*REG_X8_NDX)
+#  define REG_X9            (4*REG_X9_NDX)
+#  define REG_X10           (4*REG_X10_NDX)
+#  define REG_X11           (4*REG_X11_NDX)
+#  define REG_X12           (4*REG_X12_NDX)
+#  define REG_X13           (4*REG_X13_NDX)
+#  define REG_X14           (4*REG_X14_NDX)
+#  define REG_X15           (4*REG_X15_NDX)
+#  define REG_X16           (4*REG_X16_NDX)
+#  define REG_X17           (4*REG_X17_NDX)
+#  define REG_X18           (4*REG_X18_NDX)
+#  define REG_X19           (4*REG_X19_NDX)
+#  define REG_X20           (4*REG_X20_NDX)
+#  define REG_X21           (4*REG_X21_NDX)
+#  define REG_X22           (4*REG_X22_NDX)
+#  define REG_X23           (4*REG_X23_NDX)
+#  define REG_X24           (4*REG_X24_NDX)
+#  define REG_X25           (4*REG_X25_NDX)
+#  define REG_X26           (4*REG_X26_NDX)
+#  define REG_X27           (4*REG_X27_NDX)
+#  define REG_X28           (4*REG_X28_NDX)
+#  define REG_X29           (4*REG_X29_NDX)
+#  define REG_X30           (4*REG_X30_NDX)
+#  define REG_X31           (4*REG_X31_NDX)
+#  define REG_INT_CTX       (4*REG_INT_CTX_NDX)
+#else
+#  define REG_EPC           REG_EPC_NDX
+#  define REG_X1            REG_X1_NDX
+#  define REG_X2            REG_X2_NDX
+#  define REG_X3            REG_X3_NDX
+#  define REG_X4            REG_X4_NDX
+#  define REG_X5            REG_X5_NDX
+#  define REG_X6            REG_X6_NDX
+#  define REG_X7            REG_X7_NDX
+#  define REG_X8            REG_X8_NDX
+#  define REG_X9            REG_X9_NDX
+#  define REG_X10           REG_X10_NDX
+#  define REG_X11           REG_X11_NDX
+#  define REG_X12           REG_X12_NDX
+#  define REG_X13           REG_X13_NDX
+#  define REG_X14           REG_X14_NDX
+#  define REG_X15           REG_X15_NDX
+#  define REG_X16           REG_X16_NDX
+#  define REG_X17           REG_X17_NDX
+#  define REG_X18           REG_X18_NDX
+#  define REG_X19           REG_X19_NDX
+#  define REG_X20           REG_X20_NDX
+#  define REG_X21           REG_X21_NDX
+#  define REG_X22           REG_X22_NDX
+#  define REG_X23           REG_X23_NDX
+#  define REG_X24           REG_X24_NDX
+#  define REG_X25           REG_X25_NDX
+#  define REG_X26           REG_X26_NDX
+#  define REG_X27           REG_X27_NDX
+#  define REG_X28           REG_X28_NDX
+#  define REG_X29           REG_X29_NDX
+#  define REG_X30           REG_X30_NDX
+#  define REG_X31           REG_X31_NDX
+#  define REG_INT_CTX       REG_INT_CTX_NDX
+#endif
+
+/* Now define more user friendly alternative name that can be used either
+ * in assembly or C contexts.
+ */
+
+/* $1 = ra: Return address */
+
+#define REG_RA              REG_X1
+
+/* $2 = sp:  The value of the stack pointer on return from the exception */
+
+#define REG_SP              REG_X2
+
+/* $3 = gp: Only needs to be saved under conditions where there are
+ * multiple, per-thread values for the GP.
+ */
+
+#define REG_GP              REG_X3
+
+/* $4 = tp:  Thread Pointer */
+
+#define REG_TP              REG_X4
+
+/* $5-$7 = t0-t2: Caller saved temporary registers */
+
+#define REG_T0              REG_X5
+#define REG_T1              REG_X6
+#define REG_T2              REG_X7
+
+/* $8 = either s0 or fp:  Depends if a frame pointer is used or not */
+
+#define REG_S0              REG_X8
+#define REG_FP              REG_X8
+
+/* $9 = s1: Caller saved register */
+
+#define REG_S1              REG_X9
+
+/* $10-$17 = a0-a7: Argument registers */
+
+#define REG_A0              REG_X10
+#define REG_A1              REG_X11
+#define REG_A2              REG_X12
+#define REG_A3              REG_X13
+#define REG_A4              REG_X14
+#define REG_A5              REG_X15
+#define REG_A6              REG_X16
+#define REG_A7              REG_X17
+
+/* $18-$27 = s2-s11: Callee saved registers */
+
+#define REG_S2              REG_X18
+#define REG_S3              REG_X19
+#define REG_S4              REG_X20
+#define REG_S5              REG_X21
+#define REG_S6              REG_X22
+#define REG_S7              REG_X23
+#define REG_S8              REG_X24
+#define REG_S9              REG_X25
+#define REG_S10             REG_X26
+#define REG_S11             REG_X27
+
+/* $28-$31 = t3-t6: Caller saved temporary registers */
+
+#define REG_T3              REG_X28
+#define REG_T4              REG_X29
+#define REG_T5              REG_X30
+#define REG_T6              REG_X31
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/* This structure represents the return state from a system call */
+
+#ifdef CONFIG_BUILD_KERNEL
+struct xcpt_syscall_s
+{
+  uint32_t sysreturn;   /* The return PC */
+};
+#endif
+
+/* The following structure is included in the TCB and defines the complete
+ * state of the thread.
+ */
+
+struct xcptcontext
+{
+#ifndef CONFIG_DISABLE_SIGNALS
+  /* The following function pointer is non-NULL if there are pending signals
+   * to be processed.
+   */
+
+  void *sigdeliver; /* Actual type is sig_deliver_t */
+
+  /* These additional register save locations are used to implement the
+   * signal delivery trampoline.
+   */
+
+  uint32_t saved_epc;     /* Trampoline PC */
+  uint32_t saved_int_ctx; /* Interrupt context with interrupts disabled. */
+
+# ifdef CONFIG_BUILD_KERNEL
+  /* This is the saved address to use when returning from a user-space
+   * signal handler.
+   */
+
+  uint32_t sigreturn;
+
+# endif
+#endif
+
+#ifdef CONFIG_BUILD_KERNEL
+  /* The following array holds information needed to return from each nested
+   * system call.
+   */
+
+  uint8_t nsyscalls;
+  struct xcpt_syscall_s syscall[CONFIG_SYS_NNEST];
+
+#endif
+
+  /* Register save area */
+
+  uint32_t regs[XCPTCONTEXT_REGS];
+};
+
+#endif   /* __ASSEMBLY__ */
+
+/****************************************************************************
+ * Public Variables
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#endif /* __ARCH_RISCV_INCLUDE_RV32IM_IRQ_H */
+

arch/risc-v/include/rv32im/syscall.h

@@ -0,0 +1,208 @@
+/****************************************************************************
+ * arch/risc-v/include/rv32im/syscall.h
+ *
+ *   Copyright (C) 2011-2013, 2015 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directed but, rather, only indirectly
+ * through include/syscall.h or include/sys/sycall.h
+ */
+
+#ifndef __ARCH_RISCV_INCLUDE_RV32IM_SYSCALL_H
+#define __ARCH_RISCV_INCLUDE_RV32IM_SYSCALL_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+#  include <stdint.h>
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define SYS_syscall 0x00
+
+/* Configuration ********************************************************************/
+/* SYS call 1 and 2 are defined for internal use by the RISC-V port (see
+ * arch/riscv/include/mips32/syscall.h).  In addition, SYS call 3 is the return from
+ * a SYS call in kernel mode.  The first four syscall values must, therefore, be
+ * reserved (0 is not used).
+ */
+
+#ifdef CONFIG_BUILD_KERNEL
+#  ifndef CONFIG_SYS_RESERVED
+#    error "CONFIG_SYS_RESERVED must be defined to the value 4"
+#  elif CONFIG_SYS_RESERVED != 4
+#    error "CONFIG_SYS_RESERVED must have the value 4"
+#  endif
+#endif
+
+/* sys_call macros ******************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/* Context switching system calls ***************************************************/
+
+/* SYS call 0: (not used) */
+
+/* SYS call 1:
+ *
+ * void up_fullcontextrestore(uint32_t *restoreregs) noreturn_function;
+ */
+
+#define SYS_restore_context (1)
+#define up_fullcontextrestore(restoreregs) \
+  (void)sys_call1(SYS_restore_context, (uintptr_t)restoreregs)
+
+/* SYS call 2:
+ *
+ * void up_switchcontext(uint32_t *saveregs, uint32_t *restoreregs);
+ */
+
+#define SYS_switch_context (2)
+#define up_switchcontext(saveregs, restoreregs) \
+  (void)sys_call2(SYS_switch_context, (uintptr_t)saveregs, (uintptr_t)restoreregs)
+
+#ifdef CONFIG_BUILD_KERNEL
+/* SYS call 3:
+ *
+ * void up_syscall_return(void);
+ */
+
+#define SYS_syscall_return (3)
+#define up_syscall_return() (void)sys_call0(SYS_syscall_return)
+
+#endif
+#endif /* __ASSEMBLY__ */
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Inline functions
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Name: up_syscall0
+ *
+ * Description:
+ *   System call SYS_ argument and no additional parameters.
+ *
+ ****************************************************************************/
+
+uintptr_t sys_call0(unsigned int nbr);
+
+/****************************************************************************
+ * Name: up_syscall1
+ *
+ * Description:
+ *   System call SYS_ argument and one additional parameter.
+ *
+ ****************************************************************************/
+
+uintptr_t sys_call1(unsigned int nbr, uintptr_t parm1);
+
+/****************************************************************************
+ * Name: up_syscall2
+ *
+ * Description:
+ *   System call SYS_ argument and two additional parameters.
+ *
+ ****************************************************************************/
+
+uintptr_t sys_call2(unsigned int nbr, uintptr_t parm1, uintptr_t parm2);
+
+/****************************************************************************
+ * Name: up_syscall3
+ *
+ * Description:
+ *   System call SYS_ argument and three additional parameters.
+ *
+ ****************************************************************************/
+
+uintptr_t sys_call3(unsigned int nbr, uintptr_t parm1, uintptr_t parm2,
+                    uintptr_t parm3);
+
+/****************************************************************************
+ * Name: up_syscall4
+ *
+ * Description:
+ *   System call SYS_ argument and four additional parameters.
+ *
+ ****************************************************************************/
+
+uintptr_t sys_call4(unsigned int nbr, uintptr_t parm1, uintptr_t parm2,
+                    uintptr_t parm3, uintptr_t parm4);
+
+/****************************************************************************
+ * Name: up_syscall5
+ *
+ * Description:
+ *   System call SYS_ argument and five additional parameters.
+ *
+ ****************************************************************************/
+
+uintptr_t sys_call5(unsigned int nbr, uintptr_t parm1, uintptr_t parm2,
+                    uintptr_t parm3, uintptr_t parm4, uintptr_t parm5);
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_RISCV_INCLUDE_RV32IM_SYSCALL_H */
+

arch/risc-v/include/stdarg.h

@@ -0,0 +1,59 @@
+/****************************************************************************
+ * arch/risc-v/include/stdarg.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_INCLUDE_STDARG_H
+#define __ARCH_RISCV_INCLUDE_STDARG_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+/* This should work with any modern gcc (newer than 3.4 or so) */
+
+#define va_start(v,l)   __builtin_va_start(v,l)
+#define va_end(v)       __builtin_va_end(v)
+#define va_arg(v,l)     __builtin_va_arg(v,l)
+#define va_copy(d,s)    __builtin_va_copy(d,s)
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+typedef __builtin_va_list va_list;
+
+#endif /* __ARCH_RISCV_INCLUDE_STDARG_H */

arch/risc-v/include/syscall.h

@@ -0,0 +1,91 @@
+/****************************************************************************
+ * arch/risc-v/include/syscall.h
+ *
+ *   Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ *   Modified 2016 by Ken Pettit for RISC-V architecture.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directed but, rather, only indirectly
+ * through include/syscall.h or include/sys/sycall.h
+ */
+
+#ifndef __ARCH_RISCV_INCLUDE_SYSCALL_H
+#define __ARCH_RISCV_INCLUDE_SYSCALL_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/* Include RISC-V architecture-specific syscall macros */
+
+#ifdef CONFIG_ARCH_RV32IM
+# include <arch/rv32im/syscall.h>
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Inline functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+#endif /* __ARCH_RISCV_INCLUDE_SYSCALL_H */
+

arch/risc-v/include/types.h

@@ -0,0 +1,96 @@
+/****************************************************************************
+ * arch/risc-v/include/types.h
+ *
+ *   Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directed but, rather, only indirectly
+ * through sys/types.h
+ */
+
+#ifndef __ARCH_RISCV_INCLUDE_TYPES_H
+#define __ARCH_RISCV_INCLUDE_TYPES_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+//#include <nuttx/config.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Type Declarations
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/* These are the sizes of the standard integer types.  NOTE that these type
+ * names have a leading underscore character.  This file will be included
+ * (indirectly) by include/stdint.h and typedef'ed to the final name without
+ * the underscore character.  This roundabout way of doings things allows
+ * the stdint.h to be removed from the include/ directory in the event that
+ * the user prefers to use the definitions provided by their toolchain header
+ * files
+ */
+
+typedef signed char        _int8_t;
+typedef unsigned char      _uint8_t;
+
+typedef signed short       _int16_t;
+typedef unsigned short     _uint16_t;
+
+typedef signed int         _int32_t;
+typedef unsigned int       _uint32_t;
+
+typedef signed long long   _int64_t;
+typedef unsigned long long _uint64_t;
+#define __INT64_DEFINED
+
+/* A pointer is 4 bytes */
+
+typedef signed int         _intptr_t;
+typedef unsigned int       _uintptr_t;
+
+/* This is the size of the interrupt state save returned by irqsave().  */
+
+typedef unsigned int       irqstate_t;
+
+#endif /* __ASSEMBLY__ */
+
+/****************************************************************************
+ * Global Function Prototypes
+ ****************************************************************************/
+
+#endif /* __ARCH_RISCV_INCLUDE_TYPES_H */

arch/risc-v/src/Makefile

@@ -0,0 +1,232 @@
+############################################################################
+# arch/risc-v/src/Makefile
+#
+#   Copyright (C) 2011-2012, 2014, 2016 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt <gnutt@nuttx.org>
+#
+#   Modified for RISC-V:
+#
+#   Copyright (C) 2016 Ken Pettit. All rights reserved.
+#   Author: Ken Pettit <pettitkd@gmail.com>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+include $(TOPDIR)/Make.defs
+include chip/Make.defs
+
+ifeq ($(CONFIG_ARCH_RV32I),y)           # Base Integer support
+ARCH_SUBDIR = rv32i
+else ifeq ($(CONFIG_ARCH_RV32IM),y)     # Integer + math support
+ARCH_SUBDIR = rv32im
+else                                    
+ARCH_SUBDIR = rv32i                     # Default to base RV32I core
+endif
+
+CPPFLAGS += $(EXTRADEFINES)
+CFLAGS += $(EXTRADEFINES)
+CXXFLAGS += $(EXTRADEFINES)
+
+ifeq ($(CONFIG_WINDOWS_NATIVE),y)
+  ARCH_SRCDIR = $(TOPDIR)\arch\$(CONFIG_ARCH)\src
+  NUTTX = "$(TOPDIR)\nuttx$(EXEEXT)"
+  CFLAGS += -I$(ARCH_SRCDIR)\chip
+  CFLAGS += -I$(ARCH_SRCDIR)\common
+  CFLAGS += -I$(ARCH_SRCDIR)\$(ARCH_SUBDIR)
+  CFLAGS += -I$(TOPDIR)\sched
+else
+  ARCH_SRCDIR = $(TOPDIR)/arch/$(CONFIG_ARCH)/src
+ifeq ($(WINTOOL),y)
+  NUTTX = "${shell cygpath -w $(TOPDIR)/nuttx$(EXEEXT)}"
+  CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/chip}"
+  CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/common}"
+  CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/$(ARCH_SUBDIR)}"
+  CFLAGS += -I "${shell cygpath -w $(TOPDIR)/sched}"
+else
+  NUTTX = "$(TOPDIR)/nuttx$(EXEEXT)"
+  CFLAGS += -I$(ARCH_SRCDIR)/chip
+  CFLAGS += -I$(ARCH_SRCDIR)/common
+  CFLAGS += -I$(ARCH_SRCDIR)/$(ARCH_SUBDIR)
+  CFLAGS += -I$(TOPDIR)/sched
+endif
+endif
+
+# The "head" object
+
+HEAD_OBJ = $(HEAD_ASRC:.S=$(OBJEXT))
+STARTUP_OBJS ?= $(HEAD_OBJ)
+
+# Flat build or kernel-mode objects
+
+ASRCS = $(CHIP_ASRCS) $(CMN_ASRCS)
+AOBJS = $(ASRCS:.S=$(OBJEXT))
+
+CSRCS = $(CHIP_CSRCS) $(CMN_CSRCS)
+COBJS = $(CSRCS:.c=$(OBJEXT))
+
+SRCS = $(ASRCS) $(CSRCS)
+OBJS = $(AOBJS) $(COBJS)
+
+# User-mode objects
+
+UASRCS = $(CHIP_UASRCS) $(CMN_UASRCS)
+UAOBJS = $(UASRCS:.S=$(OBJEXT))
+
+UCSRCS = $(CHIP_UCSRCS) $(CMN_UCSRCS)
+UCOBJS = $(UCSRCS:.c=$(OBJEXT))
+
+USRCS = $(UASRCS) $(UCSRCS)
+UOBJS = $(UAOBJS) $(UCOBJS)
+
+KBIN = libkarch$(LIBEXT)
+UBIN = libuarch$(LIBEXT)
+BIN  = libarch$(LIBEXT)
+
+LDFLAGS += $(ARCHSCRIPT)
+
+EXTRA_LIBS ?=
+EXTRA_LIBPATHS ?=
+LINKLIBS ?=
+
+AFLAGS += -I$(TOPDIR)/include
+
+ifeq ($(CONFIG_WINDOWS_NATIVE),y)
+  BOARDMAKE = $(if $(wildcard .\board\Makefile),y,)
+  LIBPATHS += -L"$(TOPDIR)\lib"
+ifeq ($(BOARDMAKE),y)
+  LIBPATHS += -L"$(TOPDIR)\arch\$(CONFIG_ARCH)\src\board"
+endif
+
+else
+  BOARDMAKE = $(if $(wildcard ./board/Makefile),y,)
+
+ifeq ($(WINTOOL),y)
+  LIBPATHS += -L"${shell cygpath -w "$(TOPDIR)/lib"}"
+ifeq ($(BOARDMAKE),y)
+  LIBPATHS += -L"${shell cygpath -w "$(TOPDIR)/arch/$(CONFIG_ARCH)/src/board"}"
+endif
+
+else
+  LIBPATHS += -L"$(TOPDIR)/lib"
+ifeq ($(BOARDMAKE),y)
+  LIBPATHS += -L"$(TOPDIR)/arch/$(CONFIG_ARCH)/src/board"
+endif
+endif
+endif
+
+LDLIBS = $(patsubst %.a,%,$(patsubst lib%,-l%,$(LINKLIBS)))
+ifeq ($(BOARDMAKE),y)
+  LDLIBS += -lboard
+endif
+
+LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}"
+GCC_LIBDIR := ${shell dirname $(LIBGCC)}
+
+VPATH += chip
+VPATH += common
+VPATH += $(ARCH_SUBDIR)
+VPATH += $(CHIP_DIR)
+
+all: $(HEAD_OBJ) $(BIN)
+
+.PHONY: board/libboard$(LIBEXT) 
+
+$(AOBJS) $(UAOBJS) $(HEAD_OBJ): %$(OBJEXT): %.S
+	$(call ASSEMBLE, $<, $@)
+
+$(COBJS) $(UCOBJS): %$(OBJEXT): %.c
+	$(call COMPILE, $<, $@)
+
+$(BIN) $(KBIN): $(OBJS)
+	$(call ARCHIVE, $@, $(OBJS))
+	@$(MAKE) depend 
+
+$(UBIN): $(UOBJS)
+	$(call ARCHIVE, $@, $(UOBJS))
+
+board/libboard$(LIBEXT):
+	$(Q) $(MAKE) -C board TOPDIR="$(TOPDIR)" libboard$(LIBEXT) EXTRADEFINES=$(EXTRADEFINES)
+
+nuttx$(EXEEXT): $(HEAD_OBJ) board/libboard$(LIBEXT)
+	$(Q) echo "LD: nuttx"
+	$(Q) $(LD) --entry=__start $(LDFLAGS) $(LIBPATHS) $(EXTRA_LIBPATHS) \
+		-o $(NUTTX) $(HEAD_OBJ) $(EXTRA_OBJS) \
+		--start-group $(LDLIBS) $(EXTRA_LIBS) $(LIBGCC) --end-group
+ifneq ($(CONFIG_WINDOWS_NATIVE),y)
+	$(Q) $(NM) $(NUTTX) | \
+	grep -v '\(compiled\)\|\(\$(OBJEXT)$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \
+	sort > $(TOPDIR)/System.map
+endif
+
+# This is part of the top-level export target
+# Note that there may not be a head object if layout is handled
+# by the linker configuration.
+
+export_startup: board/libboard$(LIBEXT) $(STARTUP_OBJS)
+ifneq ($(STARTUP_OBJS),)
+	$(Q) if [ -d "$(EXPORT_DIR)/startup" ]; then \
+		cp -f $(STARTUP_OBJS) "$(EXPORT_DIR)/startup/."; \
+	 else \
+		echo "$(EXPORT_DIR)/startup does not exist"; \
+	exit 1; \
+	fi
+endif
+
+# Dependencies
+
+.depend: Makefile $(SRCS)
+ifeq ($(BOARDMAKE),y)
+	$(Q) $(MAKE) -C board TOPDIR="$(TOPDIR)" depend
+endif
+	$(Q) $(MKDEP) $(patsubst %,--dep-path %,$(subst :, ,$(VPATH))) \
+	 "$(CC)" -- $(CFLAGS) -- $(SRCS) > Make.dep
+	$(Q) touch $@
+
+depend: .depend
+
+clean:
+ifeq ($(BOARDMAKE),y)
+	$(Q) $(MAKE) -C board TOPDIR="$(TOPDIR)" clean
+endif
+	$(call DELFILE, $(KBIN))
+	$(call DELFILE, $(UBIN))
+	$(call DELFILE, $(BIN))
+	$(call DELFILE, $(HEAD_OBJ))
+	$(call CLEAN)
+
+distclean: clean
+ifeq ($(BOARDMAKE),y)
+	$(Q) $(MAKE) -C board TOPDIR="$(TOPDIR)" distclean
+endif
+	$(call DELFILE, Make.dep)
+	$(call DELFILE, .depend)
+
+info:
+	@echo $(HEAD_OBJ)
+	@echo $(ASRCS)
+	@echo $(CONFIG_ARCH_CHIP)
+
+#-include Make.dep

arch/risc-v/src/common/up_allocateheap.c

@@ -0,0 +1,88 @@
+/****************************************************************************
+ * arch/risc-v/src/common/up_allocateheap.c
+ *
+ *   Copyright (C) 2010, 2013, 2015 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <debug.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/board.h>
+#include <arch/board/board.h>
+
+#include "up_arch.h"
+#include "up_internal.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_allocate_heap
+ *
+ * Description:
+ *   This function will be called to dynamically set aside the heap region.
+ *
+ *   For the kernel build (CONFIG_BUILD_KERNEL=y) with both kernel- and
+ *   user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function provides the
+ *   size of the unprotected, user-space heap.
+ *
+ *   If a protected kernel-space heap is provided, the kernel heap must be
+ *   allocated (and protected) by an analogous up_allocate_kheap().
+ *
+ ****************************************************************************/
+
+void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
+{
+  board_autoled_on(LED_HEAPALLOCATE);
+  *heap_start = (FAR void *)g_idle_topstack;
+  *heap_size = CONFIG_RAM_END - g_idle_topstack;
+}

arch/risc-v/src/common/up_arch.h

@@ -0,0 +1,70 @@
+/****************************************************************************
+ * arch/risc-v/src/common/up_arch.h
+ *
+ *   Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef ___ARCH_RISCV_SRC_COMMON_UP_ARCH_H
+#define ___ARCH_RISCV_SRC_COMMON_UP_ARCH_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Inline Functions
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+# define getreg8(a)           (*(volatile uint8_t *)(a))
+# define putreg8(v,a)         (*(volatile uint8_t *)(a) = (v))
+# define getreg16(a)          (*(volatile uint16_t *)(a))
+# define putreg16(v,a)        (*(volatile uint16_t *)(a) = (v))
+# define getreg32(a)          (*(volatile uint32_t *)(a))
+# define putreg32(v,a)        (*(volatile uint32_t *)(a) = (v))
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#endif /* __ASSEMBLY__ */
+#endif  /* ___ARCH_ARM_SRC_COMMON_UP_ARCH_H */

arch/risc-v/src/common/up_createstack.c

@@ -0,0 +1,214 @@
+/****************************************************************************
+ * arch/riscv/src/common/up_createstack.c
+ *
+ *   Copyright (C) 2011, 2013, 2015 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <sched.h>
+#include <debug.h>
+
+#include <nuttx/kmalloc.h>
+#include <nuttx/arch.h>
+#include <nuttx/board.h>
+#include <arch/board/board.h>
+
+#include "up_arch.h"
+#include "up_internal.h"
+
+/****************************************************************************
+ * Pre-processor Macros
+ ****************************************************************************/
+
+/* MIPS requires at least a 4-byte stack alignment.  For floating point use,
+ * however, the stack must be aligned to 8-byte addresses.
+ */
+
+#ifdef CONFIG_LIBC_FLOATINGPOINT
+#  define STACK_ALIGNMENT   8
+#else
+#  define STACK_ALIGNMENT   4
+#endif
+
+/* Stack alignment macros */
+
+#define STACK_ALIGN_MASK    (STACK_ALIGNMENT-1)
+#define STACK_ALIGN_DOWN(a) ((a) & ~STACK_ALIGN_MASK)
+#define STACK_ALIGN_UP(a)   (((a) + STACK_ALIGN_MASK) & ~STACK_ALIGN_MASK)
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_create_stack
+ *
+ * Description:
+ *   Allocate a stack for a new thread and setup up stack-related information
+ *   in the TCB.
+ *
+ *   The following TCB fields must be initialized by this function:
+ *
+ *   - adj_stack_size: Stack size after adjustment for hardware, processor,
+ *     etc.  This value is retained only for debug purposes.
+ *   - stack_alloc_ptr: Pointer to allocated stack
+ *   - adj_stack_ptr: Adjusted stack_alloc_ptr for HW.  The initial value of
+ *     the stack pointer.
+ *
+ * Inputs:
+ *   - tcb: The TCB of new task
+ *   - stack_size:  The requested stack size.  At least this much
+ *     must be allocated.
+ *   - ttype:  The thread type.  This may be one of following (defined in
+ *     include/nuttx/sched.h):
+ *
+ *       TCB_FLAG_TTYPE_TASK     Normal user task
+ *       TCB_FLAG_TTYPE_PTHREAD  User pthread
+ *       TCB_FLAG_TTYPE_KERNEL   Kernel thread
+ *
+ *     This thread type is normally available in the flags field of the TCB,
+ *     however, there are certain contexts where the TCB may not be fully
+ *     initialized when up_create_stack is called.
+ *
+ *     If CONFIG_BUILD_KERNEL is defined, then this thread type may affect
+ *     how the stack is allocated.  For example, kernel thread stacks should
+ *     be allocated from protected kernel memory.  Stacks for user tasks and
+ *     threads must come from memory that is accessible to user code.
+ *
+ ****************************************************************************/
+
+int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype)
+{
+  /* Is there already a stack allocated of a different size?  Because of
+   * alignment issues, stack_size might erroneously appear to be of a
+   * different size.  Fortunately, this is not a critical operation.
+   */
+
+  if (tcb->stack_alloc_ptr && tcb->adj_stack_size != stack_size)
+    {
+      /* Yes.. Release the old stack */
+
+      up_release_stack(tcb, ttype);
+    }
+
+  /* Do we need to allocate a new stack? */
+
+  if (!tcb->stack_alloc_ptr)
+    {
+      /* Allocate the stack.  If DEBUG is enabled (but not stack debug),
+       * then create a zeroed stack to make stack dumps easier to trace.
+       */
+
+#if defined(CONFIG_BUILD_KERNEL) && defined(CONFIG_MM_KERNEL_HEAP)
+      /* Use the kernel allocator if this is a kernel thread */
+
+      if (ttype == TCB_FLAG_TTYPE_KERNEL)
+        {
+          tcb->stack_alloc_ptr = (uint32_t *)kmm_malloc(stack_size);
+        }
+      else
+#endif
+        {
+          /* Use the user-space allocator if this is a task or pthread */
+
+          tcb->stack_alloc_ptr = (uint32_t *)kumm_malloc(stack_size);
+        }
+
+#ifdef CONFIG_DEBUG_FEATURES
+      /* Was the allocation successful? */
+
+      if (!tcb->stack_alloc_ptr)
+        {
+          serr("ERROR: Failed to allocate stack, size %d\n", stack_size);
+        }
+#endif
+    }
+
+  /* Did we successfully allocate a stack? */
+
+  if (tcb->stack_alloc_ptr)
+    {
+      size_t top_of_stack;
+      size_t size_of_stack;
+
+      /* Yes.. If stack debug is enabled, then fill the stack with a
+       * recognizable value that we can use later to test for high
+       * water marks.
+       */
+
+#ifdef CONFIG_STACK_COLORATION
+      memset(tcb->stack_alloc_ptr, 0xaa, stack_size);
+#endif
+
+      /* MIPS uses a push-down stack:  the stack grows toward lower
+       * addresses in memory.  The stack pointer register points to the
+       * lowest, valid working address (the "top" of the stack).  Items on
+       * the stack are referenced as positive word offsets from sp.
+       */
+
+      top_of_stack = (uint32_t)tcb->stack_alloc_ptr + stack_size - 4;
+
+      /* The MIPS stack must be aligned at word (4 byte) boundaries; for
+       * floating point use, the stack must be aligned to 8-byte addresses.
+       * If necessary top_of_stack must be rounded down to the next
+       * boundary to meet these alignment requirements.
+       */
+
+      top_of_stack = STACK_ALIGN_DOWN(top_of_stack);
+      size_of_stack = top_of_stack - (uint32_t)tcb->stack_alloc_ptr + 4;
+
+      /* Save the adjusted stack values in the struct tcb_s */
+
+      tcb->adj_stack_ptr  = (FAR uint32_t *)top_of_stack;
+      tcb->adj_stack_size = size_of_stack;
+
+      board_autoled_on(LED_STACKCREATED);
+      return OK;
+    }
+
+   return ERROR;
+}

arch/risc-v/src/common/up_exit.c

@@ -0,0 +1,188 @@
+/****************************************************************************
+ * arch/risc-v/src/common/up_exit.c
+ *
+ *   Copyright (C) 2011, 2013-2014 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sched.h>
+#include <syscall.h>
+#include <assert.h>
+#include <debug.h>
+#include <nuttx/arch.h>
+
+#ifdef CONFIG_DUMP_ON_EXIT
+#include <nuttx/fs/fs.h>
+#endif
+
+#include "task/task.h"
+#include "sched/sched.h"
+#include "group/group.h"
+#include "up_internal.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#ifndef CONFIG_DEBUG_SCHED_INFO
+#  undef CONFIG_DUMP_ON_EXIT
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: _up_dumponexit
+ *
+ * Description:
+ *   Dump the state of all tasks whenever on task exits.  This is debug
+ *   instrumentation that was added to check file-related reference counting
+ *   but could be useful again sometime in the future.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_DUMP_ON_EXIT
+static void _up_dumponexit(FAR struct tcb_s *tcb, FAR void *arg)
+{
+#if CONFIG_NFILE_DESCRIPTORS > 0
+  FAR struct filelist *filelist;
+#if CONFIG_NFILE_STREAMS > 0
+  FAR struct streamlist *streamlist;
+#endif
+  int i;
+#endif
+
+  sinfo("  TCB=%p name=%s pid=%d\n", tcb, tcb->argv[0], tcb->pid);
+  sinfo("    priority=%d state=%d\n", tcb->sched_priority, tcb->task_state);
+
+#if CONFIG_NFILE_DESCRIPTORS > 0
+  filelist = tcb->group->tg_filelist;
+  for (i = 0; i < CONFIG_NFILE_DESCRIPTORS; i++)
+    {
+      struct inode *inode = filelist->fl_files[i].f_inode;
+      if (inode)
+        {
+          sinfo("      fd=%d refcount=%d\n",
+                i, inode->i_crefs);
+        }
+    }
+#endif
+
+#if CONFIG_NFILE_STREAMS > 0
+  streamlist = tcb->group->tg_streamlist;
+  for (i = 0; i < CONFIG_NFILE_STREAMS; i++)
+    {
+      struct file_struct *filep = &streamlist->sl_streams[i];
+      if (filep->fs_fd >= 0)
+        {
+#if CONFIG_STDIO_BUFFER_SIZE > 0
+          sinfo("      fd=%d nbytes=%d\n",
+                filep->fs_fd,
+                filep->fs_bufpos - filep->fs_bufstart);
+#else
+          sinfo("      fd=%d\n", filep->fs_fd);
+#endif
+        }
+    }
+#endif
+}
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: _exit
+ *
+ * Description:
+ *   This function causes the currently executing task to cease
+ *   to exist.  This is a special case of task_delete() where the task to
+ *   be deleted is the currently executing task.  It is more complex because
+ *   a context switch must be perform to the next ready to run task.
+ *
+ ****************************************************************************/
+
+void _exit(int status)
+{
+  struct tcb_s *tcb;
+
+  /* Disable interrupts.  They will be restored when the next
+   * task is started.
+   */
+
+  (void)up_irq_save();
+
+  sinfo("TCB=%p exiting\n", this_task());
+
+#ifdef CONFIG_DUMP_ON_EXIT
+  sinfo("Other tasks:\n");
+  sched_foreach(_up_dumponexit, NULL);
+#endif
+
+  /* Destroy the task at the head of the ready to run list. */
+
+  (void)task_exit();
+
+  /* Now, perform the context switch to the new ready-to-run task at the
+   * head of the list.
+   */
+
+  tcb = this_task();
+
+#ifdef CONFIG_ARCH_ADDRENV
+  /* Make sure that the address environment for the previously running
+   * task is closed down gracefully (data caches dump, MMU flushed) and
+   * set up the address environment for the new thread at the head of
+   * the ready-to-run list.
+   */
+
+  (void)group_addrenv(tcb);
+#endif
+
+  /* Then switch contexts */
+
+  up_fullcontextrestore(tcb->xcp.regs);
+
+  /* up_fullcontextrestore() should not return but could if the software
+   * interrupts are disabled.
+   */
+
+  PANIC();
+}
+

arch/risc-v/src/common/up_idle.c

@@ -0,0 +1,95 @@
+/****************************************************************************
+ *  arch/risc-v/src/common/up_idle.c
+ *
+ *   Copyright (C) 2011-2012, 2016 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+
+#include "up_internal.h"
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_idle
+ *
+ * Description:
+ *   up_idle() is the logic that will be executed when their is no other
+ *   ready-to-run task.  This is processor idle time and will continue until
+ *   some interrupt occurs to cause a context switch from the idle task.
+ *
+ *   Processing in this state may be processor-specific. e.g., this is where
+ *   power management operations might be performed.
+ *
+ ****************************************************************************/
+
+void up_idle(void)
+{
+#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS)
+  /* If the system is idle and there are no timer interrupts, then process
+   * "fake" timer interrupts. Hopefully, something will wake up.
+   */
+
+  sched_process_timer();
+#else
+
+  /* This would be an appropriate place to put some MCU-specific logic to
+   * sleep in a reduced power mode until an interrupt occurs to save power
+   */
+
+  /* This is a kludge that I still don't understand.  The call to kmm_trysemaphore()
+   * in the os_start.c IDLE loop seems necessary for the good health of the IDLE
+   * loop.  When the work queue is enabled, this logic is removed from the IDLE
+   * loop and it appears that we are somehow left idling with interrupts non-
+   * functional. The following should be no-op, it just disables then re-enables
+   * interrupts.  But it fixes the problem and will stay here until I understand
+   * the problem/fix better.
+   *
+   * And no, the contents of the CP0 status register are not incorrect.  But for
+   * some reason the status register needs to be re-written again on this thread
+   * for it to take effect.  This might be a PIC32-only issue?
+   */
+
+#ifdef CONFIG_SCHED_WORKQUEUE
+  irqstate_t flags = enter_critical_section();
+  leave_critical_section(flags);
+#endif
+#endif
+}

arch/risc-v/src/common/up_initialize.c

@@ -0,0 +1,203 @@
+/****************************************************************************
+ * arch/risc-v/src/common/up_initialize.c
+ *
+ *   Copyright (C) 2007-2010, 2012-2015 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <debug.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/board.h>
+
+#include <arch/board/board.h>
+
+#include "up_arch.h"
+#include "up_internal.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_calibratedelay
+ *
+ * Description:
+ *   Delay loops are provided for short timing loops.  This function, if
+ *   enabled, will just wait for 100 seconds.  Using a stopwatch, you can
+ *   can then determine if the timing loops are properly calibrated.
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_ARCH_CALIBRATION) && defined(CONFIG_DEBUG)
+static void up_calibratedelay(void)
+{
+  int i;
+  lldbg("Beginning 100s delay\n");
+  for (i = 0; i < 100; i++)
+    {
+      up_mdelay(1000);
+    }
+  lldbg("End 100s delay\n");
+}
+#else
+# define up_calibratedelay()
+#endif
+
+/****************************************************************************
+ * Name: up_color_intstack
+ *
+ * Description:
+ *   Set the interrupt stack to a value so that later we can determine how
+ *   much stack space was used by interrupt handling logic
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3
+static inline void up_color_intstack(void)
+{
+  uint32_t *ptr = (uint32_t *)&g_intstackalloc;
+  ssize_t size;
+
+  for (size = (CONFIG_ARCH_INTERRUPTSTACK & ~3);
+       size > 0;
+       size -= sizeof(uint32_t))
+    {
+      *ptr++ = INTSTACK_COLOR;
+    }
+}
+#else
+#  define up_color_intstack()
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_initialize
+ *
+ * Description:
+ *   up_initialize will be called once during OS initialization after the
+ *   basic OS services have been initialized.  The architecture specific
+ *   details of initializing the OS will be handled here.  Such things as
+ *   setting up interrupt service routines, starting the clock, and
+ *   registering device drivers are some of the things that are different
+ *   for each processor and hardware platform.
+ *
+ *   up_initialize is called after the OS initialized but before the user
+ *   initialization logic has been started and before the libraries have
+ *   been initialized.  OS services and driver services are available.
+ *
+ ****************************************************************************/
+
+void up_initialize(void)
+{
+  /* Calibrate the timing loop */
+
+  up_calibratedelay();
+
+  /* Colorize the interrupt stack */
+
+  up_color_intstack();
+
+  /* Add any extra memory fragments to the memory manager */
+
+  up_addregion();
+
+  /* Initialize the interrupt subsystem */
+
+  up_irqinitialize();
+
+  /* Initialize the system timer interrupt */
+
+#if !defined(CONFIG_SUPPRESS_INTERRUPTS) && !defined(CONFIG_SUPPRESS_TIMER_INTS) && \
+    !defined(CONFIG_SYSTEMTICK_EXTCLK)
+  up_timer_initialize();
+#endif
+
+  /* Register devices */
+
+#if CONFIG_NFILE_DESCRIPTORS > 0
+
+#if defined(CONFIG_DEV_NULL)
+  devnull_register();   /* Standard /dev/null */
+#endif
+
+#if defined(CONFIG_DEV_ZERO)
+  devzero_register();   /* Standard /dev/zero */
+#endif
+
+#endif /* CONFIG_NFILE_DESCRIPTORS */
+
+  /* Initialize the serial device driver */
+
+#ifdef USE_SERIALDRIVER
+  up_serialinit();
+#endif
+
+  /* Initialize the console device driver (if it is other than the standard
+   * serial driver).
+   */
+
+#if defined(CONFIG_DEV_LOWCONSOLE)
+  lowconsole_init();
+#elif defined(CONFIG_SYSLOG_CONSOLE)
+  syslog_console_init();
+#elif defined(CONFIG_RAMLOG_CONSOLE)
+  ramlog_consoleinit();
+#endif
+
+  /* Initialize the system logging device */
+
+#ifdef CONFIG_SYSLOG_CHAR
+  syslog_initialize();
+#endif
+#ifdef CONFIG_RAMLOG_SYSLOG
+  ramlog_sysloginit();
+#endif
+
+  board_autoled_on(LED_IRQSENABLED);
+}

arch/risc-v/src/common/up_internal.h

@@ -0,0 +1,160 @@
+/****************************************************************************
+ * arch/risc-v/src/common/up_internal.h
+ *
+ *   Copyright (C) 2007-2015 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ *   Modified for RISC-V:
+ *
+ *   Copyright (C) 2016 Ken Pettit. All rights reserved.
+ *   Author: Ken Pettit <pettitkd@gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_SRC_COMMON_UP_INTERNAL_H
+#define __ARCH_RISCV_SRC_COMMON_UP_INTERNAL_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+#  include <nuttx/compiler.h>
+#  include <sys/types.h>
+#  include <stdint.h>
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* This is the value used to mark the stack for subsequent stack monitoring
+ * logic.
+ */
+
+#define STACK_COLOR    0xdeadbeef
+#define INTSTACK_COLOR 0xdeadbeef
+#define HEAP_COLOR     'h'
+
+/* In the RISC_V model, the state is copied from the stack to the TCB, but
+ * only a referenced is passed to get the state from the TCB.
+ */
+
+#define up_savestate(regs)    up_copystate(regs, (uint32_t*)g_current_regs)
+#define up_restorestate(regs) (g_current_regs = regs)
+
+/* Determine which (if any) console driver to use.  If a console is enabled
+ * and no other console device is specified, then a serial console is
+ * assumed.
+ */
+
+#if !defined(CONFIG_DEV_CONSOLE) || CONFIG_NFILE_DESCRIPTORS <= 0
+#  undef  USE_SERIALDRIVER
+#  undef  USE_EARLYSERIALINIT
+#  undef  CONFIG_DEV_LOWCONSOLE
+#  undef  CONFIG_RAMLOG_CONSOLE
+#else
+#  if defined(CONFIG_RAMLOG_CONSOLE)
+#    undef  USE_SERIALDRIVER
+#    undef  USE_EARLYSERIALINIT
+#    undef  CONFIG_DEV_LOWCONSOLE
+#  elif defined(CONFIG_DEV_LOWCONSOLE)
+#    undef  USE_SERIALDRIVER
+#    undef  USE_EARLYSERIALINIT
+#  else
+#    define USE_SERIALDRIVER 1
+#    define USE_EARLYSERIALINIT 1
+#  endif
+#endif
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Variables
+ ****************************************************************************/
+
+extern volatile uint32_t *g_current_regs;
+
+extern uint32_t g_idle_topstack;
+
+/****************************************************************************
+ * Inline Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/* Low level initialization provided by board-level logic ******************/
+
+void up_boot(void);
+
+/* Memory allocation ********************************************************/
+
+void up_addregion(void);
+void up_allocat_eheap(FAR void **heap_start, size_t *heap_size);
+
+/* IRQ initialization *******************************************************/
+
+void up_irqinitialize(void);
+void up_copystate(uint32_t *dest, uint32_t *src);
+void up_dumpstate(void);
+void up_sigdeliver(void);
+int up_swint(int irq, FAR void *context);
+uint32_t up_get_newintctx(void);
+
+/* System timer *************************************************************/
+
+void up_timer_initialize(void);
+int  up_timerisr(int irq, void *context);
+
+/* Low level serial output **************************************************/
+
+void up_lowputc(char ch);
+void up_puts(const char *str);
+void up_lowputs(const char *str);
+
+/* The OS start routine    **************************************************/
+
+void os_start(void);
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ARCH_RISCV_SRC_COMMON_UP_INTERNAL_H */

arch/risc-v/src/common/up_interruptcontext.c

@@ -0,0 +1,70 @@
+/****************************************************************************
+ *  arch/risc-v/src/common/up_interruptcontext.c
+ *
+ *   Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdbool.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+
+#include "up_internal.h"
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_interrupt_context
+ *
+ * Description: Return true is we are currently executing in
+ * the interrupt handler context.
+ ****************************************************************************/
+
+bool up_interrupt_context(void)
+{
+   return g_current_regs != NULL;
+}

arch/risc-v/src/common/up_releasestack.c

@@ -0,0 +1,122 @@
+/****************************************************************************
+ *  arch/risc-v/src/common/up_releasestack.c
+ *
+ *   Copyright (C) 2011, 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sched.h>
+#include <debug.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/kmalloc.h>
+
+#include "up_internal.h"
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_release_stack
+ *
+ * Description:
+ *   A task has been stopped. Free all stack related resources retained in
+ *   the defunct TCB.
+ *
+ * Input Parmeters
+ *   - dtcb:  The TCB containing information about the stack to be released
+ *   - ttype:  The thread type.  This may be one of following (defined in
+ *     include/nuttx/sched.h):
+ *
+ *       TCB_FLAG_TTYPE_TASK     Normal user task
+ *       TCB_FLAG_TTYPE_PTHREAD  User pthread
+ *       TCB_FLAG_TTYPE_KERNEL   Kernel thread
+ *
+ *     This thread type is normally available in the flags field of the TCB,
+ *     however, there are certain error recovery contexts where the TCB may
+ *     not be fully initialized when up_release_stack is called.
+ *
+ *     If CONFIG_BUILD_KERNEL is defined, then this thread type may affect
+ *     how the stack is freed.  For example, kernel thread stacks may have
+ *     been allocated from protected kernel memory.  Stacks for user tasks
+ *     and threads must have come from memory that is accessible to user
+ *     code.
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void up_release_stack(FAR struct tcb_s *dtcb, uint8_t ttype)
+{
+  /* Is there a stack allocated? */
+
+  if (dtcb->stack_alloc_ptr)
+    {
+#if defined(CONFIG_BUILD_KERNEL) && defined(CONFIG_MM_KERNEL_HEAP)
+      /* Use the kernel allocator if this is a kernel thread */
+
+      if (ttype == TCB_FLAG_TTYPE_KERNEL)
+        {
+          sched_kfree(dtcb->stack_alloc_ptr);
+        }
+      else
+#endif
+        {
+          /* Use the user-space allocator if this is a task or pthread */
+
+          sched_ufree(dtcb->stack_alloc_ptr);
+        }
+
+      /* Mark the stack freed */
+
+      dtcb->stack_alloc_ptr = NULL;
+    }
+
+  /* The size of the allocated stack is now zero */
+
+  dtcb->adj_stack_size = 0;
+}

arch/risc-v/src/common/up_stackframe.c

@@ -0,0 +1,143 @@
+/****************************************************************************
+ * arch/risc-v/src/common/up_stackframe.c
+ *
+ *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <sched.h>
+#include <debug.h>
+
+#include <nuttx/arch.h>
+
+#include "up_internal.h"
+
+/****************************************************************************
+ * Pre-processor Macros
+ ****************************************************************************/
+/* MIPS requires at least a 4-byte stack alignment.  For floating point use,
+ * however, the stack must be aligned to 8-byte addresses.
+ */
+
+#ifdef CONFIG_LIBC_FLOATINGPOINT
+#  define STACK_ALIGNMENT   8
+#else
+#  define STACK_ALIGNMENT   4
+#endif
+
+/* Stack alignment macros */
+
+#define STACK_ALIGN_MASK    (STACK_ALIGNMENT-1)
+#define STACK_ALIGN_DOWN(a) ((a) & ~STACK_ALIGN_MASK)
+#define STACK_ALIGN_UP(a)   (((a) + STACK_ALIGN_MASK) & ~STACK_ALIGN_MASK)
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_stack_frame
+ *
+ * Description:
+ *   Allocate a stack frame in the TCB's stack to hold thread-specific data.
+ *   This function may be called anytime after up_create_stack() or
+ *   up_use_stack() have been called but before the task has been started.
+ *
+ *   Thread data may be kept in the stack (instead of in the TCB) if it is
+ *   accessed by the user code directly.  This includes such things as
+ *   argv[].  The stack memory is guaranteed to be in the same protection
+ *   domain as the thread.
+ *
+ *   The following TCB fields will be re-initialized:
+ *
+ *   - adj_stack_size: Stack size after removal of the stack frame from
+ *     the stack
+ *   - adj_stack_ptr: Adjusted initial stack pointer after the frame has
+ *     been removed from the stack.  This will still be the initial value
+ *     of the stack pointer when the task is started.
+ *
+ * Inputs:
+ *   - tcb:  The TCB of new task
+ *   - frame_size:  The size of the stack frame to allocate.
+ *
+ *  Returned Value:
+ *   - A pointer to bottom of the allocated stack frame.  NULL will be
+ *     returned on any failures.  The alignment of the returned value is
+ *     the same as the alignment of the stack itself.
+ *
+ ****************************************************************************/
+
+FAR void *up_stack_frame(FAR struct tcb_s *tcb, size_t frame_size)
+{
+  uintptr_t topaddr;
+
+  /* Align the frame_size */
+
+  frame_size = STACK_ALIGN_UP(frame_size);
+
+  /* Is there already a stack allocated? Is it big enough? */
+
+  if (!tcb->stack_alloc_ptr || tcb->adj_stack_size <= frame_size)
+    {
+      return NULL;
+    }
+
+  /* Save the adjusted stack values in the struct tcb_s */
+
+  topaddr               = (uintptr_t)tcb->adj_stack_ptr - frame_size;
+  tcb->adj_stack_ptr    = (FAR void *)topaddr;
+  tcb->adj_stack_size  -= frame_size;
+
+  /* Reset the initial stack pointer */
+
+  tcb->xcp.regs[REG_SP] = (uint32_t)tcb->adj_stack_ptr;
+
+  /* And return the pointer to the allocated region */
+
+  return (FAR void *)(topaddr + sizeof(uint32_t));
+}
+

arch/risc-v/src/common/up_usestack.c

@@ -0,0 +1,152 @@
+/****************************************************************************
+ * arch/risc-v/src/common/up_usestack.c
+ *
+ *   Copyright (C) 2011, 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <sched.h>
+#include <debug.h>
+
+#include <nuttx/kmalloc.h>
+#include <nuttx/arch.h>
+
+#include "up_internal.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* MIPS requires at least a 4-byte stack alignment.  For floating point use,
+ * however, the stack must be aligned to 8-byte addresses.
+ */
+
+#ifdef CONFIG_LIBC_FLOATINGPOINT
+#  define STACK_ALIGNMENT   8
+#else
+#  define STACK_ALIGNMENT   4
+#endif
+
+/* Stack alignment macros */
+
+#define STACK_ALIGN_MASK    (STACK_ALIGNMENT-1)
+#define STACK_ALIGN_DOWN(a) ((a) & ~STACK_ALIGN_MASK)
+#define STACK_ALIGN_UP(a)   (((a) + STACK_ALIGN_MASK) & ~STACK_ALIGN_MASK)
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_use_stack
+ *
+ * Description:
+ *   Setup up stack-related information in the TCB using pre-allocated stack
+ *   memory.  This function is called only from task_init() when a task or
+ *   kernel thread is started (never for pthreads).
+ *
+ *   The following TCB fields must be initialized:
+ *
+ *   - adj_stack_size: Stack size after adjustment for hardware,
+ *     processor, etc.  This value is retained only for debug
+ *     purposes.
+ *   - stack_alloc_ptr: Pointer to allocated stack
+ *   - adj_stack_ptr: Adjusted stack_alloc_ptr for HW.  The
+ *     initial value of the stack pointer.
+ *
+ * Inputs:
+ *   - tcb: The TCB of new task
+ *   - stack_size:  The allocated stack size.
+ *
+ *   NOTE:  Unlike up_stack_create() and up_stack_release, this function
+ *   does not require the task type (ttype) parameter.  The TCB flags will
+ *   always be set to provide the task type to up_use_stack() if it needs
+ *   that information.
+ *
+ ****************************************************************************/
+
+int up_use_stack(struct tcb_s *tcb, void *stack, size_t stack_size)
+{
+  size_t top_of_stack;
+  size_t size_of_stack;
+
+  /* Is there already a stack allocated? */
+
+  if (tcb->stack_alloc_ptr)
+    {
+      /* Yes.. Release the old stack allocation */
+
+      up_release_stack(tcb, tcb->flags & TCB_FLAG_TTYPE_MASK);
+    }
+
+  /* Save the new stack allocation */
+
+  tcb->stack_alloc_ptr = stack;
+
+  /* MIPS uses a push-down stack:  the stack grows toward loweraddresses in
+   * memory.  The stack pointer register, points to the lowest, valid work
+   * address (the "top" of the stack).  Items on the stack are referenced
+   * as positive word offsets from sp.
+   */
+
+  top_of_stack = (uint32_t)tcb->stack_alloc_ptr + stack_size - 4;
+
+  /* The MIPS stack must be aligned at word (4 byte) or double word (8 byte)
+   * boundaries. If necessary top_of_stack must be rounded down to the
+   * next boundary
+   */
+
+  top_of_stack = STACK_ALIGN_DOWN(top_of_stack);
+  size_of_stack = top_of_stack - (uint32_t)tcb->stack_alloc_ptr + 4;
+
+  /* Save the adjusted stack values in the struct tcb_s */
+
+  tcb->adj_stack_ptr  = (uint32_t *)top_of_stack;
+  tcb->adj_stack_size = size_of_stack;
+
+  return OK;
+}

arch/risc-v/src/nr5m100/Kconfig

@@ -0,0 +1,121 @@
+#
+# For a description of the syntax of this configuration file,
+# see the file kconfig-language.txt in the NuttX tools repository.
+#
+
+comment "NanoRisc5 Configuration Options"
+
+choice
+	prompt "NR5 Chip Selection"
+	default ARCH_CHIP_NR5M100
+	depends on ARCH_CHIP_NR5
+
+config ARCH_CHIP_NR5M100
+	bool "NR5M100"
+	select NR5_HAVE_UART1
+	select NR5_HAVE_GPIOA
+	select NR5_HAVE_GPIOB
+	select NR5_HAVE_GPIOC
+	---help---
+		NanoRisc5, RV32IM 128K PROGRAM SRAM, 128K DATA SRAM
+
+endchoice
+
+config NR5_NR5M100
+	bool
+	default y
+	select NR5_NR5M1XX
+	select NR5_HAVE_UART1
+	select NR5_HAVE_TIMER1
+
+config NR5_NR5M1XX
+	bool
+	default n
+
+config NR5_EPIC
+	bool "Has Embedded Priority Interrupt Controller (EPIC)"
+	---help---
+		NanoRisc5 core can have either single vector interrupts or priority
+		encoded interrupts.  Selects if the core was compiled with EPIC.
+
+menu "NR5 Peripheral Support"
+
+# These "hidden" settings determine is a peripheral option is available for the
+# selection MCU
+
+config NR5_HAVE_UART1
+	bool
+	default n
+	select UART1_SERIALDRIVER
+	select ARCH_HAVE_SERIAL_TERMIOS
+
+config NR5_HAVE_TIMER1
+	bool
+	default n
+
+config NR5_HAVE_TIM2
+	bool
+	default n
+
+config NR5_HAVE_I2C1
+	bool
+	default n
+
+config NR5_HAVE_SPI1
+	bool
+	default n
+
+# These are the peripheral selections proper
+
+config NR5_I2C1
+	bool "I2C1"
+	default n
+	select NR5_I2C
+
+config NR5_SPI1
+	bool "SPI1"
+	default n
+	select SPI
+	select NR5_SPI
+
+config NR5_TIMER1
+	bool "TIMER1"
+	default n
+	depends on NR5_HAVE_TIMER1
+
+config NR5_TIMER2
+	bool "TIMER2"
+	default n
+
+config NR5_UART1
+	bool "UART1"
+	default n
+	select ARCH_HAVE_UART1
+	select ARCH_HAVE_SERIAL_TERMIOS
+	select NR5_UART
+
+endmenu
+
+config NR5_SPI
+	bool
+
+config NR5_I2C
+	bool
+
+config NR5_UART
+	bool
+
+config NR5_UART_RX_BUF_SIZE
+	int "UART RX Bufer size"
+	default 64
+	depends on NR5_UART
+	---help---
+		Size of RX buffers for NR5 UARTs
+
+config NR5_UART_TX_BUF_SIZE
+	int "UART TX Bufer size"
+	default 64
+	depends on NR5_UART
+	---help---
+		Size of TX buffers for NR5 UARTs
+

arch/risc-v/src/nr5m100/Make.defs

@@ -0,0 +1,74 @@
+############################################################################
+# arch/risc-v/src/nr5m100/Make.defs
+#
+#   Copyright (C) 2016 Ken Pettit. All rights reserved.
+#   Author: Ken Pettit <pettitkd@gmail.com>
+#
+# # Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+# Specify our HEAD assembly file.  This will be linked as
+# the first object file, so it will appear at address 0
+HEAD_ASRC = nr5_vectors.S
+
+# Specify our general Assembly files
+CHIP_ASRCS = nr5_head.S nr5_csr.S up_syscall.S
+
+# If we are compiling the NELIB library, then specify it
+# in AFLAGS so we can change up our startup behavior
+ifeq ($(CONFIG_LIB_NEWLIB),y)
+AFLAGS += -DCONFIG_LIB_NEWLIB
+endif
+
+# Override the arch to enable hardware MUL during assembly.
+# This is to support our hardware mul test.  For that test,
+# we have to disable hardware mul for C code so the soft 
+# math libs will be used to compare software mul vs hw mul.
+# But hw mul must be enabled to compile the .S file, or we
+# will get an illegal instruction error.
+ASARCHCPUFLAGS += -march=RV32IMXcustom
+
+# Specify C code within the common directory to be included
+CMN_CSRCS  += up_initialize.c up_swint.c
+CMN_CSRCS  += up_allocateheap.c up_createstack.c up_dumpstate.c up_exit.c up_idle.c
+CMN_CSRCS  += up_assert.c up_blocktask.c up_copystate.c up_initialstate.c
+CMN_CSRCS  += up_interruptcontext.c up_releasepending.c up_reprioritizertr.c
+CMN_CSRCS  += up_releasestack.c up_stackframe.c up_schedulesigaction.c up_sigdeliver.c
+CMN_CSRCS  += up_unblocktask.c up_usestack.c
+
+ifeq ($(CONFIG_ARCH_HAVE_VFORK),y)
+CMN_CSRCS  += up_vfork.c
+endif
+
+# Specify our C code within this directory to be included
+CHIP_CSRCS  = nr5_init.c nr5_arch.c
+CHIP_CSRCS += nr5_lowputc.c nr5_allocateheap.c nr5_serial.c
+CHIP_CSRCS += nr5_timerisr.c nr5_irq.c nr5_irq_dispatch.c
+
+ifeq ($(CONFIG_TIMER),y)
+CHIP_CSRCS += nr5_tim_lowerhalf.c
+endif
+

arch/risc-v/src/nr5m100/chip.h

@@ -0,0 +1,67 @@
+/************************************************************************************
+ * arch/risc-v/src/nr5m100/chip.h
+ *
+ *   Copyright (C) 2016 Ken Pettit. All rights reserved.
+ *   Author: Ken Pettit <pettitkd@gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_RISCV_SRC_NR5M100_CHIP_H
+#define __ARCH_RISCV_SRC_NR5M100_CHIP_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/* If the common RV32IM vector handling logic is used, then include the
+ * required vector definitions as well.
+ */
+
+#ifdef CONFIG_RV32IM_CMNVECTOR
+#  if defined(CONFIG_NR5_NR5M1XX)
+#    include "chip/nr5m1xx_vectors.h"
+#  else
+#    error "No vector file for this NanoRisc5 family"
+#  endif
+#endif
+
+/* Include the chip memory map. */
+
+#include "nr5_memorymap.h"
+
+/* Include our custom access routines for ISR masking, priority */
+
+#include "nr5_csr.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+#endif /* __ARCH_RISCV_SRC_NR5M100_CHIP_H */
+

arch/risc-v/src/nr5m100/chip/nr5m1xx_epic.h

@@ -0,0 +1,41 @@
+/************************************************************************************
+ * arch/risc-v/src/nr5m100/chip/nr5_epic.h
+ *
+ *   Copyright (C) 2016 Ken Pettit. All rights reserved.
+ *   Author: Ken Pettit <pettitkd@gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef ARCH_RISCV_SRC_NR5M100_CHIP_NR5M1XX_EPIC_H
+#define ARCH_RISCV_SRC_NR5M100_CHIP_NR5M1XX_EPIC_H
+
+#define NR5_EPIC_PRI1_REG        0x7E1
+#define NR5_EPIC_PRI2_REG        0x7E2
+#define NR5_EPIC_PRI3_REG        0x7E3
+#define NR5_EPIC_STAT_REG        0x7E4
+
+#endif  /* _ARCH_RISCV_SRC_NR5M100_CHIP_NR5M1XX_EPIC_H */

arch/risc-v/src/nr5m100/chip/nr5m1xx_memorymap.h

@@ -0,0 +1,57 @@
+/************************************************************************************
+ * arch/risc-v/src/nr5m100/chip/nr5m1xx_memorymap.h
+ *
+ *   Copyright (C) 2016 Ken Pettit. All rights reserved.
+ *   Author: Ken Pettit <pettitkd@gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_RISCV_SRC_NR5M100_CHIP_NR5M1XX_MEMORYMAP_H
+#define __ARCH_RISCV_SRC_NR5M100_CHIP_NR5M1XX_MEMORYMAP_H
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* BOOT ROM, SRAM, PERIPHERALS ******************************************************/
+
+#define STM32_CODE_BASE     0x00000000      /* 0x00000000-0x1fffffff: 512Mb code block */
+#define STM32_SRAM_BASE     0x20000000      /* 0x20000000 - 384Kb SRAM */
+#define STM32_PERIPH_BASE   0x40000000      /* 0x40000000-0x4fffffff: Peripheral block */
+
+/* Register Base Address ************************************************************/
+
+#define NR5_UART1_BASE      0x40000000      /* 0x40000000 - 0x40000fff: UART0 */
+#define NR5_GPIO1_BASE      0x40001000      /* 0x40001000 - 0x40001fff: GPIO1 */
+#define NR5_GPIO2_BASE      0x40002000      /* 0x40002000 - 0x40002fff: GPIO2 */
+#define NR5_GPIO3_BASE      0x40003000      /* 0x40003000 - 0x40003fff: GPIO3 */
+#define NR5_TIMER1_BASE     0x40004000      /* 0x40004000 - 0x40004fff: TIMER0 timer */
+#define NR5_TIMER2_BASE     0x40005000      /* 0x40005000 - 0x40005fff: TIMER1 timer */
+#define NR5_EXTMEM_BASE     0x40006000      /* 0x40006000 - 0x40006fff: EXTMEM Controller*/
+
+#endif /* __ARCH_RISCV_SRC_NR5M100_CHIP_NR5M1XX_MEMORYMAP_H */
+

arch/risc-v/src/nr5m100/chip/nr5m1xx_timer.h

@@ -0,0 +1,190 @@
+/************************************************************************************
+ * arch/risc-v/src/nr5m100/chip/nr5_timer.h
+ *
+ *   Copyright (C) 2016 Ken Pettit. All rights reserved.
+ *   Author: Ken Pettit <pettitkd@gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef ARCH_RISCV_SRC_NR5M100_CHIP_NR5M1XX_TIMERA_H
+#define ARCH_RISCV_SRC_NR5M100_CHIP_NR5M1XX_TIMERA_H
+
+#include "nr5m1xx_memorymap.h"
+
+/* The timers used in the NR5M100 are functionally equivalent to
+ * Timer A in the MSP430.  The hardware peripheral in the FPGA uses the BSD
+ * licensed RTL code from the OpenMSP430 project on opencores.org.
+ */
+
+/* TimerA offet definitions */
+
+#define NR5_TIMERA_TACTL_OFFSET           0x00
+#define NR5_TIMERA_TAR_OFFSET             0x04
+#define NR5_TIMERA_TACCTL0_OFFSET         0x08
+#define NR5_TIMERA_TACCR0_OFFSET          0x0C
+#define NR5_TIMERA_TACCTL1_OFFSET         0x10
+#define NR5_TIMERA_TACCR1_OFFSET          0x14
+#define NR5_TIMERA_TACCTL2_OFFSET         0x18
+#define NR5_TIMERA_TACCR2_OFFSET          0x1C
+#define NR5_TIMERA_TAIV_OFFSET            0x20
+
+/* Timer 1 address definitions */
+
+#ifdef CONFIG_NR5_TIMER1 
+#define NR5_TIMER1_TACTL_OFFSET           (NR5_TIMER1_BASE+NR5_TIMERA_TACTL_OFFSET)
+#define NR5_TIMER1_TAR_OFFSET             (NR5_TIMER1_BASE+NR5_TIMERA_TAR_OFFSET)
+#define NR5_TIMER1_TACCTL0_OFFSET         (NR5_TIMER1_BASE+NR5_TIMERA_TACCTL0_OFFSET)
+#define NR5_TIMER1_TACCR0_OFFSET          (NR5_TIMER1_BASE+NR5_TIMERA_TACCR0_OFFSET)
+#define NR5_TIMER1_TACCTL1_OFFSET         (NR5_TIMER1_BASE+NR5_TIMERA_TACCTL1_OFFSET)
+#define NR5_TIMER1_TACCR1_OFFSET          (NR5_TIMER1_BASE+NR5_TIMERA_TACCR1_OFFSET)
+#define NR5_TIMER1_TACCTL2_OFFSET         (NR5_TIMER1_BASE+NR5_TIMERA_TACCTL2_OFFSET)
+#define NR5_TIMER1_TACCR2_OFFSET          (NR5_TIMER1_BASE+NR5_TIMERA_TACCR2_OFFSET)
+#define NR5_TIMER1_TAIV_OFFSET            (NR5_TIMER1_BASE+NR5_TIMERA_TAIV_OFFSET)
+#endif
+
+/* Timer 2 address definitions */
+
+#ifdef CONFIG_NR5_TIMER2 
+#define NR5_TIMER2_TACTL_OFFSET           (NR5_TIMER2_BASE+NR5_TIMERA_TACTL_OFFSET)
+#define NR5_TIMER2_TAR_OFFSET             (NR5_TIMER2_BASE+NR5_TIMERA_TAR_OFFSET)
+#define NR5_TIMER2_TACCTL0_OFFSET         (NR5_TIMER2_BASE+NR5_TIMERA_TACCTL0_OFFSET)
+#define NR5_TIMER2_TACCR0_OFFSET          (NR5_TIMER2_BASE+NR5_TIMERA_TACCR0_OFFSET)
+#define NR5_TIMER2_TACCTL1_OFFSET         (NR5_TIMER2_BASE+NR5_TIMERA_TACCTL1_OFFSET)
+#define NR5_TIMER2_TACCR1_OFFSET          (NR5_TIMER2_BASE+NR5_TIMERA_TACCR1_OFFSET)
+#define NR5_TIMER2_TACCTL2_OFFSET         (NR5_TIMER2_BASE+NR5_TIMERA_TACCTL2_OFFSET)
+#define NR5_TIMER2_TACCR2_OFFSET          (NR5_TIMER2_BASE+NR5_TIMERA_TACCR2_OFFSET)
+#define NR5_TIMER2_TAIV_OFFSET            (NR5_TIMER2_BASE+NR5_TIMERA_TAIV_OFFSET)
+#endif
+
+/* Timer 3 address definitions */
+
+#ifdef CONFIG_NR5_TIMER3 
+#define NR5_TIMER3_TACTL_OFFSET           (NR5_TIMER3_BASE+NR5_TIMERA_TACTL_OFFSET)
+#define NR5_TIMER3_TAR_OFFSET             (NR5_TIMER3_BASE+NR5_TIMERA_TAR_OFFSET)
+#define NR5_TIMER3_TACCTL0_OFFSET         (NR5_TIMER3_BASE+NR5_TIMERA_TACCTL0_OFFSET)
+#define NR5_TIMER3_TACCR0_OFFSET          (NR5_TIMER3_BASE+NR5_TIMERA_TACCR0_OFFSET)
+#define NR5_TIMER3_TACCTL1_OFFSET         (NR5_TIMER3_BASE+NR5_TIMERA_TACCTL1_OFFSET)
+#define NR5_TIMER3_TACCR1_OFFSET          (NR5_TIMER3_BASE+NR5_TIMERA_TACCR1_OFFSET)
+#define NR5_TIMER3_TACCTL2_OFFSET         (NR5_TIMER3_BASE+NR5_TIMERA_TACCTL2_OFFSET)
+#define NR5_TIMER3_TACCR2_OFFSET          (NR5_TIMER3_BASE+NR5_TIMERA_TACCR2_OFFSET)
+#define NR5_TIMER3_TAIV_OFFSET            (NR5_TIMER3_BASE+NR5_TIMERA_TAIV_OFFSET)
+#endif
+
+/* Timer 4 address definitions */
+
+#ifdef CONFIG_NR5_TIMER4 
+#define NR5_TIMER4_TACTL_OFFSET           (NR5_TIMER4_BASE+NR5_TIMERA_TACTL_OFFSET)
+#define NR5_TIMER4_TAR_OFFSET             (NR5_TIMER4_BASE+NR5_TIMERA_TAR_OFFSET)
+#define NR5_TIMER4_TACCTL0_OFFSET         (NR5_TIMER4_BASE+NR5_TIMERA_TACCTL0_OFFSET)
+#define NR5_TIMER4_TACCR0_OFFSET          (NR5_TIMER4_BASE+NR5_TIMERA_TACCR0_OFFSET)
+#define NR5_TIMER4_TACCTL1_OFFSET         (NR5_TIMER4_BASE+NR5_TIMERA_TACCTL1_OFFSET)
+#define NR5_TIMER4_TACCR1_OFFSET          (NR5_TIMER4_BASE+NR5_TIMERA_TACCR1_OFFSET)
+#define NR5_TIMER4_TACCTL2_OFFSET         (NR5_TIMER4_BASE+NR5_TIMERA_TACCTL2_OFFSET)
+#define NR5_TIMER4_TACCR2_OFFSET          (NR5_TIMER4_BASE+NR5_TIMERA_TACCR2_OFFSET)
+#define NR5_TIMER4_TAIV_OFFSET            (NR5_TIMER4_BASE+NR5_TIMERA_TAIV_OFFSET)
+#endif
+
+/* Timer 5 address definitions */
+
+#ifdef CONFIG_NR5_TIMER5 
+#define NR5_TIMER5_TACTL_OFFSET           (NR5_TIMER5_BASE+NR5_TIMERA_TACTL_OFFSET)
+#define NR5_TIMER5_TAR_OFFSET             (NR5_TIMER5_BASE+NR5_TIMERA_TAR_OFFSET)
+#define NR5_TIMER5_TACCTL0_OFFSET         (NR5_TIMER5_BASE+NR5_TIMERA_TACCTL0_OFFSET)
+#define NR5_TIMER5_TACCR0_OFFSET          (NR5_TIMER5_BASE+NR5_TIMERA_TACCR0_OFFSET)
+#define NR5_TIMER5_TACCTL1_OFFSET         (NR5_TIMER5_BASE+NR5_TIMERA_TACCTL1_OFFSET)
+#define NR5_TIMER5_TACCR1_OFFSET          (NR5_TIMER5_BASE+NR5_TIMERA_TACCR1_OFFSET)
+#define NR5_TIMER5_TACCTL2_OFFSET         (NR5_TIMER5_BASE+NR5_TIMERA_TACCTL2_OFFSET)
+#define NR5_TIMER5_TACCR2_OFFSET          (NR5_TIMER5_BASE+NR5_TIMERA_TACCR2_OFFSET)
+#define NR5_TIMER5_TAIV_OFFSET            (NR5_TIMER5_BASE+NR5_TIMERA_TAIV_OFFSET)
+#endif
+
+/* Register Bitfield Definitions ********************************************************/
+
+/* Control register TACTL Bit definitions */
+
+#define TIMERA_TACTL_TAIFG                (1 << 0)    /* Bit 0: Interrupt Pending Flag */       
+#define TIMERA_TACTL_TAIE                 (1 << 1)    /* Bit 1: Interrupt Enable */
+#define TIMERA_TACTL_TACLR                (1 << 2)    /* Bit 2: TAR counter clear */
+#define TIMERA_TACTL_MC_SHIFT             4           /* Bits 4-5: Mode Control */
+#  define TIMERA_TACTL_MC_MASK            (3 << TIMERA_TACTL_MC_SHIFT)
+#  define TIMERA_TACTL_STOP               (0 << TIMERA_TACTL_MC_SHIFT)
+#  define TIMERA_TACTL_UP                 (1 << TIMERA_TACTL_MC_SHIFT)
+#  define TIMERA_TACTL_CONTINUOUS         (2 << TIMERA_TACTL_MC_SHIFT)
+#  define TIMERA_TACTL_UPDOWN             (3 << TIMERA_TACTL_MC_SHIFT)
+#define TIMERA_TACTL_ID_SHIFT             6           /* Bits 6-7: Input Divider */
+#  define TIMERA_TACTL_DIV_1              (0 << TIMERA_TACTL_ID_SHIFT)
+#  define TIMERA_TACTL_DIV_2              (1 << TIMERA_TACTL_ID_SHIFT)
+#  define TIMERA_TACTL_DIV_4              (2 << TIMERA_TACTL_ID_SHIFT)
+#  define TIMERA_TACTL_DIV_8              (3 << TIMERA_TACTL_ID_SHIFT)
+#define TIMERA_TACTL_TASSEL_SHIFT         8           /* Bits 8-9: Clock Source Select */
+#  define TIMERA_TACTL_MED_CLOCK          (0 << TIMERA_TACTL_TASSEL_SHIFT)
+#  define TIMERA_TACTL_SLOW_CLOCK         (1 << TIMERA_TACTL_TASSEL_SHIFT)
+#  define TIMERA_TACTL_SYS_CLOCK          (2 << TIMERA_TACTL_TASSEL_SHIFT)
+#  define TIMERA_TACTL_EXT_CLOCK          (3 << TIMERA_TACTL_TASSEL_SHIFT)
+#define TIMERA_TACTL_TAPRE_SHIFT          10          /* Bits 10-15: Clock Prescaler */
+#define TIMERA_TACTL_TAPRE_MASK           0x3F  
+#  define TIMERA_TACTL_TAPRE(x)           (((x) & TIMERA_TACTL_TAPRE_MASK) << TIMERA_TACTL_TAPRE_SHIFT)
+
+/* Capture / Compare register bit definitions */
+
+#define TIMERA_TACCTL_CCIFG               (1 << 0)    /* Bit 0: Capture/compare interrupt Flag */       
+#define TIMERA_TACCTL_COV                 (1 << 1)    /* Bit 1: Capture overflow */       
+#define TIMERA_TACCTL_OUTVAL              (1 << 2)    /* Bit 2: Output value */       
+#define TIMERA_TACCTL_CCI                 (1 << 3)    /* Bit 3: Capture/compare input value */
+#define TIMERA_TACCTL_CCIE                (1 << 4)    /* Bit 4: Capture/Compare interrupt Enable */
+#define TIMERA_TACCTL_OUTMOD_SHIFT        5           /* Bits 5-7: Output Mode */
+#  define TIMERA_TACCTL_OUT               (0 << TIMERA_TACCTL_OUTMOD_SHIFT)
+#  define TIMERA_TACCTL_SET               (1 << TIMERA_TACCTL_OUTMOD_SHIFT)
+#  define TIMERA_TACCTL_TOGGLE_RESET      (2 << TIMERA_TACCTL_OUTMOD_SHIFT)
+#  define TIMERA_TACCTL_SET_RESET         (3 << TIMERA_TACCTL_OUTMOD_SHIFT)
+#  define TIMERA_TACCTL_TOGGLE            (4 << TIMERA_TACCTL_OUTMOD_SHIFT)
+#  define TIMERA_TACCTL_RESET             (5 << TIMERA_TACCTL_OUTMOD_SHIFT)
+#  define TIMERA_TACCTL_TOGGLE_SET        (6 << TIMERA_TACCTL_OUTMOD_SHIFT)
+#  define TIMERA_TACCTL_RESET_SET         (7 << TIMERA_TACCTL_OUTMOD_SHIFT)
+#define TIMERA_TACCTL_CAP                 (1 << 8)    /* Bit 8: Capture mode select  */       
+#define TIMERA_TACCTL_SCCI                (1 << 10)   /* Bit 10: Synchronized capture input */       
+#define TIMERA_TACCTL_SCS                 (1 << 11)   /* Bit 11: Syncronize capture source */       
+#define TIMERA_TACCTL_CCIS_SHIFT          12          /* Bits 12-13: Capture Input Select */
+#  define TIMERA_TACCTL_CCIS_CCIA         (0 << TIMERA_TACCTL_CCIS_SHIFT)
+#  define TIMERA_TACCTL_CCIS_CCIB         (1 << TIMERA_TACCTL_CCIS_SHIFT)
+#  define TIMERA_TACCTL_CCIS_GND          (2 << TIMERA_TACCTL_CCIS_SHIFT)
+#  define TIMERA_TACCTL_CCIS_VCC          (3 << TIMERA_TACCTL_CCIS_SHIFT)
+#define TIMERA_TACCTL_CM_SHIFT            14          /* Bits 14-15: Capture Mode */
+#  define TIMERA_TACCTL_CM_NO_CAPTURE     (0 << TIMERA_TACCTL_SM_SHIFT)
+#  define TIMERA_TACCTL_CM_RISING         (1 << TIMERA_TACCTL_SM_SHIFT)
+#  define TIMERA_TACCTL_CM_FALLING        (2 << TIMERA_TACCTL_SM_SHIFT)
+#  define TIMERA_TACCTL_CM_BOTH           (3 << TIMERA_TACCTL_SM_SHIFT)
+
+/* Interrupt Vector Register */
+
+#define TIMERA_TAIV_TAIV_SHIFT            1           /* Bits 1-3: Interrupt Source */
+#  define TIMERA_TAIV_TACCR1              (1 << TIMERA_TAIV_TAIV_SHIFT)
+#  define TIMERA_TAIV_TACCR2              (2 << TIMERA_TAIV_TAIV_SHIFT)
+#  define TIMERA_TAIV_TAIFG               (5 << TIMERA_TAIV_TAIV_SHIFT)
+
+#endif  /* _ARCH_RISCV_SRC_NR5M100_CHIP_NR5M1XX_TIMERA_H */
+

arch/risc-v/src/nr5m100/chip/nr5m1xx_uart.h

@@ -0,0 +1,75 @@
+/************************************************************************************
+ * arch/risc-v/src/nr5m100/chip/nr5_uart.h
+ *
+ *   Copyright (C) 2016 Ken Pettit. All rights reserved.
+ *   Author: Ken Pettit <pettitkd@gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef ARCH_RISCV_SRC_NR5M100_CHIP_NR5M1XX_UART_H
+#define ARCH_RISCV_SRC_NR5M100_CHIP_NR5M1XX_UART_H
+
+/* The UART in NR5M100 is a very small (i.e. dumb) peripheral.  It
+ * only supports the most common mode ever used:
+ *
+ *   8 Data bits
+ *   1 Stop bit
+ *   No parity.
+ *
+ *   It has a programmable baud rate and RX / TX interrupt capability
+ *   and that's about it.  The primary goal for the UART is to provide a 
+ *   debug console to the part.
+ */
+
+#define NR5_UART_BAUD_RATE_OFFSET         0x000
+#define NR5_UART_TX_REG_OFFSET            0x004
+#define NR5_UART_RX_REG_OFFSET            0x008
+#define NR5_UART_STATUS_REG_OFFSET        0x00C
+#define NR5_UART_CTRL_REG_OFFSET          0x010
+
+#ifdef CONFIG_NR5_UART1
+#  define NR5_UART1_BAUD_RATE_REG         (NR5_UART1_BASE+NR5_UART_BAUD_RATE_OFFSET)
+#  define NR5_UART1_TX_REG                (NR5_UART1_BASE+NR5_UART_TX_REG_OFFSET)
+#  define NR5_UART1_RX_REG                (NR5_UART1_BASE+NR5_UART_RX_REG_OFFSET)
+#  define NR5_UART1_STATUS_REG            (NR5_UART1_BASE+NR5_UART_STATUS_REG_OFFSET)
+#  define NR5_UART1_CTRL_REG              (NR5_UART1_BASE+NR5_UART_CTRL_REG_OFFSET)
+#endif
+
+/* Status Register Bit definitions */
+
+#define NR5_UART_STATUS_TX_EMPTY          0x01
+#define NR5_UART_STATUS_RX_AVAIL          0x02
+#define NR5_UART_STATUS_RX_OVERRUN        0x04
+#define NR5_UART_RX_IRQ_PENDING           0x08
+#define NR5_UART_TX_IRQ_PENDING           0x10
+
+/* Control Register Bit definitions */
+
+#define NR5_UART_CTRL_ENABLE_RX_IRQ       0x01
+#define NR5_UART_CTRL_ENABLE_TX_IRQ       0x02
+
+#endif  /* _ARCH_RISCV_SRC_NR5M100_CHIP_NR5M1XX_UART_H */

arch/risc-v/src/nr5m100/nr5.h

@@ -0,0 +1,68 @@
+/************************************************************************************
+ * arch/risc-v/src/nr5m100/nr5.h
+ *
+ *   Copyright (C) 2011 Uros Platise. All rights reserved.
+ *   Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2016 Ken Pettit. All rights reserved.
+ *   Authors: Uros Platise <uros.platise@isotel.eu>
+ *            Gregory Nutt <gnutt@nuttx.org>
+ *            Ken Pettit <pettitkd@gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_RISCV_SRC_NR5M100_NR5_H
+#define __ARCH_RISCV_SRC_NR5M100_NR5_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+#include <arch/irq.h>
+#include "up_internal.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Peripherals **********************************************************************/
+
+#include "chip.h"
+#include "nr5_csr.h"
+#include "nr5_lowputc.h"
+#include "nr5_timer.h"
+#include "nr5_uart.h"
+
+#endif /* __ARCH_RISCV_SRC_NR5_NR5_H */
+

arch/risc-v/src/nr5m100/nr5_allocateheap.c

@@ -0,0 +1,63 @@
+/************************************************************************************
+ * arch/risc-v/src/nr5m100/nr5_allocateheap.c
+ *
+ *   Copyright (C) 2016 Ken Pettit. All rights reserved.
+ *   Author: Ken Pettit <pettitkd@gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <arch/board/board.h>
+
+#include "nr5.h"
+
+/************************************************************************************
+ * Private Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Private Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: up_addregion
+ *
+ * Descripton:
+ *   RAM may be added in non-contiguous chunks.  This routine adds all chunks
+ *   that may be used for heap.
+ *
+ ************************************************************************************/
+
+void up_addregion(void)
+{
+}
+

arch/risc-v/src/nr5m100/nr5_arch.c

@@ -0,0 +1,43 @@
+/************************************************************************************
+ * arch/risc-v/src/nr5m100/nr5_arch.c
+ *
+ *   Copyright (C) 2016 Ken Pettit. All rights reserved.
+ *   Author: Ken Pettit <pettitkd@gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#include <string.h>
+#include <nuttx/arch.h>
+#include "nr5.h"
+
+void up_puts(const char *p)
+{
+	while (*p != 0)
+      up_lowputc(*(p++));
+   up_lowputc('\n');
+}
+

arch/risc-v/src/nr5m100/nr5_config.h

@@ -0,0 +1,97 @@
+/************************************************************************************
+ * arch/risc-v/src/nr5m100/nr5_config.h
+ *
+ *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ *   Modified for RISC-V:
+ *
+ *   Copyright (C) 2016 Ken Pettit. All rights reserved.
+ *   Author: Ken Pettit <pettitkd@gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_RISCV_SRC_NR5M100_NR5_CONFIG_H
+#define __ARCH_RISCV_SRC_NR5M100_NR5_CONFIG_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <arch/chip/chip.h>
+#include <arch/board/board.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+/* UARTs ****************************************************************************/
+
+/* Are any UARTs enabled? */
+
+#undef HAVE_UART_DEVICE
+#if defined(CONFIG_NR5_UART1) || defined(CONFIG_NR5_UART2)
+#  define HAVE_UART_DEVICE 1
+#endif
+
+/* Is there a serial console?  There should be no more than one defined.  It
+ * could be on any UARTn, n=1,.. CHIP_NUARTS
+ */
+
+#if defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_NR5_UART1)
+#  undef CONFIG_UART2_SERIAL_CONSOLE
+#  define HAVE_SERIAL_CONSOLE 1
+#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_NR5_UART2)
+#  undef CONFIG_UART1_SERIAL_CONSOLE
+#  define HAVE_SERIAL_CONSOLE 1
+#else
+#  undef CONFIG_UART1_SERIAL_CONSOLE
+#  undef CONFIG_UART2_SERIAL_CONSOLE
+#  undef HAVE_SERIAL_CONSOLE
+#endif
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Inline Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_RISCV_SRC_NR5M100_NR5_CONFIG_H */

arch/risc-v/src/nr5m100/nr5_csr.S

@@ -0,0 +1,289 @@
+/************************************************************************************
+ * arch/risc-v/src/nr5m100/nr5_csr.c
+ *
+ *   Copyright (C) 2016 Ken Pettit. All rights reserved.
+ *   Author: Ken Pettit <pettitkd@gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/*
+ * Provide C level access function to asm only CSR registers
+ */
+
+#define ENABLE_QREGS
+#include "nr5_custom_ops.h"
+#include "nr5_csr.h"
+
+	.global up_getmisa
+	.global up_getarchid
+	.global up_getimpid
+	.global up_getvendorid
+	.global up_gethartid
+	.global up_getepicprimask
+	.global up_setepicprimask
+	.global up_setepicstat
+	.global up_setsystick
+	.global up_setpri1bit
+	.global up_clearpri1bit
+	.global up_setpri2bit
+	.global up_clearpri2bit
+	.global up_setpri3bit
+	.global up_clearpri3bit
+	.global up_setirqmaskbit
+	.global up_clearirqmaskbit
+	.global up_disableints
+	.global up_enableints
+	.global up_getq0
+	.global up_getq1
+	.global up_getq2
+	.global up_setq0
+	.global up_setq1
+	.global up_setq2
+	.global up_lsbenc
+
+	.section .text
+
+/****************************************************************************
+ * Returns the Read Only RV32IM Machine ISA (capabilities)
+ ****************************************************************************/
+
+up_getmisa:
+    csrr  a0, CSR_MISA
+    ret
+
+/****************************************************************************
+ * Returns the Read Only RV32IM Vendor ID
+ ****************************************************************************/
+
+up_getvendorid:
+    csrr  a0, CSR_MVENDORID
+    ret
+
+/****************************************************************************
+ * Returns the Read Only RV32IM ARCH ID
+ ****************************************************************************/
+
+up_getarchid:
+    csrr  a0, CSR_MARCHID
+    ret
+
+/****************************************************************************
+ * Returns the Read Only RV32IM IMP ID
+ ****************************************************************************/
+
+up_getimpid:
+    csrr  a0, CSR_MIMPID
+    ret
+
+/****************************************************************************
+ * Returns the Read Only RV32IM HART ID
+ ****************************************************************************/
+
+up_gethartid:
+    csrr  a0, CSR_MHARTID
+    ret
+
+/****************************************************************************
+ * Returns the NR5M100 specific Embedded Priority Interrupt Controller (EPIC)
+ * IRQ MASK register
+ ****************************************************************************/
+
+up_getepicmask:
+    csrr  a0, NR5_EPIC_IRQ_MASK
+    ret
+
+/****************************************************************************
+ * Returns the NR5M100 specific EPIC IRQ Priority register
+ ****************************************************************************/
+
+up_getepicpri:
+    csrr  a0, NR5_EPIC_PRIMASK
+    ret
+
+/****************************************************************************
+ * Sets the NR5M100 specific EPIC IRQ Priority register
+ ****************************************************************************/
+
+up_setepicpri:
+    csrrw  a0, NR5_EPIC_PRIMASK, a0
+    ret
+
+/****************************************************************************
+ * Sets the NR5M100 specific SYSTICK control register
+ ****************************************************************************/
+
+up_setsystick:
+    csrw  NR5_MSYSTICK_REG, a0
+    ret
+
+/****************************************************************************
+ * Sets bits in the NR5M100 specific PRI1 mask control register
+ ****************************************************************************/
+
+up_setpri1bit:
+    csrrs a0, NR5_EPIC_PRI1, a0
+    ret
+
+/****************************************************************************
+ * Clears bits in the NR5M100 specific PRI1 mask control register
+ ****************************************************************************/
+
+up_clearpri1bit:
+    csrrc a0, NR5_EPIC_PRI1, a0
+    ret
+
+/****************************************************************************
+ * Sets bits in the NR5M100 specific PRI2 mask control register
+ ****************************************************************************/
+
+up_setpri2bit:
+    csrrs a0, NR5_EPIC_PRI2, a0
+    ret
+
+/****************************************************************************
+ * Clears bits in the NR5M100 specific PRI2 mask control register
+ ****************************************************************************/
+
+up_clearpri2bit:
+    csrrc a0, NR5_EPIC_PRI2, a0
+    ret
+
+/****************************************************************************
+ * Sets bits in the NR5M100 specific PRI3 mask control register
+ ****************************************************************************/
+
+up_setpri3bit:
+    csrrs a0, NR5_EPIC_PRI3, a0
+    ret
+
+/****************************************************************************
+ * Clears bits in the NR5M100 specific PRI3 mask control register
+ ****************************************************************************/
+
+up_clearpri3bit:
+    csrrc a0, NR5_EPIC_PRI3, a0
+    ret
+
+/****************************************************************************
+ * Sets bits in the NR5M100 specific IRQ mask control register
+ ****************************************************************************/
+
+up_setirqmaskbit:
+    csrrs a0, NR5_EPIC_IRQ_MASK, a0
+    ret
+
+/****************************************************************************
+ * Clears bits in the NR5M100 specific IRQ mask control register
+ ****************************************************************************/
+
+up_clearirqmaskbit:
+    csrrc a0, NR5_EPIC_IRQ_MASK, a0
+    ret
+
+/****************************************************************************
+ * Disables global interrupts in NR5M100 specific IRQ PRI control register
+ ****************************************************************************/
+
+up_disableints:
+    csrrc a0, NR5_EPIC_PRIMASK, 1
+    ret
+
+/****************************************************************************
+ * Enables global interrupts in NR5M100 specific IRQ PRI control register
+ ****************************************************************************/
+
+up_enableints:
+    csrrs a0, NR5_EPIC_PRIMASK, 1
+    ret
+
+/****************************************************************************
+ * Reads NR5M100 specific Q0 register (used for interrupt processing)
+ ****************************************************************************/
+
+up_getq0:
+    getq a0, q0
+    ret
+
+/****************************************************************************
+ * Reads NR5M100 specific Q1 register (used for interrupt processing)
+ ****************************************************************************/
+
+up_getq1:
+    getq a0, q1
+    ret
+
+/****************************************************************************
+ * Reads NR5M100 specific Q2 register (used for interrupt processing)
+ ****************************************************************************/
+
+up_getq2:
+    getq a0, q2
+    ret
+
+/****************************************************************************
+ * Sets NR5M100 specific Q0 register (used for interrupt processing)
+ ****************************************************************************/
+
+up_setq0:
+    setq q0, a0
+    ret
+
+/****************************************************************************
+ * Sets NR5M100 specific Q1 register (used for interrupt processing)
+ ****************************************************************************/
+
+up_setq1:
+    setq q1, a0
+    ret
+
+/****************************************************************************
+ * Sets NR5M100 specific Q2 register (used for interrupt processing)
+ ****************************************************************************/
+
+up_setq2:
+    setq q2, a0
+    ret
+
+/****************************************************************************
+ * Calls the  NR5M100 specific LSBENC opcode.  This opcode will find the 
+ * first least significant non-zero bit in a0 and return it's ordinal value.
+ ****************************************************************************/
+
+up_lsbenc:
+   lsbenc a0, a0
+   ret
+
+/****************************************************************************
+ * Modeline to set vim formatting options for ASM file.  For this to work,
+ * you must enable moeline processing in your ~/.vimrc file with:
+ *
+ *    ~/.vimrc:
+ *      set modeline
+ *
+ * vim: noet:ts=4:sw=4
+ ****************************************************************************/
+

arch/risc-v/src/nr5m100/nr5_csr.h

@@ -0,0 +1,94 @@
+/************************************************************************************
+ * arch/riscv/src/nr5/nr5_csr.h
+ *
+ *   Copyright (C) 2016 Ken Pettit. All rights reserved.
+ *   Author: Ken Pettit <pettitkd@gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/* CSR Definitions */
+
+#ifndef __ARCH_RISCV_SRC_NR5_NR5_CSR_H
+#define __ARCH_RISCV_SRC_NR5_NR5_CSR_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+#include <arch/arch.h>
+#endif
+
+#if defined(CONFIG_NR5_NR5M1XX)
+#  include "chip/nr5m1xx_epic.h"
+#endif
+
+#include <arch/rv32im/csr.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+#define NR5_EPIC_IRQ_MASK        0x7E0
+#define NR5_EPIC_PRI1            0x7E1
+#define NR5_EPIC_PRI2            0x7E2
+#define NR5_EPIC_PRI3            0x7E3
+#define NR5_EPIC_PRIMASK         0x7E4
+#define NR5_MSYSTICK_REG         0x7E5
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+void up_setsystick(uint32_t);
+
+void up_setpri1bit(uint32_t);
+void up_setpri2bit(uint32_t);
+void up_setpri3bit(uint32_t);
+
+void up_clearpri1bit(uint32_t);
+void up_clearpri2bit(uint32_t);
+void up_clearpri3bit(uint32_t);
+
+void up_setirqmaskbit(uint32_t);
+void up_clearirqmaskbit(uint32_t);
+
+void up_disableints(void);
+void up_enableints(void);
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ARCH_RISCV_SRC_NR5_NR5_CSR_H */
+

arch/risc-v/src/nr5m100/nr5_custom_ops.h

@@ -0,0 +1,61 @@
+/************************************************************************************
+ * arch/risc-v/src/nr5m100/nr5_custom_ops.h
+ *
+ *   Copyright (C) 2016 Ken Pettit. All rights reserved.
+ *   Author: Ken Pettit <pettitkd@gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define q0 0
+#define q1 1
+#define q2 2
+#define q3 3
+
+/****************************************************************************
+ * Assmebler Macros
+ ****************************************************************************/
+
+.macro getq rd qs
+custom0 \rd,\qs,0,0
+.endm
+
+.macro setq qd rs
+custom0 \qd,\rs,0,1
+.endm
+
+.macro lsbenc rd rs
+custom0 \rd,\rs,0,2
+.endm
+
+.macro timer rd rs
+custom0 \rd,\rs,0,5
+.endm
+

arch/risc-v/src/nr5m100/nr5_init.c

@@ -0,0 +1,76 @@
+/************************************************************************************
+ * arch/risc-v/src/nr5m100/nr5_init.c
+ *
+ *   Copyright (C) 2016 Ken Pettit. All rights reserved.
+ *   Author: Ken Pettit <pettitkd@gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <arch/board/board.h>
+
+#include "nr5.h"
+
+/************************************************************************************
+ * Private Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Private Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Function - Initialization
+ *
+ * Performs low level board initializaiton tasks.
+ ************************************************************************************/
+
+void __nr5_init(void)
+{
+  /* Configure the UART so we can get debug output */
+
+  nr5_lowsetup();
+
+  /* Do board initialization */
+
+  nr5_boardinitialize();
+
+  /* Call os_start() */
+
+  os_start();
+
+  /* Shouldn't get here */
+
+  for (;;);
+}
+
+