diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_lcd.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_lcd.c
index 3f55b1d10bf..bed6287efeb 100644
--- a/arch/arm/src/lpc17xx_40xx/lpc17_40_lcd.c
+++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_lcd.c
@@ -292,11 +292,11 @@ static int lpc17_40_getcmap(FAR struct fb_vtable_s *vtable,
         {
           /* Save the even palette value */
 
-          cmap->red[i+1]    = (rgb & LCD_PAL_R1_MASK) >> LCD_PAL_R1_SHIFT;
-          cmap->green[i+1]  = (rgb & LCD_PAL_G1_MASK) >> LCD_PAL_G1_SHIFT;
-          cmap->blue[i+1]   = (rgb & LCD_PAL_B1_MASK) >> LCD_PAL_B1_SHIFT;
+          cmap->red[i + 1]    = (rgb & LCD_PAL_R1_MASK) >> LCD_PAL_R1_SHIFT;
+          cmap->green[i + 1]  = (rgb & LCD_PAL_G1_MASK) >> LCD_PAL_G1_SHIFT;
+          cmap->blue[i + 1]   = (rgb & LCD_PAL_B1_MASK) >> LCD_PAL_B1_SHIFT;
 #ifdef CONFIG_FB_TRANSPARENCY
-          cmap->transp[i+1] = 0;
+          cmap->transp[i + 1] = 0;
 #endif
         }
     }
@@ -333,7 +333,8 @@ static int lpc17_40_putcmap(FAR struct fb_vtable_s *vtable,
   if ((i & 1) != 0)
     {
       rgb0  = *pal;
-      rgb0 &= (LCD_PAL_R0_MASK | LCD_PAL_G0_MASK | LCD_PAL_B0_MASK | LCD_PAL_I0);
+      rgb0 &= (LCD_PAL_R0_MASK | LCD_PAL_G0_MASK | LCD_PAL_B0_MASK |
+               LCD_PAL_I0);
       rgb1 |= ((uint32_t)cmap->red[i]   << LCD_PAL_R0_SHIFT |
                (uint32_t)cmap->green[i] << LCD_PAL_G0_SHIFT |
                (uint32_t)cmap->blue[i]  << LCD_PAL_B0_SHIFT);
@@ -357,13 +358,14 @@ static int lpc17_40_putcmap(FAR struct fb_vtable_s *vtable,
       if ((i + 1) >= last)
         {
           rgb1  = *pal;
-          rgb1 &= (LCD_PAL_R1_MASK | LCD_PAL_G1_MASK | LCD_PAL_B1_MASK | LCD_PAL_I1);
+          rgb1 &= (LCD_PAL_R1_MASK | LCD_PAL_G1_MASK | LCD_PAL_B1_MASK |
+                   LCD_PAL_I1);
         }
       else
         {
-          rgb1  = ((uint32_t)cmap->red[i+1]   << LCD_PAL_R1_SHIFT |
-                   (uint32_t)cmap->green[i+1] << LCD_PAL_G1_SHIFT |
-                   (uint32_t)cmap->blue[i+1]  << LCD_PAL_B1_SHIFT);
+          rgb1  = ((uint32_t)cmap->red[i + 1]   << LCD_PAL_R1_SHIFT |
+                   (uint32_t)cmap->green[i + 1] << LCD_PAL_G1_SHIFT |
+                   (uint32_t)cmap->blue[i + 1]  << LCD_PAL_B1_SHIFT);
         }
 
       /* Save the new palette value */
@@ -425,6 +427,7 @@ static int lpc17_40_setcursor(FAR struct fb_vtable_s *vtable,
           g_cpos = settings->pos;
           lcdinfo("pos: (h:%d, w:%d)\n", g_cpos.x, g_cpos.y);
         }
+
 #ifdef CONFIG_FB_HWCURSORSIZE
       if ((flags & FB_CUR_SETSIZE) != 0)
         {
@@ -432,6 +435,7 @@ static int lpc17_40_setcursor(FAR struct fb_vtable_s *vtable,
           lcdinfo("size: (h:%d, w:%d)\n", g_csize.h, g_csize.w);
         }
 #endif
+
 #ifdef CONFIG_FB_HWCURSORIMAGE
       if ((flags & FB_CUR_SETIMAGE) != 0)
         {
@@ -440,6 +444,7 @@ static int lpc17_40_setcursor(FAR struct fb_vtable_s *vtable,
                   settings->img.image);
         }
 #endif
+
       return OK;
     }
 
@@ -483,9 +488,11 @@ int up_fbinitialize(int display)
   putreg32(regval, LPC17_40_SYSCON_MATRIXARB);
 
   /* Configure pins */
+
   /* Video data:
    *
-   * REVISIT:  The conditional logic is not correct here.  See arch/arm/src/lpc54xx/lpc454_lcd.c
+   * REVISIT:  The conditional logic is not correct here.
+   * See arch/arm/src/lpc54xx/lpc454_lcd.c
    */
 
   lcdinfo("Configuring pins\n");
@@ -549,7 +556,8 @@ int up_fbinitialize(int display)
 
   /* Initialize pixel clock (assuming clock source is the peripheral clock) */
 
-  putreg32(((uint32_t)BOARD_PCLK_FREQUENCY / (uint32_t)LPC17_40_LCD_PIXEL_CLOCK)+1,
+  putreg32(((uint32_t)BOARD_PCLK_FREQUENCY /
+            (uint32_t)LPC17_40_LCD_PIXEL_CLOCK) + 1,
            LPC17_40_SYSCON_LCDCFG);
 
   /* Set the bits per pixel */
@@ -624,10 +632,10 @@ int up_fbinitialize(int display)
 
   putreg32(0, LPC17_40_LCD_TIMH);
 
-  regval = (((CONFIG_LPC17_40_LCD_HWIDTH/16) - 1) << LCD_TIMH_PPL_SHIFT |
-            (CONFIG_LPC17_40_LCD_HPULSE - 1)      << LCD_TIMH_HSW_SHIFT |
-            (CONFIG_LPC17_40_LCD_HFRONTPORCH - 1) << LCD_TIMH_HFP_SHIFT |
-            (CONFIG_LPC17_40_LCD_HBACKPORCH - 1)  << LCD_TIMH_HBP_SHIFT);
+  regval = (((CONFIG_LPC17_40_LCD_HWIDTH / 16) - 1) << LCD_TIMH_PPL_SHIFT |
+            (CONFIG_LPC17_40_LCD_HPULSE - 1)        << LCD_TIMH_HSW_SHIFT |
+            (CONFIG_LPC17_40_LCD_HFRONTPORCH - 1)   << LCD_TIMH_HFP_SHIFT |
+            (CONFIG_LPC17_40_LCD_HBACKPORCH - 1)    << LCD_TIMH_HBP_SHIFT);
   putreg32(regval, LPC17_40_LCD_TIMH);
 
   /* Initialize vertical timing */
@@ -658,7 +666,7 @@ int up_fbinitialize(int display)
 
   /* Set number of clocks per line */
 
-  regval |= ((CONFIG_LPC17_40_LCD_HWIDTH-1) << LCD_POL_CPL_SHIFT);
+  regval |= ((CONFIG_LPC17_40_LCD_HWIDTH - 1) << LCD_POL_CPL_SHIFT);
 
   /* Bypass internal pixel clock divider */
 
@@ -715,7 +723,8 @@ int up_fbinitialize(int display)
  *
  * Description:
  *   Return a a reference to the framebuffer object for the specified video
- *   plane of the specified plane.  Many OSDs support multiple planes of video.
+ *   plane of the specified plane.  Many OSDs support multiple planes of
+ *   video.
  *
  * Input Parameters:
  *   display - In the case of hardware with multiple displays, this
@@ -787,16 +796,16 @@ void up_fbuninitialize(int display)
   modifyreg32(LPC17_40_SYSCON_PCONP, SYSCON_PCONP_PCLCD, 0);
 }
 
-/************************************************************************************
+/****************************************************************************
  * Name:  lpc17_40_lcdclear
  *
  * Description:
- *   This is a non-standard LCD interface just for the LPC17xx/LPC40xx.  Clearing the display
- *   in the normal way by writing a sequences of runs that covers the entire display
- *   can be slow.  Here the display is cleared by simply setting all VRAM memory to
- *   the specified color.
+ *   This is a non-standard LCD interface just for the LPC17xx/LPC40xx.
+ *   Clearing the display in the normal way by writing a sequences of runs
+ *   that covers the entire display can be slow.  Here the display is
+ *   cleared by simply setting all VRAM memory to the specified color.
  *
- ************************************************************************************/
+ ****************************************************************************/
 
 void lpc17_40_lcdclear(nxgl_mxpixel_t color)
 {
@@ -806,17 +815,20 @@ void lpc17_40_lcdclear(nxgl_mxpixel_t color)
 
   lcdinfo("Clearing display: color=%08x VRAM=%08x size=%d\n",
           color, CONFIG_LPC17_40_LCD_VRAMBASE,
-          CONFIG_LPC17_40_LCD_HWIDTH * CONFIG_LPC17_40_LCD_VHEIGHT * sizeof(uint32_t));
+          CONFIG_LPC17_40_LCD_HWIDTH * CONFIG_LPC17_40_LCD_VHEIGHT *
+          sizeof(uint32_t));
 
 #else
   uint16_t *dest = (uint16_t *)CONFIG_LPC17_40_LCD_VRAMBASE;
 
   lcdinfo("Clearing display: color=%08x VRAM=%08x size=%d\n",
           color, CONFIG_LPC17_40_LCD_VRAMBASE,
-          CONFIG_LPC17_40_LCD_HWIDTH * CONFIG_LPC17_40_LCD_VHEIGHT * sizeof(uint16_t));
+          CONFIG_LPC17_40_LCD_HWIDTH * CONFIG_LPC17_40_LCD_VHEIGHT *
+          sizeof(uint16_t));
 #endif
 
-  for (i = 0; i < (CONFIG_LPC17_40_LCD_HWIDTH * CONFIG_LPC17_40_LCD_VHEIGHT); i++)
+  for (i = 0; i < (CONFIG_LPC17_40_LCD_HWIDTH * CONFIG_LPC17_40_LCD_VHEIGHT);
+       i++)
     {
       *dest++ = color;
     }