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Cosmetic changes to conditional compilation

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This commit is contained in:
Gregory Nutt
2015-03-09 18:14:31 -06:00
parent 4e306087af
commit 26dec2c333
1 changed files with 10 additions and 5 deletions
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arch/arm/src/samv7/sam_xdmac.c
+10 -5
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@@ -92,6 +92,11 @@
# define CONFIG_SAMV7_NLLDESC SAMV7_NDMACHAN # define CONFIG_SAMV7_NLLDESC SAMV7_NDMACHAN
#endif #endif
/* These cache operations are not yet available */
#undef HAVE_CLEAN_DCACHE_RANGE
#undef HAVE_INVALIDATE_DCACHE_RANGE
/**************************************************************************** /****************************************************************************
* Private Types * Private Types
****************************************************************************/ ****************************************************************************/
@@ -1086,7 +1091,7 @@ sam_allocdesc(struct sam_xdmach_s *xdmach, struct chnext_view1_s *prev,
xdmach->lltail = descr; xdmach->lltail = descr;
#if 0 /* REVISIT */ #ifdef HAVE_CLEAN_DCACHE_RANGE /* REVISIT */
/* Assume that we will be doing multiple buffer transfers and that /* Assume that we will be doing multiple buffer transfers and that
* that hardware will be accessing the descriptor via DMA. * that hardware will be accessing the descriptor via DMA.
*/ */
@@ -1098,7 +1103,7 @@ sam_allocdesc(struct sam_xdmach_s *xdmach, struct chnext_view1_s *prev,
} }
} }
#if 1 /* REVISIT */ #ifndef HAVE_CLEAN_DCACHE_RANGE /* REVISIT */
/* Assume that we will be doing multiple buffer transfers and that /* Assume that we will be doing multiple buffer transfers and that
* that hardware will be accessing the descriptors via DMA. * that hardware will be accessing the descriptors via DMA.
*/ */
@@ -1502,7 +1507,7 @@ static void sam_dmaterminate(struct sam_xdmach_s *xdmach, int result)
* to force reloads from memory. * to force reloads from memory.
*/ */
#if 0 /* Revisit */ #ifdef HAVE_INVALIDATE_DCACHE_RANGE /* Revisit */
if (xdmach->rx) if (xdmach->rx)
{ {
arch_invalidate_dcache(xdmach->rxaddr, xdmach->rxaddr + xdmach->rxsize); arch_invalidate_dcache(xdmach->rxaddr, xdmach->rxaddr + xdmach->rxsize);
@@ -1868,7 +1873,7 @@ int sam_dmatxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
/* Clean caches associated with the DMA memory */ /* Clean caches associated with the DMA memory */
#if 0 /* REVISIT */ #ifdef HAVE_CLEAN_DCACHE_RANGE /* REVISIT */
arch_clean_dcache(maddr, maddr + nbytes); arch_clean_dcache(maddr, maddr + nbytes);
#else #else
arch_clean_dcache_all(); arch_clean_dcache_all();
@@ -1953,7 +1958,7 @@ int sam_dmarxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
/* Clean caches associated with the DMA memory */ /* Clean caches associated with the DMA memory */
#if 0 /* REVISIT */ #ifdef HAVE_CLEAN_DCACHE_RANGE /* REVISIT */
arch_clean_dcache(maddr, maddr + nbytes); arch_clean_dcache(maddr, maddr + nbytes);
#else #else
arch_clean_dcache_all(); arch_clean_dcache_all();