Cosmetic changes from review of last PR

arch/arm/src/armv7-a/arm_restorefpu.S

@@ -45,10 +45,6 @@
 
 	.file		"arm_restorefpu.S"
 
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
 /************************************************************************************
  * Public Symbols
  ************************************************************************************/

arch/arm/src/armv7-a/arm_saveusercontext.S

@@ -42,28 +42,12 @@
 
 	.file	"arm_saveusercontext.S"
 
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
 /****************************************************************************
  * Public Symbols
  ****************************************************************************/
 
 	.globl	up_saveusercontext
 
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/

arch/arm/src/stm32l4/chip/stm32l4_qspi.h

@@ -48,12 +48,12 @@
 /****************************************************************************************
  * Pre-processor Definitions
  ****************************************************************************************/
+
 /* General Characteristics **************************************************************/
 
 #define STM32L4_QSPI_MINBITS            8         /* Minimum word width */
 #define STM32L4_QSPI_MAXBITS            32        /* Maximum word width */
 
-
 /* QSPI register offsets ****************************************************************/
 
 #define STM32L4_QUADSPI_CR_OFFSET       0x0000    /* Control Register */

arch/arm/src/stm32l4/stm32l4_qspi.c

@@ -77,8 +77,7 @@
 
 #define MEMORY_SYNC()     do { ARM_DSB(); ARM_ISB(); } while (0)
 
-/* Ensure that the DMA buffers are word-aligned.
+/* Ensure that the DMA buffers are word-aligned. */
- */
 
 #define ALIGN_SHIFT       2
 #define ALIGN_MASK        3
@@ -134,7 +133,8 @@
 #undef QSPI_USE_INTERRUPTS
 #undef CONFIG_STM32L4_QSPI_DMA
 
-/* sanity check that board.h defines requisite QSPI pinmap options for */
+/* Sanity check that board.h defines requisite QSPI pinmap options for */
+
 #if (!defined(GPIO_QSPI_CS) || !defined(GPIO_QSPI_IO0) || !defined(GPIO_QSPI_IO1) || \
     !defined(GPIO_QSPI_IO2) || !defined(GPIO_QSPI_IO3) || !defined(GPIO_QSPI_SCK))
 # error you must define QSPI pinmapping options for GPIO_QSPI_CS GPIO_QSPI_IO0 \
@@ -214,11 +214,11 @@ struct qspi_xctnspec_s
   uint8_t instr;          /* the (8-bit) Instruction (if any) */
 
   uint8_t addrmode;       /* 'address mode'; 0=none, 1=single, 2=dual, 3=quad */
-  uint8_t addrsize;       /* address size ( n - 1 ); 0, 1, 2, 3 */
+  uint8_t addrsize;       /* address size (n - 1); 0, 1, 2, 3 */
   uint32_t addr;          /* the address (if any) (1 to 4 bytes as per addrsize) */
 
   uint8_t altbytesmode;   /* 'alt bytes mode'; 0=none, 1=single, 2=dual, 3=quad */
-  uint8_t altbytessize;   /* 'alt bytes' size ( n - 1 ); 0, 1, 2, 3 */
+  uint8_t altbytessize;   /* 'alt bytes' size (n - 1); 0, 1, 2, 3 */
   uint32_t altbytes;      /* the 'alt bytes' (if any) */
 
   uint8_t dummycycles;    /* number of Dummy Cycles; 0 - 32 */
@@ -231,7 +231,6 @@ struct qspi_xctnspec_s
   uint32_t issioo;        /* true if 'send instruction only once' mode */
 };
 
-
 /****************************************************************************
  * Private Function Prototypes
  ****************************************************************************/
@@ -322,10 +321,6 @@ static struct stm32l4_qspidev_s g_qspi0dev =
 #endif
 };
 
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
 /****************************************************************************
  * Private Functions
  ****************************************************************************/
@@ -603,14 +598,17 @@ static int qspi_setupxctnfromcmd(struct qspi_xctnspec_s *xctn,
   DEBUGASSERT(cmdinfo->cmd < 256);
 
   /* Specify the instruction as per command info */
-
   /* XXX III instruction mode, single dual quad option bits */
+
   xctn->instrmode = CCR_IMODE_SINGLE;
   xctn->instr = cmdinfo->cmd;
+
   /* XXX III option bits for 'send instruction only once' */
+
   xctn->issioo = 0;
 
   /* XXX III options for alt bytes, dummy cycles */
+
   xctn->altbytesmode = CCR_ABMODE_NONE;
   xctn->altbytessize = CCR_ABSIZE_8;
   xctn->altbytes = 0;
@@ -621,6 +619,7 @@ static int qspi_setupxctnfromcmd(struct qspi_xctnspec_s *xctn,
   if (QSPICMD_ISADDRESS(cmdinfo->flags))
     {
       /* XXX III address mode mode, single, dual, quad option bits */
+
       xctn->addrmode = CCR_ADMODE_SINGLE;
       if (cmdinfo->addrlen == 1)
         {
@@ -642,6 +641,7 @@ static int qspi_setupxctnfromcmd(struct qspi_xctnspec_s *xctn,
         {
           return -EINVAL;
         }
+
       xctn->addr = cmdinfo->addr;
     }
   else
@@ -657,9 +657,12 @@ static int qspi_setupxctnfromcmd(struct qspi_xctnspec_s *xctn,
   if (QSPICMD_ISDATA(cmdinfo->flags))
     {
       /* XXX III data mode mode, single, dual, quad option bits */
+
       xctn->datamode = CCR_DMODE_SINGLE;
       xctn->datasize = cmdinfo->buflen;
+
       /* XXX III double data rate option bits */
+
       xctn->isddr = 0;
     }
   else
@@ -707,12 +710,16 @@ static int qspi_setupxctnfrommem(struct qspi_xctnspec_s *xctn,
   /* Specify the instruction as per command info */
 
   /* XXX III instruction mode, single dual quad option bits */
+
   xctn->instrmode = CCR_IMODE_SINGLE;
   xctn->instr = meminfo->cmd;
+
   /* XXX III option bits for 'send instruction only once' */
+
   xctn->issioo = 0;
 
   /* XXX III options for alt bytes */
+
   xctn->altbytesmode = CCR_ABMODE_NONE;
   xctn->altbytessize = CCR_ABSIZE_8;
   xctn->altbytes = 0;
@@ -721,13 +728,22 @@ static int qspi_setupxctnfrommem(struct qspi_xctnspec_s *xctn,
 
   /* Specify the address size as needed */
 
-  /* XXX III there should be a separate flags for single/dual/quad for each of i,a,d */
+  /* XXX III there should be a separate flags for single/dual/quad for each
+   * of i,a,d
+   */
+
   if (QSPIMEM_ISDUALIO(meminfo->flags))
-    xctn->addrmode = CCR_ADMODE_DUAL;
+    {
+      xctn->addrmode = CCR_ADMODE_DUAL;
+    }
   else if (QSPIMEM_ISQUADIO(meminfo->flags))
-    xctn->addrmode = CCR_ADMODE_QUAD;
+    {
+      xctn->addrmode = CCR_ADMODE_QUAD;
+    }
   else
-    xctn->addrmode = CCR_ADMODE_SINGLE;
+    {
+      xctn->addrmode = CCR_ADMODE_SINGLE;
+    }
 
   if (meminfo->addrlen == 1)
     {
@@ -749,23 +765,33 @@ static int qspi_setupxctnfrommem(struct qspi_xctnspec_s *xctn,
     {
       return -EINVAL;
     }
+
   xctn->addr = meminfo->addr;
 
   /* Specify the data as needed */
 
   xctn->buffer = meminfo->buffer;
+
   /* XXX III there should be a separate flags for single/dual/quad for each of i,a,d */
+
   if (QSPIMEM_ISDUALIO(meminfo->flags))
-    xctn->datamode = CCR_DMODE_DUAL;
+    {
+      xctn->datamode = CCR_DMODE_DUAL;
+    }
   else if (QSPIMEM_ISQUADIO(meminfo->flags))
-    xctn->datamode = CCR_DMODE_QUAD;
+    {
+      xctn->datamode = CCR_DMODE_QUAD;
+    }
   else
-    xctn->datamode = CCR_DMODE_SINGLE;
+    {
+      xctn->datamode = CCR_DMODE_SINGLE;
+    }
 
   xctn->datasize = meminfo->buflen;
-  /* XXX III double data rate option bits */
-  xctn->isddr = 0;
 
+  /* XXX III double data rate option bits */
+
+  xctn->isddr = 0;
   return OK;
 }
 
@@ -790,14 +816,14 @@ static void qspi_waitstatusflags(struct stm32l4_qspidev_s *priv,
 {
   uint32_t regval;
 
-  if ( polarity )
+  if (polarity)
-  {
+    {
-    while ( !((regval = qspi_getreg(priv, STM32L4_QUADSPI_SR_OFFSET)) & mask)) ;
+      while (!((regval = qspi_getreg(priv, STM32L4_QUADSPI_SR_OFFSET)) & mask));
-  }
+    }
   else
-  {
+    {
-    while ( ((regval = qspi_getreg(priv, STM32L4_QUADSPI_SR_OFFSET)) & mask)) ;
+      while (((regval = qspi_getreg(priv, STM32L4_QUADSPI_SR_OFFSET)) & mask));
-  }
+    }
 }
 
 /****************************************************************************
@@ -822,21 +848,21 @@ static void qspi_ccrconfig(struct stm32l4_qspidev_s *priv,
 {
   uint32_t regval;
 
-  /* if we have data, and it's not memory mapped, write the length */
+  /* If we have data, and it's not memory mapped, write the length */
 
-  if ( CCR_DMODE_NONE != xctn->datamode && CCR_FMODE_MEMMAP != fctn )
+  if (CCR_DMODE_NONE != xctn->datamode && CCR_FMODE_MEMMAP != fctn)
     {
       qspi_putreg(priv, xctn->datasize-1, STM32L4_QUADSPI_DLR_OFFSET);
     }
 
-  /* if we have alternate bytes, stick them in now */
+  /* If we have alternate bytes, stick them in now */
 
-  if ( CCR_ABMODE_NONE != xctn->altbytesmode )
+  if (CCR_ABMODE_NONE != xctn->altbytesmode)
     {
       qspi_putreg(priv, xctn->altbytes, STM32L4_QUADSPI_ABR_OFFSET);
     }
 
-  /* build the CCR value and set it */
+  /* Build the CCR value and set it */
 
   regval  = QSPI_CCR_INST(xctn->instr) |
             QSPI_CCR_IMODE(xctn->instrmode) |
@@ -851,9 +877,9 @@ static void qspi_ccrconfig(struct stm32l4_qspidev_s *priv,
             (xctn->issioo ? QSPI_CCR_DDRM : 0);
   qspi_putreg(priv, regval, STM32L4_QUADSPI_CCR_OFFSET);
 
-  /* if we have and need and address, set that now, too */
+  /* If we have and need and address, set that now, too */
 
-  if ( CCR_ADMODE_NONE != xctn->addrmode && CCR_FMODE_MEMMAP != fctn )
+  if (CCR_ADMODE_NONE != xctn->addrmode && CCR_FMODE_MEMMAP != fctn)
     {
       qspi_putreg(priv, xctn->addr, STM32L4_QUADSPI_AR_OFFSET);
     }
@@ -884,12 +910,13 @@ static int qspi_receive_blocking(struct stm32l4_qspidev_s *priv,
   uint32_t regval;
 
   addrval = qspi_getreg(priv, STM32L4_QUADSPI_AR_OFFSET);
-  if(dest != NULL )
+  if (dest != NULL)
     {
-      /* counter of remaining data */
+      /* Counter of remaining data */
+
       uint32_t remaining = xctn->datasize;
 
-      /* ensure CCR register specifies indirect read */
+      /* Ensure CCR register specifies indirect read */
 
       regval  = qspi_getreg(priv, STM32L4_QUADSPI_CCR_OFFSET);
       regval &= ~QSPI_CCR_FMODE_MASK;
@@ -900,9 +927,9 @@ static int qspi_receive_blocking(struct stm32l4_qspidev_s *priv,
 
       qspi_putreg(priv, addrval, STM32L4_QUADSPI_AR_OFFSET);
 
-      /* transfer loop */
+      /* Transfer loop */
 
-      while(remaining > 0)
+      while (remaining > 0)
         {
           /* Wait for Fifo Threshold, or Transfer Complete, to read data */
 
@@ -920,7 +947,7 @@ static int qspi_receive_blocking(struct stm32l4_qspidev_s *priv,
           qspi_waitstatusflags(priv, QSPI_SR_TCF, 1);
           qspi_putreg(priv, QSPI_FCR_CTCF, STM32L4_QUADSPI_FCR);
 
-          /* use Abort to clear the busy flag, and ditch any extra bytes in fifo */
+          /* Use Abort to clear the busy flag, and ditch any extra bytes in fifo */
 
           regval  = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET);
           regval |= QSPI_CR_ABORT;
@@ -958,14 +985,15 @@ static int qspi_transmit_blocking(struct stm32l4_qspidev_s *priv,
   uint8_t *src = (uint8_t*)xctn->buffer;
   uint32_t regval;
 
-  if(src != NULL )
+  if (src != NULL)
     {
-      /* counter of remaining data */
+      /* Counter of remaining data */
+
       uint32_t remaining = xctn->datasize;
 
-      /* transfer loop */
+      /* Transfer loop */
 
-      while(remaining > 0)
+      while (remaining > 0)
         {
           /* Wait for Fifo Threshold to write data */
 
@@ -982,7 +1010,7 @@ static int qspi_transmit_blocking(struct stm32l4_qspidev_s *priv,
           qspi_waitstatusflags(priv, QSPI_SR_TCF, 1);
           qspi_putreg(priv, QSPI_FCR_CTCF, STM32L4_QUADSPI_FCR);
 
-          /* use Abort to cler the Busy flag */
+          /* Use Abort to cler the Busy flag */
 
           regval  = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET);
           regval |= QSPI_CR_ABORT;
@@ -1013,7 +1041,7 @@ static int qspi_transmit_blocking(struct stm32l4_qspidev_s *priv,
  *
  ****************************************************************************/
 
-static int     qspi0_interrupt(int irq, void *context)
+static int qspi0_interrupt(int irq, void *context)
 {
   /* XXX III needs implementation */
   (void)g_qspi0dev;
@@ -1021,8 +1049,7 @@ static int     qspi0_interrupt(int irq, void *context)
 }
 #endif
 
-
+/****************************************************************************
- /****************************************************************************
  * Name: qspi_lock
  *
  * Description:
@@ -1054,8 +1081,8 @@ static int qspi_lock(struct qspi_dev_s *dev, bool lock)
 
       while (sem_wait(&priv->exclsem) != 0)
         {
-          /* The only case that an error should occur here is if the wait was awakened
+          /* The only case that an error should occur here is if the wait
-           * by a signal.
+           * was awakened by a signal.
            */
 
           ASSERT(errno == EINTR);
@@ -1083,6 +1110,7 @@ static int qspi_lock(struct qspi_dev_s *dev, bool lock)
  *   Returns the actual frequency selected
  *
  ****************************************************************************/
+
 /*XXX partial*/
 static uint32_t qspi_setfrequency(struct qspi_dev_s *dev, uint32_t frequency)
 {
@@ -1245,8 +1273,9 @@ static void qspi_setmode(struct qspi_dev_s *dev, enum qspi_mode_e mode)
 
 static void qspi_setbits(struct qspi_dev_s *dev, int nbits)
 {
-  /* not meaningful for the STM32L4x6 */
+  /* Not meaningful for the STM32L4x6 */
-  if ( 8 != nbits )
+
+  if (8 != nbits)
     {
       qspivdbg("unsupported nbits=%d\n", nbits);
       DEBUGASSERT(FALSE);
@@ -1278,27 +1307,30 @@ static int qspi_command(struct qspi_dev_s *dev,
   /* Set up the transaction descriptor as per command info */
 
   ret = qspi_setupxctnfromcmd(&xctn, cmdinfo);
-  if ( OK != ret )
+  if (OK != ret)
   {
     return ret;
   }
 
   /* Prepare for transaction */
 
-  /* wait 'till non-busy */
+  /* Wait 'till non-busy */
 
   qspi_waitstatusflags(priv, QSPI_SR_BUSY, 0);
 
   /* Clear flags */
 
-  qspi_putreg(priv, QSPI_FCR_CTEF | QSPI_FCR_CTCF | QSPI_FCR_CSMF | QSPI_FCR_CTOF, STM32L4_QUADSPI_FCR);
+  qspi_putreg(priv, QSPI_FCR_CTEF | QSPI_FCR_CTCF | QSPI_FCR_CSMF | QSPI_FCR_CTOF,
+              STM32L4_QUADSPI_FCR);
 
-  /* XXX III this is for polling mode; support interrupt and dma modes also and 'autopolling' */
+  /* XXX III this is for polling mode; support interrupt and dma modes also
+   * and 'autopolling'
+   */
 
   /* Set up the Communications Configuration Register as per command info */
 
   qspi_ccrconfig(priv, &xctn,
-                 QSPICMD_ISWRITE(cmdinfo->flags) ? CCR_FMODE_INDWR : CCR_FMODE_INDRD );
+                 QSPICMD_ISWRITE(cmdinfo->flags) ? CCR_FMODE_INDWR : CCR_FMODE_INDRD);
 
   /* That may be it, unless there is also data to transfer */
 
@@ -1309,17 +1341,21 @@ static int qspi_command(struct qspi_dev_s *dev,
 
       if (QSPICMD_ISWRITE(cmdinfo->flags))
         {
-          /* XXX III we are going to do polling; revisit when we get interrupt and/or DMA up. */
+          /* XXX III we are going to do polling; revisit when we get
-
+           * interrupt and/or DMA up.
+           */
 
           ret = qspi_transmit_blocking(priv, &xctn);
         }
       else
         {
-          /* XXX III we are going to do polling; revisit when we get interrupt and/or DMA up. */
+          /* XXX III we are going to do polling; revisit when we get
+           * interrupt and/or DMA up.
+           */
 
           ret = qspi_receive_blocking(priv, &xctn);
         }
+
       MEMORY_SYNC();
     }
   else
@@ -1329,7 +1365,8 @@ static int qspi_command(struct qspi_dev_s *dev,
 
   /* XXX III this is for polling mode; support interrupt and dma modes also */
 
-  /* wait for Transfer complete, and not busy */
+  /* Wait for Transfer complete, and not busy */
+
   qspi_waitstatusflags(priv, QSPI_SR_TCF,1);
   qspi_waitstatusflags(priv, QSPI_SR_BUSY,0);
 
@@ -1361,27 +1398,30 @@ static int qspi_memory(struct qspi_dev_s *dev,
   /* Set up the transaction descriptor as per command info */
 
   ret = qspi_setupxctnfrommem(&xctn, meminfo);
-  if ( OK != ret )
+  if (OK != ret)
   {
     return ret;
   }
 
   /* Prepare for transaction */
 
-  /* wait 'till non-busy */
+  /* Wait 'till non-busy */
 
   qspi_waitstatusflags(priv, QSPI_SR_BUSY, 0);
 
   /* Clear flags */
 
-  qspi_putreg(priv, QSPI_FCR_CTEF | QSPI_FCR_CTCF | QSPI_FCR_CSMF | QSPI_FCR_CTOF, STM32L4_QUADSPI_FCR);
+  qspi_putreg(priv, QSPI_FCR_CTEF | QSPI_FCR_CTCF | QSPI_FCR_CSMF | QSPI_FCR_CTOF,
+              STM32L4_QUADSPI_FCR);
 
-  /* XXX III this is for polling mode; support interrupt and dma modes also and 'autopolling' */
+  /* XXX III this is for polling mode; support interrupt and dma modes also
+   * nd 'autopolling'
+   */
 
   /* Set up the Communications Configuration Register as per command info */
 
   qspi_ccrconfig(priv, &xctn,
-                 QSPICMD_ISWRITE(meminfo->flags) ? CCR_FMODE_INDWR : CCR_FMODE_INDRD );
+                 QSPICMD_ISWRITE(meminfo->flags) ? CCR_FMODE_INDWR : CCR_FMODE_INDRD);
 
   /* Transfer data */
 
@@ -1390,13 +1430,17 @@ static int qspi_memory(struct qspi_dev_s *dev,
 
   if (QSPICMD_ISWRITE(meminfo->flags))
     {
-      /* XXX III we are going to do polling; revisit when we get interrupt and/or DMA up. */
+      /* XXX III we are going to do polling; revisit when we get interrupt
+       * and/or DMA up.
+       */
 
       ret = qspi_transmit_blocking(priv, &xctn);
     }
   else
     {
-      /* XXX III we are going to do polling; revisit when we get interrupt and/or DMA up. */
+      /* XXX III we are going to do polling; revisit when we get interrupt
+       * and/or DMA up.
+       */
 
       ret = qspi_receive_blocking(priv, &xctn);
     }
@@ -1405,6 +1449,7 @@ static int qspi_memory(struct qspi_dev_s *dev,
 #if 0
 #ifdef CONFIG_STM32L4_QSPI_DMA
   /* Can we perform DMA?  Should we perform DMA? */
+
   if (priv->candma &&
       meminfo->buflen > CONFIG_STM32L4_QSPI_DMATHRESHOLD &&
       IS_ALIGNED((uintptr_t)meminfo->buffer) &&
@@ -1421,7 +1466,8 @@ static int qspi_memory(struct qspi_dev_s *dev,
 
   /* XXX III this is for polling mode; support interrupt and dma modes also */
 
-  /* wait for Transfer complete, and not busy */
+  /* Wait for Transfer complete, and not busy */
+
   qspi_waitstatusflags(priv, QSPI_SR_TCF,1);
   qspi_waitstatusflags(priv, QSPI_SR_BUSY,0);
 
@@ -1538,7 +1584,7 @@ static int qspi_hw_initialize(struct stm32l4_qspidev_s *priv)
   regval &= ~(QSPI_DCR_CKMODE | QSPI_DCR_CSHT_MASK | QSPI_DCR_FSIZE_MASK);
   regval |= (0x00);
   regval |= ((CONFIG_STM32L4_QSPI_CSHT-1) << QSPI_DCR_CSHT_SHIFT);
-  if ( 0 != CONFIG_STM32L4_QSPI_FLASH_SIZE )
+  if (0 != CONFIG_STM32L4_QSPI_FLASH_SIZE)
     {
       unsigned int nSize = CONFIG_STM32L4_QSPI_FLASH_SIZE;
       int nLog2Size = 31;

configs/stm32l476vg-disco/include/board.h

@@ -122,9 +122,7 @@
 #define GPIO_I2C1_SDA_GPIO \
    (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN7)
 
-/*
+/* XXX Is I2C2 used on Disco? */
- * XXX Is I2C2 used on Disco?
- */
 
 #if 0
 
@@ -146,18 +144,19 @@
 #define GPIO_QSPI_IO3        (GPIO_QSPI_BK1_IO3_2 | GPIO_FLOAT | GPIO_PUSHPULL | GPIO_SPEED_100MHz)
 #define GPIO_QSPI_SCK        (GPIO_QSPI_CLK_2 | GPIO_FLOAT | GPIO_PUSHPULL | GPIO_SPEED_100MHz)
 
-//XXX hmm, elsewhere
+#if 0
-//#define QSPI_USE_INTERRUPTS  1
+/* XXX hmm, elsewhere */
-//XXX hmm, better? (2^(23+1)); this is the value that goes into FSIZE
-//#define QSPI_FLASH_SIZE      23
 
+#define QSPI_USE_INTERRUPTS  1
 
-/* SPI
+/* XXX hmm, better? (2^(23+1)); this is the value that goes into FSIZE */
- */
 
-/*
+#define QSPI_FLASH_SIZE      23
- * XXX is SPI1 used on Disco?
+#endif
- */
+
+/* SPI */
+
+/* XXX is SPI1 used on Disco? */
 
 #if 0
 
@@ -167,7 +166,6 @@
 
 #endif
 
-
 /* SPI2 is used for several peripherals on the Discovery board, including
  * L3GD20 - 3 axis Gyroscope
  * LSM303CTR - eCompass, comprising an accelerometer and magnetometer

configs/stm32l476vg-disco/src/stm32_appinit.c

@@ -125,9 +125,9 @@ int board_app_initialize(void)
 
   (void)ret;
   
+#ifdef CONFIG_SCHED_INSTRUMENTATION
   /* Configure CPU load estimation */
 
-#ifdef CONFIG_SCHED_INSTRUMENTATION
   cpuload_initialize_once();
 #endif