diff --git a/arch/arm/src/sama5/sama5d3x4x_pio.c b/arch/arm/src/sama5/sama5d3x4x_pio.c index c054625ac8c..1fde4bacfe5 100644 --- a/arch/arm/src/sama5/sama5d3x4x_pio.c +++ b/arch/arm/src/sama5/sama5d3x4x_pio.c @@ -40,6 +40,17 @@ #include +#ifdef CONFIG_DEBUG_GPIO +/* Output informational debug info even if debug output is not enabled. */ + +# undef CONFIG_DEBUG_ERROR +# undef CONFIG_DEBUG_WARN +# undef CONFIG_DEBUG_INFO +# define CONFIG_DEBUG_ERROR 1 +# define CONFIG_DEBUG_WARN 1 +# define CONFIG_DEBUG_INFO 1 +#endif + #include #include #include @@ -67,10 +78,6 @@ #define PIO_INPUT_BITS (PIO_INPUT | PIO_CFG_DEFAULT) #define MK_INPUT(p) (((p) & (PIO_PORT_MASK | PIO_PIN_MASK)) | PIO_INPUT_BITS) -/**************************************************************************** - * Private Types - ****************************************************************************/ - /**************************************************************************** * Public Data ****************************************************************************/ @@ -869,41 +876,41 @@ int sam_dumppio(uint32_t pinset, const char *msg) /* The following requires exclusive access to the PIO registers */ flags = enter_critical_section(); - llerr("PIO%c pinset: %08x base: %08x -- %s\n", - g_portchar[port], pinset, base, msg); + llinfo("PIO%c pinset: %08x base: %08x -- %s\n", + g_portchar[port], pinset, base, msg); #ifdef SAM_PIO_ISLR_OFFSET - llerr(" PSR: %08x ISLR: %08x OSR: %08x IFSR: %08x\n", - getreg32(base + SAM_PIO_PSR_OFFSET), getreg32(base + SAM_PIO_ISLR_OFFSET), - getreg32(base + SAM_PIO_OSR_OFFSET), getreg32(base + SAM_PIO_IFSR_OFFSET)); + llinfo(" PSR: %08x ISLR: %08x OSR: %08x IFSR: %08x\n", + getreg32(base + SAM_PIO_PSR_OFFSET), getreg32(base + SAM_PIO_ISLR_OFFSET), + getreg32(base + SAM_PIO_OSR_OFFSET), getreg32(base + SAM_PIO_IFSR_OFFSET)); #else - llerr(" PSR: %08x OSR: %08x IFSR: %08x\n", - getreg32(base + SAM_PIO_PSR_OFFSET), getreg32(base + SAM_PIO_OSR_OFFSET), - getreg32(base + SAM_PIO_IFSR_OFFSET)); + llinfo(" PSR: %08x OSR: %08x IFSR: %08x\n", + getreg32(base + SAM_PIO_PSR_OFFSET), getreg32(base + SAM_PIO_OSR_OFFSET), + getreg32(base + SAM_PIO_IFSR_OFFSET)); #endif - llerr(" ODSR: %08x PDSR: %08x IMR: %08x ISR: %08x\n", - getreg32(base + SAM_PIO_ODSR_OFFSET), getreg32(base + SAM_PIO_PDSR_OFFSET), - getreg32(base + SAM_PIO_IMR_OFFSET), getreg32(base + SAM_PIO_ISR_OFFSET)); - llerr(" MDSR: %08x PUSR: %08x ABDCSR: %08x %08x\n", - getreg32(base + SAM_PIO_MDSR_OFFSET), getreg32(base + SAM_PIO_PUSR_OFFSET), - getreg32(base + SAM_PIO_ABCDSR1_OFFSET), getreg32(base + SAM_PIO_ABCDSR2_OFFSET)); - llerr(" IFSCSR: %08x SCDR: %08x PPDSR: %08x OWSR: %08x\n", - getreg32(base + SAM_PIO_IFSCSR_OFFSET), getreg32(base + SAM_PIO_SCDR_OFFSET), - getreg32(base + SAM_PIO_PPDSR_OFFSET), getreg32(base + SAM_PIO_OWSR_OFFSET)); + llinfo(" ODSR: %08x PDSR: %08x IMR: %08x ISR: %08x\n", + getreg32(base + SAM_PIO_ODSR_OFFSET), getreg32(base + SAM_PIO_PDSR_OFFSET), + getreg32(base + SAM_PIO_IMR_OFFSET), getreg32(base + SAM_PIO_ISR_OFFSET)); + llinfo(" MDSR: %08x PUSR: %08x ABDCSR: %08x %08x\n", + getreg32(base + SAM_PIO_MDSR_OFFSET), getreg32(base + SAM_PIO_PUSR_OFFSET), + getreg32(base + SAM_PIO_ABCDSR1_OFFSET), getreg32(base + SAM_PIO_ABCDSR2_OFFSET)); + llinfo(" IFSCSR: %08x SCDR: %08x PPDSR: %08x OWSR: %08x\n", + getreg32(base + SAM_PIO_IFSCSR_OFFSET), getreg32(base + SAM_PIO_SCDR_OFFSET), + getreg32(base + SAM_PIO_PPDSR_OFFSET), getreg32(base + SAM_PIO_OWSR_OFFSET)); #ifdef SAM_PIO_LOCKSR_OFFSET - llerr(" AIMMR: %08x ELSR: %08x FRLHSR: %08x LOCKSR: %08x\n", - getreg32(base + SAM_PIO_AIMMR_OFFSET), getreg32(base + SAM_PIO_ELSR_OFFSET), - getreg32(base + SAM_PIO_FRLHSR_OFFSET), getreg32(base + SAM_PIO_LOCKSR_OFFSET)); + llinfo(" AIMMR: %08x ELSR: %08x FRLHSR: %08x LOCKSR: %08x\n", + getreg32(base + SAM_PIO_AIMMR_OFFSET), getreg32(base + SAM_PIO_ELSR_OFFSET), + getreg32(base + SAM_PIO_FRLHSR_OFFSET), getreg32(base + SAM_PIO_LOCKSR_OFFSET)); #else - llerr(" AIMMR: %08x ELSR: %08x FRLHSR: %08x\n", - getreg32(base + SAM_PIO_AIMMR_OFFSET), getreg32(base + SAM_PIO_ELSR_OFFSET), - getreg32(base + SAM_PIO_FRLHSR_OFFSET)); + llinfo(" AIMMR: %08x ELSR: %08x FRLHSR: %08x\n", + getreg32(base + SAM_PIO_AIMMR_OFFSET), getreg32(base + SAM_PIO_ELSR_OFFSET), + getreg32(base + SAM_PIO_FRLHSR_OFFSET)); #endif - llerr("SCHMITT: %08x DRIVER: %08x %08x\n", - getreg32(base + SAM_PIO_SCHMITT_OFFSET), getreg32(base + SAM_PIO_DRIVER1_OFFSET), - getreg32(base + SAM_PIO_DRIVER2_OFFSET)); - llerr(" WPMR: %08x WPSR: %08x\n", - getreg32(base + SAM_PIO_WPMR_OFFSET), getreg32(base + SAM_PIO_WPSR_OFFSET)); + llinfo("SCHMITT: %08x DRIVER: %08x %08x\n", + getreg32(base + SAM_PIO_SCHMITT_OFFSET), getreg32(base + SAM_PIO_DRIVER1_OFFSET), + getreg32(base + SAM_PIO_DRIVER2_OFFSET)); + llinfo(" WPMR: %08x WPSR: %08x\n", + getreg32(base + SAM_PIO_WPMR_OFFSET), getreg32(base + SAM_PIO_WPSR_OFFSET)); leave_critical_section(flags); return OK; diff --git a/arch/arm/src/stm32/stm32_allocateheap.c b/arch/arm/src/stm32/stm32_allocateheap.c index 8a844b6d22d..02ba165a13e 100644 --- a/arch/arm/src/stm32/stm32_allocateheap.c +++ b/arch/arm/src/stm32/stm32_allocateheap.c @@ -41,6 +41,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/stm32/stm32_dma.h b/arch/arm/src/stm32/stm32_dma.h index b2f968fe1f7..d26428c35bb 100644 --- a/arch/arm/src/stm32/stm32_dma.h +++ b/arch/arm/src/stm32/stm32_dma.h @@ -104,7 +104,7 @@ typedef FAR void *DMA_HANDLE; typedef void (*dma_callback_t)(DMA_HANDLE handle, uint8_t status, void *arg); -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG_DEBUG_DMA_INFO #if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \ defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) struct stm32_dmaregs_s @@ -299,7 +299,7 @@ bool stm32_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr); * ****************************************************************************/ -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG_DEBUG_DMA_INFO void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs); #else # define stm32_dmasample(handle,regs) @@ -316,7 +316,7 @@ void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs); * ****************************************************************************/ -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG_DEBUG_DMA_INFO void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs, const char *msg); #else diff --git a/arch/arm/src/stm32/stm32_dumpgpio.c b/arch/arm/src/stm32/stm32_dumpgpio.c index c3023c21a88..3731e4158bb 100644 --- a/arch/arm/src/stm32/stm32_dumpgpio.c +++ b/arch/arm/src/stm32/stm32_dumpgpio.c @@ -39,6 +39,15 @@ #include +/* Output debug info even if debug output is not selected. */ + +#undef CONFIG_DEBUG_ERROR +#undef CONFIG_DEBUG_WARN +#undef CONFIG_DEBUG_INFO +#define CONFIG_DEBUG_ERROR 1 +#define CONFIG_DEBUG_WARN 1 +#define CONFIG_DEBUG_INFO 1 + #include #include @@ -56,7 +65,6 @@ ****************************************************************************/ /* Port letters for prettier debug output */ -#ifdef CONFIG_DEBUG_FEATURES static const char g_portchar[STM32_NGPIO_PORTS] = { #if STM32_NGPIO_PORTS > 11 @@ -87,15 +95,6 @@ static const char g_portchar[STM32_NGPIO_PORTS] = # error "Bad number of GPIOs" #endif }; -#endif - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ /**************************************************************************** * Public Functions @@ -125,111 +124,107 @@ int stm32_dumpgpio(uint32_t pinset, const char *msg) flags = enter_critical_section(); #if defined(CONFIG_STM32_STM32F10XX) - - llerr("GPIO%c pinset: %08x base: %08x -- %s\n", - g_portchar[port], pinset, base, msg); + llinfo("GPIO%c pinset: %08x base: %08x -- %s\n", + g_portchar[port], pinset, base, msg); if ((getreg32(STM32_RCC_APB2ENR) & RCC_APB2ENR_IOPEN(port)) != 0) { - llerr(" CR: %08x %08x IDR: %04x ODR: %04x LCKR: %04x\n", - getreg32(base + STM32_GPIO_CRH_OFFSET), - getreg32(base + STM32_GPIO_CRL_OFFSET), - getreg32(base + STM32_GPIO_IDR_OFFSET), - getreg32(base + STM32_GPIO_ODR_OFFSET), - getreg32(base + STM32_GPIO_LCKR_OFFSET)); - llerr(" EVCR: %02x MAPR: %08x CR: %04x %04x %04x %04x\n", - getreg32(STM32_AFIO_EVCR), getreg32(STM32_AFIO_MAPR), - getreg32(STM32_AFIO_EXTICR1), - getreg32(STM32_AFIO_EXTICR2), - getreg32(STM32_AFIO_EXTICR3), - getreg32(STM32_AFIO_EXTICR4)); + llinfo(" CR: %08x %08x IDR: %04x ODR: %04x LCKR: %04x\n", + getreg32(base + STM32_GPIO_CRH_OFFSET), + getreg32(base + STM32_GPIO_CRL_OFFSET), + getreg32(base + STM32_GPIO_IDR_OFFSET), + getreg32(base + STM32_GPIO_ODR_OFFSET), + getreg32(base + STM32_GPIO_LCKR_OFFSET)); + llinfo(" EVCR: %02x MAPR: %08x CR: %04x %04x %04x %04x\n", + getreg32(STM32_AFIO_EVCR), getreg32(STM32_AFIO_MAPR), + getreg32(STM32_AFIO_EXTICR1), + getreg32(STM32_AFIO_EXTICR2), + getreg32(STM32_AFIO_EXTICR3), + getreg32(STM32_AFIO_EXTICR4)); } else { - llerr(" GPIO%c not enabled: APB2ENR: %08x\n", + llinfo(" GPIO%c not enabled: APB2ENR: %08x\n", g_portchar[port], getreg32(STM32_RCC_APB2ENR)); } #elif defined(CONFIG_STM32_STM32L15XX) - DEBUGASSERT(port < STM32_NGPIO_PORTS); - llerr("GPIO%c pinset: %08x base: %08x -- %s\n", - g_portchar[port], pinset, base, msg); + llinfo("GPIO%c pinset: %08x base: %08x -- %s\n", + g_portchar[port], pinset, base, msg); if ((getreg32(STM32_RCC_AHBENR) & RCC_AHBENR_GPIOEN(port)) != 0) { - llerr(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n", - getreg32(base + STM32_GPIO_MODER_OFFSET), - getreg32(base + STM32_GPIO_OTYPER_OFFSET), - getreg32(base + STM32_GPIO_OSPEED_OFFSET), - getreg32(base + STM32_GPIO_PUPDR_OFFSET)); - llerr(" IDR: %04x ODR: %04x BSRR: %08x LCKR: %04x\n", - getreg32(base + STM32_GPIO_IDR_OFFSET), - getreg32(base + STM32_GPIO_ODR_OFFSET), - getreg32(base + STM32_GPIO_BSRR_OFFSET), - getreg32(base + STM32_GPIO_LCKR_OFFSET)); - llerr(" AFRH: %08x AFRL: %08x\n", - getreg32(base + STM32_GPIO_AFRH_OFFSET), - getreg32(base + STM32_GPIO_AFRL_OFFSET)); + llinfo(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n", + getreg32(base + STM32_GPIO_MODER_OFFSET), + getreg32(base + STM32_GPIO_OTYPER_OFFSET), + getreg32(base + STM32_GPIO_OSPEED_OFFSET), + getreg32(base + STM32_GPIO_PUPDR_OFFSET)); + llinfo(" IDR: %04x ODR: %04x BSRR: %08x LCKR: %04x\n", + getreg32(base + STM32_GPIO_IDR_OFFSET), + getreg32(base + STM32_GPIO_ODR_OFFSET), + getreg32(base + STM32_GPIO_BSRR_OFFSET), + getreg32(base + STM32_GPIO_LCKR_OFFSET)); + llinfo(" AFRH: %08x AFRL: %08x\n", + getreg32(base + STM32_GPIO_AFRH_OFFSET), + getreg32(base + STM32_GPIO_AFRL_OFFSET)); } else { - llerr(" GPIO%c not enabled: AHBENR: %08x\n", - g_portchar[port], getreg32(STM32_RCC_AHBENR)); + llinfo(" GPIO%c not enabled: AHBENR: %08x\n", + g_portchar[port], getreg32(STM32_RCC_AHBENR)); } #elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) - DEBUGASSERT(port < STM32_NGPIO_PORTS); - llerr("GPIO%c pinset: %08x base: %08x -- %s\n", - g_portchar[port], pinset, base, msg); + llinfo("GPIO%c pinset: %08x base: %08x -- %s\n", + g_portchar[port], pinset, base, msg); /* GPIOs are always enabled */ - llerr(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n", - getreg32(base + STM32_GPIO_MODER_OFFSET), - getreg32(base + STM32_GPIO_OTYPER_OFFSET), - getreg32(base + STM32_GPIO_OSPEED_OFFSET), - getreg32(base + STM32_GPIO_PUPDR_OFFSET)); - llerr(" IDR: %04x ODR: %04x BSRR: %08x LCKR: %04x\n", - getreg32(base + STM32_GPIO_IDR_OFFSET), - getreg32(base + STM32_GPIO_ODR_OFFSET), - getreg32(base + STM32_GPIO_BSRR_OFFSET), - getreg32(base + STM32_GPIO_LCKR_OFFSET)); - llerr(" AFRH: %08x AFRL: %08x BRR: %04x\n", - getreg32(base + STM32_GPIO_AFRH_OFFSET), - getreg32(base + STM32_GPIO_AFRL_OFFSET), - getreg32(base + STM32_GPIO_BRR_OFFSET)); + llinfo(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n", + getreg32(base + STM32_GPIO_MODER_OFFSET), + getreg32(base + STM32_GPIO_OTYPER_OFFSET), + getreg32(base + STM32_GPIO_OSPEED_OFFSET), + getreg32(base + STM32_GPIO_PUPDR_OFFSET)); + llinfo(" IDR: %04x ODR: %04x BSRR: %08x LCKR: %04x\n", + getreg32(base + STM32_GPIO_IDR_OFFSET), + getreg32(base + STM32_GPIO_ODR_OFFSET), + getreg32(base + STM32_GPIO_BSRR_OFFSET), + getreg32(base + STM32_GPIO_LCKR_OFFSET)); + llinfo(" AFRH: %08x AFRL: %08x BRR: %04x\n", + getreg32(base + STM32_GPIO_AFRH_OFFSET), + getreg32(base + STM32_GPIO_AFRL_OFFSET), + getreg32(base + STM32_GPIO_BRR_OFFSET)); #elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) - DEBUGASSERT(port < STM32_NGPIO_PORTS); - llerr("GPIO%c pinset: %08x base: %08x -- %s\n", - g_portchar[port], pinset, base, msg); + llinfo("GPIO%c pinset: %08x base: %08x -- %s\n", + g_portchar[port], pinset, base, msg); if ((getreg32(STM32_RCC_AHB1ENR) & RCC_AHB1ENR_GPIOEN(port)) != 0) { - llerr(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n", - getreg32(base + STM32_GPIO_MODER_OFFSET), - getreg32(base + STM32_GPIO_OTYPER_OFFSET), - getreg32(base + STM32_GPIO_OSPEED_OFFSET), - getreg32(base + STM32_GPIO_PUPDR_OFFSET)); - llerr(" IDR: %04x ODR: %04x BSRR: %08x LCKR: %04x\n", - getreg32(base + STM32_GPIO_IDR_OFFSET), - getreg32(base + STM32_GPIO_ODR_OFFSET), - getreg32(base + STM32_GPIO_BSRR_OFFSET), - getreg32(base + STM32_GPIO_LCKR_OFFSET)); - llerr(" AFRH: %08x AFRL: %08x\n", - getreg32(base + STM32_GPIO_AFRH_OFFSET), - getreg32(base + STM32_GPIO_AFRL_OFFSET)); + llinfo(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n", + getreg32(base + STM32_GPIO_MODER_OFFSET), + getreg32(base + STM32_GPIO_OTYPER_OFFSET), + getreg32(base + STM32_GPIO_OSPEED_OFFSET), + getreg32(base + STM32_GPIO_PUPDR_OFFSET)); + llinfo(" IDR: %04x ODR: %04x BSRR: %08x LCKR: %04x\n", + getreg32(base + STM32_GPIO_IDR_OFFSET), + getreg32(base + STM32_GPIO_ODR_OFFSET), + getreg32(base + STM32_GPIO_BSRR_OFFSET), + getreg32(base + STM32_GPIO_LCKR_OFFSET)); + llinfo(" AFRH: %08x AFRL: %08x\n", + getreg32(base + STM32_GPIO_AFRH_OFFSET), + getreg32(base + STM32_GPIO_AFRL_OFFSET)); } else { - llerr(" GPIO%c not enabled: AHB1ENR: %08x\n", - g_portchar[port], getreg32(STM32_RCC_AHB1ENR)); + llinfo(" GPIO%c not enabled: AHB1ENR: %08x\n", + g_portchar[port], getreg32(STM32_RCC_AHB1ENR)); } #else # error "Unsupported STM32 chip" diff --git a/arch/arm/src/stm32/stm32_sdio.c b/arch/arm/src/stm32/stm32_sdio.c index 49bf6f1bcf2..7fdf1c6caef 100644 --- a/arch/arm/src/stm32/stm32_sdio.c +++ b/arch/arm/src/stm32/stm32_sdio.c @@ -345,7 +345,7 @@ struct stm32_sdioregs_s struct stm32_sampleregs_s { struct stm32_sdioregs_s sdio; -#if defined(CONFIG_DEBUG_DMA) && defined(CONFIG_SDIO_DMA) +#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_SDIO_DMA) struct stm32_dmaregs_s dma; #endif }; @@ -789,12 +789,14 @@ static void stm32_sdiosample(struct stm32_sdioregs_s *regs) static void stm32_sample(struct stm32_dev_s *priv, int index) { struct stm32_sampleregs_s *regs = &g_sampleregs[index]; -#if defined(CONFIG_DEBUG_DMA) && defined(CONFIG_SDIO_DMA) + +#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_SDIO_DMA) if (priv->dmamode) { stm32_dmasample(priv->dma, ®s->dma); } #endif + stm32_sdiosample(®s->sdio); } #endif @@ -835,12 +837,13 @@ static void stm32_sdiodump(struct stm32_sdioregs_s *regs, const char *msg) static void stm32_dumpsample(struct stm32_dev_s *priv, struct stm32_sampleregs_s *regs, const char *msg) { -#if defined(CONFIG_DEBUG_DMA) && defined(CONFIG_SDIO_DMA) +#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_SDIO_DMA) if (priv->dmamode) { stm32_dmadump(priv->dma, ®s->dma, msg); } #endif + stm32_sdiodump(®s->sdio, msg); } #endif @@ -857,15 +860,18 @@ static void stm32_dumpsample(struct stm32_dev_s *priv, static void stm32_dumpsamples(struct stm32_dev_s *priv) { stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_BEFORE_SETUP], "Before setup"); -#if defined(CONFIG_DEBUG_DMA) && defined(CONFIG_SDIO_DMA) + +#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_SDIO_DMA) if (priv->dmamode) { stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_BEFORE_ENABLE], "Before DMA enable"); } #endif + stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_AFTER_SETUP], "After setup"); stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_END_TRANSFER], "End of transfer"); -#if defined(CONFIG_DEBUG_DMA) && defined(CONFIG_SDIO_DMA) + +#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_SDIO_DMA) if (priv->dmamode) { stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_DMA_CALLBACK], "DMA Callback"); diff --git a/arch/arm/src/stm32/stm32f10xxx_dma.c b/arch/arm/src/stm32/stm32f10xxx_dma.c index 32f485c447e..8a7782773e2 100644 --- a/arch/arm/src/stm32/stm32f10xxx_dma.c +++ b/arch/arm/src/stm32/stm32f10xxx_dma.c @@ -707,7 +707,7 @@ bool stm32_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) * ****************************************************************************/ -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG_DEBUG_DMA_INFO void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs) { struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle; @@ -734,19 +734,19 @@ void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs) * ****************************************************************************/ -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG_DEBUG_DMA_INFO void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs, const char *msg) { struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle; uint32_t dmabase = DMA_BASE(dmach->base); - dmaerr("DMA Registers: %s\n", msg); - dmaerr(" ISRC[%08x]: %08x\n", dmabase + STM32_DMA_ISR_OFFSET, regs->isr); - dmaerr(" CCR[%08x]: %08x\n", dmach->base + STM32_DMACHAN_CCR_OFFSET, regs->ccr); - dmaerr(" CNDTR[%08x]: %08x\n", dmach->base + STM32_DMACHAN_CNDTR_OFFSET, regs->cndtr); - dmaerr(" CPAR[%08x]: %08x\n", dmach->base + STM32_DMACHAN_CPAR_OFFSET, regs->cpar); - dmaerr(" CMAR[%08x]: %08x\n", dmach->base + STM32_DMACHAN_CMAR_OFFSET, regs->cmar); + dmainfo("DMA Registers: %s\n", msg); + dmainfo(" ISRC[%08x]: %08x\n", dmabase + STM32_DMA_ISR_OFFSET, regs->isr); + dmainfo(" CCR[%08x]: %08x\n", dmach->base + STM32_DMACHAN_CCR_OFFSET, regs->ccr); + dmainfo(" CNDTR[%08x]: %08x\n", dmach->base + STM32_DMACHAN_CNDTR_OFFSET, regs->cndtr); + dmainfo(" CPAR[%08x]: %08x\n", dmach->base + STM32_DMACHAN_CPAR_OFFSET, regs->cpar); + dmainfo(" CMAR[%08x]: %08x\n", dmach->base + STM32_DMACHAN_CMAR_OFFSET, regs->cmar); } #endif diff --git a/arch/arm/src/stm32/stm32f20xxx_dma.c b/arch/arm/src/stm32/stm32f20xxx_dma.c index 8dbe917e93b..335a9cd0096 100644 --- a/arch/arm/src/stm32/stm32f20xxx_dma.c +++ b/arch/arm/src/stm32/stm32f20xxx_dma.c @@ -973,7 +973,7 @@ bool stm32_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) * ****************************************************************************/ -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG_DEBUG_DMA_INFO void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs) { struct stm32_dma_s *dmast = (struct stm32_dma_s *)handle; @@ -1003,22 +1003,22 @@ void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs) * ****************************************************************************/ -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG_DEBUG_DMA_INFO void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs, const char *msg) { struct stm32_dma_s *dmast = (struct stm32_dma_s *)handle; uint32_t dmabase = DMA_BASE(dmast->base); - dmaerr("DMA Registers: %s\n", msg); - dmaerr(" LISR[%08x]: %08x\n", dmabase + STM32_DMA_LISR_OFFSET, regs->lisr); - dmaerr(" HISR[%08x]: %08x\n", dmabase + STM32_DMA_HISR_OFFSET, regs->hisr); - dmaerr(" SCR[%08x]: %08x\n", dmast->base + STM32_DMA_SCR_OFFSET, regs->scr); - dmaerr(" SNDTR[%08x]: %08x\n", dmast->base + STM32_DMA_SNDTR_OFFSET, regs->sndtr); - dmaerr(" SPAR[%08x]: %08x\n", dmast->base + STM32_DMA_SPAR_OFFSET, regs->spar); - dmaerr(" SM0AR[%08x]: %08x\n", dmast->base + STM32_DMA_SM0AR_OFFSET, regs->sm0ar); - dmaerr(" SM1AR[%08x]: %08x\n", dmast->base + STM32_DMA_SM1AR_OFFSET, regs->sm1ar); - dmaerr(" SFCR[%08x]: %08x\n", dmast->base + STM32_DMA_SFCR_OFFSET, regs->sfcr); + dmainfo("DMA Registers: %s\n", msg); + dmainfo(" LISR[%08x]: %08x\n", dmabase + STM32_DMA_LISR_OFFSET, regs->lisr); + dmainfo(" HISR[%08x]: %08x\n", dmabase + STM32_DMA_HISR_OFFSET, regs->hisr); + dmainfo(" SCR[%08x]: %08x\n", dmast->base + STM32_DMA_SCR_OFFSET, regs->scr); + dmainfo(" SNDTR[%08x]: %08x\n", dmast->base + STM32_DMA_SNDTR_OFFSET, regs->sndtr); + dmainfo(" SPAR[%08x]: %08x\n", dmast->base + STM32_DMA_SPAR_OFFSET, regs->spar); + dmainfo(" SM0AR[%08x]: %08x\n", dmast->base + STM32_DMA_SM0AR_OFFSET, regs->sm0ar); + dmainfo(" SM1AR[%08x]: %08x\n", dmast->base + STM32_DMA_SM1AR_OFFSET, regs->sm1ar); + dmainfo(" SFCR[%08x]: %08x\n", dmast->base + STM32_DMA_SFCR_OFFSET, regs->sfcr); } #endif diff --git a/arch/arm/src/stm32/stm32f40xxx_dma.c b/arch/arm/src/stm32/stm32f40xxx_dma.c index b7a968c84b9..8aae23d833f 100644 --- a/arch/arm/src/stm32/stm32f40xxx_dma.c +++ b/arch/arm/src/stm32/stm32f40xxx_dma.c @@ -1001,7 +1001,7 @@ bool stm32_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) * ****************************************************************************/ -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG_DEBUG_DMA_INFO void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs) { struct stm32_dma_s *dmast = (struct stm32_dma_s *)handle; @@ -1031,22 +1031,22 @@ void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs) * ****************************************************************************/ -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG_DEBUG_DMA_INFO void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs, const char *msg) { struct stm32_dma_s *dmast = (struct stm32_dma_s *)handle; uint32_t dmabase = DMA_BASE(dmast->base); - dmaerr("DMA Registers: %s\n", msg); - dmaerr(" LISR[%08x]: %08x\n", dmabase + STM32_DMA_LISR_OFFSET, regs->lisr); - dmaerr(" HISR[%08x]: %08x\n", dmabase + STM32_DMA_HISR_OFFSET, regs->hisr); - dmaerr(" SCR[%08x]: %08x\n", dmast->base + STM32_DMA_SCR_OFFSET, regs->scr); - dmaerr(" SNDTR[%08x]: %08x\n", dmast->base + STM32_DMA_SNDTR_OFFSET, regs->sndtr); - dmaerr(" SPAR[%08x]: %08x\n", dmast->base + STM32_DMA_SPAR_OFFSET, regs->spar); - dmaerr(" SM0AR[%08x]: %08x\n", dmast->base + STM32_DMA_SM0AR_OFFSET, regs->sm0ar); - dmaerr(" SM1AR[%08x]: %08x\n", dmast->base + STM32_DMA_SM1AR_OFFSET, regs->sm1ar); - dmaerr(" SFCR[%08x]: %08x\n", dmast->base + STM32_DMA_SFCR_OFFSET, regs->sfcr); + dmainfo("DMA Registers: %s\n", msg); + dmainfo(" LISR[%08x]: %08x\n", dmabase + STM32_DMA_LISR_OFFSET, regs->lisr); + dmainfo(" HISR[%08x]: %08x\n", dmabase + STM32_DMA_HISR_OFFSET, regs->hisr); + dmainfo(" SCR[%08x]: %08x\n", dmast->base + STM32_DMA_SCR_OFFSET, regs->scr); + dmainfo(" SNDTR[%08x]: %08x\n", dmast->base + STM32_DMA_SNDTR_OFFSET, regs->sndtr); + dmainfo(" SPAR[%08x]: %08x\n", dmast->base + STM32_DMA_SPAR_OFFSET, regs->spar); + dmainfo(" SM0AR[%08x]: %08x\n", dmast->base + STM32_DMA_SM0AR_OFFSET, regs->sm0ar); + dmainfo(" SM1AR[%08x]: %08x\n", dmast->base + STM32_DMA_SM1AR_OFFSET, regs->sm1ar); + dmainfo(" SFCR[%08x]: %08x\n", dmast->base + STM32_DMA_SFCR_OFFSET, regs->sfcr); } #endif