diff --git a/arch/arm/src/armv7-r/arm_head.S b/arch/arm/src/armv7-r/arm_head.S index 6813f1ba51c..a4bff790749 100644 --- a/arch/arm/src/armv7-r/arm_head.S +++ b/arch/arm/src/armv7-r/arm_head.S @@ -91,17 +91,25 @@ * - Clear .bss section (data should be fully initialized) */ -/* Beginning (BOTTOM) and End+1 (TOP) of the IDLE stack. +/* Beginning (BOTTOM/BASE) and End+1 (TOP) of the IDLE stack. * - * REVISIT: There are issues here. The stack point is initialized very - * early in the boot sequence, but in some architectures the memory supporting - * the may not be initialized (SDRAM, for example). In that case, ideally - * the IDLE stack should be in some other memory that does not require - * initialization (such as internal SRAM) + * The IDLE stack is the stack that is used during intialization and, + * eventually, becomes the stack of the IDLE task when initialization + * is complete. + * + * REVISIT: There are issues here in some configurations. The stack + * pointer is initialized very early in the boot sequence. But in some + * architectures the memory supporting the stack may not yet be + * initialized (SDRAM, for example, would not be ready yet). In that + * case, ideally the IDLE stack should be in some other memory that does + * not require initialization (such as internal SRAM) */ -#define IDLE_STACK_BASE _ebss -#define IDLE_STACK_TOP _ebss+CONFIG_IDLETHREAD_STACKSIZE +#ifndef IDLE_STACK_BASE +# define IDLE_STACK_BASE _ebss +#endif + +#define IDLE_STACK_TOP IDLE_STACK_BASE+CONFIG_IDLETHREAD_STACKSIZE /**************************************************************************** * Global Symbols diff --git a/arch/arm/src/tms570/chip/tms570_iomm.h b/arch/arm/src/tms570/chip/tms570_iomm.h new file mode 100644 index 00000000000..cbf38a3d862 --- /dev/null +++ b/arch/arm/src/tms570/chip/tms570_iomm.h @@ -0,0 +1,184 @@ +/**************************************************************************************************** + * arch/arm/src/tms570/chip/tms570_iomm.h + * I/O Muliplexing and Control Module (IOMM) Definitions + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * References: + * + * TMS570LS04x/03x 16/32-Bit RISC Flash Microcontroller, Technical Reference Manual, Texas + * Instruments, Literature Number: SPNU517A, September 2013 + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_TMS570_CHIP_TMS570_IOMM_H +#define __ARCH_ARM_SRC_TMS570_CHIP_TMS570_IOMM_H + +/**************************************************************************************************** + * Included Files + ****************************************************************************************************/ + +#include +#include "chip/tms570_memorymap.h" + +/**************************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************************/ + +/* Register Offsets *********************************************************************************/ + +#define TMS570_IOMM_REVISION_OFFSET 0x0000 /* Revision Register */ +#define TMS570_IOMM_BOOT_OFFSET 0x0020 /* Boot Mode Register */ +#define TMS570_IOMM_KICK0_OFFSET 0x0038 /* Kicker Register 0 */ +#define TMS570_IOMM_KICK1_OFFSET 0x003c /* Kicker Register 1 */ +#define TMS570_IOMM_ERRRAWSTATUS_OFFSET 0x00e0 /* Error Raw Status / Set Register */ +#define TMS570_IOMM_ERRSTATUS_OFFSET 0x00e4 /* Error Enabled Status / Clear Register */ +#define TMS570_IOMM_ERRENABLE_OFFSET 0x00e8 /* Error Signaling Enable Register */ +#define TMS570_IOMM_ERRENABLECLR_OFFSET 0x00ec /* Error Signaling Enable Clear Register */ +#define TMS570_IOMM_FAULTADDRESS_OFFSET 0x00f4 /* Fault Address Register */ +#define TMS570_IOMM_FAULTSTATUS_OFFSET 0x00f8 /* Fault Status Register */ +#define TMS570_IOMM_FAULTCLR_OFFSET 0x00fc /* Fault Clear Register */ + +#define TMS570_IOMM_PINMMR_OFFSET(n) (0x0110 + ((unsigned int)(n) << 2)) +# define TMS570_IOMM_PINMMR0_OFFSET 0x0110 /* Pin Multiplexing Control Register 0 */ +# define TMS570_IOMM_PINMMR1_OFFSET 0x0114 /* Pin Multiplexing Control Register 1 */ +# define TMS570_IOMM_PINMMR2_OFFSET 0x0118 /* Pin Multiplexing Control Register 2 */ +# define TMS570_IOMM_PINMMR3_OFFSET 0x011c /* Pin Multiplexing Control Register 3 */ +# define TMS570_IOMM_PINMMR4_OFFSET 0x0120 /* Pin Multiplexing Control Register 4 */ +# define TMS570_IOMM_PINMMR5_OFFSET 0x0124 /* Pin Multiplexing Control Register 5 */ +# define TMS570_IOMM_PINMMR6_OFFSET 0x0128 /* Pin Multiplexing Control Register 6 */ +# define TMS570_IOMM_PINMMR7_OFFSET 0x012c /* Pin Multiplexing Control Register 7 */ +# define TMS570_IOMM_PINMMR8_OFFSET 0x0130 /* Pin Multiplexing Control Register 8 */ +# define TMS570_IOMM_PINMMR9_OFFSET 0x0134 /* Pin Multiplexing Control Register 9 */ +# define TMS570_IOMM_PINMMR10_OFFSET 0x0138 /* Pin Multiplexing Control Register 10 */ +# define TMS570_IOMM_PINMMR11_OFFSET 0x013c /* Pin Multiplexing Control Register 11 */ +# define TMS570_IOMM_PINMMR12_OFFSET 0x0140 /* Pin Multiplexing Control Register 12 */ +# define TMS570_IOMM_PINMMR13_OFFSET 0x0144 /* Pin Multiplexing Control Register 13 */ +# define TMS570_IOMM_PINMMR14_OFFSET 0x0148 /* Pin Multiplexing Control Register 14 */ +# define TMS570_IOMM_PINMMR15_OFFSET 0x014c /* Pin Multiplexing Control Register 15 */ +# define TMS570_IOMM_PINMMR16_OFFSET 0x0150 /* Pin Multiplexing Control Register 16 */ +# define TMS570_IOMM_PINMMR17_OFFSET 0x0154 /* Pin Multiplexing Control Register 17 */ +# define TMS570_IOMM_PINMMR18_OFFSET 0x0158 /* Pin Multiplexing Control Register 18 */ +# define TMS570_IOMM_PINMMR19_OFFSET 0x015c /* Pin Multiplexing Control Register 19 */ +# define TMS570_IOMM_PINMMR20_OFFSET 0x0160 /* Pin Multiplexing Control Register 20 */ +# define TMS570_IOMM_PINMMR21_OFFSET 0x0164 /* Pin Multiplexing Control Register 21 */ +# define TMS570_IOMM_PINMMR22_OFFSET 0x0168 /* Pin Multiplexing Control Register 22 */ +# define TMS570_IOMM_PINMMR23_OFFSET 0x016c /* Pin Multiplexing Control Register 23 */ +# define TMS570_IOMM_PINMMR24_OFFSET 0x0170 /* Pin Multiplexing Control Register 24 */ +# define TMS570_IOMM_PINMMR25_OFFSET 0x0174 /* Pin Multiplexing Control Register 25 */ +# define TMS570_IOMM_PINMMR26_OFFSET 0x0178 /* Pin Multiplexing Control Register 26 */ +# define TMS570_IOMM_PINMMR27_OFFSET 0x017c /* Pin Multiplexing Control Register 27 */ +# define TMS570_IOMM_PINMMR28_OFFSET 0x0180 /* Pin Multiplexing Control Register 28 */ +# define TMS570_IOMM_PINMMR29_OFFSET 0x0184 /* Pin Multiplexing Control Register 29 */ +# define TMS570_IOMM_PINMMR30_OFFSET 0x0188 /* Pin Multiplexing Control Register 30 */ + +/* Register Addresses *******************************************************************************/ + +#define TMS570_IOMM_REVISION (TMS570_IOMM_BASE+TMS570_IOMM_REVISION_OFFSET) +#define TMS570_IOMM_BOOT (TMS570_IOMM_BASE+TMS570_IOMM_BOOT_OFFSET) +#define TMS570_IOMM_KICK0 (TMS570_IOMM_BASE+TMS570_IOMM_KICK0_OFFSET) +#define TMS570_IOMM_KICK1 (TMS570_IOMM_BASE+TMS570_IOMM_KICK1_OFFSET) +#define TMS570_IOMM_ERRRAWSTATUS (TMS570_IOMM_BASE+TMS570_IOMM_ERRRAWSTATUS_OFFSET) +#define TMS570_IOMM_ERRSTATUS (TMS570_IOMM_BASE+TMS570_IOMM_ERRSTATUS_OFFSET) +#define TMS570_IOMM_ERRENABLE (TMS570_IOMM_BASE+TMS570_IOMM_ERRENABLE_OFFSET) +#define TMS570_IOMM_ERRENABLECLR (TMS570_IOMM_BASE+TMS570_IOMM_ERRENABLECLR_OFFSET) +#define TMS570_IOMM_FAULTADDRESS (TMS570_IOMM_BASE+TMS570_IOMM_FAULTADDRESS_OFFSET) +#define TMS570_IOMM_FAULTSTATUS (TMS570_IOMM_BASE+TMS570_IOMM_FAULTSTATUS_OFFSET) +#define TMS570_IOMM_FAULTCLR (TMS570_IOMM_BASE+TMS570_IOMM_FAULTCLR_OFFSET) + +#define TMS570_IOMM_PINMMR(n) (TMS570_IOMM_BASE+TMS570_IOMM_PINMMR_OFFSET(n)) +# define TMS570_IOMM_PINMMR0 (TMS570_IOMM_BASE+TMS570_IOMM_PINMMR0_OFFSET) +# define TMS570_IOMM_PINMMR1 (TMS570_IOMM_BASE+TMS570_IOMM_PINMMR1_OFFSET) +# define TMS570_IOMM_PINMMR2 (TMS570_IOMM_BASE+TMS570_IOMM_PINMMR2_OFFSET) +# define TMS570_IOMM_PINMMR3 (TMS570_IOMM_BASE+TMS570_IOMM_PINMMR3_OFFSET) +# define TMS570_IOMM_PINMMR4 (TMS570_IOMM_BASE+TMS570_IOMM_PINMMR4_OFFSET) +# define TMS570_IOMM_PINMMR5 (TMS570_IOMM_BASE+TMS570_IOMM_PINMMR5_OFFSET) +# define TMS570_IOMM_PINMMR6 (TMS570_IOMM_BASE+TMS570_IOMM_PINMMR6_OFFSET) +# define TMS570_IOMM_PINMMR7 (TMS570_IOMM_BASE+TMS570_IOMM_PINMMR7_OFFSET) +# define TMS570_IOMM_PINMMR8 (TMS570_IOMM_BASE+TMS570_IOMM_PINMMR8_OFFSET) +# define TMS570_IOMM_PINMMR9 (TMS570_IOMM_BASE+TMS570_IOMM_PINMMR9_OFFSET) +# define TMS570_IOMM_PINMMR10 (TMS570_IOMM_BASE+TMS570_IOMM_PINMMR10_OFFSET) +# define TMS570_IOMM_PINMMR11 (TMS570_IOMM_BASE+TMS570_IOMM_PINMMR11_OFFSET) +# define TMS570_IOMM_PINMMR12 (TMS570_IOMM_BASE+TMS570_IOMM_PINMMR12_OFFSET) +# define TMS570_IOMM_PINMMR13 (TMS570_IOMM_BASE+TMS570_IOMM_PINMMR13_OFFSET) +# define TMS570_IOMM_PINMMR14 (TMS570_IOMM_BASE+TMS570_IOMM_PINMMR14_OFFSET) +# define TMS570_IOMM_PINMMR15 (TMS570_IOMM_BASE+TMS570_IOMM_PINMMR15_OFFSET) +# define TMS570_IOMM_PINMMR16 (TMS570_IOMM_BASE+TMS570_IOMM_PINMMR16_OFFSET) +# define TMS570_IOMM_PINMMR17 (TMS570_IOMM_BASE+TMS570_IOMM_PINMMR17_OFFSET) +# define TMS570_IOMM_PINMMR18 (TMS570_IOMM_BASE+TMS570_IOMM_PINMMR18_OFFSET) +# define TMS570_IOMM_PINMMR19 (TMS570_IOMM_BASE+TMS570_IOMM_PINMMR19_OFFSET) +# define TMS570_IOMM_PINMMR20 (TMS570_IOMM_BASE+TMS570_IOMM_PINMMR20_OFFSET) +# define TMS570_IOMM_PINMMR21 (TMS570_IOMM_BASE+TMS570_IOMM_PINMMR21_OFFSET) +# define TMS570_IOMM_PINMMR22 (TMS570_IOMM_BASE+TMS570_IOMM_PINMMR22_OFFSET) +# define TMS570_IOMM_PINMMR23 (TMS570_IOMM_BASE+TMS570_IOMM_PINMMR23_OFFSET) +# define TMS570_IOMM_PINMMR24 (TMS570_IOMM_BASE+TMS570_IOMM_PINMMR24_OFFSET) +# define TMS570_IOMM_PINMMR25 (TMS570_IOMM_BASE+TMS570_IOMM_PINMMR25_OFFSET) +# define TMS570_IOMM_PINMMR26 (TMS570_IOMM_BASE+TMS570_IOMM_PINMMR26_OFFSET) +# define TMS570_IOMM_PINMMR27 (TMS570_IOMM_BASE+TMS570_IOMM_PINMMR27_OFFSET) +# define TMS570_IOMM_PINMMR28 (TMS570_IOMM_BASE+TMS570_IOMM_PINMMR28_OFFSET) +# define TMS570_IOMM_PINMMR29 (TMS570_IOMM_BASE+TMS570_IOMM_PINMMR29_OFFSET) +# define TMS570_IOMM_PINMMR30 (TMS570_IOMM_BASE+TMS570_IOMM_PINMMR30_OFFSET) + +/* Register Bit-Field Definitions *******************************************************************/ + +/* Revision Register */ +#define IOMM_REVISION_ +/* Boot Mode Register */ +#define IOMM_BOOT_ +/* Kicker Register 0 */ +#define IOMM_KICK0_ +/* Kicker Register 1 */ +#define IOMM_KICK1_ +/* Error Raw Status / Set Register */ +#define IOMM_ERRRAWSTATUS_ +/* Error Enabled Status / Clear Register */ +#define IOMM_ERRSTATUS_ +/* Error Signaling Enable Register */ +#define IOMM_ERRENABLE_ +/* Error Signaling Enable Clear Register */ +#define IOMM_ERRENABLECLR_ +/* Fault Address Register */ +#define IOMM_FAULTADDRESS_ +/* Fault Status Register */ +#define IOMM_FAULTSTATUS_ +/* Fault Clear Register */ +#define IOMM_FAULTCLR_ + +/* Pin Multiplexing Control Register n, n=0..30. Each 8-bit field controls the functionality of + * one pin/ball. There are then a maximum of 31*4 = 124 pin/ball configurations supported. + */ + +#define IOMM_PINMMR_REGNDX(n) ((n) >> 2) +#define IOMM_PINMMR_PINSHIFT(n) (((n) & 3) << 3) +#define IOMM_PINMMR_PINMASK(n) (0xff << IOMM_PINMMR_PINSHIFT(n)) +# define IOMM_PINMMR_PINVALUE(n,v) ((uint32_t)(v) << IOMM_PINMMR_PINSHIFT(n)) + +#endif /* __ARCH_ARM_SRC_TMS570_CHIP_TMS570_IOMM_H */ diff --git a/arch/arm/src/tms570/chip/tms570_pinmux.h b/arch/arm/src/tms570/chip/tms570_pinmux.h new file mode 100644 index 00000000000..281fc09b9f0 --- /dev/null +++ b/arch/arm/src/tms570/chip/tms570_pinmux.h @@ -0,0 +1,76 @@ +/**************************************************************************************************** + * arch/arm/src/tms570/chip/tms570_pinmux.h + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_TMS570_CHIP_TMS570_PINMUX_H +#define __ARCH_ARM_SRC_TMS570_CHIP_TMS570_PINMUX_H + +/**************************************************************************************************** + * Included Files + ****************************************************************************************************/ + +#include + +#if defined(CONFIG_ARCH_CHIP_TMS570LS0232PZ) +# error No pin multiplexing for the TMS570LS0232PZ +#elif defined(CONFIG_ARCH_CHIP_TMS570LS0332PZ) +# include "chip/tms570ls04x03x_pinmux.h" +#elif defined(CONFIG_ARCH_CHIP_TMS570LS0432PZ) +# include "chip/tms570ls04x03x_pinmux.h" +#elif defined(CONFIG_ARCH_CHIP_TMS570LS0714PZ) +# error No pin multiplexing for the TMS570LS0714PZ +#elif defined(CONFIG_ARCH_CHIP_TMS570LS0714PGE) +# error No pin multiplexing for the TMS570LS0714PGE +#elif defined(CONFIG_ARCH_CHIP_TMS570LS0714ZWT) +# error No pin multiplexing for the TMS570LS0714ZWT +#elif defined(CONFIG_ARCH_CHIP_TMS570LS1227ZWT) +# error No pin multiplexing for the TMS570LS1227ZWT +#else +# error "Unrecognized Hercules chip" +#endif + +/**************************************************************************************************** + * Pulbic Type Definitions + ****************************************************************************************************/ + +/* Each chip-specific pinmux header file defines initializers for a type like: */ + +struct tms570_pinmux_s +{ + uint8_t mmrndx; /* Index to the PINMMR register, 0-30 */ + uint8_t shift; /* Shift value to isolate the pin field in the PINMMR register */ + uint8_t value; /* The new value for the pin field in the PINMMR register */ +}; + +#endif /* __ARCH_ARM_SRC_TMS570_CHIP_TMS570_PINMUX_H */ diff --git a/arch/arm/src/tms570/chip/tms570ls04x03x_pinmux.h b/arch/arm/src/tms570/chip/tms570ls04x03x_pinmux.h new file mode 100644 index 00000000000..113d9dfc757 --- /dev/null +++ b/arch/arm/src/tms570/chip/tms570ls04x03x_pinmux.h @@ -0,0 +1,257 @@ +/**************************************************************************************************** + * arch/arm/src/tms570/chip/tms570ls04x03x_pinmux.h + * Secondary System Control Register Definitions + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * References: + * + * TMS570LS04x/03x 16/32-Bit RISC Flash Microcontroller, Technical Reference Manual, Texas + * Instruments, Literature Number: SPNU517A, September 2013 + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_TMS570_CHIP_TMS570LS04X03X_PINMUX_H +#define __ARCH_ARM_SRC_TMS570_CHIP_TMS570LS04X03X_PINMUX_H + +/**************************************************************************************************** + * Included Files + ****************************************************************************************************/ + +#include +#include "chip/tms570_memorymap.h" + +/**************************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************************/ + +/* DEFAULT SELECTION ALTERNATE SELECTION ALTERNATE SELECTION BIT + * FUNCTION BIT FUNCTION 1 BIT FUNCTION 2 BIT + * + * GIOA[0] PINMMR0[8] SPI3nCS[3] PINMMR0[9] - - + * GIOA[1] PINMMR1[0] SPI3nCS[2] PINMMR1[1] - - + * GIOA[2] PINMMR1[8] SPI3nCS[1] PINMMR1[9] - - + * GIOA[3] PINMMR1[16] SPI2nCS[3] PINMMR1[17] - - + * GIOA[4] PINMMR1[24] SPI2nCS[2] PINMMR1[25] - - + * GIOA[5] PINMMR2[0] EXTCLKIN PINMMR2[1] - - + * GIOA[6] PINMMR2[8] SPI2nCS[1] PINMMR2[9] N2HET[31] PINMMR2[10] + * GIOA[7] PINMMR2[16] N2HET[29] PINMMR2[17] - - + * MIBSPI1nCS[2] PINMMR3[0] N2HET[20] PINMMR3[1] N2HET[19] PINMMR3[2] + * SPI3CLK PINMMR3[16] EQEPA PINMMR3[17] - - + * SPI3nENA PINMMR3[24] EQEPB PINMMR3[25] - - + * SPI3nCS[0] PINMMR4[0] EQEPI PINMMR4[1] - - + * MIBSPI1nCS[3] PINMMR4[8] N2HET[26] PINMMR4[9] - - + * ADEVT PINMMR4[16] N2HET[28] PINMMR4[17] - - + * MIBSPI1nENA PINMMR5[8] N2HET[23] PINMMR5[9] NHET[30] PINMMR5[10] + * MIBSPI1nCS[1] PINMMR6[8] EQEPS PINMMR6[9] N2HET[17] PINMMR6[10] + */ + +#define PINMUX_GIOA0_PINMMR 0 +#define PINMUX_GIOA0_SHIFT 8 +#define PINMUX_GIOA0_VALUE 1 +#define PINMUX_GIOA0_PIN {PINMUX_GIOA0_PINMMR, PINMUX_GIOA0_SHIFT, PINMUX_GIOA0_VALUE} + +#define PINMUX_SPI3NCS3_PINMMR 0 +#define PINMUX_SPI3NCS3_SHIFT 8 +#define PINMUX_SPI3NCS3_VALUE 2 +#define PINMUX_SPI3NCS3_PIN {PINMUX_SPI3NCS3_PINMMR, PINMUX_SPI3NCS3_SHIFT, PINMUX_SPI3NCS3_VALUE} + +#define PINMUX_GIOA1_PINMMR 1 +#define PINMUX_GIOA1_SHIFT 0 +#define PINMUX_GIOA1_VALUE 1 +#define PINMUX_GIOA1_PIN {PINMUX_GIOA1_PINMMR, PINMUX_GIOA1_SHIFT, PINMUX_GIOA1_VALUE} + +#define PINMUX_SPI3NCS2_PINMMR 1 +#define PINMUX_SPI3NCS2_SHIFT 0 +#define PINMUX_SPI3NCS2_VALUE 2 +#define PINMUX_SPI3NCS2_PIN {PINMUX_SPI3NCS2_PINMMR, PINMUX_SPI3NCS2_SHIFT, PINMUX_SPI3NCS2_VALUE} + +#define PINMUX_GIOA2_PINMMR 1 +#define PINMUX_GIOA2_SHIFT 8 +#define PINMUX_GIOA2_VALUE 1 +#define PINMUX_GIOA2_PIN {PINMUX_GIOA2_PINMMR, PINMUX_GIOA2_SHIFT, PINMUX_GIOA2_VALUE} + +#define PINMUX_SPI3NCS1_PINMMR 1 +#define PINMUX_SPI3NCS1_SHIFT 8 +#define PINMUX_SPI3NCS1_VALUE 2 +#define PINMUX_SPI3NCS1_PIN {PINMUX_SPI3NCS1_PINMMR, PINMUX_SPI3NCS1_SHIFT, PINMUX_SPI3NCS1_VALUE} + +#define PINMUX_GIOA3_PINMMR 1 +#define PINMUX_GIOA3_SHIFT 16 +#define PINMUX_GIOA3_VALUE 1 +#define PINMUX_GIOA3_PIN {PINMUX_GIOA3_PINMMR, PINMUX_GIOA3_SHIFT, PINMUX_GIOA3_VALUE} + +#define PINMUX_SPI2NCS3_PINMMR 1 +#define PINMUX_SPI2NCS3_SHIFT 16 +#define PINMUX_SPI2NCS3_VALUE 2 +#define PINMUX_SPI2NCS3_PIN {PINMUX_SPI2NCS3_PINMMR, PINMUX_SPI2NCS3_SHIFT, PINMUX_SPI2NCS3_VALUE} + +#define PINMUX_GIOA4_PINMMR 1 +#define PINMUX_GIOA4_SHIFT 24 +#define PINMUX_GIOA4_VALUE 1 +#define PINMUX_GIOA4_PIN {PINMUX_GIOA4_PINMMR, PINMUX_GIOA4_SHIFT, PINMUX_GIOA4_VALUE} + +#define PINMUX_SPI2NCS2_PINMMR 1 +#define PINMUX_SPI2NCS2_SHIFT 24 +#define PINMUX_SPI2NCS2_VALUE 2 +#define PINMUX_SPI2NCS2_PIN {PINMUX_SPI2NCS2_PINMMR, PINMUX_SPI2NCS2_SHIFT, PINMUX_SPI2NCS2_VALUE} + +#define PINMUX_GIOA5_PINMMR 2 +#define PINMUX_GIOA5_SHIFT 0 +#define PINMUX_GIOA5_VALUE 1 +#define PINMUX_GIOA5_PIN {PINMUX_GIOA5_PINMMR, PINMUX_GIOA5_SHIFT, PINMUX_GIOA5_VALUE} + +#define PINMUX_EXTCLKIN_PINMMR 2 +#define PINMUX_EXTCLKIN_SHIFT 0 +#define PINMUX_EXTCLKIN_VALUE 2 +#define PINMUX_EXTCLKIN_PIN {PINMUX_EXTCLKIN_PINMMR, PINMUX_EXTCLKIN_SHIFT, PINMUX_EXTCLKIN_VALUE} + +#define PINMUX_GIOA6_PINMMR 2 +#define PINMUX_GIOA6_SHIFT 8 +#define PINMUX_GIOA6_VALUE 1 +#define PINMUX_GIOA6_PIN {PINMUX_GIOA6_PINMMR, PINMUX_GIOA6_SHIFT, PINMUX_GIOA6_VALUE} + +#define PINMUX_SPI2NCS1_PINMMR 2 +#define PINMUX_SPI2NCS1_SHIFT 8 +#define PINMUX_SPI2NCS1_VALUE 2 +#define PINMUX_SPI2NCS1_PIN {PINMUX_SPI2NCS1_PINMMR, PINMUX_SPI2NCS1_SHIFT, PINMUX_SPI2NCS1_VALUE} + +#define PINMUX_N2HET31_PINMMR 2 +#define PINMUX_N2HET31_SHIFT 8 +#define PINMUX_N2HET31_VALUE 4 +#define PINMUX_N2HET31_PIN {PINMUX_N2HET31_PINMMR, PINMUX_N2HET31_SHIFT, PINMUX_N2HET31_VALUE} + +#define PINMUX_GIOA7_PINMMR 2 +#define PINMUX_GIOA7_SHIFT 16 +#define PINMUX_GIOA7_VALUE 1 +#define PINMUX_GIOA7_PIN {PINMUX_GIOA7_PINMMR, PINMUX_GIOA7_SHIFT, PINMUX_GIOA7_VALUE} + +#define PINMUX_N2HET29_PINMMR 2 +#define PINMUX_N2HET29_SHIFT 16 +#define PINMUX_N2HET29_VALUE 2 +#define PINMUX_N2HET29_PIN {PINMUX_N2HET29_PINMMR, PINMUX_N2HET29_SHIFT, PINMUX_N2HET29_VALUE} + +#define PINMUX_MIBSPI1NCS2_PINMMR 3 +#define PINMUX_MIBSPI1NCS2_SHIFT 0 +#define PINMUX_MIBSPI1NCS2_VALUE 1 +#define PINMUX_MIBSPI1NCS2_PIN {PINMUX_MIBSPI1NCS2_PINMMR, PINMUX_MIBSPI1NCS2_SHIFT, PINMUX_MIBSPI1NCS2_VALUE} + +#define PINMUX_N2HET20_PINMMR 3 +#define PINMUX_N2HET20_SHIFT 0 +#define PINMUX_N2HET20_VALUE 2 +#define PINMUX_N2HET20_PIN {PINMUX_N2HET20_PINMMR, PINMUX_N2HET20_SHIFT, PINMUX_N2HET20_VALUE} + +#define PINMUX_N2HET19_PINMMR 3 +#define PINMUX_N2HET19_SHIFT 0 +#define PINMUX_N2HET19_VALUE 4 +#define PINMUX_N2HET19_PIN {PINMUX_N2HET19_PINMMR, PINMUX_N2HET19_SHIFT, PINMUX_N2HET19_VALUE} + +#define PINMUX_SPI3CLK_PINMMR 3 +#define PINMUX_SPI3CLK_SHIFT 16 +#define PINMUX_SPI3CLK_VALUE 1 +#define PINMUX_SPI3CLK_PIN {PINMUX_SPI3CLK_PINMMR, PINMUX_SPI3CLK_SHIFT, PINMUX_N2HET20_VALUE} + +#define PINMUX_EQEPA_PINMMR 3 +#define PINMUX_EQEPA_SHIFT 16 +#define PINMUX_EQEPA_VALUE 2 +#define PINMUX_EQEPA_PIN {PINMUX_EQEPA_PINMMR, PINMUX_EQEPA_SHIFT, PINMUX_EQEPA_VALUE} + +#define PINMUX_SPI3NENA_PINMMR 3 +#define PINMUX_SPI3NENA_SHIFT 24 +#define PINMUX_SPI3NENA_VALUE 1 +#define PINMUX_SPI3NENA_PIN {PINMUX_SPI3NENA_PINMMR, PINMUX_SPI3NENA_SHIFT, PINMUX_SPI3NENA_VALUE} + +#define PINMUX_EQEPB_PINMMR 3 +#define PINMUX_EQEPB_SHIFT 24 +#define PINMUX_EQEPB_VALUE 2 +#define PINMUX_EQEPB_PIN {PINMUX_EQEPB_PINMMR, PINMUX_EQEPB_SHIFT, PINMUX_EQEPB_VALUE} + +#define PINMUX_SPI3NCS0_PINMMR 4 +#define PINMUX_SPI3NCS0_SHIFT 0 +#define PINMUX_SPI3NCS0_VALUE 1 +#define PINMUX_SPI3NCS0_PIN {PINMUX_SPI3NCS0_PINMMR, PINMUX_SPI3NCS0_SHIFT, PINMUX_SPI3NCS0_VALUE} + +#define PINMUX_EQEPI_PINMMR 4 +#define PINMUX_EQEPI_SHIFT 0 +#define PINMUX_EQEPI_VALUE 2 +#define PINMUX_EQEPI_PIN {PINMUX_EQEPI_PINMMR, PINMUX_EQEPI_SHIFT, PINMUX_EQEPI_VALUE} + +#define PINMUX_MIBSPI1NCS3_PINMMR 4 +#define PINMUX_MIBSPI1NCS3_SHIFT 8 +#define PINMUX_MIBSPI1NCS3_VALUE 1 +#define PINMUX_MIBSPI1NCS3_PIN {PINMUX_MIBSPI1NCS3_PINMMR, PINMUX_MIBSPI1NCS3_SHIFT, PINMUX_MIBSPI1NCS3_VALUE} + +#define PINMUX_N2HET26_PINMMR 4 +#define PINMUX_N2HET26_SHIFT 8 +#define PINMUX_N2HET26_VALUE 2 +#define PINMUX_N2HET26_PIN {PINMUX_N2HET26_PINMMR, PINMUX_N2HET26_SHIFT, PINMUX_N2HET26_VALUE} + +#define PINMUX_ADEVT_PINMMR 4 +#define PINMUX_ADEVT_SHIFT 16 +#define PINMUX_ADEVT_VALUE 1 +#define PINMUX_ADEVT_PIN {PINMUX_ADEVT_PINMMR, PINMUX_ADEVT_SHIFT, PINMUX_ADEVT_VALUE} + +#define PINMUX_N2HET28_PINMMR 4 +#define PINMUX_N2HET28_SHIFT 16 +#define PINMUX_N2HET28_VALUE 2 +#define PINMUX_N2HET28_PIN {PINMUX_N2HET28_PINMMR, PINMUX_N2HET28_SHIFT, PINMUX_N2HET28_VALUE} + +#define PINMUX_MIBSPI1NENA_PINMMR 5 +#define PINMUX_MIBSPI1NENA_SHIFT 8 +#define PINMUX_MIBSPI1NENA_VALUE 1 +#define PINMUX_MIBSPI1NENA_PIN {PINMUX_MIBSPI1NENA_PINMMR, PINMUX_MIBSPI1NENA_SHIFT, PINMUX_MIBSPI1NENA_VALUE} + +#define PINMUX_N2HET23_PINMMR 5 +#define PINMUX_N2HET23_SHIFT 8 +#define PINMUX_N2HET23_VALUE 2 +#define PINMUX_N2HET23_PIN {PINMUX_N2HET23_PINMMR, PINMUX_N2HET23_SHIFT, PINMUX_N2HET23_VALUE} + +#define PINMUX_N2HET30_PINMMR 5 +#define PINMUX_N2HET30_SHIFT 8 +#define PINMUX_N2HET30_VALUE 4 +#define PINMUX_N2HET30_PIN {PINMUX_N2HET30_PINMMR, PINMUX_N2HET30_SHIFT, PINMUX_N2HET30_VALUE} + +#define PINMUX_MIBSPI1NCS1_PINMMR 6 +#define PINMUX_MIBSPI1NCS1_SHIFT 8 +#define PINMUX_MIBSPI1NCS1_VALUE 1 +#define PINMUX_MIBSPI1NCS1_PIN {PINMUX_MIBSPI1NCS1_PINMMR, PINMUX_MIBSPI1NCS1_SHIFT, PINMUX_MIBSPI1NCS1_VALUE} + +#define PINMUX_EQEPS_PINMMR 6 +#define PINMUX_EQEPS_SHIFT 8 +#define PINMUX_EQEPS_VALUE 2 +#define PINMUX_EQEPS_PIN {PINMUX_EQEPS_PINMMR, PINMUX_EQEPS_SHIFT, PINMUX_EQEPS_VALUE} + +#define PINMUX_N2HET17_PINMMR 6 +#define PINMUX_N2HET17_SHIFT 8 +#define PINMUX_N2HET17_VALUE 4 +#define PINMUX_N2HET17_PIN {PINMUX_N2HET17_PINMMR, PINMUX_N2HET17_SHIFT, PINMUX_N2HET17_VALUE} + +#endif /* __ARCH_ARM_SRC_TMS570_CHIP_TMS570LS04X03X_PINMUX_H */ diff --git a/arch/arm/src/tms570/tms570_clockconfig.c b/arch/arm/src/tms570/tms570_clockconfig.c index ca40dc1a177..ec5206d8e5f 100644 --- a/arch/arm/src/tms570/tms570_clockconfig.c +++ b/arch/arm/src/tms570/tms570_clockconfig.c @@ -47,15 +47,28 @@ #include -#include - #include "up_arch.h" #include "chip/tms570_sys.h" #include "chip/tms570_pcr.h" #include "chip/tms570_flash.h" +#include "chip/tms570_iomm.h" +#include "chip/tms570_pinmux.h" #include "tms570_clockconfig.h" +#include + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct tms570_pinmux_s g_pinmux_table[] = +{ + BOARD_PINMUX_INITIALIZER +}; + +#define NPINMUX (sizeof(g_pinmux_table) / sizeof(struct tms570_pinmux_s)) + /**************************************************************************** * Private Functions ****************************************************************************/ @@ -208,6 +221,44 @@ static void tms570_peripheral_initialize(void) putreg32(clkcntl, TMS570_SYS_CLKCNTL); } +/**************************************************************************** + * Name: tms570_pin_multiplex + * + * Description: + * Configure the field for a single pin in a PINMMR register + * + ****************************************************************************/ + +static void tms570_pin_multiplex(FAR const struct tms570_pinmux_s *pinmux) +{ + uintptr_t regaddr; + uint32_t regval; + + regaddr = TMS570_IOMM_PINMMR(pinmux->mmrndx); + regval = getreg32(regaddr); + regval &= ~(0xff << pinmux->shift); + regval |= ((uint32_t)(pinmux->value) << pinmux->shift); + putreg32(regval, regaddr); +} + +/**************************************************************************** + * Name: tms570_io_multiplex + * + * Description: + * Configure the all pins in the board-provided pinmux table. + * + ****************************************************************************/ + +static void tms570_io_multiplex(void) +{ + int i; + + for (i = 0; i < NPINMUX; i++) + { + tms570_pin_multiplex(&g_pinmux_table[i]); + } +} + /**************************************************************************** * Name: tms570_lpo_trim * @@ -457,7 +508,8 @@ void tms570_clockconfig(void) tms570_peripheral_initialize(); /* Configure device-level multiplexing and I/O multiplexing */ -#warning Missing Logic + + tms570_io_multiplex(); #ifdef CONFIG_TMS570_SELFTEST /* Wait for eFuse controller self-test to complete and check results */