More trailing whilespace removal

arch/8051/include/irq.h

@@ -160,7 +160,7 @@ struct xcptcontext
 
    uint8_t nbytes;
 
-   /* This is the saved stack.  Space is allocated for the 
+   /* This is the saved stack.  Space is allocated for the
     * entire 256 byte IRAM (minus register and bit usage at
     * the beginning).
     */

arch/8051/include/limits.h

@@ -33,8 +33,8 @@
  *
  ************************************************************/
 
-#ifndef __ARCH_8051_INCLUDE_LIMITS_H 
+#ifndef __ARCH_8051_INCLUDE_LIMITS_H
-#define __ARCH_8051_INCLUDE_LIMITS_H 
+#define __ARCH_8051_INCLUDE_LIMITS_H
 
 /************************************************************
  * Included Files

arch/8051/include/types.h

@@ -37,8 +37,8 @@
  * only indirectly through sys/types.h
  */
 
-#ifndef __ARCH_8051_INCLUDE_TYPES_H 
+#ifndef __ARCH_8051_INCLUDE_TYPES_H
-#define __ARCH_8051_INCLUDE_TYPES_H 
+#define __ARCH_8051_INCLUDE_TYPES_H
 
 /************************************************************************
  * Included Files

arch/8051/src/Makefile.sdccl

@@ -200,7 +200,7 @@ up_mem.h: pass1.mem
 libarch$(LIBEXT): up_mem.h $(OBJS)
 	$(call ARCHIVE, $@, $(OBJS))
 
-# This builds the libboard library in the board/ subdirectory 
+# This builds the libboard library in the board/ subdirectory
 
 board/libboard$(LIBEXT):
 	$(Q) $(MAKE) -C board TOPDIR="$(TOPDIR)" libboard$(LIBEXT) EXTRADEFINES=$(EXTRADEFINES)

arch/8051/src/up_blocktask.c

@@ -131,7 +131,7 @@ void up_block_task(FAR struct tcb_s *tcb, tstate_t task_state)
 
           up_saveirqcontext(&tcb->xcp);
 
-          /* Restore the exception context of the rtcb at the (new) head 
+          /* Restore the exception context of the rtcb at the (new) head
            * of the g_readytorun task list.
            */
 
@@ -152,7 +152,7 @@ void up_block_task(FAR struct tcb_s *tcb, tstate_t task_state)
 
       else if (!up_savecontext(&rtcb->xcp))
         {
-          /* Restore the exception context of the rtcb at the (new) head 
+          /* Restore the exception context of the rtcb at the (new) head
            * of the g_readytorun task list.
            */
 

arch/8051/src/up_head.S

@@ -178,7 +178,7 @@ _up_timer0:
 	push	ie
 	clr	ea
 
-	/* Save the remaining registers with interrupts disabled 
+	/* Save the remaining registers with interrupts disabled
 	 *
 	 * a, ie, and dptr go on the stack.
 	 */
@@ -232,7 +232,7 @@ _up_interrupt:
 	push	ie
 	clr	ea
 
-	/* Save the remaining registers with interrupts disabled 
+	/* Save the remaining registers with interrupts disabled
 	 *
 	 * a, ie, and dptr go on the stack.
 	 */

arch/8051/src/up_initialize.c

@@ -86,7 +86,7 @@ FAR struct xcptcontext *g_irqcontext;
  * to comput them.
  */
 
-const uint8_t g_ntobit[8] = 
+const uint8_t g_ntobit[8] =
   { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 };
 
 /************************************************************************

arch/8051/src/up_irqtest.c

@@ -72,7 +72,7 @@ bool g_irqtest;
 volatile uint8_t g_irqtos;
 uint8_t g_irqregs[REGS_SIZE];
 int g_nirqs;
-FAR struct xcptcontext *g_irqcontext; 
+FAR struct xcptcontext *g_irqcontext;
 
 /************************************************************************
  * Private Functions

arch/8051/src/up_putc.c

@@ -76,6 +76,6 @@ int up_putc(int ch)
     {
       _up_putc('\r');
     }
-  return ch;  
+  return ch;
 }
 

arch/8051/src/up_releasepending.c

@@ -98,7 +98,7 @@ void up_release_pending(void)
 
            up_saveirqcontext(&rtcb->xcp);
 
-          /* Restore the exception context of the rtcb at the (new) head 
+          /* Restore the exception context of the rtcb at the (new) head
            * of the g_readytorun task list.
            */
 
@@ -114,13 +114,13 @@ void up_release_pending(void)
 
       /* Copy the exception context into the TCB of the task that
        * was currently active. if up_savecontext returns a non-zero
-       * value, then this is really the previously running task 
+       * value, then this is really the previously running task
        * restarting!
        */
 
       else if (!up_savecontext(&rtcb->xcp))
         {
-          /* Restore the exception context of the rtcb at the (new) head 
+          /* Restore the exception context of the rtcb at the (new) head
            * of the g_readytorun task list.
            */
 

arch/8051/src/up_reprioritizertr.c

@@ -70,7 +70,7 @@
  *
  * Description:
  *   Called when the priority of a running or
- *   ready-to-run task changes and the reprioritization will 
+ *   ready-to-run task changes and the reprioritization will
  *   cause a context switch.  Two cases:
  *
  *   1) The priority of the currently running task drops and the next
@@ -153,7 +153,7 @@ void up_reprioritize_rtr(FAR struct tcb_s *tcb, uint8_t priority)
 
                up_saveirqcontext(&tcb->xcp);
 
-              /* Restore the exception context of the rtcb at the (new) head 
+              /* Restore the exception context of the rtcb at the (new) head
                * of the g_readytorun task list.
                */
 
@@ -174,7 +174,7 @@ void up_reprioritize_rtr(FAR struct tcb_s *tcb, uint8_t priority)
 
           else if (!up_savecontext(&rtcb->xcp))
             {
-              /* Restore the exception context of the rtcb at the (new) head 
+              /* Restore the exception context of the rtcb at the (new) head
                * of the g_readytorun task list.
                */
 

arch/8051/src/up_restorecontext.c

@@ -276,7 +276,7 @@ void up_restorecontext(FAR struct xcptcontext *context) __naked
 	/* Restore registers from the new stack */
 
 	pop	dph
-	pop	dpl 
+	pop	dpl
 
 	/* Restore the interrupt state per the stored IE value */
 

arch/8051/src/up_unblocktask.c

@@ -112,7 +112,7 @@ void up_unblock_task(FAR struct tcb_s *tcb)
       /* The currently active task has changed! We need to do
        * a context switch to the new task.
        *
-       * Are we in an interrupt handler? 
+       * Are we in an interrupt handler?
        */
 
       if (g_irqtos)
@@ -123,7 +123,7 @@ void up_unblock_task(FAR struct tcb_s *tcb)
 
            up_saveirqcontext(&rtcb->xcp);
 
-          /* Restore the exception context of the rtcb at the (new) head 
+          /* Restore the exception context of the rtcb at the (new) head
            * of the g_readytorun task list.
            */
 
@@ -138,7 +138,7 @@ void up_unblock_task(FAR struct tcb_s *tcb)
         }
 
       /* We are not in an interrupt andler.  Copy the user C context
-       * into the TCB of the task that was previously active.  if 
+       * into the TCB of the task that was previously active.  if
        * up_savecontext returns a non-zero value, then this is really the
        * previously running task restarting!
        */

arch/README.txt

@@ -171,7 +171,7 @@ arch/arm - ARM-based micro-controllers
         is complete on the basic port (timer, serial console, SPI).
 
     arch/arm/include/lm and arch/arm/src/lm
-        These directories contain support for the Luminary LM3S/4F family. The 
+        These directories contain support for the Luminary LM3S/4F family. The
         initial, release of this port was included in NuttX version 0.4.6.  The
         current port includes timer, serial console, Ethernet, SSI, and microSD
         support. There are working configurations the NuttX OS test, to run the
@@ -211,7 +211,7 @@ arch/arm - ARM-based micro-controllers
         STATUS: The basic AT91SAM3U port was released in NuttX version 5.1.
         The basic port includes boot-up logic, interrupt driven serial
         console, and system timer interrupts. That release passes the
-        NuttX OS test and is proven to have a valid OS implementation. A 
+        NuttX OS test and is proven to have a valid OS implementation. A
         onfiguration to support the NuttShell is also included.
 
     arch/arm/include/stm32 and arch/arm/src/stm32

arch/arm/include/a1x/a10_irq.h

@@ -48,7 +48,7 @@
  * Pre-Processor Definitions
  ****************************************************************************************/
 
-/* External interrupts numbers */ 
+/* External interrupts numbers */
 
 #define A1X_IRQ_NMI         0 /* External Non-Mask Interrupt */
 #  define A1X_IRQ_POWER     0 /* Power module */

arch/arm/include/armv7-a/irq.h

@@ -60,7 +60,7 @@
  *   (1) stmia rx, {r0-r14}
  *   (2) then the PC and CPSR
  *
- * This results in the following set of indices that can be used to access 
+ * This results in the following set of indices that can be used to access
  * individual registers in the xcp.regs array:
  */
 

arch/arm/include/armv7-m/irq_cmnvector.h

@@ -70,7 +70,7 @@
 #ifdef CONFIG_ARCH_FPU
 
 /* If the MCU supports a floating point unit, then it will be necessary
- * to save the state of the non-volatile registers before calling code 
+ * to save the state of the non-volatile registers before calling code
  * that may save and overwrite them.
  */
 

arch/arm/include/elf.h

@@ -64,7 +64,7 @@
 #define EF_ARM_EABI_VER4         0x04000000
 #define EF_ARM_EABI_VER5         0x05000000
 
-#define EF_ARM_BE8               0x00800000 
+#define EF_ARM_BE8               0x00800000
 
 /* Table 4-4, Processor specific section types */
 

arch/arm/include/lpc2378/irq.h

@@ -56,7 +56,7 @@
 /****************************************************************************
  * Definitions
  ****************************************************************************/
- 
+
 /* LPC2378 Interrupts */
 
 #define WDT_IRQ        0 /* Watchdog */

arch/arm/include/lpc43xx/irq.h

@@ -51,7 +51,7 @@
 /********************************************************************************************
  * Pre-processor Definitions
  ********************************************************************************************/
- 
+
 /* IRQ numbers.  The IRQ number corresponds vector number and hence map directly to bits in
  * the NVIC.  This does, however, waste several words of memory in the IRQ to handle mapping
  * tables.

arch/arm/include/nuc1xx/nuc120_irq.h

@@ -82,7 +82,7 @@
 #define NUC_IRQ_ADC    (45) /* ADC */
                             /* 46: Reserved */
 #define NUC_IRQ_RTC    (47) /* Real time clock */
- 
+
 #define NR_IRQS        (48)
 
 /************************************************************************************

arch/arm/include/sama5/chip.h

@@ -46,7 +46,7 @@
  * Pre-processor Definitions
  ****************************************************************************************************/
 /* SAMA5D3 Family
- * 
+ *
  *                           ATSAMA5D31    ATSAMA5D33    ATSAMA5D34    ATSAMA5D35    ATSAMA5D36
  * ------------------------- ------------- ------------- ------------- ------------- -------------
  * Pin Count                 324           324           324           324           324

arch/arm/src/a1x/a1x_pio.c

@@ -113,7 +113,7 @@ static int a1x_pio_interrupt(int irq, void *context)
   int irq;
 
   /* Read the set of pending GPIO interrupts */
-  
+
   status  = getreg32(A1X_PIO_INT_STA);
   mask    = getreg32(A1X_PIO_INT_CTL);
   pending = status & mask;

arch/arm/src/a1x/a1x_timerisr.c

@@ -120,7 +120,7 @@ void up_timerinit(void)
   uint32_t regval;
 
   /* Set the timer reload interval value */
- 
+
   putreg32(TMR_INTERVAL, A1X_TMR0_INTV_VALUE);
 
   /* Configure timer 0:

arch/arm/src/arm/arm.h

@@ -332,7 +332,7 @@ static inline unsigned int get_cp15c3(void)
  * ARM926EJ-S operation:  Invalidate set-associative
  * Data:                  Should be zero
  */
- 
+
 static inline void tlb_invalidate(void)
 {
   unsigned int sbz = 0;

arch/arm/src/arm/pg_macros.h

@@ -183,7 +183,7 @@
  * larger than the size of the physical paged region.  That is the
  * core of what the On-Demanding Paging feature provides.
  */
- 
+
 #define PG_L1_PAGED_PADDR       (PGTABLE_BASE_PADDR + ((PG_PAGED_VBASE >> 20) << 2))
 #define PG_L1_PAGED_VADDR       (PGTABLE_BASE_VADDR + ((PG_PAGED_VBASE >> 20) << 2))
 
@@ -261,10 +261,10 @@
 /* Case 2: Vectors are in low memory and the locked text region starts at
  * the beginning of SRAM (which will be aliased to address 0x00000000).
  * However, the beginning of SRAM may not be aligned to the beginning
- * of the L2 page table (because the beginning of RAM is offset into 
+ * of the L2 page table (because the beginning of RAM is offset into
  * the table.
  */
- 
+
 #elif defined(CONFIG_ARCH_LOWVECTORS) && !defined(CONFIG_PAGING_LOCKED_PBASE)
 #  define PG_VECT_PBASE         PG_LOCKED_PBASE
 #  define PG_L2_VECT_OFFSET     (((PG_LOCKED_VBASE & 0x000fffff) >> PAGESHIFT) << 2)
@@ -327,7 +327,7 @@
  *                            text region (the address at the beginning of
  *                            the page).
  * PG_POOL_MAXL2NDX         - This is the maximum value+1 of such an index.
- * 
+ *
  * PG_POOL_PGPADDR(ndx)     - Converts an page index into the corresponding
  *                            (physical) address of the backing page memory.
  * PG_POOL_PGVADDR(ndx)     - Converts an page index into the corresponding
@@ -340,7 +340,7 @@
  * written.
  */
 
-#define PG_POOL_VA2L1OFFSET(va) (((va) >> 20) << 2) 
+#define PG_POOL_VA2L1OFFSET(va) (((va) >> 20) << 2)
 #define PG_POOL_VA2L1VADDR(va)  (PGTABLE_BASE_VADDR + PG_POOL_VA2L1OFFSET(va))
 #define PG_POOL_L12PPTABLE(L1)  ((L1) & PG_L1_PADDRMASK)
 #define PG_POOL_L12VPTABLE(L1)  (PG_POOL_L12PPTABLE(L1) - PGTABLE_BASE_PADDR + PGTABLE_BASE_VADDR)
@@ -442,7 +442,7 @@
  *   follows:
  *
  *	ldr	r0, =PG_L1_PGTABLE_PADDR	<-- Address in the L1 table
- *	ldr	r1, =PG_L2_PGTABLE_PADDR	<-- Physical address of L2 page table 
+ *	ldr	r1, =PG_L2_PGTABLE_PADDR	<-- Physical address of L2 page table
  *	ldr	r2, =PG_PGTABLE_NPAGES		<-- Total number of pages
  *	ldr	r3, =PG_PGTABLE_NPAGE1		<-- Number of pages in the first PTE
  *      ldr	r4, =MMU_L1_PGTABFLAGS		<-- L1 MMU flags

arch/arm/src/arm/up_allocpage.c

@@ -171,7 +171,7 @@ int up_allocpage(FAR struct tcb_s *tcb, FAR void **vpage)
   uintptr_t paddr;
   uint32_t *pte;
   unsigned int pgndx;
-  
+
   /* Since interrupts are disabled, we don't need to anything special. */
 
   DEBUGASSERT(tcb && vpage);
@@ -199,7 +199,7 @@ int up_allocpage(FAR struct tcb_s *tcb, FAR void **vpage)
   if (g_pgwrap)
     {
       /* Yes.. Get a pointer to the L2 entry corresponding to the previous
-       * mapping -- then zero it!  
+       * mapping -- then zero it!
        */
 
        uintptr_t oldvaddr = PG_POOL_NDX2VA(g_ptemap[pgndx]);
@@ -214,7 +214,7 @@ int up_allocpage(FAR struct tcb_s *tcb, FAR void **vpage)
        * case:  The I-Cache uses a virtual address index and, hence, since the
        * NuttX address space is flat, the cached instruction value should be
        * correct even if the page mapping is no longer in place.
-       */ 
+       */
     }
 
   /* Then convert the index to a (physical) page address. */
@@ -231,7 +231,7 @@ int up_allocpage(FAR struct tcb_s *tcb, FAR void **vpage)
   *pte = (paddr | MMU_L2_ALLOCFLAGS);
 
   /* And save the new L1 index */
- 
+
   g_ptemap[pgndx] = PG_POOL_VA2L2NDX(vaddr);
 
   /* Finally, return the virtual address of allocated page */

arch/arm/src/arm/up_blocktask.c

@@ -130,7 +130,7 @@ void up_block_task(struct tcb_s *tcb, tstate_t task_state)
 
           up_savestate(rtcb->xcp.regs);
 
-          /* Restore the exception context of the rtcb at the (new) head 
+          /* Restore the exception context of the rtcb at the (new) head
            * of the g_readytorun task list.
            */
 
@@ -148,7 +148,7 @@ void up_block_task(struct tcb_s *tcb, tstate_t task_state)
 
       else if (!up_saveusercontext(rtcb->xcp.regs))
         {
-          /* Restore the exception context of the rtcb at the (new) head 
+          /* Restore the exception context of the rtcb at the (new) head
            * of the g_readytorun task list.
            */
 

arch/arm/src/arm/up_cache.S

@@ -88,7 +88,7 @@
  * Wait for interrupt SBZ                              MCR p15, 0, <Rd>, c7, c0, 4
  */
 
-/* Esure coherency between the Icache and the Dcache in the region described 
+/* Esure coherency between the Icache and the Dcache in the region described
  * by r0=start and r1=end.  Cleans the corresponding D-cache lines and invalidates
  * the corresponding I-Cache lines.
  */

arch/arm/src/arm/up_dataabort.c

@@ -56,7 +56,7 @@
  * Pre-processor Definitions
  ****************************************************************************/
 
-/* Output debug info if stack dump is selected -- even if 
+/* Output debug info if stack dump is selected -- even if
  * debug is not selected.
  */
 
@@ -139,7 +139,7 @@ void up_dataabort(uint32_t *regs, uint32_t far, uint32_t fsr)
    * the exception occurred, this address was provided in the FAR register.
    * (It has not yet been saved in the register context save area).
    */
- 
+
   pgllvdbg("VBASE: %08x VEND: %08x\n", PG_PAGED_VBASE, PG_PAGED_VEND);
   if (far < PG_PAGED_VBASE || far >= PG_PAGED_VEND)
     {

arch/arm/src/arm/up_prefetchabort.c

@@ -56,7 +56,7 @@
 
 /* Debug ********************************************************************/
 
-/* Output debug info if stack dump is selected -- even if 
+/* Output debug info if stack dump is selected -- even if
  * debug is not selected.
  */
 

arch/arm/src/arm/up_releasepending.c

@@ -97,7 +97,7 @@ void up_release_pending(void)
 
            up_savestate(rtcb->xcp.regs);
 
-          /* Restore the exception context of the rtcb at the (new) head 
+          /* Restore the exception context of the rtcb at the (new) head
            * of the g_readytorun task list.
            */
 
@@ -111,13 +111,13 @@ void up_release_pending(void)
 
       /* Copy the exception context into the TCB of the task that
        * was currently active. if up_saveusercontext returns a non-zero
-       * value, then this is really the previously running task 
+       * value, then this is really the previously running task
        * restarting!
        */
 
       else if (!up_saveusercontext(rtcb->xcp.regs))
         {
-          /* Restore the exception context of the rtcb at the (new) head 
+          /* Restore the exception context of the rtcb at the (new) head
            * of the g_readytorun task list.
            */
 

arch/arm/src/arm/up_reprioritizertr.c

@@ -69,7 +69,7 @@
  *
  * Description:
  *   Called when the priority of a running or
- *   ready-to-run task changes and the reprioritization will 
+ *   ready-to-run task changes and the reprioritization will
  *   cause a context switch.  Two cases:
  *
  *   1) The priority of the currently running task drops and the next
@@ -152,7 +152,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority)
 
                up_savestate(rtcb->xcp.regs);
 
-              /* Restore the exception context of the rtcb at the (new) head 
+              /* Restore the exception context of the rtcb at the (new) head
                * of the g_readytorun task list.
                */
 
@@ -171,7 +171,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority)
 
           else if (!up_saveusercontext(rtcb->xcp.regs))
             {
-              /* Restore the exception context of the rtcb at the (new) head 
+              /* Restore the exception context of the rtcb at the (new) head
                * of the g_readytorun task list.
                */
 

arch/arm/src/arm/up_syscall.c

@@ -50,7 +50,7 @@
  * Pre-processor Definitions
  ****************************************************************************/
 
-/* Output debug info if stack dump is selected -- even if 
+/* Output debug info if stack dump is selected -- even if
  * debug is not selected.
  */
 

arch/arm/src/arm/up_unblocktask.c

@@ -109,7 +109,7 @@ void up_unblock_task(struct tcb_s *tcb)
       /* The currently active task has changed! We need to do
        * a context switch to the new task.
        *
-       * Are we in an interrupt handler? 
+       * Are we in an interrupt handler?
        */
 
       if (current_regs)
@@ -120,7 +120,7 @@ void up_unblock_task(struct tcb_s *tcb)
 
           up_savestate(rtcb->xcp.regs);
 
-          /* Restore the exception context of the rtcb at the (new) head 
+          /* Restore the exception context of the rtcb at the (new) head
            * of the g_readytorun task list.
            */
 
@@ -132,7 +132,7 @@ void up_unblock_task(struct tcb_s *tcb)
         }
 
       /* We are not in an interrupt handler.  Copy the user C context
-       * into the TCB of the task that was previously active.  if 
+       * into the TCB of the task that was previously active.  if
        * up_saveusercontext returns a non-zero value, then this is really the
        * previously running task restarting!
        */

arch/arm/src/arm/up_undefinedinsn.c

@@ -48,7 +48,7 @@
  * Pre-processor Definitions
  ****************************************************************************/
 
-/* Output debug info if stack dump is selected -- even if 
+/* Output debug info if stack dump is selected -- even if
  * debug is not selected.
  */
 

arch/arm/src/arm/up_vectors.S

@@ -156,7 +156,7 @@ up_vectorirq:
 
 /************************************************************************************
  * Function: up_vectorswi
- * 
+ *
  * Description:
  *   SWI interrupt. We enter the SWI in SVC mode.
  *

arch/arm/src/arm/vfork.S

@@ -64,7 +64,7 @@
  *   undefined if the process created by vfork() either modifies any data other than
  *   a variable of type pid_t used to store the return value from vfork(), or returns
  *   from the function in which vfork() was called, or calls any other function before
- *   successfully calling _exit() or one of the exec family of functions. 
+ *   successfully calling _exit() or one of the exec family of functions.
  *
  *   This thin layer implements vfork by simply calling up_vfork() with the vfork()
  *   context as an argument.  The overall sequence is:
@@ -93,7 +93,7 @@
  *   Upon successful completion, vfork() returns 0 to the child process and returns
  *   the process ID of the child process to the parent process. Otherwise, -1 is
  *   returned to the parent, no child process is created, and errno is set to
- *   indicate the error. 
+ *   indicate the error.
  *
  ************************************************************************************/
 

arch/arm/src/armv6-m/nvic.h

@@ -368,7 +368,7 @@
 #undef EXTERN
 #if defined(__cplusplus)
 #define EXTERN extern "C"
-extern "C" 
+extern "C"
 {
 #else
 #define EXTERN extern

arch/arm/src/armv6-m/up_blocktask.c

@@ -129,7 +129,7 @@ void up_block_task(struct tcb_s *tcb, tstate_t task_state)
 
           up_savestate(rtcb->xcp.regs);
 
-          /* Restore the exception context of the rtcb at the (new) head 
+          /* Restore the exception context of the rtcb at the (new) head
            * of the g_readytorun task list.
            */
 

arch/arm/src/armv6-m/up_elf.c

@@ -296,7 +296,7 @@ int arch_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
         S  = (offset >> 24) & 1;
         J1 = S ^ (~(offset >> 23) & 1);
         J2 = S ^ (~(offset >> 22) & 1);
- 
+
         upper_insn = ((upper_insn & 0xf800) | (S << 10) | ((offset >> 12) & 0x03ff));
         *(uint16_t*)addr = (uint16_t)upper_insn;
 

arch/arm/src/armv6-m/up_initialstate.c

@@ -96,7 +96,7 @@ void up_initial_state(struct tcb_s *tcb)
   /* Save the task entry point (stripping off the thumb bit) */
 
   xcp->regs[REG_PC]      = (uint32_t)tcb->start & ~1;
-  
+
   /* Specify thumb mode */
 
   xcp->regs[REG_XPSR]    = ARMV6M_XPSR_T;

arch/arm/src/armv6-m/up_releasepending.c

@@ -96,7 +96,7 @@ void up_release_pending(void)
 
            up_savestate(rtcb->xcp.regs);
 
-          /* Restore the exception context of the rtcb at the (new) head 
+          /* Restore the exception context of the rtcb at the (new) head
            * of the g_readytorun task list.
            */
 

arch/arm/src/armv6-m/up_reprioritizertr.c

@@ -69,7 +69,7 @@
  *
  * Description:
  *   Called when the priority of a running or
- *   ready-to-run task changes and the reprioritization will 
+ *   ready-to-run task changes and the reprioritization will
  *   cause a context switch.  Two cases:
  *
  *   1) The priority of the currently running task drops and the next
@@ -153,7 +153,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority)
 
                up_savestate(rtcb->xcp.regs);
 
-              /* Restore the exception context of the rtcb at the (new) head 
+              /* Restore the exception context of the rtcb at the (new) head
                * of the g_readytorun task list.
                */
 

arch/arm/src/armv6-m/up_systemreset.c

@@ -68,7 +68,7 @@ void up_systemreset(void)
   regval = ((0x5fa << SYSCON_AIRCR_VECTKEY_SHIFT) | SYSCON_AIRCR_SYSRESETREQ);
   putreg32(regval, ARMV6M_SYSCON_AIRCR);
 
-  /* Ensure completion of memory accesses */              
+  /* Ensure completion of memory accesses */
 
   __asm volatile ("dsb");
 

arch/arm/src/armv6-m/up_unblocktask.c

@@ -108,7 +108,7 @@ void up_unblock_task(struct tcb_s *tcb)
       /* The currently active task has changed! We need to do
        * a context switch to the new task.
        *
-       * Are we in an interrupt handler? 
+       * Are we in an interrupt handler?
        */
 
       if (current_regs)
@@ -119,7 +119,7 @@ void up_unblock_task(struct tcb_s *tcb)
 
           up_savestate(rtcb->xcp.regs);
 
-          /* Restore the exception context of the rtcb at the (new) head 
+          /* Restore the exception context of the rtcb at the (new) head
            * of the g_readytorun task list.
            */
 

arch/arm/src/armv6-m/up_vectors.c

@@ -84,7 +84,7 @@ extern char _ebss;
  * Note that the [ ... ] desginated initialiser is a GCC extension.
  */
 
-unsigned _vectors[] __attribute__((section(".vectors"))) = 
+unsigned _vectors[] __attribute__((section(".vectors"))) =
   {
     /* Initial stack */
 

arch/arm/src/armv6-m/vfork.S

@@ -65,7 +65,7 @@
  *   undefined if the process created by vfork() either modifies any data other than
  *   a variable of type pid_t used to store the return value from vfork(), or returns
  *   from the function in which vfork() was called, or calls any other function before
- *   successfully calling _exit() or one of the exec family of functions. 
+ *   successfully calling _exit() or one of the exec family of functions.
  *
  *   This thin layer implements vfork by simply calling up_vfork() with the vfork()
  *   context as an argument.  The overall sequence is:
@@ -94,7 +94,7 @@
  *   Upon successful completion, vfork() returns 0 to the child process and returns
  *   the process ID of the child process to the parent process. Otherwise, -1 is
  *   returned to the parent, no child process is created, and errno is set to
- *   indicate the error. 
+ *   indicate the error.
  *
  ************************************************************************************/
 

arch/arm/src/armv7-a/arm_allocpage.c

@@ -171,7 +171,7 @@ int arm_allocpage(FAR struct tcb_s *tcb, FAR void **vpage)
   uintptr_t paddr;
   uint32_t *pte;
   unsigned int pgndx;
-  
+
   /* Since interrupts are disabled, we don't need to anything special. */
 
   DEBUGASSERT(tcb && vpage);
@@ -199,7 +199,7 @@ int arm_allocpage(FAR struct tcb_s *tcb, FAR void **vpage)
   if (g_pgwrap)
     {
       /* Yes.. Get a pointer to the L2 entry corresponding to the previous
-       * mapping -- then zero it!  
+       * mapping -- then zero it!
        */
 
        uintptr_t oldvaddr = PG_POOL_NDX2VA(g_ptemap[pgndx]);
@@ -214,7 +214,7 @@ int arm_allocpage(FAR struct tcb_s *tcb, FAR void **vpage)
        * case:  The I-Cache uses a virtual address index and, hence, since the
        * NuttX address space is flat, the cached instruction value should be
        * correct even if the page mapping is no longer in place.
-       */ 
+       */
     }
 
   /* Then convert the index to a (physical) page address. */
@@ -231,7 +231,7 @@ int arm_allocpage(FAR struct tcb_s *tcb, FAR void **vpage)
   *pte = (paddr | MMU_L2_ALLOCFLAGS);
 
   /* And save the new L1 index */
- 
+
   g_ptemap[pgndx] = PG_POOL_VA2L2NDX(vaddr);
 
   /* Finally, return the virtual address of allocated page */

arch/arm/src/armv7-a/arm_blocktask.c

@@ -130,7 +130,7 @@ void up_block_task(struct tcb_s *tcb, tstate_t task_state)
 
           up_savestate(rtcb->xcp.regs);
 
-          /* Restore the exception context of the rtcb at the (new) head 
+          /* Restore the exception context of the rtcb at the (new) head
            * of the g_readytorun task list.
            */
 
@@ -148,7 +148,7 @@ void up_block_task(struct tcb_s *tcb, tstate_t task_state)
 
       else if (!up_saveusercontext(rtcb->xcp.regs))
         {
-          /* Restore the exception context of the rtcb at the (new) head 
+          /* Restore the exception context of the rtcb at the (new) head
            * of the g_readytorun task list.
            */