diff --git a/arch/arm/src/stm32/stm32_sdio.h b/arch/arm/src/stm32/stm32_sdio.h
index e2b8e31cc12..73a29d8cfda 100755
--- a/arch/arm/src/stm32/stm32_sdio.h
+++ b/arch/arm/src/stm32/stm32_sdio.h
@@ -101,6 +101,8 @@
 #  define SDIO_POWER_PWRCTRL_RSVDPWRUP (2 << POWER_PWRCTRL_SHIFT) /* 10: Reserved power-up */
 #  define SDIO_POWER_PWRCTRL_ON        (3 << POWER_PWRCTRL_SHIFT) /* 11: Power-on: card is clocked */
 
+#define SDIO_POWER_RESET               (0)       /* Reset value */
+
 #define SDIO_CLKCR_CLKDIV_SHIFT        (0)       /* Bits 7-0: Clock divide factor */
 #define SDIO_CLKCR_CLKDIV_MASK         (0xff << SDIO_CLKCR_CLKDIV_SHIFT)
 #define SDIO_CLKCR_CLKEN               (1 << 8)  /* Bit 8: Clock enable bit */
@@ -114,6 +116,9 @@
 #define SDIO_CLKCR_NEGEDGE             (1 << 13) /* Bit 13: SDIO_CK dephasing selection bit */
 #define SDIO_CLKCR_HWFC_EN             (1 << 14) /* Bit 14: HW Flow Control enable */
 
+#define SDIO_CLKCR_RESET               (0)       /* Reset value */
+#define SDIO_ARG_RESET                 (0)       /* Reset value */
+
 #define SDIO_CMD_CMDINDEX_SHIFT        (0)
 #define SDIO_CMD_CMDINDEX_MASK         (0x3f << SDIO_CMD_CMDINDEX_SHIFT)
 #define SDIO_CMD_WAITRESP_SHIFT        (6)       /* Bits 7-6: Wait for response bits */
@@ -129,12 +134,18 @@
 #define SDIO_CMD_NIEN                  (1 << 13) /* Bit 13: not Interrupt Enable */
 #define SDIO_CMD_ATACMD                (1 << 14) /* Bit 14: CE-ATA command */
 
+#define SDIO_CMD_RESET                 (0)       /* Reset value */
+
 #define SDIO_RESPCMD_SHIFT             (0)
 #define SDIO_RESPCMD_MASK              (0x3f << SDIO_RESPCMD_SHIFT)
 
+#define SDIO_DTIMER_RESET              (0)       /* Reset value */
+
 #define SDIO_DLEN_SHIFT                (0)
 #define SDIO_DLEN_MASK                 (0x01ffffff << SDIO_DLEN_SHIFT)
 
+#define SDIO_DLEN_RESET                (0)       /* Reset value */
+
 #define SDIO_DCTRL_DTEN                (1 << 0)  /* Bit 0: Data transfer enabled bit */
 #define SDIO_DCTRL_DTDIR               (1 << 1)  /* Bit 1: Data transfer direction */
 #define SDIO_DCTRL_DTMODE              (1 << 2)  /* Bit 2: Data transfer mode */
@@ -161,6 +172,8 @@
 #define SDIO_DCTRL_RWMOD               (1 << 10) /* Bit 10: Read wait mode */
 #define SDIO_DCTRL_SDIOEN              (1 << 11) /* Bit 11: SD I/O enable functions */
 
+#define SDIO_DCTRL_RESET               (0)       /* Reset value */
+
 #define SDIO_DATACOUNT_SHIFT           (0)
 #define SDIO_DATACOUNT_MASK            (0x01ffffff << SDIO_DATACOUNT_SHIFT)
 
@@ -203,6 +216,8 @@
 #define SDIO_ICR_SDIOITC               (1 << 22) /* Bit 22: SDIOIT flag clear bit */
 #define SDIO_ICR_CEATAENDC             (1 << 23) /* Bit 23: CEATAEND flag clear bit */
 
+#define SDIO_ICR_RESET                 0x00c007ff
+
 #define SDIO_MASK_CCRCFAILIE           (1 << 0)  /* Bit 0: Command CRC fail interrupt enable */
 #define SDIO_MASK_DCRCFAILIE           (1 << 1)  /* Bit 1: Data CRC fail interrupt enable */
 #define SDIO_MASK_CTIMEOUTIE           (1 << 2)  /* Bit 2: Command timeout interrupt enable */
@@ -228,6 +243,8 @@
 #define SDIO_MASK_SDIOITIE             (1 << 22) /* Bit 22: SDIO mode interrupt received interrupt enable */
 #define SDIO_MASK_CEATAENDIE           (1 << 23) /* Bit 23: CE-ATA command completion interrupt enable */
 
+#define SDIO_MASK_RESET                (0)
+
 #define SDIO_FIFOCNT_SHIFT             (0)
 #define SDIO_FIFOCNT_MASK              (0x01ffffff << SDIO_FIFOCNT_SHIFT)