diff --git a/arch/arm/src/lpc54xx/chip/lpc54_ethernet.h b/arch/arm/src/lpc54xx/chip/lpc54_ethernet.h
index a73eff73582..2b81ea5890c 100644
--- a/arch/arm/src/lpc54xx/chip/lpc54_ethernet.h
+++ b/arch/arm/src/lpc54xx/chip/lpc54_ethernet.h
@@ -345,9 +345,35 @@
 #  define ETH_MAC_RXQ_CTRL0_RXQ1EN_ENABLE                (1 << ETH_MAC_RXQ_CTRL0_RXQ1EN_SHIFT) /* Queue 1 enabled for AV */
 
 /* Receive Queue control 1 */
-#define ETH_MAC_RXQ_CTRL1_
+
+#define ETH_MAC_RXQ_CTRL1_AVCPQ_SHIFT                    (0)       /* Bits 0-2: AV untagged control packets queue */
+#define ETH_MAC_RXQ_CTRL1_AVCPQ_MASK                     (7 < ETH_MAC_RXQ_CTRL1_AVCPQ_SHIFT)
+#  define ETH_MAC_RXQ_CTRL1_AVCPQ(n)                     ((uint32_t)(n) < ETH_MAC_RXQ_CTRL1_AVCPQ_SHIFT) /* Rx Queue n, n=0..1 */
+#define ETH_MAC_RXQ_CTRL1_AVPTPQ_SHIFT                   (4)       /* Bits 4-6: AV PTP packets queue */
+#define ETH_MAC_RXQ_CTRL1_AVPTPQ_MASK                    (7 < ETH_MAC_RXQ_CTRL1_AVCPQ_SHIFT)
+#  define ETH_MAC_RXQ_CTRL1_AVPTPQ(n)                    ((uint32_t)(n) < ETH_MAC_RXQ_CTRL1_AVCPQ_SHIFT) /* Rx Queue n, n=0..1 */
+#define ETH_MAC_RXQ_CTRL1_UPQ_SHIFT                      (12)      /* Bits 12-14: Untagged packet queue */
+#define ETH_MAC_RXQ_CTRL1_UPQ_MASK                       (7 < ETH_MAC_RXQ_CTRL1_AVCPQ_SHIFT)
+#  define ETH_MAC_RXQ_CTRL1_UPQ(n)                       ((uint32_t)(n) < ETH_MAC_RXQ_CTRL1_AVCPQ_SHIFT) /* Rx Queue n, n=0..1 */
+#define ETH_MAC_RXQ_CTRL1_MCBCQ_SHIFT                    (16)      /* Bits 16-18: Multicast and broadcast queue */
+#define ETH_MAC_RXQ_CTRL1_MCBCQ_MASK                     (7 < ETH_MAC_RXQ_CTRL1_AVCPQ_SHIFT)
+#  define ETH_MAC_RXQ_CTRL1_MCBCQ(n)                     ((uint32_t)(n) < ETH_MAC_RXQ_CTRL1_AVCPQ_SHIFT) /* Rx Queue n, n=0..1 */
+#define ETH_MAC_RXQ_CTRL1_MCBCQEN                        (1 << 20) /* Bit 20: Multicast and broadcast queue enable */
+
 /* Receive Queue control 2 */
-#define ETH_MAC_RXQ_CTRL2_
+
+#define ETH_MAC_RXQ_CTRL2_PSRQ0_SHIFT                    (0)       /* Bits 0-7:   Priorities selected in the Rx Queue 0 */
+#define ETH_MAC_RXQ_CTRL2_PSRQ0_MASK                     (0xff << ETH_MAC_RXQ_CTRL2_PSRQ0_SHIFT)
+#  define ETH_MAC_RXQ_CTRL2_PSRQ0(n)                     ((uint32_t)(n) << ETH_MAC_RXQ_CTRL2_PSRQ0_SHIFT)
+#define ETH_MAC_RXQ_CTRL2_PSRQ1_SHIFT                    (8)       /* Bits 8-15:  Priorities selected in the Rx Queue 1 */
+#define ETH_MAC_RXQ_CTRL2_PSRQ1_MASK                     (0xff << ETH_MAC_RXQ_CTRL2_PSRQ1_SHIFT)
+#  define ETH_MAC_RXQ_CTRL2_PSRQ1(n)                     ((uint32_t)(n) << ETH_MAC_RXQ_CTRL2_PSRQ1_SHIFT)
+#define ETH_MAC_RXQ_CTRL2_PSRQ2_SHIFT                    (16)      /* Bits 16-23: Priorities selected in the Rx Queue 2 */
+#define ETH_MAC_RXQ_CTRL2_PSRQ2_MASK                     (0xff << ETH_MAC_RXQ_CTRL2_PSRQ2_SHIFT)
+#  define ETH_MAC_RXQ_CTRL2_PSRQ2(n)                     ((uint32_t)(n) << ETH_MAC_RXQ_CTRL2_PSRQ2_SHIFT)
+#define ETH_MAC_RXQ_CTRL2_PSRQ3_SHIFT                    (24)      /* Bits 24-31: Priorities selected in the Rx Queue 3 */
+#define ETH_MAC_RXQ_CTRL2_PSRQ3_MASK                     (0xff << ETH_MAC_RXQ_CTRL2_PSRQ3_SHIFT)
+#  define ETH_MAC_RXQ_CTRL2_PSRQ3(n)                     ((uint32_t)(n) << ETH_MAC_RXQ_CTRL2_PSRQ3_SHIFT)
 
 /* Interrupt enable and interrupt status */
 
diff --git a/arch/arm/src/lpc54xx/lpc54_ethernet.c b/arch/arm/src/lpc54xx/lpc54_ethernet.c
index 5f22c092bf5..e12e43efab0 100644
--- a/arch/arm/src/lpc54xx/lpc54_ethernet.c
+++ b/arch/arm/src/lpc54xx/lpc54_ethernet.c
@@ -164,7 +164,7 @@
 #  define LPC54_MTL_OPMODE_RAA    ETH_MTL_OP_MODE_RAA_SP
 #endif
 
-/* MAC-related definitinons */
+/* MAC-related definitions */
 
 #define LPC54_MAC_HALFDUPLEX_IPG ETH_MAC_CONFIG_IPG_64 /* Default half-duplex IPG */
 
@@ -1936,16 +1936,22 @@ static int lpc54_eth_ifup(struct net_driver_s *dev)
 #endif
 
   /* Initialize the Ethernet MAC ********************************************/
-  /* Instantiate the MAC address that application logic should have set in the
-   * device structure:
+  /* Instantiate the MAC address that application logic should have set in
+   * the device structure.
+   *
+   * "Note that the first DA byte that is received on the MII interface
+   *  corresponds to the LS Byte (bits 7:0) of the MAC address low register.
+   *  For example, if 0x1122 3344 5566 is received (0x11 is the first byte)
+   *  on the MII as the destination address, then the MAC address
+   *  register[47:0] is compared with 0x6655 4433 2211."
    */
 
   mptr   = (uint8_t *)priv->eth_dev.d_mac.ether.ether_addr_octet;
-  regval = ((uint32_t)mptr[2] << 24) | ((uint32_t)mptr[3] << 16) |
-           ((uint32_t)mptr[4] << 8)  | ((uint32_t)mptr[5]);
+  regval = ((uint32_t)mptr[3] << 24) | ((uint32_t)mptr[2] << 16) |
+           ((uint32_t)mptr[1] << 8)  | ((uint32_t)mptr[0]);
   lpc54_putreg(regval, LPC54_ETH_MAC_ADDR_LOW);
 
-  regval = ((uint32_t)mptr[0] << 8)  | ((uint32_t)mptr[1]);
+  regval = ((uint32_t)mptr[5] << 8)  | ((uint32_t)mptr[4]);
   lpc54_putreg(regval, LPC54_ETH_MAC_ADDR_HIGH);
 
   /* Set the receive address filter */