diff --git a/arch/arm/src/lpc17xx/Make.defs b/arch/arm/src/lpc17xx/Make.defs index 09204152c92..53c6b5fc89f 100755 --- a/arch/arm/src/lpc17xx/Make.defs +++ b/arch/arm/src/lpc17xx/Make.defs @@ -51,7 +51,7 @@ CMN_CSRCS = up_assert.c up_blocktask.c up_copystate.c up_createstack.c \ # Required LPC17xx files CHIP_ASRCS = -CHIP_CSRCS = lpc17_irq.c lpc17_gpio.c lpc17_start.c +CHIP_CSRCS = lpc17_allocateheap.c lpc17_irq.c lpc17_lowputc.c lpc17_gpio.c lpc17_gpioint.c lpc17_serial.c lpc17_start.c #CHIP_CSRCS = lpc17_allocateheap.c lpc17_clockconfig.c lpc17_gpioirq.c \ # lpc17_irq.c lpc17_lowputc.c lpc17_gpio.c lpc17_serial.c \ # lpc17_start.c lpc17_timerisr.c diff --git a/arch/arm/src/lpc17xx/chip.h b/arch/arm/src/lpc17xx/chip.h index 90e3c422f65..52c6b45f279 100755 --- a/arch/arm/src/lpc17xx/chip.h +++ b/arch/arm/src/lpc17xx/chip.h @@ -51,6 +51,8 @@ #if defined(CONFIG_ARCH_CHIP_LPC1769) || defined(CONFIG_ARCH_CHIP_LPC1768) # define LPC17_FLASH_SIZE (512*1024) /* 512Kb */ # define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ +# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ +# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */ # define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ # define LPC17_NUSBHOST 1 /* One USB host controller */ # define LPC17_NUSBOTG 1 /* One USB OTG controller */ @@ -61,6 +63,8 @@ #elif defined(CONFIG_ARCH_CHIP_LPC1767) # define LPC17_FLASH_SIZE (512*1024) /* 512Kb */ # define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ +# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ +# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */ # define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ # define LPC17_NUSBHOST 0 /* No USB host controller */ # define LPC17_NUSBOTG 0 /* No USB OTG controller */ @@ -71,6 +75,8 @@ #elif defined(CONFIG_ARCH_CHIP_LPC1766) # define LPC17_FLASH_SIZE (256*1024) /* 256Kb */ # define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ +# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ +# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */ # define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ # define LPC17_NUSBHOST 1 /* One USB host controller */ # define LPC17_NUSBOTG 1 /* One USB OTG controller */ @@ -81,6 +87,8 @@ #elif defined(CONFIG_ARCH_CHIP_LPC1765) # define LPC17_FLASH_SIZE (256*1024) /* 256Kb */ # define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ +# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ +# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */ # define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */ # define LPC17_NUSBHOST 1 /* One USB host controller */ # define LPC17_NUSBOTG 1 /* One USB OTG controller */ @@ -91,6 +99,8 @@ #elif defined(CONFIG_ARCH_CHIP_LPC1764) # define LPC17_FLASH_SIZE (128*1024) /* 128Kb */ # define LPC17_SRAM_SIZE (32*1024) /* 32Kb */ +# undef LPC17_HAVE_BANK0 1 /* No AHB SRAM bank 0 */ +# undef LPC17_HAVE_BANK1 1 /* No AHB SRAM bank 1 */ # define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ # define LPC17_NUSBHOST 0 /* No USB host controller */ # define LPC17_NUSBOTG 0 /* No USB OTG controller */ @@ -101,6 +111,8 @@ #elif defined(CONFIG_ARCH_CHIP_LPC1759) # define LPC17_FLASH_SIZE (512*1024) /* 512Kb */ # define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ +# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ +# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */ # define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */ # define LPC17_NUSBHOST 1 /* One USB host controller */ # define LPC17_NUSBOTG 1 /* One USB OTG controller */ @@ -111,6 +123,8 @@ #elif defined(CONFIG_ARCH_CHIP_LPC1758) # define LPC17_FLASH_SIZE (512*1024) /* 512Kb */ # define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ +# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ +# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */ # define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ # define LPC17_NUSBHOST 1 /* One USB host controller */ # define LPC17_NUSBOTG 1 /* One USB OTG controller */ @@ -121,6 +135,8 @@ #elif defined(CONFIG_ARCH_CHIP_LPC1756) # define LPC17_FLASH_SIZE (256*1024) /* 256Kb */ # define LPC17_SRAM_SIZE (32*1024) /* 32Kb */ +# undef LPC17_HAVE_BANK0 1 /* No AHB SRAM bank 0 */ +# undef LPC17_HAVE_BANK1 1 /* No AHB SRAM bank 1 */ # define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */ # define LPC17_NUSBHOST 1 /* One USB host controller */ # define LPC17_NUSBOTG 1 /* One USB OTG controller */ @@ -131,6 +147,8 @@ #elif defined(CONFIG_ARCH_CHIP_LPC1754) # define LPC17_FLASH_SIZE (128*1024) /* 128Kb */ # define LPC17_SRAM_SIZE (32*1024) /* 32Kb */ +# undef LPC17_HAVE_BANK0 1 /* No AHB SRAM bank 0 */ +# undef LPC17_HAVE_BANK1 1 /* No AHB SRAM bank 1 */ # define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */ # define LPC17_NUSBHOST 1 /* One USB host controller */ # define LPC17_NUSBOTG 1 /* One USB OTG controller */ @@ -141,6 +159,8 @@ #elif defined(CONFIG_ARCH_CHIP_LPC1752) # define LPC17_FLASH_SIZE (64*1024) /* 65Kb */ # define LPC17_SRAM_SIZE (16*1024) /* 16Kb */ +# undef LPC17_HAVE_BANK0 1 /* No AHB SRAM bank 0 */ +# undef LPC17_HAVE_BANK1 1 /* No AHB SRAM bank 1 */ # define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */ # define LPC17_NUSBHOST 0 /* No USB host controller */ # define LPC17_NUSBOTG 0 /* No USB OTG controller */ @@ -151,6 +171,8 @@ #elif defined(CONFIG_ARCH_CHIP_LPC1751) # define LPC17_FLASH_SIZE (32*1024) /* 32Kb */ # define LPC17_SRAM_SIZE (8*1024) /* 8Kb */ +# undef LPC17_HAVE_BANK0 1 /* No AHB SRAM bank 0 */ +# undef LPC17_HAVE_BANK1 1 /* No AHB SRAM bank 1 */ # define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */ # define LPC17_NUSBHOST 0 /* No USB host controller */ # define LPC17_NUSBOTG 0 /* No USB OTG controller */ diff --git a/arch/arm/src/lpc17xx/lpc17_allocateheap.c b/arch/arm/src/lpc17xx/lpc17_allocateheap.c new file mode 100755 index 00000000000..3fee5301844 --- /dev/null +++ b/arch/arm/src/lpc17xx/lpc17_allocateheap.c @@ -0,0 +1,132 @@ +/**************************************************************************** + * arch/arm/src/lpc17xx/lpc17_allocateheap.c + * + * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "chip.h" +#include "up_arch.h" +#include "up_internal.h" + +/**************************************************************************** + * Private Definitions + ****************************************************************************/ + +#if CONFIG_DRAM_END > (LPC17_SRAM_BASE+LPC17_SRAM_SIZE) +# error "CONFIG_DRAM_END is beyond the end of CPU SRAM" +# undef CONFIG_DRAM_END +# define CONFIG_DRAM_END (LPC17_SRAM_BASE+LPC17_SRAM_SIZE) +#elif CONFIG_DRAM_END < (LPC17_SRAM_BASE+LPC17_SRAM_SIZE) +# warning "CONFIG_DRAM_END is before end of CPU SRAM... not all of CPU SRAM used" +#endif + +#ifdef LPC17_HAVE_BANK0 +# if CONFIG_MM_REGIONS < 2 +# warning "CONFIG_MM_REGIONS < 2: AHB SRAM Bank0 not included in HEAP" +# endif +#else +# if CONFIG_MM_REGIONS > 1 +# warning "CONFIG_MM_REGIONS > 1: This MCH has no AHB SRAM Bank0" +# endif +#endif + +#ifdef LPC17_HAVE_BANK1 +# if CONFIG_MM_REGIONS < 3 +# warning "CONFIG_MM_REGIONS < 3: AHB SRAM Bank1 not included in HEAP" +# endif +#else +# if CONFIG_MM_REGIONS > 2 +# warning "CONFIG_MM_REGIONS > 2: This MCH has no AHB SRAM Bank1" +# endif +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_allocate_heap + * + * Description: + * The heap may be statically allocated by + * defining CONFIG_HEAP_BASE and CONFIG_HEAP_SIZE. If these + * are not defined, then this function will be called to + * dynamically set aside the heap region. + * + ****************************************************************************/ + +void up_allocate_heap(FAR void **heap_start, size_t *heap_size) +{ + up_ledon(LED_HEAPALLOCATE); + *heap_start = (FAR void*)g_heapbase; + *heap_size = CONFIG_DRAM_END - g_heapbase; +} + +/************************************************************************ + * Name: up_addregion + * + * Description: + * Memory may be added in non-contiguous chunks. Additional chunks are + * added by calling this function. + * + ************************************************************************/ + +#if CONFIG_MM_REGIONS > 1 +void up_addregion(void) +{ + mm_addregion((FAR void*)LPC17_HAVE_BANK0, 16*1024); + +#if CONFIG_MM_REGIONS > 2 + mm_addregion((FAR void*)LPC17_HAVE_BANK1, 16*1024); +#endif +} +#endif diff --git a/arch/arm/src/lpc17xx/lpc17_internal.h b/arch/arm/src/lpc17xx/lpc17_internal.h index 1566dba916d..b6e9ce3b0d3 100755 --- a/arch/arm/src/lpc17xx/lpc17_internal.h +++ b/arch/arm/src/lpc17xx/lpc17_internal.h @@ -331,7 +331,7 @@ #define GPIO_UART3_TXD_3 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN28) #define GPIO_TXMCLK (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN29) #define GPIO_MAT2p1_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN29) -#define GPIO_UART3_RXD (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN29) +#define GPIO_UART3_RXD_3 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN29) /************************************************************************************ * Public Types diff --git a/arch/arm/src/lpc17xx/lpc17_lowputc.c b/arch/arm/src/lpc17xx/lpc17_lowputc.c new file mode 100755 index 00000000000..64966c7ebb3 --- /dev/null +++ b/arch/arm/src/lpc17xx/lpc17_lowputc.c @@ -0,0 +1,293 @@ +/************************************************************************** + * arch/arm/src/lpc17xx/lpc17_lowputc.c + * + * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************/ + +/************************************************************************** + * Included Files + **************************************************************************/ + +#include + +#include + +#include +#include + +#include "up_internal.h" +#include "up_arch.h" + +#include "lpc17_internal.h" +#include "lpc17_uart.h" +#include "lpc17_serial.h" + +/************************************************************************** + * Private Definitions + **************************************************************************/ + +/* Baud calculations + +BAUD = PCLK / (16 x (256 x DLM + DLL) x (1 + DIVADDVAL/MULVAL)) + +Where PCLK is the peripheral clock, DLM and DLL are the standard +UART baud rate divider registers, and DIVADDVAL and MULVAL are UART +fractional baud rate generator specific parameters. + +The value of MULVAL and DIVADDVAL should comply to the following conditions: + +1. 1 <= MULVAL <= 15 +2. 0 <= DIVADDVAL <= 14 +3. DIVADDVAL < MULVAL + +The peripheral clock is controlled by: + +#define SYSCON_PCLKSET_CCLK4 PCLK_peripheral = CCLK/4 +#define SYSCON_PCLKSET_CCLK PCLK_peripheral = CCLK +#define SYSCON_PCLKSET_CCLK2 PCLK_peripheral = CCLK/2 +#define SYSCON_PCLKSET_CCLK6 PCLK_peripheral = CCLK/8 (except CAN1, CAN2, and CAN) +#define SYSCON_PCLKSET_CCLK8 PCLK_peripheral = CCLK/6 (CAN1, CAN2, and CAN) + */ + +/************************************************************************** + * Private Types + **************************************************************************/ + +/************************************************************************** + * Private Function Prototypes + **************************************************************************/ + +/************************************************************************** + * Global Variables + **************************************************************************/ + +/************************************************************************** + * Private Variables + **************************************************************************/ + +/************************************************************************** + * Private Functions + **************************************************************************/ + +/************************************************************************** + * Public Functions + **************************************************************************/ + +/************************************************************************** + * Name: up_lowputc + * + * Description: + * Output one byte on the serial console + * + **************************************************************************/ + +void up_lowputc(char ch) +{ + /* Wait for the transmitter to be available */ + + while ((getreg32(CONSOLE_BASE+LPC17_UART_LSR_OFFSET) & UART_LSR_THRE) == 0); + + /* Send the character */ + + putreg32((uint32_t)ch, CONSOLE_BASE+LPC17_UART_THR_OFFSET); +} + +/************************************************************************** + * Name: lpc17_lowsetup + * + * Description: + * This performs basic initialization of the UART used for the serial + * console. Its purpose is to get the console output availabe as soon + * as possible. + * + * The UART0/2/3 peripherals are configured using the following registers: + * 1. Power: In the PCONP register, set bits PCUART0/1/2/3. + * On reset, UART0 and UART 1 are enabled (PCUART0 = 1 and PCUART1 = 1) + * and UART2/3 are disabled (PCUART1 = 0 and PCUART3 = 0). + * 2. Peripheral clock: In the PCLKSEL0 register, select PCLK_UART0 and + * PCLK_UART1; in the PCLKSEL1 register, select PCLK_UART2 and PCLK_UART3. + * 3. Baud rate: In the LCR register, set bit DLAB = 1. This enables access + * to registers DLL and DLM for setting the baud rate. Also, if needed, + * set the fractional baud rate in the fractional divider + * 4. UART FIFO: Use bit FIFO enable (bit 0) in FCR register to + * enable FIFO. + * 5. Pins: Select UART pins through the PINSEL registers and pin modes + * through the PINMODE registers. UART receive pins should not have + * pull-down resistors enabled. + * 6. Interrupts: To enable UART interrupts set bit DLAB = 0 in the LCRF + * register. This enables access to IER. Interrupts are enabled + * in the NVIC using the appropriate Interrupt Set Enable register. + * 7. DMA: UART transmit and receive functions can operate with the + * GPDMA controller. + * + **************************************************************************/ + +void lpc17_lowsetup(void) +{ +#if 0 + uint32_t regval; + + /* Step 1: Enable power for all selected UARTs */ + + regval = getreg32(LPC17_SYSCON_PCONP); + regval &= ~(SYSCON_PCONP_PCUART0|SYSCON_PCONP_PCUART1|SYSCON_PCONP_PCUART2|SYSCON_PCONP_PCUART3) +#ifdef CONFIG_LPC17_UART0 + regval |= SYSCON_PCONP_PCUART0; +#endif +#ifdef CONFIG_LPC17_UART1 + regval |= SYSCON_PCONP_PCUART1; +#endif +#ifdef CONFIG_LPC17_UART2 + regval |= SYSCON_PCONP_PCUART2; +#endif +#ifdef CONFIG_LPC17_UART3 + regval |= SYSCON_PCONP_PCUART3; +#endif + putreg32(regval, LPC17_SYSCON_PCONP); + +/* Step 2: Enable peripheral clocking for all selected UARTs */ + +#define SYSCON_PCLKSET_MASK (3) + +#define SYSCON_PCLKSEL0_UART0_SHIFT (6) /* Bits 6-7: Peripheral clock UART0 */ +#define SYSCON_PCLKSEL0_UART0_MASK (3 << SYSCON_PCLKSEL0_UART0_MASK) +#define SYSCON_PCLKSEL0_UART1_SHIFT (8) /* Bits 8-9: Peripheral clock UART1 */ +#define SYSCON_PCLKSEL0_UART1_MASK (3 << SYSCON_PCLKSEL0_UART1_SHIFT) + + +#define SYSCON_PCLKSEL1_UART2_SHIFT (16) /* Bits 16-17: Peripheral clock UART2 */ +#define SYSCON_PCLKSEL1_UART2_MASK (3 << SYSCON_PCLKSEL1_UART2_SHIFT) +#define SYSCON_PCLKSEL1_UART3_SHIFT (18) /* Bits 18-19: Peripheral clock UART3 */ +#define SYSCON_PCLKSEL1_UART3_MASK (3 << SYSCON_PCLKSEL1_UART3_SHIFT) + + /* Configure UART pins for all selected UARTs */ + +#define GPIO_UART0_TXD (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN2) +#define GPIO_UART0_RXD (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN3 + +#define GPIO_UART1_TXD_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN15) +#define GPIO_UART1_RXD_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN16) +#define GPIO_UART1_CTS_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN17) +#define GPIO_UART1_DCD_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN18) +#define GPIO_UART1_DSR_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN19) +#define GPIO_UART1_DTR_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN20) +#define GPIO_UART1_RI_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN21) +#define GPIO_UART1_RTS_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN22) + +#define GPIO_UART1_TXD_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN0) +#define GPIO_UART1_RXD_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN1) +#define GPIO_UART1_CTS_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN2) +#define GPIO_UART1_DCD_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN3) +#define GPIO_UART1_DSR_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN4) +#define GPIO_UART1_DTR_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN5) +#define GPIO_UART1_RI_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN6) +#define GPIO_UART1_RTS_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN7) + +#define GPIO_UART2_TXD_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN10) +#define GPIO_UART2_RXD_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN11) +#define GPIO_UART2_TXD_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN8) +#define GPIO_UART2_RXD_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN9) + +#define GPIO_UART3_TXD_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN0) +#define GPIO_UART3_RXD_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN1) +#define GPIO_UART3_TXD_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN25) +#define GPIO_UART3_RXD_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN26) +#define GPIO_UART3_TXD_3 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN28) +#define GPIO_UART3_RXD_3 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN29) + + +#ifdef CONFIG_LPC17_UART0 + (void)lpc17_configgpio(GPIO_UART0_RXD); + (void)lpc17_configgpio(GPIO_UART0_TXD); + (void)lpc17_configgpio(GPIO_UART0_CTS); + (void)lpc17_configgpio(GPIO_UART0_RTS); +#endif +#ifdef CONFIG_LPC17_UART1 + (void)lpc17_configgpio(GPIO_UART1_RXD); + (void)lpc17_configgpio(GPIO_UART1_TXD); + (void)lpc17_configgpio(GPIO_UART1_CTS); + (void)lpc17_configgpio(GPIO_UART1_RTS); +#endif +#ifdef CONFIG_LPC17_UART2 + (void)lpc17_configgpio(GPIO_UART2_RXD); + (void)lpc17_configgpio(GPIO_UART2_TXD); + (void)lpc17_configgpio(GPIO_UART2_CTS); + (void)lpc17_configgpio(GPIO_UART2_RTS); +#endif +#ifdef CONFIG_LPC17_UART3 + (void)lpc17_configgpio(GPIO_UART3_RXD); + (void)lpc17_configgpio(GPIO_UART3_TXD); + (void)lpc17_configgpio(GPIO_UART3_CTS); + (void)lpc17_configgpio(GPIO_UART3_RTS); +#endif + +#ifdef GPIO_CONSOLE_RXD +#endif +#ifdef GPIO_CONSOLE_TXD + (void)lpc17_configgpio(GPIO_CONSOLE_TXD); +#endif +#ifdef GPIO_CONSOLE_CTS + (void)lpc17_configgpio(GPIO_CONSOLE_CTS); +#endif +#ifdef GPIO_CONSOLE_RTS + (void)lpc17_configgpio(GPIO_CONSOLE_RTS); +#endif + + /* Configure the console (only) */ +#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) + /* Reset and disable receiver and transmitter */ + + putreg32((UART_CR_RSTRX|UART_CR_RSTTX|UART_CR_RXDIS|UART_CR_TXDIS), + CONSOLE_BASE+LPC17_UART_CR_OFFSET); + + /* Disable all interrupts */ + + putreg32(0xffffffff, CONSOLE_BASE+LPC17_UART_IDR_OFFSET); + + /* Set up the mode register */ + + putreg32(MR_VALUE, CONSOLE_BASE+LPC17_UART_MR_OFFSET); + + /* Configure the console baud */ + + putreg32(((LPC17_MCK_FREQUENCY + (LPC17_CONSOLE_BAUD << 3))/(LPC17_CONSOLE_BAUD << 4)), + CONSOLE_BASE+LPC17_UART_BRGR_OFFSET); + + /* Enable receiver & transmitter */ + + putreg32((UART_CR_RXEN|UART_CR_TXEN), + CONSOLE_BASE+LPC17_UART_CR_OFFSET); +#endif +#endif /* 0 */ +} + + diff --git a/arch/arm/src/lpc17xx/lpc17_serial.c b/arch/arm/src/lpc17xx/lpc17_serial.c new file mode 100755 index 00000000000..5a39e9f74e8 --- /dev/null +++ b/arch/arm/src/lpc17xx/lpc17_serial.c @@ -0,0 +1,1066 @@ +/**************************************************************************** + * arch/arm/src/lpc17xx/lpc17_serial.c + * + * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "chip.h" +#include "up_arch.h" +#include "os_internal.h" +#include "up_internal.h" + +#include "lpc17_uart.h" +#include "lpc17_serial.h" + +/**************************************************************************** + * Pre-processor definitions + ****************************************************************************/ + +/* If we are not using the serial driver for the console, then we still must + * provide some minimal implementation of up_putc. + */ + +#ifdef CONFIG_USE_SERIALDRIVER + +/* Configuration *********************************************************************/ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct up_dev_s +{ + uint32_t uartbase; /* Base address of UART registers */ + uint32_t baud; /* Configured baud */ + uint8_t ier; /* Saved IER value */ + uint8_t irq; /* IRQ associated with this UART */ + uint8_t parity; /* 0=none, 1=odd, 2=even */ + uint8_t bits; /* Number of bits (7 or 8) */ + bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int up_setup(struct uart_dev_s *dev); +static void up_shutdown(struct uart_dev_s *dev); +static int up_attach(struct uart_dev_s *dev); +static void up_detach(struct uart_dev_s *dev); +static int up_interrupt(int irq, void *context); +static int up_ioctl(struct file *filep, int cmd, unsigned long arg); +static int up_receive(struct uart_dev_s *dev, uint32_t *status); +static void up_rxint(struct uart_dev_s *dev, bool enable); +static bool up_rxavailable(struct uart_dev_s *dev); +static void up_send(struct uart_dev_s *dev, int ch); +static void up_txint(struct uart_dev_s *dev, bool enable); +static bool up_txready(struct uart_dev_s *dev); +static bool up_txempty(struct uart_dev_s *dev); + +/**************************************************************************** + * Private Variables + ****************************************************************************/ + +struct uart_ops_s g_uart_ops = +{ + .setup = up_setup, + .shutdown = up_shutdown, + .attach = up_attach, + .detach = up_detach, + .ioctl = up_ioctl, + .receive = up_receive, + .rxint = up_rxint, + .rxavailable = up_rxavailable, + .send = up_send, + .txint = up_txint, + .txready = up_txready, + .txempty = up_txempty, +}; + +/* I/O buffers */ + +#ifdef CONFIG_LPC17_UART0 +static char g_uart0rxbuffer[CONFIG_UART0_RXBUFSIZE]; +static char g_uart0txbuffer[CONFIG_UART0_TXBUFSIZE]; +#endif +#ifdef CONFIG_LPC17_UART1 +static char g_uart1rxbuffer[CONFIG_UART1_RXBUFSIZE]; +static char g_uart1txbuffer[CONFIG_UART1_TXBUFSIZE]; +#endif +#ifdef CONFIG_LPC17_UART2 +static char g_uart2rxbuffer[CONFIG_UART1_RXBUFSIZE]; +static char g_uart2txbuffer[CONFIG_UART1_TXBUFSIZE]; +#endif +#ifdef CONFIG_LPC17_UART3 +static char g_uart3rxbuffer[CONFIG_UART1_RXBUFSIZE]; +static char g_uart3txbuffer[CONFIG_UART1_TXBUFSIZE]; +#endif + +/* This describes the state of the LPC17xx uart0 port. */ + +#ifdef CONFIG_LPC17_UART0 +static struct up_dev_s g_uart0priv = +{ + .uartbase = LPC17_UART0_BASE, + .baud = CONFIG_UART0_BAUD, + .irq = LPC17_IRQ_UART0, + .parity = CONFIG_UART0_PARITY, + .bits = CONFIG_UART0_BITS, + .stopbits2 = CONFIG_UART0_2STOP, +}; + +static uart_dev_t g_uart0port = +{ + .recv = + { + .size = CONFIG_UART0_RXBUFSIZE, + .buffer = g_uart0rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART0_TXBUFSIZE, + .buffer = g_uart0txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart0priv, +}; +#endif + +/* This describes the state of the LPC17xx uart1 port. */ + +#ifdef CONFIG_LPC17_UART1 +static struct up_dev_s g_uart1priv = +{ + .uartbase = LPC17_UART1_BASE, + .baud = CONFIG_UART1_BAUD, + .irq = LPC17_IRQ_UART1, + .parity = CONFIG_UART1_PARITY, + .bits = CONFIG_UART1_BITS, + .stopbits2 = CONFIG_UART1_2STOP, +}; + +static uart_dev_t g_uart1port = +{ + .recv = + { + .size = CONFIG_UART1_RXBUFSIZE, + .buffer = g_uart1rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART1_TXBUFSIZE, + .buffer = g_uart1txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart1priv, +}; +#endif + +/* This describes the state of the LPC17xx uart1 port. */ + +#ifdef CONFIG_LPC17_UART2 +static struct up_dev_s g_uart2priv = +{ + .uartbase = LPC17_UART2_BASE, + .baud = CONFIG_UART2_BAUD, + .irq = LPC17_IRQ_UART2, + .parity = CONFIG_UART2_PARITY, + .bits = CONFIG_UART2_BITS, + .stopbits2 = CONFIG_UART2_2STOP, +}; + +static uart_dev_t g_uart2port = +{ + .recv = + { + .size = CONFIG_UART2_RXBUFSIZE, + .buffer = g_uart2rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART2_TXBUFSIZE, + .buffer = g_uart2txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart2priv, +}; +#endif + +/* This describes the state of the LPC17xx uart1 port. */ + +#ifdef CONFIG_LPC17_UART3 +static struct up_dev_s g_uart3priv = +{ + .uartbase = LPC17_UART3_BASE, + .baud = CONFIG_UART3_BAUD, + .irq = LPC17_IRQ_UART3, + .parity = CONFIG_UART3_PARITY, + .bits = CONFIG_UART3_BITS, + .stopbits2 = CONFIG_UART3_2STOP, +}; + +static uart_dev_t g_uart3port = +{ + .recv = + { + .size = CONFIG_UART3_RXBUFSIZE, + .buffer = g_uart3rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART3_TXBUFSIZE, + .buffer = g_uart3txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart3priv, +}; +#endif + +/* Which UART with be tty0/console and which tty1? tty2? tty3? */ + +#if defined(CONFIG_UART0_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart0port /* UART0=console */ +# define TTYS0_DEV g_uart0port /* UART0=ttyS0 */ +# ifdef CONFIG_LPC17_UART1 +# define TTYS1_DEV g_uart1port /* UART0=ttyS0;UART1=ttyS1 */ +# ifdef CONFIG_LPC17_UART2 +# define TTYS2_DEV g_uart2port /* UART0=ttyS0;UART1=ttyS1;UART2=ttyS2 */ +# ifdef CONFIG_LPC17_UART3 +# define TTYS3_DEV g_uart3port /* UART0=ttyS0;UART1=ttyS1;UART2=ttyS2;UART3=ttyS3 */ +# else + undef TTYS3_DEV /* UART0=ttyS0;UART1=ttyS1;UART2=ttyS;No ttyS3 */ +# endif +# else +# ifdef CONFIG_LPC17_UART3 +# define TTYS2_DEV g_uart3port /* UART0=ttyS0;UART1=ttyS1;UART3=ttys2;No ttyS3 */ +# else +# undef TTYS2_DEV /* UART0=ttyS0;UART1=ttyS1;No ttyS2;No ttyS3 */ +# endif +# undef TTYS3_DEV /* No ttyS3 */ +# endif +# else +# ifdef CONFIG_LPC17_UART2 +# define TTYS1_DEV g_uart2port /* UART0=ttyS0;UART2=ttyS1;No ttyS3 */ +# ifdef CONFIG_LPC17_UART3 +# define TTYS2_DEV g_uart3port /* UART0=ttyS0;UART2=ttyS1;UART3=ttyS2;No ttyS3 */ +# else +# undef TTYS2_DEV /* UART0=ttyS0;UART2=ttyS1;No ttyS2;No ttyS3 */ +# endif +# undef TTYS3_DEV /* No ttyS3 */ +# else +# ifdef CONFIG_LPC17_UART3 +# define TTYS1_DEV g_uart3port /* UART0=ttyS0;UART3=ttyS1;No ttyS2;No ttyS3 */ +# else +# undef TTYS1_DEV /* UART0=ttyS0;No ttyS1;No ttyS2;No ttyS3 */ +# endif +# undef TTYS2_DEV /* No ttyS2 */ +# undef TTYS3_DEV /* No ttyS3 */ +# endif +# endif +#elif defined(CONFIG_UART1_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart1port /* UART1=console */ +# define TTYS0_DEV g_uart1port /* UART1=ttyS0 */ +# ifdef CONFIG_LPC17_UART +# define TTYS1_DEV g_uart0port /* UART1=ttyS0;UART0=ttyS1 */ +# ifdef CONFIG_LPC17_UART2 +# define TTYS2_DEV g_uart2port /* UART1=ttyS0;UART0=ttyS1;UART2=ttyS2 */ +# ifdef CONFIG_LPC17_UART3 +# define TTYS3_DEV g_uart3port /* UART1=ttyS0;UART0=ttyS1;UART2=ttyS2;UART3=ttyS3 */ +# else +# undef TTYS3_DEV /* UART1=ttyS0;UART0=ttyS1;UART2=ttyS;No ttyS3 */ +# endif +# else +# ifdef CONFIG_LPC17_UART3 +# define TTYS2_DEV g_uart3port /* UART1=ttyS0;UART0=ttyS1;UART3=ttys2;No ttyS3 */ +# else +# undef TTYS2_DEV /* UART1=ttyS0;UART0=ttyS1;No ttyS2;No ttyS3 */ +# endif +# undef TTYS3_DEV /* No ttyS3 */ +# endif +# else +# ifdef CONFIG_LPC17_UART2 +# define TTYS1_DEV g_uart2port /* UART1=ttyS0;UART2=ttyS1 */ +# ifdef CONFIG_LPC17_UART3 +# define TTYS2_DEV g_uart3port /* UART1=ttyS0;UART2=ttyS1;UART3=ttyS2;No ttyS3 */ +# else +# undef TTYS2_DEV /* UART1=ttyS0;UART2=ttyS1;No ttyS2;No ttyS3 */ +# endif +# undef TTYS3_DEV /* No ttyS3 */ +# else +# ifdef CONFIG_LPC17_UART3 +# define TTYS1_DEV g_uart3port /* UART1=ttyS0;UART3=ttyS1;No ttyS2;No ttyS3 */ +# else +# undef TTYS1_DEV /* UART1=ttyS0;No ttyS1;No ttyS2;No ttyS3 */ +# endif +# undef TTYS2_DEV /* No ttyS2 */ +# undef TTYS3_DEV /* No ttyS3 */ +# endif +# endif +#elif defined(CONFIG_UART2_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart2port /* UART2=console */ +# define TTYS0_DEV g_uart2port /* UART2=ttyS0 */ +# ifdef CONFIG_LPC17_UART +# define TTYS1_DEV g_uart0port /* UART2=ttyS0;UART0=ttyS1 */ +# ifdef CONFIG_LPC17_UART1 +# define TTYS2_DEV g_uart1port /* UART2=ttyS0;UART0=ttyS1;UART1=ttyS2 */ +# ifdef CONFIG_LPC17_UART3 +# define TTYS3_DEV g_uart3port /* UART2=ttyS0;UART0=ttyS1;UART1=ttyS2;UART3=ttyS3 */ +# else +# undef TTYS3_DEV /* UART2=ttyS0;UART0=ttyS1;UART1=ttyS;No ttyS3 */ +# endif +# else +# ifdef CONFIG_LPC17_UART3 +# define TTYS2_DEV g_uart3port /* UART2=ttyS0;UART0=ttyS1;UART3=ttys2;No ttyS3 */ +# else +# undef TTYS2_DEV /* UART2=ttyS0;UART0=ttyS1;No ttyS2;No ttyS3 */ +# endif +# undef TTYS3_DEV /* No ttyS3 */ +# endif +# else +# ifdef CONFIG_LPC17_UART1 +# define TTYS1_DEV g_uart1port /* UART2=ttyS0;UART1=ttyS1 */ +# ifdef CONFIG_LPC17_UART3 +# define TTYS2_DEV g_uart3port /* UART2=ttyS0;UART1=ttyS1;UART3=ttyS2 */ +# else +# undef TTYS2_DEV /* UART2=ttyS0;UART1=ttyS1;No ttyS2;No ttyS3 */ +# endif +# undef TTYS3_DEV /* No ttyS3 */ +# else +# ifdef CONFIG_LPC17_UART3 +# define TTYS1_DEV g_uart3port /* UART2=ttyS0;UART3=ttyS1;No ttyS3 */ +# else +# undef TTYS1_DEV /* UART2=ttyS0;No ttyS1;No ttyS2;No ttyS3 */ +# endif +# undef TTYS2_DEV /* No ttyS2 */ +# undef TTYS3_DEV /* No ttyS3 */ +# endif +# endif +#elif defined(CONFIG_UART3_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart3port /* UART3=console */ +# define TTYS0_DEV g_uart3port /* UART3=ttyS0 */ +# ifdef CONFIG_LPC17_UART +# define TTYS1_DEV g_uart0port /* UART3=ttyS0;UART0=ttyS1 */ +# ifdef CONFIG_LPC17_UART1 +# define TTYS2_DEV g_uart1port /* UART3=ttyS0;UART0=ttyS1;UART1=ttyS2 */ +# ifdef CONFIG_LPC17_UART2 +# define TTYS3_DEV g_uart2port /* UART3=ttyS0;UART0=ttyS1;UART1=ttyS2;UART2=ttyS3 */ +# else +# undef TTYS3_DEV /* UART3=ttyS0;UART0=ttyS1;UART1=ttyS;No ttyS3 */ +# endif +# else +# ifdef CONFIG_LPC17_UART2 +# define TTYS2_DEV g_uart2port /* UART3=ttyS0;UART0=ttyS1;UART2=ttys2;No ttyS3 */ +# else +# undef TTYS2_DEV /* UART3=ttyS0;UART0=ttyS1;No ttyS2;No ttyS3 */ +# endif +# undef TTYS3_DEV /* No ttyS3 */ +# endif +# else +# ifdef CONFIG_LPC17_UART1 +# define TTYS1_DEV g_uart1port /* UART3=ttyS0;UART1=ttyS1 */ +# ifdef CONFIG_LPC17_UART2 +# define TTYS2_DEV g_uart2port /* UART3=ttyS0;UART1=ttyS1;UART2=ttyS2;No ttyS3 */ +# else +# undef TTYS2_DEV /* UART3=ttyS0;UART1=ttyS1;No ttyS2;No ttyS3 */ +# endif +# undef TTYS3_DEV /* No ttyS3 */ +# else +# ifdef CONFIG_LPC17_UART2 +# define TTYS1_DEV g_uart2port /* UART3=ttyS0;UART2=ttyS1;No ttyS3;No ttyS3 */ +# undef TTYS3_DEV /* UART3=ttyS0;UART2=ttyS1;No ttyS2;No ttyS3 */ +# else +# undef TTYS1_DEV /* UART3=ttyS0;No ttyS1;No ttyS2;No ttyS3 */ +# endif +# undef TTYS2_DEV /* No ttyS2 */ +# undef TTYS3_DEV /* No ttyS3 */ +# endif +# endif +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_serialin + ****************************************************************************/ + +static inline uint8_t up_serialin(struct up_dev_s *priv, int offset) +{ + return getreg8(priv->uartbase + offset); +} + +/**************************************************************************** + * Name: up_serialout + ****************************************************************************/ + +static inline void up_serialout(struct up_dev_s *priv, int offset, uint8_t value) +{ + putreg8(value, priv->uartbase + offset); +} + +/**************************************************************************** + * Name: up_disableuartint + ****************************************************************************/ + +static inline void up_disableuartint(struct up_dev_s *priv, uint8_t *ier) +{ + if (ier) + { + *ier = priv->ier & UART_IER_ALLIE; + } + + priv->ier &= ~UART_IER_ALLIE; + up_serialout(priv, LPC17_UART_IER_OFFSET, priv->ier); +} + +/**************************************************************************** + * Name: up_restoreuartint + ****************************************************************************/ + +static inline void up_restoreuartint(struct up_dev_s *priv, uint8_t ier) +{ + priv->ier |= ier & UART_IER_ALLIE; + up_serialout(priv, LPC17_UART_IER_OFFSET, priv->ier); +} + +/**************************************************************************** + * Name: up_enablebreaks + ****************************************************************************/ + +static inline void up_enablebreaks(struct up_dev_s *priv, bool enable) +{ + uint8_t lcr = up_serialin(priv, LPC17_UART_LCR_OFFSET); + if (enable) + { + lcr |= UART_LCR_BRK; + } + else + { + lcr &= ~UART_LCR_BRK; + } + up_serialout(priv, LPC17_UART_LCR_OFFSET, lcr); +} + +/**************************************************************************** + * Name: up_setup + * + * Description: + * Configure the UART baud, bits, parity, fifos, etc. This + * method is called the first time that the serial port is + * opened. + * + ****************************************************************************/ + +static int up_setup(struct uart_dev_s *dev) +{ +#ifndef CONFIG_SUPPRESS_LPC17_UART_CONFIG + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + uint16_t baud; + uint8_t lcr; + + /* Clear fifos */ + + up_serialout(priv, LPC17_UART_FCR_OFFSET, (UART_FCR_RXRST|UART_FCR_TXRST)); + + /* Set trigger */ + + up_serialout(priv, LPC17_UART_FCR_OFFSET, (UART_FCR_FIFOEN|UART_FCR_RXTRIGGER_8)); + + /* Set up the IER */ + + priv->ier = up_serialin(priv, LPC17_UART_IER_OFFSET); + + /* Set up the LCR */ + + lcr = 0; + + if (priv->bits == 7) + { + lcr |= UART_LCR_WLS_7BIT; + } + else + { + lcr |= UART_LCR_WLS_8BIT; + } + + if (priv->stopbits2) + { + lcr |= UART_LCR_STOP; + } + + if (priv->parity == 1) + { + lcr |= (UART_LCR_PE|UART_LCR_PS_ODD); + } + else if (priv->parity == 2) + { + lcr |= (UART_LCR_PE|UART_LCR_PS_EVEN); + } + + /* Enter DLAB=1 */ + + up_serialout(priv, LPC17_UART_LCR_OFFSET, (lcr | UART_LCR_DLAB)); + + /* Set the BAUD divisor */ + + baud = UART_BAUD(priv->baud); + up_serialout(priv, LPC17_UART_DLM_OFFSET, baud >> 8); + up_serialout(priv, LPC17_UART_DLL_OFFSET, baud & 0xff); + + /* Clear DLAB */ + + up_serialout(priv, LPC17_UART_LCR_OFFSET, lcr); + + /* Configure the FIFOs */ + + up_serialout(priv, LPC17_UART_FCR_OFFSET, + (UART_FCR_RXTRIGGER_8|UART_FCR_TXRST|UART_FCR_RXRST|UART_FCR_FIFOEN)); + + /* The NuttX serial driver waits for the first THRE interrrupt before + * sending serial data... However, it appears that the lpc17xx hardware + * does not generate that interrupt until a transition from not-empty + * to empty. So, the current kludge here is to send one NULL at + * startup to kick things off. + */ + + up_serialout(priv, LPC17_UART_THR_OFFSET, '\0'); +#endif + return OK; +} + +/**************************************************************************** + * Name: up_shutdown + * + * Description: + * Disable the UART. This method is called when the serial + * port is closed + * + ****************************************************************************/ + +static void up_shutdown(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + up_disableuartint(priv, NULL); +} + +/**************************************************************************** + * Name: up_attach + * + * Description: + * Configure the UART to operation in interrupt driven mode. This method is + * called when the serial port is opened. Normally, this is just after the + * the setup() method is called, however, the serial console may operate in + * a non-interrupt driven mode during the boot phase. + * + * RX and TX interrupts are not enabled when by the attach method (unless the + * hardware supports multiple levels of interrupt enabling). The RX and TX + * interrupts are not enabled until the txint() and rxint() methods are called. + * + ****************************************************************************/ + +static int up_attach(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + int ret; + + /* Attach and enable the IRQ */ + + ret = irq_attach(priv->irq, up_interrupt); + if (ret == OK) + { + /* Enable the interrupt (RX and TX interrupts are still disabled + * in the UART + */ + + up_enable_irq(priv->irq); + } + return ret; +} + +/**************************************************************************** + * Name: up_detach + * + * Description: + * Detach UART interrupts. This method is called when the serial port is + * closed normally just before the shutdown method is called. The exception is + * the serial console which is never shutdown. + * + ****************************************************************************/ + +static void up_detach(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + up_disable_irq(priv->irq); + irq_detach(priv->irq); +} + +/**************************************************************************** + * Name: up_interrupt + * + * Description: + * This is the UART interrupt handler. It will be invoked + * when an interrupt received on the 'irq' It should call + * uart_transmitchars or uart_receivechar to perform the + * appropriate data transfers. The interrupt handling logic\ + * must be able to map the 'irq' number into the approprite + * uart_dev_s structure in order to call these functions. + * + ****************************************************************************/ + +static int up_interrupt(int irq, void *context) +{ + struct uart_dev_s *dev = NULL; + struct up_dev_s *priv; + uint8_t status; + int passes; + + if (g_uart1priv.irq == irq) + { + dev = &g_uart1port; + } + else if (g_uart0priv.irq == irq) + { + dev = &g_uart0port; + } + else + { + PANIC(OSERR_INTERNAL); + } + priv = (struct up_dev_s*)dev->priv; + + /* Loop until there are no characters to be transferred or, + * until we have been looping for a long time. + */ + + for (passes = 0; passes < 256; passes++) + { + /* Get the current UART status and check for loop + * termination conditions + */ + + status = up_serialin(priv, LPC17_UART_IIR_OFFSET); + + /* The UART_IIR_INTSTATUS bit should be zero if there are pending + * interrupts + */ + + if ((status & UART_IIR_INTSTATUS) != 0) + { + /* Break out of the loop when there is no longer a + * pending interrupt + */ + + break; + } + + /* Handle the interrupt by its interrupt ID field */ + + switch (status & UART_IIR_INTID_MASK) + { + /* Handle incoming, receive bytes (with or without timeout) */ + + case UART_IIR_INTID_RDA: + case UART_IIR_INTID_CTI: + { + uart_recvchars(dev); + break; + } + + /* Handle outgoing, transmit bytes */ + + case UART_IIR_INTID_THRE: + { + uart_xmitchars(dev); + break; + } + + /* Just clear modem status interrupts (UART1 only) */ + + case UART_IIR_INTID_MSI: + { + /* Read the modem status register (MSR) to clear */ + + status = up_serialin(priv, LPC17_UART_MSR_OFFSET); + vdbg("MSR: %02x\n", status); + break; + } + + /* Just clear any line status interrupts */ + + case UART_IIR_INTID_RLS: + { + /* Read the line status register (LSR) to clear */ + + status = up_serialin(priv, LPC17_UART_LSR_OFFSET); + vdbg("LSR: %02x\n", status); + break; + } + + /* There should be no other values */ + + default: + { + dbg("Unexpected IIR: %02x\n", status); + break; + } + } + } + return OK; +} + +/**************************************************************************** + * Name: up_ioctl + * + * Description: + * All ioctl calls will be routed through this method + * + ****************************************************************************/ + +static int up_ioctl(struct file *filep, int cmd, unsigned long arg) +{ + struct inode *inode = filep->f_inode; + struct uart_dev_s *dev = inode->i_private; + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + int ret = OK; + + switch (cmd) + { + case TIOCSERGSTRUCT: + { + struct up_dev_s *user = (struct up_dev_s*)arg; + if (!user) + { + *get_errno_ptr() = EINVAL; + ret = ERROR; + } + else + { + memcpy(user, dev, sizeof(struct up_dev_s)); + } + } + break; + + case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ + { + irqstate_t flags = irqsave(); + up_enablebreaks(priv, true); + irqrestore(flags); + } + break; + + case TIOCCBRK: /* BSD compatibility: Turn break off, unconditionally */ + { + irqstate_t flags; + flags = irqsave(); + up_enablebreaks(priv, false); + irqrestore(flags); + } + break; + + default: + *get_errno_ptr() = ENOTTY; + ret = ERROR; + break; + } + + return ret; +} + +/**************************************************************************** + * Name: up_receive + * + * Description: + * Called (usually) from the interrupt level to receive one + * character from the UART. Error bits associated with the + * receipt are provided in the return 'status'. + * + ****************************************************************************/ + +static int up_receive(struct uart_dev_s *dev, uint32_t *status) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + uint8_t rbr; + + *status = up_serialin(priv, LPC17_UART_LSR_OFFSET); + rbr = up_serialin(priv, LPC17_UART_RBR_OFFSET); + return rbr; +} + +/**************************************************************************** + * Name: up_rxint + * + * Description: + * Call to enable or disable RX interrupts + * + ****************************************************************************/ + +static void up_rxint(struct uart_dev_s *dev, bool enable) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + if (enable) + { +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + priv->ier |= UART_IER_RBRIE; +#endif + } + else + { + priv->ier &= ~UART_IER_RBRIE; + } + up_serialout(priv, LPC17_UART_IER_OFFSET, priv->ier); +} + +/**************************************************************************** + * Name: up_rxavailable + * + * Description: + * Return true if the receive fifo is not empty + * + ****************************************************************************/ + +static bool up_rxavailable(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + return ((up_serialin(priv, LPC17_UART_LSR_OFFSET) & UART_LSR_RDR) != 0); +} + +/**************************************************************************** + * Name: up_send + * + * Description: + * This method will send one byte on the UART + * + ****************************************************************************/ + +static void up_send(struct uart_dev_s *dev, int ch) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + up_serialout(priv, LPC17_UART_THR_OFFSET, (uint8_t)ch); +} + +/**************************************************************************** + * Name: up_txint + * + * Description: + * Call to enable or disable TX interrupts + * + ****************************************************************************/ + +static void up_txint(struct uart_dev_s *dev, bool enable) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + if (enable) + { +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + priv->ier |= UART_IER_THREIE; +#endif + } + else + { + priv->ier &= ~UART_IER_THREIE; + } + up_serialout(priv, LPC17_UART_IER_OFFSET, priv->ier); +} + +/**************************************************************************** + * Name: up_txready + * + * Description: + * Return true if the tranmsit fifo is not full + * + ****************************************************************************/ + +static bool up_txready(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + return ((up_serialin(priv, LPC17_UART_LSR_OFFSET) & UART_LSR_THRE) != 0); +} + +/**************************************************************************** + * Name: up_txempty + * + * Description: + * Return true if the transmit fifo is empty + * + ****************************************************************************/ + +static bool up_txempty(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + return ((up_serialin(priv, LPC17_UART_LSR_OFFSET) & UART_LSR_THRE) != 0); +} + +/**************************************************************************** + * Public Funtions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_serialinit + * + * Description: + * Performs the low level UART initialization early in debug so that the + * serial console will be available during bootup. This must be called + * before up_serialinit. + * + * NOTE: Power, clocking, and pin configuration was performed in + * up_lowsetup() very, early in the boot sequence. + * + ****************************************************************************/ + +void up_earlyserialinit(void) +{ + /* Disable all UARTS */ + +#ifdef TTYS0_DEV + up_disableuartint(TTYS0_DEV.priv, NULL); +#endif +#ifdef TTYS1_DEV + up_disableuartint(TTYS1_DEV.priv, NULL); +#endif +#ifdef TTYS2_DEV + up_disableuartint(TTYS2_DEV.priv, NULL); +#endif +#ifdef TTYS3_DEV + up_disableuartint(TTYS3_DEV.priv, NULL); +#endif + + /* Configuration whichever one is the console */ + +#ifdef CONSOLE_DEV + CONSOLE_DEV.isconsole = true; + up_setup(&CONSOLE_DEV); +#endif +} + +/**************************************************************************** + * Name: up_serialinit + * + * Description: + * Register serial console and serial ports. This assumes that + * up_earlyserialinit was called previously. + * + ****************************************************************************/ + +void up_serialinit(void) +{ +#ifdef CONSOLE_DEV + (void)uart_register("/dev/console", &CONSOLE_DEV); +#endif +#ifdef TTYS0_DEV + (void)uart_register("/dev/ttyS0", &TTYS0_DEV); +#endif +#ifdef TTYS1_DEV + (void)uart_register("/dev/ttyS1", &TTYS1_DEV); +#endif +#ifdef TTYS2_DEV + (void)uart_register("/dev/ttyS2", &TTYS2_DEV); +#endif +#ifdef TTYS3_DEV + (void)uart_register("/dev/ttyS3", &TTYS3_DEV); +#endif +} + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +int up_putc(int ch) +{ + struct up_dev_s *priv = (struct up_dev_s*)CONSOLE_DEV.priv; + uint8_t ier; + + up_disableuartint(priv, &ier); + + /* Check for LF */ + + if (ch == '\n') + { + /* Add CR */ + + up_lowputc('\r'); + } + + up_lowputc(ch); + up_restoreuartint(priv, ier); + return ch; +} + +#else /* CONFIG_USE_SERIALDRIVER */ + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +int up_putc(int ch) +{ + /* Check for LF */ + + if (ch == '\n') + { + /* Add CR */ + + up_lowputc('\r'); + } + + up_lowputc(ch); + return ch; +} + +#endif /* CONFIG_USE_SERIALDRIVER */ diff --git a/arch/arm/src/lpc17xx/lpc17_serial.h b/arch/arm/src/lpc17xx/lpc17_serial.h new file mode 100755 index 00000000000..9f3355011b0 --- /dev/null +++ b/arch/arm/src/lpc17xx/lpc17_serial.h @@ -0,0 +1,327 @@ +/************************************************************************************ + * arch/arm/src/lpc17xx/lpc17_serial.h + * + * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_SERIAL_H +#define __ARCH_ARM_SRC_LPC17XX_LPC17_SERIAL_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Configuration *********************************************************************/ + +/* Is there a serial console? It could be on any UARTn, n=0,1,2,3 */ + +#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_LPC17_UART0) +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# define HAVE_CONSOLE 1 +#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_LPC17_UART1) +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# define HAVE_CONSOLE 1 +#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_LPC17_UART2) +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# define HAVE_CONSOLE 1 +#elif defined(CONFIG_UART3_SERIAL_CONSOLE) && defined(CONFIG_LPC17_UART3) +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# define HAVE_CONSOLE 1 +#else +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef HAVE_CONSOLE +#endif + +/* Select UART parameters for the selected console */ + +#if defined(CONFIG_UART0_SERIAL_CONSOLE) +# define CONSOLE_BASE LPC17_UART0_BASE +# define CONSOLE_BAUD CONFIG_UART0_BAUD +# define CONSOLE_BITS CONFIG_UART0_BITS +# define CONSOLE_PARITY CONFIG_UART0_PARITY +# define CONSOLE_2STOP CONFIG_UART0_2STOP +#elif defined(CONFIG_UART1_SERIAL_CONSOLE) +# define CONSOLE_BASE LPC17_UART1_BASE +# define CONSOLE_BAUD CONFIG_UART1_BAUD +# define CONSOLE_BITS CONFIG_UART1_BITS +# define CONSOLE_PARITY CONFIG_UART1_PARITY +# define CONSOLE_2STOP CONFIG_UART1_2STOP +#elif defined(CONFIG_UART2_SERIAL_CONSOLE) +# define CONSOLE_BASE LPC17_UART2_BASE +# define CONSOLE_BAUD CONFIG_UART2_BAUD +# define CONSOLE_BITS CONFIG_UART2_BITS +# define CONSOLE_PARITY CONFIG_UART2_PARITY +# define CONSOLE_2STOP CONFIG_UART2_2STOP +#elif defined(CONFIG_UART3_SERIAL_CONSOLE) +# define CONSOLE_BASE LPC17_UART3_BASE +# define CONSOLE_BAUD CONFIG_UART3_BAUD +# define CONSOLE_BITS CONFIG_UART3_BITS +# define CONSOLE_PARITY CONFIG_UART3_PARITY +# define CONSOLE_2STOP CONFIG_UART3_2STOP +#else +# error "No CONFIG_UARTn_SERIAL_CONSOLE Setting" +#endif + +/* Get word length setting for the console UART and UART0-3 */ + +#if CONSOLE_BITS == 5 +# define CONSOLE_LCR_WLS UART_LCR_WLS_5BIT +#elif CONSOLE_BITS == 6 +# define CONSOLE_LCR_WLS UART_LCR_WLS_6BIT +#elif CONSOLE_BITS == 7 +# define CONSOLE_LCR_WLS UART_LCR_WLS_7BIT +#elif CONSOLE_BITS == 8 +# define CONSOLE_LCR_WLS UART_LCR_WLS_8BIT +#else +# error "Invalid CONFIG_UARTn_BITS setting for console " +#endif + +#ifdef CONFIG_LPC17_UART0 +# if CONFIG_UART0_BITS == 5 +# define UART0_LCR_WLS UART_LCR_WLS_5BIT +# elif CONFIG_UART0_BITS == 6 +# define UART0_LCR_WLS UART_LCR_WLS_6BIT +# elif CONFIG_UART0_BITS == 7 +# define UART0_LCR_WLS UART_LCR_WLS_7BIT +# elif CONFIG_UART0_BITS == 8 +# define UART0_LCR_WLS UART_LCR_WLS_8BIT +# else +# error "Invalid CONFIG_UARTn_BITS setting for UART0 " +# endif +#endif + +#ifdef CONFIG_LPC17_UART1 +# if CONFIG_UART1_BITS == 5 +# define UART1_LCR_WLS UART_LCR_WLS_5BIT +# elif CONFIG_UART1_BITS == 6 +# define UART1_LCR_WLS UART_LCR_WLS_6BIT +# elif CONFIG_UART1_BITS == 7 +# define UART1_LCR_WLS UART_LCR_WLS_7BIT +# elif CONFIG_UART1_BITS == 8 +# define UART1_LCR_WLS UART_LCR_WLS_8BIT +# else +# error "Invalid CONFIG_UARTn_BITS setting for UART1 " +# endif +#endif + +#ifdef CONFIG_LPC17_UART2 +# if CONFIG_UART2_BITS == 5 +# define UART2_LCR_WLS UART_LCR_WLS_5BIT +# elif CONFIG_UART2_BITS == 6 +# define UART2_LCR_WLS UART_LCR_WLS_6BIT +# elif CONFIG_UART2_BITS == 7 +# define UART2_LCR_WLS UART_LCR_WLS_7BIT +# elif CONFIG_UART2_BITS == 8 +# define UART2_LCR_WLS UART_LCR_WLS_8BIT +# else +# error "Invalid CONFIG_UARTn_BITS setting for UART2 " +# endif +#endif + +#ifdef CONFIG_LPC17_UART3 +# if CONFIG_UART3_BITS == 5 +# define UART3_LCR_WLS UART_LCR_WLS_5BIT +# elif CONFIG_UART3_BITS == 6 +# define UART3_LCR_WLS UART_LCR_WLS_6BIT +# elif CONFIG_UART3_BITS == 7 +# define UART3_LCR_WLS UART_LCR_WLS_7BIT +# elif CONFIG_UART3_BITS == 8 +# define UART3_LCR_WLS UART_LCR_WLS_8BIT +# else +# error "Invalid CONFIG_UARTn_BITS setting for UART3 " +# endif +#endif + +/* Get parity setting for the console UART and UART0-3 */ + +#if CONSOLE_PARITY == 0 +# define CONSOLE_LCR_PAR 0 +#elif CONSOLE_PARITY == 1 +# define CONSOLE_LCR_PAR (UART_LCR_PE|UART_LCR_PS_ODD) +#elif CONSOLE_PARITY == 2 +# define CONSOLE_LCR_PAR (UART_LCR_PE|UART_LCR_PS_EVEN) +#elif CONSOLE_PARITY == 3 +# define CONSOLE_LCR_PAR (UART_LCR_PE|UART_LCR_PS_STICK1) +#elif CONSOLE_PARITY == 4 +# define CONSOLE_LCR_PAR (UART_LCR_PE|UART_LCR_PS_STICK0) +#else +# error "Invalid CONFIG_UARTn_PARITY setting for CONSOLE" +#endif + +#ifdef CONFIG_LPC17_UART0 +# if CONFIG_UART0_PARITY == 0 +# define UART0_LCR_PAR 0 +# elif CONFIG_UART0_PARITY == 1 +# define UART0_LCR_PAR (UART_LCR_PE|UART_LCR_PS_ODD) +# elif CONFIG_UART0_PARITY == 2 +# define UART0_LCR_PAR (UART_LCR_PE|UART_LCR_PS_EVEN) +# elif CONFIG_UART0_PARITY == 3 +# define UART0_LCR_PAR (UART_LCR_PE|UART_LCR_PS_STICK1) +# elif CONFIG_UART0_PARITY == 4 +# define UART0_LCR_PAR (UART_LCR_PE|UART_LCR_PS_STICK0) +# else +# error "Invalid CONFIG_UARTn_PARITY setting for UART0" +# endif +#endif + +#ifdef CONFIG_LPC17_UART1 +# if CONFIG_UART1_PARITY == 0 +# define UART1_LCR_PAR 0 +# elif CONFIG_UART1_PARITY == 1 +# define UART1_LCR_PAR (UART_LCR_PE|UART_LCR_PS_ODD) +# elif CONFIG_UART1_PARITY == 2 +# define UART1_LCR_PAR (UART_LCR_PE|UART_LCR_PS_EVEN) +# elif CONFIG_UART1_PARITY == 3 +# define UART1_LCR_PAR (UART_LCR_PE|UART_LCR_PS_STICK1) +# elif CONFIG_UART1_PARITY == 4 +# define UART1_LCR_PAR (UART_LCR_PE|UART_LCR_PS_STICK0) +# else +# error "Invalid CONFIG_UARTn_PARITY setting for UART1" +# endif +#endif + +#ifdef CONFIG_LPC17_UART2 +# if CONFIG_UART2_PARITY == 0 +# define UART2_LCR_PAR 0 +# elif CONFIG_UART2_PARITY == 1 +# define UART2_LCR_PAR (UART_LCR_PE|UART_LCR_PS_ODD) +# elif CONFIG_UART2_PARITY == 2 +# define UART2_LCR_PAR (UART_LCR_PE|UART_LCR_PS_EVEN) +# elif CONFIG_UART2_PARITY == 3 +# define UART2_LCR_PAR (UART_LCR_PE|UART_LCR_PS_STICK1) +# elif CONFIG_UART2_PARITY == 4 +# define UART2_LCR_PAR (UART_LCR_PE|UART_LCR_PS_STICK0) +# else +# error "Invalid CONFIG_UARTn_PARITY setting for UART2" +# endif +#endif + +#ifdef CONFIG_LPC17_UART3 +# if CONFIG_UART3_PARITY == 0 +# define UART3_LCR_PAR 0 +# elif CONFIG_UART3_PARITY == 1 +# define UART3_LCR_PAR (UART_LCR_PE|UART_LCR_PS_ODD) +# elif CONFIG_UART3_PARITY == 2 +# define UART3_LCR_PAR (UART_LCR_PE|UART_LCR_PS_EVEN) +# elif CONFIG_UART3_PARITY == 3 +# define UART3_LCR_PAR (UART_LCR_PE|UART_LCR_PS_STICK1) +# elif CONFIG_UART3_PARITY == 4 +# define UART3_LCR_PAR (UART_LCR_PE|UART_LCR_PS_STICK0) +# else +# error "Invalid CONFIG_UARTn_PARITY setting for UART3" +# endif +#endif + +/* Get stop-bit setting for the console UART and UART0-3 */ + +#if CONSOLE_2STOP != 0 +# define CONSOLE_LCR_STOP LPC214X_LCR_STOP_2 +#else +# define CONSOLE_LCR_STOP LPC214X_LCR_STOP_1 +#endif + +#if CONFIG_UART0_2STOP != 0 +# define UART0_LCR_STOP LPC214X_LCR_STOP_2 +#else +# define UART0_LCR_STOP LPC214X_LCR_STOP_1 +#endif + +#if CONFIG_UART1_2STOP != 0 +# define UART1_LCR_STOP LPC214X_LCR_STOP_2 +#else +# define UART1_LCR_STOP LPC214X_LCR_STOP_1 +#endif + +#if CONFIG_UART2_2STOP != 0 +# define UART2_LCR_STOP LPC214X_LCR_STOP_2 +#else +# define UART2_LCR_STOP LPC214X_LCR_STOP_1 +#endif + +#if CONFIG_UART3_2STOP != 0 +# define UART3_LCR_STOP LPC214X_LCR_STOP_2 +#else +# define UART3_LCR_STOP LPC214X_LCR_STOP_1 +#endif + +/* LCR and FCR values */ + +#define CONSOLE_LCR_VALUE (CONSOLE_LCR_WLS | CONSOLE_LCR_PAR | CONSOLE_LCR_STOP) +#define CONSOLE_FCR_VALUE (UART_FCR_RXTRIGGER_8 | UART_FCR_TXRST |\ + UART_FCR_RXRST | UART_FCR_FIFOEN) + +#define UART0_LCR_VALUE (UART0_LCR_WLS | UART0_LCR_PAR | UART0_LCR_STOP) +#define UART0_FCR_VALUE (UART_FCR_RXTRIGGER_8 | UART_FCR_TXRST |\ + UART_FCR_RXRST | UART_FCR_FIFOEN) + +#define UART1_LCR_VALUE (UART1_LCR_WLS | UART1_LCR_PAR | UART1_LCR_STOP) +#define UART1_FCR_VALUE (UART_FCR_RXTRIGGER_8 | UART_FCR_TXRST |\ + UART_FCR_RXRST | UART_FCR_FIFOEN) + +#define UART2_LCR_VALUE (UART2_LCR_WLS | UART2_LCR_PAR | UART2_LCR_STOP) +#define UART2_FCR_VALUE (UART_FCR_RXTRIGGER_8 | UART_FCR_TXRST |\ + UART_FCR_RXRST | UART_FCR_FIFOEN) + +#define UART3_LCR_VALUE (UART3_LCR_WLS | UART3_LCR_PAR | UART3_LCR_STOP) +#define UART3_FCR_VALUE (UART_FCR_RXTRIGGER_8 | UART_FCR_TXRST |\ + UART_FCR_RXRST | UART_FCR_FIFOEN) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_SERIAL_H */ diff --git a/arch/arm/src/lpc17xx/lpc17_uart.h b/arch/arm/src/lpc17xx/lpc17_uart.h index 5dfbfe16063..36ede428ba0 100755 --- a/arch/arm/src/lpc17xx/lpc17_uart.h +++ b/arch/arm/src/lpc17xx/lpc17_uart.h @@ -175,19 +175,21 @@ #define UART_IER_ABEOIE (1 << 8) /* Bit 8: Enables the end of auto-baud interrupt */ #define UART_IER_ABTOIE (1 << 9) /* Bit 9: Enables the auto-baud time-out interrupt */ /* Bits 10-31: Reserved */ +#define UART_IER_ALLIE (0x038f) + /* IIR Interrupt ID Register (all) */ #define UART_IIR_INTSTATUS (1 << 0) /* Bit 0: Interrupt status (active low) */ #define UART_IIR_INTID_SHIFT (1) /* Bits 1-3: Interrupt identification */ -#define UART_IIR_INTID_MASK (7 < UART_IIR_INTID_SHIFT) -# define UART_IIR_INTID_MSI (0 < UART_IIR_INTID_SHIFT) /* Modem Status (UART1 only) */ -# define UART_IIR_INTID_THRE (1 < UART_IIR_INTID_SHIFT) /* THRE Interrupt */ -# define UART_IIR_INTID_RDA (2 < UART_IIR_INTID_SHIFT) /* 2a - Receive Data Available (RDA */ -# define UART_IIR_INTID_RLS (3 < UART_IIR_INTID_SHIFT) /* 1 - Receive Line Status (RLS) */ -# define UART_IIR_INTID_CTI (6 < UART_IIR_INTID_SHIFT) /* 2b - Character Time-out Indicator (CTI) */ +#define UART_IIR_INTID_MASK (7 << UART_IIR_INTID_SHIFT) +# define UART_IIR_INTID_MSI (0 << UART_IIR_INTID_SHIFT) /* Modem Status (UART1 only) */ +# define UART_IIR_INTID_THRE (1 << UART_IIR_INTID_SHIFT) /* THRE Interrupt */ +# define UART_IIR_INTID_RDA (2 << UART_IIR_INTID_SHIFT) /* 2a - Receive Data Available (RDA */ +# define UART_IIR_INTID_RLS (3 << UART_IIR_INTID_SHIFT) /* 1 - Receive Line Status (RLS) */ +# define UART_IIR_INTID_CTI (6 << UART_IIR_INTID_SHIFT) /* 2b - Character Time-out Indicator (CTI) */ /* Bits 4-5: Reserved */ #define UART_IIR_FIFOEN_SHIFT (6) /* Bits 6-7: Copies of FCR bit 0 */ -#define UART_IIR_FIFOEN_MASK (3 < UART_IIR_FIFOEN_SHIFT) +#define UART_IIR_FIFOEN_MASK (3 << UART_IIR_FIFOEN_SHIFT) #define UART_IIR_ABEOINT (1 << 8) /* Bit 8: End of auto-baud interrupt */ #define UART_IIR_ABTOINT (1 << 9) /* Bit 9: Auto-baud time-out interrupt */ /* Bits 10-31: Reserved */ @@ -243,7 +245,7 @@ #define UART_LSR_BI (1 << 4) /* Bit 4: Break Interrupt */ #define UART_LSR_THRE (1 << 5) /* Bit 5: Transmitter Holding Register Empty */ #define UART_LSR_TEMT (1 << 6) /* Bit 6: Transmitter Empty */ -#define UART_LSR_RXFE (1 << 7) /* Bit 7: Error in RX FIFO (RXFE) +#define UART_LSR_RXFE (1 << 7) /* Bit 7: Error in RX FIFO (RXFE) */ /* Bits 8-31: Reserved */ /* MSR Modem Status Register (UART1 only) */ diff --git a/arch/arm/src/sam3u/sam3u_serial.c b/arch/arm/src/sam3u/sam3u_serial.c index 93ce1e8d514..4e32e8fa979 100755 --- a/arch/arm/src/sam3u/sam3u_serial.c +++ b/arch/arm/src/sam3u/sam3u_serial.c @@ -212,7 +212,7 @@ # ifdef CONFIG_SAM3U_USART3 # define TTYS2_DEV g_usart3port /* UART=ttyS0;USART2=ttyS1;USART3=ttyS2;No ttyS3;No ttyS4 */ # else -# undef TTYS3_DEV /* UART=ttyS0;USART2=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ +# undef TTYS2_DEV /* UART=ttyS0;USART2=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ # endif # else # ifdef CONFIG_SAM3U_USART3 @@ -449,7 +449,7 @@ # ifdef CONFIG_SAM3U_USART3 # define TTYS2_DEV g_usart3port /* USART2=ttyS0;USART1=ttyS1;USART3=ttyS2;No ttyS3;No ttyS4 */ # else -# undef TTYS3_DEV /* USART2=ttyS0;USART1=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ +# undef TTYS2_DEV /* USART2=ttyS0;USART1=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ # endif # else # ifdef CONFIG_SAM3U_USART3 @@ -528,7 +528,7 @@ # ifdef CONFIG_SAM3U_USART2 # define TTYS2_DEV g_EEEEport /* USART3=ttyS0;USART1=ttyS1;USART2=ttyS2;No ttyS3;No ttyS4 */ # else -# undef TTYS3_DEV /* USART3=ttyS0;USART1=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ +# undef TTYS2_DEV /* USART3=ttyS0;USART1=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ # endif # else # ifdef CONFIG_SAM3U_USART2 diff --git a/configs/nucleus2g/ostest/defconfig b/configs/nucleus2g/ostest/defconfig index 72e29a9e491..0e1b80f22eb 100755 --- a/configs/nucleus2g/ostest/defconfig +++ b/configs/nucleus2g/ostest/defconfig @@ -102,31 +102,35 @@ CONFIG_LPC17_BUILDROOT=y # Individual subsystems can be enabled: # # Individual subsystems can be enabled: -CONFIG_LP17_ETHERNET=n -CONFIG_LP17_USBHOST=n -CONFIG_LP17_USBOTG=n -CONFIG_LP17_USBDEV=n -CONFIG_LP17_CAN1=n -CONFIG_LP17_CAN2=n -CONFIG_LP17_SPI=n -CONFIG_LP17_SSP0=n -CONFIG_LP17_SSP1=n -CONFIG_LP17_I2C0=n -CONFIG_LP17_I2C1=n -CONFIG_LP17_I2S=n -CONFIG_LP17_TMR0=n -CONFIG_LP17_TMR1=n -CONFIG_LP17_TMR2=n -CONFIG_LP17_TMR3=n -CONFIG_LP17_RIT=n -CONFIG_LP17_PWM=n -CONFIG_LP17_MCPWM=n -CONFIG_LP17_QEI=n -CONFIG_LP17_RTC=n -CONFIG_LP17_WDT=n -CONFIG_LP17_ADC=n -CONFIG_LP17_DAC=n -CONFIG_LP17_GPDMA=n +CONFIG_LPC17_ETHERNET=n +CONFIG_LPC17_USBHOST=n +CONFIG_LPC17_USBOTG=n +CONFIG_LPC17_USBDEV=n +CONFIG_LPC17_UART0=y +CONFIG_LPC17_UART1=n +CONFIG_LPC17_UART2=n +CONFIG_LPC17_UART3=n +CONFIG_LPC17_CAN1=n +CONFIG_LPC17_CAN2=n +CONFIG_LPC17_SPI=n +CONFIG_LPC17_SSP0=n +CONFIG_LPC17_SSP1=n +CONFIG_LPC17_I2C0=n +CONFIG_LPC17_I2C1=n +CONFIG_LPC17_I2S=n +CONFIG_LPC17_TMR0=n +CONFIG_LPC17_TMR1=n +CONFIG_LPC17_TMR2=n +CONFIG_LPC17_TMR3=n +CONFIG_LPC17_RIT=n +CONFIG_LPC17_PWM=n +CONFIG_LPC17_MCPWM=n +CONFIG_LPC17_QEI=n +CONFIG_LPC17_RTC=n +CONFIG_LPC17_WDT=n +CONFIG_LPC17_ADC=n +CONFIG_LPC17_DAC=n +CONFIG_LPC17_GPDMA=n # # LPC17xx specific serial device driver settings @@ -142,40 +146,40 @@ CONFIG_LP17_GPDMA=n # CONFIG_UARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity # CONFIG_UARTn_2STOP - Two stop bits # -CONFIG_UART1_SERIAL_CONSOLE=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_UART1_SERIAL_CONSOLE=n CONFIG_UART2_SERIAL_CONSOLE=n CONFIG_UART3_SERIAL_CONSOLE=n -CONFIG_UART4_SERIAL_CONSOLE=n +CONFIG_UART0_TXBUFSIZE=256 CONFIG_UART1_TXBUFSIZE=256 CONFIG_UART2_TXBUFSIZE=256 CONFIG_UART3_TXBUFSIZE=256 -CONFIG_UART4_TXBUFSIZE=256 +CONFIG_UART0_RXBUFSIZE=256 CONFIG_UART1_RXBUFSIZE=256 CONFIG_UART2_RXBUFSIZE=256 CONFIG_UART3_RXBUFSIZE=256 -CONFIG_UART4_RXBUFSIZE=256 -CONFIG_UART1_BAUD=115200 +CONFIG_UART0_BAUD=115200 CONFIG_UART2_BAUD=115200 CONFIG_UART3_BAUD=115200 -CONFIG_UART4_BAUD=115200 +CONFIG_UART1_BAUD=115200 +CONFIG_UART0_BITS=8 CONFIG_UART1_BITS=8 CONFIG_UART2_BITS=8 CONFIG_UART3_BITS=8 -CONFIG_UART4_BITS=8 +CONFIG_UART0_PARITY=0 CONFIG_UART1_PARITY=0 CONFIG_UART2_PARITY=0 CONFIG_UART3_PARITY=0 -CONFIG_UART4_PARITY=0 +CONFIG_UART0_2STOP=0 CONFIG_UART1_2STOP=0 CONFIG_UART2_2STOP=0 CONFIG_UART3_2STOP=0 -CONFIG_UART4_2STOP=0 # # General build options @@ -295,7 +299,7 @@ CONFIG_EXAMPLE=ostest CONFIG_DEBUG=n CONFIG_DEBUG_VERBOSE=n CONFIG_DEBUG_SYMBOLS=n -CONFIG_MM_REGIONS=1 +CONFIG_MM_REGIONS=3 CONFIG_ARCH_LOWPUTC=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_INSTRUMENTATION=n