diff --git a/arch/arm/src/stm32/chip/stm32f33xxx_rcc.h b/arch/arm/src/stm32/chip/stm32f33xxx_rcc.h
index 806b22e0502..20c1f21756a 100644
--- a/arch/arm/src/stm32/chip/stm32f33xxx_rcc.h
+++ b/arch/arm/src/stm32/chip/stm32f33xxx_rcc.h
@@ -344,7 +344,7 @@
 #  define RCC_CFGR3_USART1SW_HSI    (0 << RCC_CFGR3_USART1SW_SHIFT) /* HSI clock */
 #define RCC_CFGR3_I2C1SW            (1 << 4)  /* Bit 4: I2C1 clock source selection */
 #define RCC_CFGR3_TIM1SW            (1 << 8)  /* Bit 8: TIM1 clock source selection */
-#define RCC_CFGR3_HRTIM1SW          (1 << 9)  /* Bit 9: HRTIM clock source selection */
+#define RCC_CFGR3_HRTIM1SW          (1 << 12)  /* Bit 12: HRTIM clock source selection */
 #define RCC_CFGR3_USART2SW_SHIFT    (16)      /* Bits 16-17: USART2 clock source selection */
 #define RCC_CFGR3_USART2SW_MASK     (3 << RCC_CFGR3_USART2SW_SHIFT)
 #  define RCC_CFGR3_USART2SW_PCLK   (0 << RCC_CFGR3_USART2SW_SHIFT) /* PCLK */
diff --git a/arch/arm/src/stm32/stm32_hrtim.c b/arch/arm/src/stm32/stm32_hrtim.c
index 109cf19da36..c553fdd6e22 100644
--- a/arch/arm/src/stm32/stm32_hrtim.c
+++ b/arch/arm/src/stm32/stm32_hrtim.c
@@ -437,10 +437,8 @@ static int stm32_hrtim_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
 
 /* HRTIM Register access */
 
-#ifdef HRTIM_HAVE_CLK_FROM_PLL
 static void stm32_modifyreg32(unsigned int addr, uint32_t clrbits,
                               uint32_t setbits);
-#endif
 static uint32_t hrtim_cmn_getreg(FAR struct stm32_hrtim_s *priv, int offset);
 static void hrtim_cmn_putreg(FAR struct stm32_hrtim_s *priv, int offset,
                              uint32_t value);
@@ -954,13 +952,11 @@ static int stm32_hrtim_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
  *
  ****************************************************************************/
 
-#ifdef HRTIM_HAVE_CLK_FROM_PLL
 static void stm32_modifyreg32(unsigned int addr, uint32_t clrbits,
                               uint32_t setbits)
 {
   putreg32((getreg32(addr) & ~clrbits) | setbits, addr);
 }
-#endif
 
 /****************************************************************************
  * Name: hrtim_cmn_getreg
@@ -2921,12 +2917,6 @@ static int stm32_hrtimconfig(FAR struct stm32_hrtim_s *priv)
   int ret;
   uint32_t regval = 0;
 
-  /* Configure PLL VCO output as HRTIM clock source */
-
-#ifdef HRTIM_HAVE_CLK_FROM_PLL
-  stm32_modifyreg32(STM32_RCC_CFGR3, 0, RCC_CFGR3_HRTIM1SW);
-#endif
-
   /* HRTIM DLL calibration */
 
   ret = hrtim_dll_cal(priv);
diff --git a/arch/arm/src/stm32/stm32f33xxx_rcc.c b/arch/arm/src/stm32/stm32f33xxx_rcc.c
index 6254294f5e2..76e19858f4b 100644
--- a/arch/arm/src/stm32/stm32f33xxx_rcc.c
+++ b/arch/arm/src/stm32/stm32f33xxx_rcc.c
@@ -342,129 +342,13 @@ static inline void rcc_enableapb2(void)
  * Name: stm32_stdclockconfig
  *
  * Description:
- *   Called to change to new clock based on settings in board.h.  This
- *   version is for the Connectivity Line parts.
+ *   Called to change to new clock based on settings in board.h.
  *
  *   NOTE:  This logic would need to be extended if you need to select low-
  *   power clocking modes!
  ****************************************************************************/
 
-#if !defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) && defined(CONFIG_STM32_CONNECTIVITYLINE)
-static void stm32_stdclockconfig(void)
-{
-  uint32_t regval;
-
-  /* Enable HSE */
-
-  regval  = getreg32(STM32_RCC_CR);
-  regval &= ~RCC_CR_HSEBYP;         /* Disable HSE clock bypass */
-  regval |= RCC_CR_HSEON;           /* Enable HSE */
-  putreg32(regval, STM32_RCC_CR);
-
-  /* Set flash wait states
-   * Sysclk runs with 72MHz -> 2 waitstates.
-   * 0WS from 0-24MHz
-   * 1WS from 24-48MHz
-   * 2WS from 48-72MHz
-   */
-
-  regval  = getreg32(STM32_FLASH_ACR);
-  regval &= ~FLASH_ACR_LATENCY_MASK;
-  regval |= (FLASH_ACR_LATENCY_2 | FLASH_ACR_PRTFBE);
-  putreg32(regval, STM32_FLASH_ACR);
-
-  /* Set up PLL input scaling (with source = PLL2) */
-
-  regval = getreg32(STM32_RCC_CFGR2);
-  regval &= ~(RCC_CFGR2_PREDIV2_MASK | RCC_CFGR2_PLL2MUL_MASK |
-              RCC_CFGR2_PREDIV1SRC_MASK | RCC_CFGR2_PREDIV1_MASK);
-  regval |=  (STM32_PLL_PREDIV2 | STM32_PLL_PLL2MUL |
-              RCC_CFGR2_PREDIV1SRC_PLL2 | STM32_PLL_PREDIV1);
-  putreg32(regval, STM32_RCC_CFGR2);
-
-  /* Set the PCLK2 divider */
-
-  regval = getreg32(STM32_RCC_CFGR);
-  regval &= ~(RCC_CFGR_PPRE2_MASK | RCC_CFGR_HPRE_MASK);
-  regval |= STM32_RCC_CFGR_PPRE2;
-  regval |= RCC_CFGR_HPRE_SYSCLK;
-  putreg32(regval, STM32_RCC_CFGR);
-
-  /* Set the PCLK1 divider */
-
-  regval = getreg32(STM32_RCC_CFGR);
-  regval &= ~RCC_CFGR_PPRE1_MASK;
-  regval |= STM32_RCC_CFGR_PPRE1;
-  putreg32(regval, STM32_RCC_CFGR);
-
-  /* Enable PLL2 */
-
-  regval = getreg32(STM32_RCC_CR);
-  regval |= RCC_CR_PLL2ON;
-  putreg32(regval, STM32_RCC_CR);
-
-  /* Wait for PLL2 ready */
-
-  while ((getreg32(STM32_RCC_CR) & RCC_CR_PLL2RDY) == 0);
-
-  /* Setup PLL3 for MII/RMII clock on MCO */
-
-#if defined(CONFIG_STM32_MII_MCO) || defined(CONFIG_STM32_RMII_MCO)
-  regval = getreg32(STM32_RCC_CFGR2);
-  regval &= ~(RCC_CFGR2_PLL3MUL_MASK);
-  regval |= STM32_PLL_PLL3MUL;
-  putreg32(regval, STM32_RCC_CFGR2);
-
-  /* Switch PLL3 on */
-
-  regval = getreg32(STM32_RCC_CR);
-  regval |= RCC_CR_PLL3ON;
-  putreg32(regval, STM32_RCC_CR);
-
-  while ((getreg32(STM32_RCC_CR) & RCC_CR_PLL3RDY) == 0);
-#endif
-
-  /* Set main PLL source and multiplier */
-
-  regval = getreg32(STM32_RCC_CFGR);
-  regval &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL_MASK);
-  regval |= (RCC_CFGR_PLLSRC | STM32_PLL_PLLMUL);
-  putreg32(regval, STM32_RCC_CFGR);
-
-  /* Switch main PLL on */
-
-  regval = getreg32(STM32_RCC_CR);
-  regval |= RCC_CR_PLLON;
-  putreg32(regval, STM32_RCC_CR);
-
-  while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0);
-
-  /* Select PLL as system clock source */
-
-  regval  = getreg32(STM32_RCC_CFGR);
-  regval &= ~RCC_CFGR_SW_MASK;
-  regval |= RCC_CFGR_SW_PLL;
-  putreg32(regval, STM32_RCC_CFGR);
-
-  /* Wait until PLL is used as the system clock source */
-
-  while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_PLL) == 0);
-}
-#endif
-
-/****************************************************************************
- * Name: stm32_stdclockconfig
- *
- * Description:
- *   Called to change to new clock based on settings in board.h.  This
- *   version is for the non-Connectivity Line parts.
- *
- *   NOTE:  This logic would need to be extended if you need to select low-
- *   power clocking modes!
- ****************************************************************************/
-
-#if !defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) && \
-    !defined(CONFIG_STM32_CONNECTIVITYLINE)
+#if !defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG)
 static void stm32_stdclockconfig(void)
 {
   uint32_t regval;
@@ -507,29 +391,6 @@ static void stm32_stdclockconfig(void)
       }
   }
 
-# if defined(CONFIG_STM32_VALUELINE) && (STM32_CFGR_PLLSRC == RCC_CFGR_PLLSRC)
-  /* If this is a value-line part and we are using the HSE as the PLL */
-
-# if (STM32_CFGR_PLLXTPRE >> 17) != (STM32_CFGR2_PREDIV1 & 1)
-#  error STM32_CFGR_PLLXTPRE must match the LSB of STM32_CFGR2_PREDIV1
-# endif
-
-  /* Set the HSE prescaler */
-
-  regval = STM32_CFGR2_PREDIV1;
-  putreg32(regval, STM32_RCC_CFGR2);
-
-# endif
-#endif
-
-#ifndef CONFIG_STM32_VALUELINE
-  /* Value-line devices don't implement flash prefetch/waitstates */
-  /* Enable FLASH prefetch buffer and 2 wait states */
-
-  regval  = getreg32(STM32_FLASH_ACR);
-  regval &= ~FLASH_ACR_LATENCY_MASK;
-  regval |= (FLASH_ACR_LATENCY_2 | FLASH_ACR_PRTFBE);
-  putreg32(regval, STM32_FLASH_ACR);
 #endif
 
   /* Set the HCLK source/divider */
@@ -607,6 +468,12 @@ static void stm32_stdclockconfig(void)
 
   stm32_rcc_enablelse();
 #endif
+
+#ifdef CONFIG_STM32_HRTIM_CLK_FROM_PLL
+  regval  = getreg32(STM32_RCC_CFGR3);
+  regval |= RCC_CFGR3_HRTIM1SW;
+  putreg32(regval, STM32_RCC_CFGR3);
+#endif
 }
 #endif