diff --git a/configs/sama5d3-xplained/include/board.h b/configs/sama5d3-xplained/include/board.h index 29ee7a96246..a49c5761370 100644 --- a/configs/sama5d3-xplained/include/board.h +++ b/configs/sama5d3-xplained/include/board.h @@ -80,7 +80,7 @@ * In this configuration, UPLL is the source of the UHPHS clock (if enabled). */ -# include +# include #else /* #elif defined(CONFIG_SAMA5D3XPLAINED_396MHZ) */ /* This is the configuration provided in the Atmel example code. This setup results diff --git a/configs/sama5d3-xplained/src/sam_sdram.c b/configs/sama5d3-xplained/src/sam_sdram.c index e5b6a64614c..c9cf8a5ea2d 100644 --- a/configs/sama5d3-xplained/src/sam_sdram.c +++ b/configs/sama5d3-xplained/src/sam_sdram.c @@ -4,7 +4,7 @@ * Copyright (C) 2014 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * - * Most of this file derives from Atmel sample code for the SAMA5D3 Xplained + * Most of this file derives from Atmel sample code for the SAMA5D3x-E * board. That sample code has licensing that is compatible with the NuttX * modified BSD license: * @@ -89,6 +89,38 @@ # error Unknown SDRAM type #endif +/* The delay loop in sam_sdram_delay requires 6 core cycles per iteration. + * + * At 384MHz: + * + * (6 cycles/iteration) / (0.384 cycles/nanosecond) = + * 15.6250 nanoseconds per iteration + * + * At 396MHz: + * + * (6 cycles/iteration) / (0.396 cycles/nanosecond) = + * 15.1515 nanoseconds per iteration + * + * At 528MHz: + * + * (6 cycles/iteration) / (0.528 cycles/nanosecond) = + * 11.3636 nanoseconds per iteration + */ + +#define LOOP_GUARD 100 +# define CYCLES_TO_COUNT(cycles) (((cycles) / 6) + LOOP_GUARD) + +#if defined(CONFIG_SAMA5D3XPLAINED_384MHZ) +# define NSEC_TO_COUNT(nsec) ((((nsec) * 1000) / 15625) + LOOP_GUARD) +# define USEC_TO_COUNT(usec) (((usec) * 1000000) / 15625) + LOOP_GUARD) +#elif defined(CONFIG_SAMA5D3XPLAINED_528MHZ) +# define NSEC_TO_COUNT(nsec) ((((nsec) * 1000) / 11364) + LOOP_GUARD) +# define USEC_TO_COUNT(usec) (((usec) * 1000000) / 11364) + LOOP_GUARD) +#else /* #elif defined(CONFIG_SAMA5D3XPLAINED_396MHZ) */ +# define NSEC_TO_COUNT(nsec) ((((nsec) * 1000) / 15152) + LOOP_GUARD) +# define USEC_TO_COUNT(usec) (((usec) * 1000000) / 15152) + LOOP_GUARD) +#endif + /**************************************************************************** * Private Functions ****************************************************************************/ @@ -99,8 +131,8 @@ * Description: * Precision delay function for SDRAM configuration. * - * This delay loop requires 6 core cycles per iteration. At 396MHz, that - * is equivalent to 15.1515 nanoseconds per iteration. + * This delay loop requires 6 core cycles per iteration. The actual + * amount of time delayed will then vary with PCK. * ****************************************************************************/ @@ -137,7 +169,7 @@ static inline void sam_sdram_delay(unsigned int loops) * Column address A[9:0] (1K) * Bank address BA[2:0] a(24,25) (8) * - * This logic was taken from Atmel sample code for the SAMA5D3-Xplained. + * This logic was taken from Atmel sample code for the SAMA5D3x-EK. * * Input Parameters: * devtype - Either DDRAM_MT47H128M16RT or DDRAM_MT47H64M16HR @@ -324,7 +356,7 @@ void sam_sdram_config(void) /* DDRSDRC Low-power Register */ - sam_sdram_delay(13300); + sam_sdram_delay(USEC_TO_COUNT(200)); regval = MPDDRC_LPR_LPCB_DISABLED | /* Low-power Feature is inhibited */ MPDDRC_LPR_TIMEOUT_0CLKS | /* Activates low-power mode after the end of transfer */ @@ -350,7 +382,7 @@ void sam_sdram_config(void) * (6 core cycles per iteration, core is at 396MHz: min 13200 loops) */ - sam_sdram_delay(13300); + sam_sdram_delay(USEC_TO_COUNT(200)); /* Step 4: An NOP command is issued to the DDR2-SDRAM */ @@ -363,7 +395,7 @@ void sam_sdram_config(void) /* Now CKE is driven high.*/ /* Wait 400 ns min */ - sam_sdram_delay(100); + sam_sdram_delay(NSEC_TO_COUNT(400)); /* Step 5: An all banks precharge command is issued to the DDR2-SDRAM. */ @@ -375,7 +407,7 @@ void sam_sdram_config(void) /* Wait 400 ns min */ - sam_sdram_delay(100); + sam_sdram_delay(NSEC_TO_COUNT(400)); /* Step 6: An Extended Mode Register set (EMRS2) cycle is issued to chose * between commercialor high temperature operations. @@ -389,7 +421,7 @@ void sam_sdram_config(void) /* Wait 2 cycles min */ - sam_sdram_delay(100); + sam_sdram_delay(100 /* CYCLES_TO_COUNT(2) */); /* Step 7: An Extended Mode Register set (EMRS3) cycle is issued to set * all registers to 0. @@ -403,7 +435,7 @@ void sam_sdram_config(void) /* Wait 2 cycles min */ - sam_sdram_delay(100); + sam_sdram_delay(100 /* CYCLES_TO_COUNT(2) */); /* Step 8: An Extended Mode Register set (EMRS1) cycle is issued to enable DLL. * @@ -415,7 +447,7 @@ void sam_sdram_config(void) /* An additional 200 cycles of clock are required for locking DLL */ - sam_sdram_delay(10000); + sam_sdram_delay(10000 /* CYCLES_TO_COUNT(200) */); /* Step 9: Program DLL field into the Configuration Register.*/ @@ -433,7 +465,7 @@ void sam_sdram_config(void) /* Wait 2 cycles min */ - sam_sdram_delay(100); + sam_sdram_delay(100 /* CYCLES_TO_COUNT(2) */); /* Step 11: An all banks precharge command is issued to the DDR2-SDRAM. * @@ -446,7 +478,7 @@ void sam_sdram_config(void) /* Wait 2 cycles min */ - sam_sdram_delay(100); + sam_sdram_delay(100 /* CYCLES_TO_COUNT(2) */); /* Step 12: Two auto-refresh (CBR) cycles are provided. Program the auto * refresh command (CBR) into the Mode Register. @@ -460,7 +492,7 @@ void sam_sdram_config(void) /* Wait 2 cycles min */ - sam_sdram_delay(100); + sam_sdram_delay(100 /* CYCLES_TO_COUNT(2) */); /* Configure 2nd CBR. * @@ -472,7 +504,7 @@ void sam_sdram_config(void) /* Wait 2 cycles min */ - sam_sdram_delay(100); + sam_sdram_delay(100 /* CYCLES_TO_COUNT(2) */); /* Step 13: Program DLL field into the Configuration Register to low * (Disable DLL reset). @@ -493,7 +525,7 @@ void sam_sdram_config(void) /* Wait 2 cycles min */ - sam_sdram_delay(100); + sam_sdram_delay(100 /* CYCLES_TO_COUNT(2) */); /* Step 15: Program OCD field into the Configuration Register to high (OCD * calibration default). @@ -515,7 +547,7 @@ void sam_sdram_config(void) /* Wait 2 cycles min */ - sam_sdram_delay(100); + sam_sdram_delay(100 /* CYCLES_TO_COUNT(2) */); /* Step 17: Program OCD field into the Configuration Register to low (OCD * calibration mode exit). @@ -539,7 +571,7 @@ void sam_sdram_config(void) /* Wait 2 cycles min */ - sam_sdram_delay(100); + sam_sdram_delay(100 /* CYCLES_TO_COUNT(2) */); /* Step 19,20: A mode Normal command is provided. Program the Normal mode * into Mode Register. diff --git a/configs/sama5d3x-ek/include/board.h b/configs/sama5d3x-ek/include/board.h index 2aad81d95e2..5f3ad98f133 100644 --- a/configs/sama5d3x-ek/include/board.h +++ b/configs/sama5d3x-ek/include/board.h @@ -80,7 +80,7 @@ * In this configuration, UPLL is the source of the UHPHS clock (if enabled). */ -# include +# include #else /* #elif defined(CONFIG_SAMA5D3xEK_396MHZ) */ /* This is the configuration provided in the Atmel example code. This setup results diff --git a/configs/sama5d3x-ek/src/sam_sdram.c b/configs/sama5d3x-ek/src/sam_sdram.c index 40cdbc5abd5..efb40684a5a 100644 --- a/configs/sama5d3x-ek/src/sam_sdram.c +++ b/configs/sama5d3x-ek/src/sam_sdram.c @@ -1,7 +1,7 @@ /**************************************************************************** * configs/sama5d3x-ek/src/sam_sdram.c * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2013-2014 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Most of this file derives from Atmel sample code for the SAMA5D3x-E @@ -89,6 +89,38 @@ # error Unknown SDRAM type #endif +/* The delay loop in sam_sdram_delay requires 6 core cycles per iteration. + * + * At 384MHz: + * + * (6 cycles/iteration) / (0.384 cycles/nanosecond) = + * 15.6250 nanoseconds per iteration + * + * At 396MHz: + * + * (6 cycles/iteration) / (0.396 cycles/nanosecond) = + * 15.1515 nanoseconds per iteration + * + * At 528MHz: + * + * (6 cycles/iteration) / (0.528 cycles/nanosecond) = + * 11.3636 nanoseconds per iteration + */ + +#define LOOP_GUARD 100 +# define CYCLES_TO_COUNT(cycles) (((cycles) / 6) + LOOP_GUARD) + +#if defined(CONFIG_SAMA5D3xEK_384MHZ) +# define NSEC_TO_COUNT(nsec) ((((nsec) * 1000) / 15625) + LOOP_GUARD) +# define USEC_TO_COUNT(usec) (((usec) * 1000000) / 15625) + LOOP_GUARD) +#elif defined(CONFIG_SAMA5D3xEK_528MHZ) +# define NSEC_TO_COUNT(nsec) ((((nsec) * 1000) / 11364) + LOOP_GUARD) +# define USEC_TO_COUNT(usec) (((usec) * 1000000) / 11364) + LOOP_GUARD) +#else /* #elif defined(CONFIG_SAMA5D3xEK_396MHZ) */ +# define NSEC_TO_COUNT(nsec) ((((nsec) * 1000) / 15152) + LOOP_GUARD) +# define USEC_TO_COUNT(usec) (((usec) * 1000000) / 15152) + LOOP_GUARD) +#endif + /**************************************************************************** * Private Functions ****************************************************************************/ @@ -99,8 +131,8 @@ * Description: * Precision delay function for SDRAM configuration. * - * This delay loop requires 6 core cycles per iteration. At 396MHz, that - * is equivalent to 15.1515 nanoseconds per iteration. + * This delay loop requires 6 core cycles per iteration. The actual + * amount of time delayed will then vary with PCK. * ****************************************************************************/ @@ -323,7 +355,7 @@ void sam_sdram_config(void) /* DDRSDRC Low-power Register */ - sam_sdram_delay(13300); + sam_sdram_delay(USEC_TO_COUNT(200)); regval = MPDDRC_LPR_LPCB_DISABLED | /* Low-power Feature is inhibited */ MPDDRC_LPR_TIMEOUT_0CLKS | /* Activates low-power mode after the end of transfer */ @@ -349,7 +381,7 @@ void sam_sdram_config(void) * (6 core cycles per iteration, core is at 396MHz: min 13200 loops) */ - sam_sdram_delay(13300); + sam_sdram_delay(USEC_TO_COUNT(200)); /* Step 4: An NOP command is issued to the DDR2-SDRAM */ @@ -362,7 +394,7 @@ void sam_sdram_config(void) /* Now CKE is driven high.*/ /* Wait 400 ns min */ - sam_sdram_delay(100); + sam_sdram_delay(NSEC_TO_COUNT(400)); /* Step 5: An all banks precharge command is issued to the DDR2-SDRAM. */ @@ -374,7 +406,7 @@ void sam_sdram_config(void) /* Wait 400 ns min */ - sam_sdram_delay(100); + sam_sdram_delay(NSEC_TO_COUNT(400)); /* Step 6: An Extended Mode Register set (EMRS2) cycle is issued to chose * between commercialor high temperature operations. @@ -388,7 +420,7 @@ void sam_sdram_config(void) /* Wait 2 cycles min */ - sam_sdram_delay(100); + sam_sdram_delay(100 /* CYCLES_TO_COUNT(2) */); /* Step 7: An Extended Mode Register set (EMRS3) cycle is issued to set * all registers to 0. @@ -402,7 +434,7 @@ void sam_sdram_config(void) /* Wait 2 cycles min */ - sam_sdram_delay(100); + sam_sdram_delay(100 /* CYCLES_TO_COUNT(2) */); /* Step 8: An Extended Mode Register set (EMRS1) cycle is issued to enable DLL. * @@ -414,7 +446,7 @@ void sam_sdram_config(void) /* An additional 200 cycles of clock are required for locking DLL */ - sam_sdram_delay(10000); + sam_sdram_delay(10000 /* CYCLES_TO_COUNT(200) */); /* Step 9: Program DLL field into the Configuration Register.*/ @@ -432,7 +464,7 @@ void sam_sdram_config(void) /* Wait 2 cycles min */ - sam_sdram_delay(100); + sam_sdram_delay(100 /* CYCLES_TO_COUNT(2) */); /* Step 11: An all banks precharge command is issued to the DDR2-SDRAM. * @@ -445,7 +477,7 @@ void sam_sdram_config(void) /* Wait 2 cycles min */ - sam_sdram_delay(100); + sam_sdram_delay(100 /* CYCLES_TO_COUNT(2) */); /* Step 12: Two auto-refresh (CBR) cycles are provided. Program the auto * refresh command (CBR) into the Mode Register. @@ -459,7 +491,7 @@ void sam_sdram_config(void) /* Wait 2 cycles min */ - sam_sdram_delay(100); + sam_sdram_delay(100 /* CYCLES_TO_COUNT(2) */); /* Configure 2nd CBR. * @@ -471,7 +503,7 @@ void sam_sdram_config(void) /* Wait 2 cycles min */ - sam_sdram_delay(100); + sam_sdram_delay(100 /* CYCLES_TO_COUNT(2) */); /* Step 13: Program DLL field into the Configuration Register to low * (Disable DLL reset). @@ -492,7 +524,7 @@ void sam_sdram_config(void) /* Wait 2 cycles min */ - sam_sdram_delay(100); + sam_sdram_delay(100 /* CYCLES_TO_COUNT(2) */); /* Step 15: Program OCD field into the Configuration Register to high (OCD * calibration default). @@ -514,7 +546,7 @@ void sam_sdram_config(void) /* Wait 2 cycles min */ - sam_sdram_delay(100); + sam_sdram_delay(100 /* CYCLES_TO_COUNT(2) */); /* Step 17: Program OCD field into the Configuration Register to low (OCD * calibration mode exit). @@ -538,7 +570,7 @@ void sam_sdram_config(void) /* Wait 2 cycles min */ - sam_sdram_delay(100); + sam_sdram_delay(100 /* CYCLES_TO_COUNT(2) */); /* Step 19,20: A mode Normal command is provided. Program the Normal mode * into Mode Register.