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Fixes for the STM32 OTG FS device driver

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4583 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
2012-04-10 18:27:13 +00:00
parent fb202ee945
commit 2272d671f0
2 changed files with 75 additions and 72 deletions
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arch/arm/src/stm32/chip/stm32_otgfs.h
+2 -2
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@@ -153,7 +153,7 @@
#define STM32_OTGFS_DIEPCTL2_OFFSET 0x0940 /* Device control IN endpoint 3 control register */
#define STM32_OTGFS_DIEPCTL3_OFFSET 0x0960 /* Device control IN endpoint 4 control register */
#define STM32_OTGFS_DIEPINT_OFFSET(n) 0x0908 /* Device endpoint-n interrupt register */
#define STM32_OTGFS_DIEPINT_OFFSET(n) (0x0908 + ((n) << 5))
#define STM32_OTGFS_DIEPINT0_OFFSET 0x0908 /* Device endpoint-0 interrupt register */
#define STM32_OTGFS_DIEPINT1_OFFSET 0x0928 /* Device endpoint-1 interrupt register */
#define STM32_OTGFS_DIEPINT2_OFFSET 0x0948 /* Device endpoint-2 interrupt register */
@@ -171,7 +171,7 @@
#define STM32_OTGFS_DTXFSTS2_OFFSET 0x0958 /* Device OUT endpoint-2 transfer size register */
#define STM32_OTGFS_DTXFSTS3_OFFSET 0x0978 /* Device OUT endpoint-3 transfer size register */
#define STM32_OTGFS_DOEP_OFFSET(n) 0x0b00 + ((n) << 5))
#define STM32_OTGFS_DOEP_OFFSET(n) (0x0b00 + ((n) << 5))
#define STM32_OTGFS_DOEPCTL_EPOFFSET 0x0000 /* Device control OUT endpoint 0 control register */
#define STM32_OTGFS_DOEPINT_EPOFFSET 0x0008 /* Device endpoint-x interrupt register */
arch/arm/src/stm32/stm32_otgfsdev.c
+73 -70
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