diff --git a/arch/Kconfig b/arch/Kconfig index 319419bb2d1..a3c43d12d8b 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -52,6 +52,13 @@ config ARCH_RENESAS ---help--- Renesas architectures (SH and M16C). +config ARCH_RISCV + bool "RISC-V" + select ARCH_HAVE_INTERRUPTSTACK + select ARCH_HAVE_CUSTOMOPT + ---help--- + RISC-V 32 and 64-bit RV32 / RV64 architectures. + config ARCH_SIM bool "Simulation" select ARCH_HAVE_MULTICPU @@ -89,6 +96,7 @@ config ARCH default "mips" if ARCH_MIPS default "rgmp" if ARCH_RGMP default "renesas" if ARCH_RENESAS + default "risc-v" if ARCH_RISCV default "sim" if ARCH_SIM default "x86" if ARCH_X86 default "z16" if ARCH_Z16 @@ -100,6 +108,7 @@ source arch/hc/Kconfig source arch/mips/Kconfig source arch/rgmp/Kconfig source arch/renesas/Kconfig +source arch/risc-v/Kconfig source arch/sim/Kconfig source arch/x86/Kconfig source arch/z16/Kconfig @@ -540,6 +549,7 @@ config ARCH_USBDUMP config ENDIAN_BIG bool "Big Endian Architecture" default n + depends on !ARCH_RISCV ---help--- Select if architecture operates using big-endian byte ordering. diff --git a/arch/README.txt b/arch/README.txt index bd49fb31a7c..60676699764 100644 --- a/arch/README.txt +++ b/arch/README.txt @@ -233,6 +233,15 @@ arch/rgmp See http://rgmp.sourceforge.net/wiki/index.php/Main_Page for further information about RGMP. +arch/risc-v + This directory is dedicated to ports to the RISC-V family. + + Architecture Support + arch/risc-v/include/rv32im + + MCU support + arch/risc-v/include/nr5m100 + arch/x86 - Intel x86 architectures This directory holds related, 32- and 64-bit architectures from Intel. At present, this includes the following subdirectories: diff --git a/arch/risc-v/Kconfig b/arch/risc-v/Kconfig new file mode 100644 index 00000000000..65ed34459fb --- /dev/null +++ b/arch/risc-v/Kconfig @@ -0,0 +1,55 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_RISCV +comment "RISC-V Options" + +choice + prompt "RISC-V chip selection" + default ARCH_CHIP_NR5M100 + +config ARCH_CHIP_NR5M100 + bool "NEXT NanoRisc5 M100" + select ARCH_RV32IM + default ARCH_CHIP_NR5 + ---help--- + NEXT RISC-V NR5Mxx architectures (RISC-V RV32IM cores). + +endchoice + +config ARCH_RV32I + bool + default n + +config ARCH_RV32IM + bool + default n + +config ARCH_FAMILY + string + default "rv32im" if ARCH_RM32IM + +config ARCH_CHIP + string + default "nr5m100" if ARCH_CHIP_NR5M100 + +config NR5_MPU + bool "MPU support" + default n + depends on ARCH_HAVE_MPU + select ARCH_USE_MPU + ---help--- + Build in support for the RISC-V Memory Protection Unit (MPU). + Check your chip specifications first; not all RISC-V architectures + support the MPU. + +if ARCH_RV32IM +source arch/risc-v/src/rv32im/Kconfig +endif +if ARCH_CHIP_NR5M100 +source arch/risc-v/src/nr5m100/Kconfig +endif + +endif diff --git a/arch/risc-v/include/arch.h b/arch/risc-v/include/arch.h new file mode 100644 index 00000000000..e0e60b4e1b2 --- /dev/null +++ b/arch/risc-v/include/arch.h @@ -0,0 +1,119 @@ +/**************************************************************************** + * arch/risc-v/include/arch.h + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* This file should never be included directed but, rather, + * only indirectly through nuttx/arch.h + */ + +#ifndef __ARCH_RISCV_INCLUDE_ARCH_H +#define __ARCH_RISCV_INCLUDE_ARCH_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +#ifdef CONFIG_ARCH_RV32IM +# include "rv32im/csr.h" +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Macros to get the core and vendor ID, HART, arch and ISA codes, etc. + */ +#ifdef CONFIG_RV32IM_SYSTEM_CSRRS_SUPPORT + +uint32_t up_getmisa(void); +uint32_t up_getarchid(void); +uint32_t up_getimpid(void); +uint32_t up_getvendorid(void); +uint32_t up_gethartid(void); + +#else + +#define up_getmisa() 0 +#define up_getarchid() 0 +#define up_getimpid() 0 +#define up_getvendorid() 0 +#define up_gethartid() 0 + +#endif + +/**************************************************************************** + * Inline functions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Variables + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef CONFIG_RV32IM_HW_MULDIV +uint32_t up_hard_mul(uint32_t a, uint32_t b); +uint32_t up_hard_mulh(uint32_t a, uint32_t b); +uint32_t up_hard_mulhsu(uint32_t a, uint32_t b); +uint32_t up_hard_mulhu(uint32_t a, uint32_t b); +uint32_t up_hard_div(uint32_t a, uint32_t b); +uint32_t up_hard_rem(uint32_t a, uint32_t b); +uint32_t up_hard_divu(uint32_t a, uint32_t b); +uint32_t up_hard_remu(uint32_t a, uint32_t b); +uint32_t time_hard_mul(uint32_t a, uint32_t b, uint32_t *t); +#endif + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ARCH_RISCV_INCLUDE_ARCH_H */ + diff --git a/arch/risc-v/include/irq.h b/arch/risc-v/include/irq.h new file mode 100644 index 00000000000..7de60dc316a --- /dev/null +++ b/arch/risc-v/include/irq.h @@ -0,0 +1,79 @@ +/**************************************************************************** + * arch/risc-v/include/irq.h + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly + * through nuttx/irq.h + */ + +#ifndef __ARCH_RISCV_INCLUDE_IRQ_H +#define __ARCH_RISCV_INCLUDE_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* Include chip-specific IRQ definitions (including IRQ numbers) */ + +#include +#include +#include + +/* Include RISC-V architecture-specific IRQ definitions */ + +#if defined(CONFIG_ARCH_RV32IM) || defined(CONFIG_ARCH_RV32I) +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +typedef uint32_t irqstate_t; + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Variables + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +irqstate_t irqsave(void); + +void irqrestore(irqstate_t); + +#endif /* __ARCH_RISCV_INCLUDE_IRQ_H */ + diff --git a/arch/risc-v/include/limits.h b/arch/risc-v/include/limits.h new file mode 100644 index 00000000000..6be24b9b417 --- /dev/null +++ b/arch/risc-v/include/limits.h @@ -0,0 +1,90 @@ +/**************************************************************************** + * arch/risc-v/include/limits.h + * + * Copyright (C) 2007-2009, 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_INCLUDE_LIMITS_H +#define __ARCH_RISCV_INCLUDE_LIMITS_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define CHAR_BIT 8 +#define SCHAR_MIN (-SCHAR_MAX - 1) +#define SCHAR_MAX 127 +#define UCHAR_MAX 255 + +/* These could be different on machines where char is unsigned */ + +#ifdef __CHAR_UNSIGNED__ +#define CHAR_MIN 0 +#define CHAR_MAX UCHAR_MAX +#else +#define CHAR_MIN SCHAR_MIN +#define CHAR_MAX SCHAR_MAX +#endif + +#define SHRT_MIN (-SHRT_MAX - 1) +#define SHRT_MAX 32767 +#define USHRT_MAX 65535U + +#define INT_MIN (-INT_MAX - 1) +#define INT_MAX 2147483647 +#define UINT_MAX 4294967295U + +/* These change on 32-bit and 64-bit platforms */ + +#if defined(CONFIG_ARCH_32IM) || defined(CONFIG_ARCH_32I) + +#define LONG_MIN (-LONG_MAX - 1) +#define LONG_MAX 2147483647L +#define ULONG_MAX 4294967295UL + +#define LLONG_MIN (-LLONG_MAX - 1) +#define LLONG_MAX 9223372036854775807LL +#define ULLONG_MAX 18446744073709551615ULL + +/* A pointer is 4 bytes */ + +#define PTR_MIN (-PTR_MAX - 1) +#define PTR_MAX 2147483647 +#define UPTR_MAX 4294967295U + +#endif /* defined(CONFIG_ARCH_32IM) || defined(CONFIG_ARCH_32I) */ + +#endif /* __ARCH_RISCV_INCLUDE_LIMITS_H */ diff --git a/arch/risc-v/include/nr5m100/chip.h b/arch/risc-v/include/nr5m100/chip.h new file mode 100644 index 00000000000..79d681f6e22 --- /dev/null +++ b/arch/risc-v/include/nr5m100/chip.h @@ -0,0 +1,61 @@ +/**************************************************************************** + * arch/risc-v/include/nr5m100/chip.h + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly + * through nuttx/irq.h + */ + +#ifndef __ARCH_RISCV_INCLUDE_NR5M100_CHIP_H +#define __ARCH_RISCV_INCLUDE_NR5M100_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Variables + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#endif /* __ARCH_RISCV_INCLUDE_NR5M100_CHIP_H */ + diff --git a/arch/risc-v/include/nr5m100/irq.h b/arch/risc-v/include/nr5m100/irq.h new file mode 100644 index 00000000000..d8d1806d1e8 --- /dev/null +++ b/arch/risc-v/include/nr5m100/irq.h @@ -0,0 +1,73 @@ +/**************************************************************************** + * arch/risc-v/include/nr5m100/irq.h + * include/arch/nr5m100/irq.h + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_INCLUDE_NR5M100_IRQ_H +#define __ARCH_RISCV_INCLUDE_NR5M100_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if defined(CONFIG_NR5_NR5M1XX) +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define NR5_IRQ_TRAP 0 + +#define EPIC_STATUS_PRI_MASK 0x001C +#define EPIC_STATUS_INT_PRI_MASK 0x01C0 +#define EPIC_STATUS_INT_PRI1 0x0040 + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Variables + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +void up_enable_irq(int irq); + +irqstate_t up_irq_save(void); +void up_irq_restore(irqstate_t irqstate); + +#endif /* __ARCH_RISCV_INCLUDE_NR5M100_IRQ_H */ + diff --git a/arch/risc-v/include/nr5m100/nr5m1xx_irq.h b/arch/risc-v/include/nr5m100/nr5m1xx_irq.h new file mode 100644 index 00000000000..ceffbb2985d --- /dev/null +++ b/arch/risc-v/include/nr5m100/nr5m1xx_irq.h @@ -0,0 +1,71 @@ +/**************************************************************************** + * arch/risc-v/include/nr5m100/nr5m1xx_irq.h + * include/arch/nr5m100/nr5m1xx_irq.h + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_INCLUDE_NR5M100_NR5M1XX_IRQ_H +#define __ARCH_RISCV_INCLUDE_NR5M100_NR5M1XX_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define NR5_IRQ_SYSTICK 1 +#define NR5_IRQ_TIMER 2 +#define NR5_IRQ_SOFTWARE 3 +#define NR5_IRQ_DEBUG 4 +#define NR5_IRQ_UART1_RX 5 +#define NR5_IRQ_UART1_TX 6 +#define NR5_IRQ_TIMER1_A 7 +#define NR5_IRQ_TIMER1_B 8 +#define NR5_IRQ_TIMER2_A 9 +#define NR5_IRQ_TIMER2_B 10 + +#define NR_IRQS 11 + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Variables + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#endif /* __ARCH_RISCV_INCLUDE_NR5M100_NR5M1XX_IRQ_H */ + diff --git a/arch/risc-v/include/rv32im/csr.h b/arch/risc-v/include/rv32im/csr.h new file mode 100644 index 00000000000..3aac4173e65 --- /dev/null +++ b/arch/risc-v/include/rv32im/csr.h @@ -0,0 +1,100 @@ +/**************************************************************************** + * arch/risc-v/include/rv32im/csr.h + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly + * through nuttx/irq.h + */ + +#ifndef __ARCH_RISCV_INCLUDE_RV32IM_CSR_H +#define __ARCH_RISCV_INCLUDE_RV32IM_CSR_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Machine Information Registers */ + +#define CSR_MISA 0xF10 +#define CSR_MVENDORID 0xF11 +#define CSR_MARCHID 0xF12 +#define CSR_MIMPID 0xF13 +#define CSR_MHARTID 0xF14 + +/* Machine Trap Registers */ + +#define CSR_MSTATUS 0x300 +#define CSR_MTDELEG 0x302 +#define CSR_MIE 0x304 +#define CSR_MTVEC 0x305 +#define CSR_MIVEC 0x30f + +/* Machine Trap Handling */ + +#define CSR_MSCRATCH 0x340 +#define CSR_MEPC 0x341 +#define CSR_MCAUSE 0x342 +#define CSR_MBADADDR 0x343 +#define CSR_MIP 0x344 + +/* Machine Timers and Counters */ + +#define CSR_CYCLE 0xF00 +#define CSR_TIME 0xF01 +#define CSR_INSTRET 0xF02 +#define CSR_CYCLEH 0xF80 +#define CSR_TIMEH 0xF81 +#define CSR_INSTRETH 0xF82 + +/* Debug interface CSRs */ + +#define CSR_DCSR 0x7B0 +#define CSR_DPC 0x7B1 +#define CSR_DSCRATCH 0x7B2 + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Variables + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#endif /* __ARCH_RISCV_INCLUDE_RV32IM_CSR_H */ + diff --git a/arch/risc-v/include/rv32im/irq.h b/arch/risc-v/include/rv32im/irq.h new file mode 100644 index 00000000000..0a9010703f4 --- /dev/null +++ b/arch/risc-v/include/rv32im/irq.h @@ -0,0 +1,347 @@ +/**************************************************************************** + * arch/risc-v/include/rv32im/irq.h + * + * Copyright (C) 2011, 2013, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Modified for RISC-V: + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly + * through nuttx/irq.h + */ + +#ifndef __ARCH_RISCV_INCLUDE_RV32IM_IRQ_H +#define __ARCH_RISCV_INCLUDE_RV32IM_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* Configuration ************************************************************/ + +/* If this is a kernel build, how many nested system calls should we support? */ + +#ifndef CONFIG_SYS_NNEST +# define CONFIG_SYS_NNEST 2 +#endif + +/* Processor PC */ +#define REG_EPC_NDX 0 + +/* General pupose registers */ +/* $0: Zero register does not need to be saved */ +/* $1: ra (return address) */ + +#define REG_X1_NDX 1 + +/* $2: Stack POinter + * $3: Global Pointer + * $4: Thread Pointer + */ + +#define REG_X2_NDX 2 +#define REG_X3_NDX 3 +#define REG_X4_NDX 4 + +/* $5-$7 = t0-t3: Temporary registers */ + +#define REG_X5_NDX 5 +#define REG_X6_NDX 6 +#define REG_X7_NDX 7 + +/* $8: s0 / fp Frame pointer */ + +#define REG_X8_NDX 8 + +/* $89 s1 Saved register */ + +#define REG_X9_NDX 9 + +/* $10-$17 = a0-a7: Argument registers */ + +#define REG_X10_NDX 10 +#define REG_X11_NDX 11 +#define REG_X12_NDX 12 +#define REG_X13_NDX 13 +#define REG_X14_NDX 14 +#define REG_X15_NDX 15 +#define REG_X16_NDX 16 +#define REG_X17_NDX 17 + +/* $18-$27 = s2-s11: Saved registers */ + +#define REG_X18_NDX 18 +#define REG_X19_NDX 19 +#define REG_X20_NDX 20 +#define REG_X21_NDX 21 +#define REG_X22_NDX 22 +#define REG_X23_NDX 23 +#define REG_X24_NDX 24 +#define REG_X25_NDX 25 +#define REG_X26_NDX 26 +#define REG_X27_NDX 27 + +/* $28-31 = t3-t6: Temporary (Volatile) registers */ + +#define REG_X28_NDX 28 +#define REG_X29_NDX 29 +#define REG_X30_NDX 30 +#define REG_X31_NDX 31 + +/* Interrupt Context register */ + +#define REG_INT_CTX_NDX 32 + +#define XCPTCONTEXT_REGS 33 +#define XCPTCONTEXT_SIZE (4 * XCPTCONTEXT_REGS) + +/* In assembly language, values have to be referenced as byte address + * offsets. But in C, it is more convenient to reference registers as + * register save table offsets. + */ + +#ifdef __ASSEMBLY__ +# define REG_EPC (4*REG_EPC_NDX) +# define REG_X1 (4*REG_X1_NDX) +# define REG_X2 (4*REG_X2_NDX) +# define REG_X3 (4*REG_X3_NDX) +# define REG_X4 (4*REG_X4_NDX) +# define REG_X5 (4*REG_X5_NDX) +# define REG_X6 (4*REG_X6_NDX) +# define REG_X7 (4*REG_X7_NDX) +# define REG_X8 (4*REG_X8_NDX) +# define REG_X9 (4*REG_X9_NDX) +# define REG_X10 (4*REG_X10_NDX) +# define REG_X11 (4*REG_X11_NDX) +# define REG_X12 (4*REG_X12_NDX) +# define REG_X13 (4*REG_X13_NDX) +# define REG_X14 (4*REG_X14_NDX) +# define REG_X15 (4*REG_X15_NDX) +# define REG_X16 (4*REG_X16_NDX) +# define REG_X17 (4*REG_X17_NDX) +# define REG_X18 (4*REG_X18_NDX) +# define REG_X19 (4*REG_X19_NDX) +# define REG_X20 (4*REG_X20_NDX) +# define REG_X21 (4*REG_X21_NDX) +# define REG_X22 (4*REG_X22_NDX) +# define REG_X23 (4*REG_X23_NDX) +# define REG_X24 (4*REG_X24_NDX) +# define REG_X25 (4*REG_X25_NDX) +# define REG_X26 (4*REG_X26_NDX) +# define REG_X27 (4*REG_X27_NDX) +# define REG_X28 (4*REG_X28_NDX) +# define REG_X29 (4*REG_X29_NDX) +# define REG_X30 (4*REG_X30_NDX) +# define REG_X31 (4*REG_X31_NDX) +# define REG_INT_CTX (4*REG_INT_CTX_NDX) +#else +# define REG_EPC REG_EPC_NDX +# define REG_X1 REG_X1_NDX +# define REG_X2 REG_X2_NDX +# define REG_X3 REG_X3_NDX +# define REG_X4 REG_X4_NDX +# define REG_X5 REG_X5_NDX +# define REG_X6 REG_X6_NDX +# define REG_X7 REG_X7_NDX +# define REG_X8 REG_X8_NDX +# define REG_X9 REG_X9_NDX +# define REG_X10 REG_X10_NDX +# define REG_X11 REG_X11_NDX +# define REG_X12 REG_X12_NDX +# define REG_X13 REG_X13_NDX +# define REG_X14 REG_X14_NDX +# define REG_X15 REG_X15_NDX +# define REG_X16 REG_X16_NDX +# define REG_X17 REG_X17_NDX +# define REG_X18 REG_X18_NDX +# define REG_X19 REG_X19_NDX +# define REG_X20 REG_X20_NDX +# define REG_X21 REG_X21_NDX +# define REG_X22 REG_X22_NDX +# define REG_X23 REG_X23_NDX +# define REG_X24 REG_X24_NDX +# define REG_X25 REG_X25_NDX +# define REG_X26 REG_X26_NDX +# define REG_X27 REG_X27_NDX +# define REG_X28 REG_X28_NDX +# define REG_X29 REG_X29_NDX +# define REG_X30 REG_X30_NDX +# define REG_X31 REG_X31_NDX +# define REG_INT_CTX REG_INT_CTX_NDX +#endif + +/* Now define more user friendly alternative name that can be used either + * in assembly or C contexts. + */ + +/* $1 = ra: Return address */ + +#define REG_RA REG_X1 + +/* $2 = sp: The value of the stack pointer on return from the exception */ + +#define REG_SP REG_X2 + +/* $3 = gp: Only needs to be saved under conditions where there are + * multiple, per-thread values for the GP. + */ + +#define REG_GP REG_X3 + +/* $4 = tp: Thread Pointer */ + +#define REG_TP REG_X4 + +/* $5-$7 = t0-t2: Caller saved temporary registers */ + +#define REG_T0 REG_X5 +#define REG_T1 REG_X6 +#define REG_T2 REG_X7 + +/* $8 = either s0 or fp: Depends if a frame pointer is used or not */ + +#define REG_S0 REG_X8 +#define REG_FP REG_X8 + +/* $9 = s1: Caller saved register */ + +#define REG_S1 REG_X9 + +/* $10-$17 = a0-a7: Argument registers */ + +#define REG_A0 REG_X10 +#define REG_A1 REG_X11 +#define REG_A2 REG_X12 +#define REG_A3 REG_X13 +#define REG_A4 REG_X14 +#define REG_A5 REG_X15 +#define REG_A6 REG_X16 +#define REG_A7 REG_X17 + +/* $18-$27 = s2-s11: Callee saved registers */ + +#define REG_S2 REG_X18 +#define REG_S3 REG_X19 +#define REG_S4 REG_X20 +#define REG_S5 REG_X21 +#define REG_S6 REG_X22 +#define REG_S7 REG_X23 +#define REG_S8 REG_X24 +#define REG_S9 REG_X25 +#define REG_S10 REG_X26 +#define REG_S11 REG_X27 + +/* $28-$31 = t3-t6: Caller saved temporary registers */ + +#define REG_T3 REG_X28 +#define REG_T4 REG_X29 +#define REG_T5 REG_X30 +#define REG_T6 REG_X31 + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/* This structure represents the return state from a system call */ + +#ifdef CONFIG_BUILD_KERNEL +struct xcpt_syscall_s +{ + uint32_t sysreturn; /* The return PC */ +}; +#endif + +/* The following structure is included in the TCB and defines the complete + * state of the thread. + */ + +struct xcptcontext +{ +#ifndef CONFIG_DISABLE_SIGNALS + /* The following function pointer is non-NULL if there are pending signals + * to be processed. + */ + + void *sigdeliver; /* Actual type is sig_deliver_t */ + + /* These additional register save locations are used to implement the + * signal delivery trampoline. + */ + + uint32_t saved_epc; /* Trampoline PC */ + uint32_t saved_int_ctx; /* Interrupt context with interrupts disabled. */ + +# ifdef CONFIG_BUILD_KERNEL + /* This is the saved address to use when returning from a user-space + * signal handler. + */ + + uint32_t sigreturn; + +# endif +#endif + +#ifdef CONFIG_BUILD_KERNEL + /* The following array holds information needed to return from each nested + * system call. + */ + + uint8_t nsyscalls; + struct xcpt_syscall_s syscall[CONFIG_SYS_NNEST]; + +#endif + + /* Register save area */ + + uint32_t regs[XCPTCONTEXT_REGS]; +}; + +#endif /* __ASSEMBLY__ */ + +/**************************************************************************** + * Public Variables + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#endif /* __ARCH_RISCV_INCLUDE_RV32IM_IRQ_H */ + diff --git a/arch/risc-v/include/rv32im/syscall.h b/arch/risc-v/include/rv32im/syscall.h new file mode 100644 index 00000000000..5269b21e877 --- /dev/null +++ b/arch/risc-v/include/rv32im/syscall.h @@ -0,0 +1,208 @@ +/**************************************************************************** + * arch/risc-v/include/rv32im/syscall.h + * + * Copyright (C) 2011-2013, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly + * through include/syscall.h or include/sys/sycall.h + */ + +#ifndef __ARCH_RISCV_INCLUDE_RV32IM_SYSCALL_H +#define __ARCH_RISCV_INCLUDE_RV32IM_SYSCALL_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define SYS_syscall 0x00 + +/* Configuration ********************************************************************/ +/* SYS call 1 and 2 are defined for internal use by the RISC-V port (see + * arch/riscv/include/mips32/syscall.h). In addition, SYS call 3 is the return from + * a SYS call in kernel mode. The first four syscall values must, therefore, be + * reserved (0 is not used). + */ + +#ifdef CONFIG_BUILD_KERNEL +# ifndef CONFIG_SYS_RESERVED +# error "CONFIG_SYS_RESERVED must be defined to the value 4" +# elif CONFIG_SYS_RESERVED != 4 +# error "CONFIG_SYS_RESERVED must have the value 4" +# endif +#endif + +/* sys_call macros ******************************************************************/ + +#ifndef __ASSEMBLY__ + +/* Context switching system calls ***************************************************/ + +/* SYS call 0: (not used) */ + +/* SYS call 1: + * + * void up_fullcontextrestore(uint32_t *restoreregs) noreturn_function; + */ + +#define SYS_restore_context (1) +#define up_fullcontextrestore(restoreregs) \ + (void)sys_call1(SYS_restore_context, (uintptr_t)restoreregs) + +/* SYS call 2: + * + * void up_switchcontext(uint32_t *saveregs, uint32_t *restoreregs); + */ + +#define SYS_switch_context (2) +#define up_switchcontext(saveregs, restoreregs) \ + (void)sys_call2(SYS_switch_context, (uintptr_t)saveregs, (uintptr_t)restoreregs) + +#ifdef CONFIG_BUILD_KERNEL +/* SYS call 3: + * + * void up_syscall_return(void); + */ + +#define SYS_syscall_return (3) +#define up_syscall_return() (void)sys_call0(SYS_syscall_return) + +#endif +#endif /* __ASSEMBLY__ */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Inline functions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: up_syscall0 + * + * Description: + * System call SYS_ argument and no additional parameters. + * + ****************************************************************************/ + +uintptr_t sys_call0(unsigned int nbr); + +/**************************************************************************** + * Name: up_syscall1 + * + * Description: + * System call SYS_ argument and one additional parameter. + * + ****************************************************************************/ + +uintptr_t sys_call1(unsigned int nbr, uintptr_t parm1); + +/**************************************************************************** + * Name: up_syscall2 + * + * Description: + * System call SYS_ argument and two additional parameters. + * + ****************************************************************************/ + +uintptr_t sys_call2(unsigned int nbr, uintptr_t parm1, uintptr_t parm2); + +/**************************************************************************** + * Name: up_syscall3 + * + * Description: + * System call SYS_ argument and three additional parameters. + * + ****************************************************************************/ + +uintptr_t sys_call3(unsigned int nbr, uintptr_t parm1, uintptr_t parm2, + uintptr_t parm3); + +/**************************************************************************** + * Name: up_syscall4 + * + * Description: + * System call SYS_ argument and four additional parameters. + * + ****************************************************************************/ + +uintptr_t sys_call4(unsigned int nbr, uintptr_t parm1, uintptr_t parm2, + uintptr_t parm3, uintptr_t parm4); + +/**************************************************************************** + * Name: up_syscall5 + * + * Description: + * System call SYS_ argument and five additional parameters. + * + ****************************************************************************/ + +uintptr_t sys_call5(unsigned int nbr, uintptr_t parm1, uintptr_t parm2, + uintptr_t parm3, uintptr_t parm4, uintptr_t parm5); + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_RISCV_INCLUDE_RV32IM_SYSCALL_H */ + diff --git a/arch/risc-v/include/stdarg.h b/arch/risc-v/include/stdarg.h new file mode 100644 index 00000000000..143009f2c21 --- /dev/null +++ b/arch/risc-v/include/stdarg.h @@ -0,0 +1,59 @@ +/**************************************************************************** + * arch/risc-v/include/stdarg.h + * + * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_INCLUDE_STDARG_H +#define __ARCH_RISCV_INCLUDE_STDARG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* This should work with any modern gcc (newer than 3.4 or so) */ + +#define va_start(v,l) __builtin_va_start(v,l) +#define va_end(v) __builtin_va_end(v) +#define va_arg(v,l) __builtin_va_arg(v,l) +#define va_copy(d,s) __builtin_va_copy(d,s) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +typedef __builtin_va_list va_list; + +#endif /* __ARCH_RISCV_INCLUDE_STDARG_H */ diff --git a/arch/risc-v/include/syscall.h b/arch/risc-v/include/syscall.h new file mode 100644 index 00000000000..1616cb46850 --- /dev/null +++ b/arch/risc-v/include/syscall.h @@ -0,0 +1,91 @@ +/**************************************************************************** + * arch/risc-v/include/syscall.h + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Modified 2016 by Ken Pettit for RISC-V architecture. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly + * through include/syscall.h or include/sys/sycall.h + */ + +#ifndef __ARCH_RISCV_INCLUDE_SYSCALL_H +#define __ARCH_RISCV_INCLUDE_SYSCALL_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* Include RISC-V architecture-specific syscall macros */ + +#ifdef CONFIG_ARCH_RV32IM +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Inline functions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif + +#endif /* __ARCH_RISCV_INCLUDE_SYSCALL_H */ + diff --git a/arch/risc-v/include/types.h b/arch/risc-v/include/types.h new file mode 100644 index 00000000000..8b7b09457c8 --- /dev/null +++ b/arch/risc-v/include/types.h @@ -0,0 +1,96 @@ +/**************************************************************************** + * arch/risc-v/include/types.h + * + * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly + * through sys/types.h + */ + +#ifndef __ARCH_RISCV_INCLUDE_TYPES_H +#define __ARCH_RISCV_INCLUDE_TYPES_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +//#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Type Declarations + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/* These are the sizes of the standard integer types. NOTE that these type + * names have a leading underscore character. This file will be included + * (indirectly) by include/stdint.h and typedef'ed to the final name without + * the underscore character. This roundabout way of doings things allows + * the stdint.h to be removed from the include/ directory in the event that + * the user prefers to use the definitions provided by their toolchain header + * files + */ + +typedef signed char _int8_t; +typedef unsigned char _uint8_t; + +typedef signed short _int16_t; +typedef unsigned short _uint16_t; + +typedef signed int _int32_t; +typedef unsigned int _uint32_t; + +typedef signed long long _int64_t; +typedef unsigned long long _uint64_t; +#define __INT64_DEFINED + +/* A pointer is 4 bytes */ + +typedef signed int _intptr_t; +typedef unsigned int _uintptr_t; + +/* This is the size of the interrupt state save returned by irqsave(). */ + +typedef unsigned int irqstate_t; + +#endif /* __ASSEMBLY__ */ + +/**************************************************************************** + * Global Function Prototypes + ****************************************************************************/ + +#endif /* __ARCH_RISCV_INCLUDE_TYPES_H */ diff --git a/arch/risc-v/src/Makefile b/arch/risc-v/src/Makefile new file mode 100644 index 00000000000..e5916c35342 --- /dev/null +++ b/arch/risc-v/src/Makefile @@ -0,0 +1,232 @@ +############################################################################ +# arch/risc-v/src/Makefile +# +# Copyright (C) 2011-2012, 2014, 2016 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Modified for RISC-V: +# +# Copyright (C) 2016 Ken Pettit. All rights reserved. +# Author: Ken Pettit +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include $(TOPDIR)/Make.defs +include chip/Make.defs + +ifeq ($(CONFIG_ARCH_RV32I),y) # Base Integer support +ARCH_SUBDIR = rv32i +else ifeq ($(CONFIG_ARCH_RV32IM),y) # Integer + math support +ARCH_SUBDIR = rv32im +else +ARCH_SUBDIR = rv32i # Default to base RV32I core +endif + +CPPFLAGS += $(EXTRADEFINES) +CFLAGS += $(EXTRADEFINES) +CXXFLAGS += $(EXTRADEFINES) + +ifeq ($(CONFIG_WINDOWS_NATIVE),y) + ARCH_SRCDIR = $(TOPDIR)\arch\$(CONFIG_ARCH)\src + NUTTX = "$(TOPDIR)\nuttx$(EXEEXT)" + CFLAGS += -I$(ARCH_SRCDIR)\chip + CFLAGS += -I$(ARCH_SRCDIR)\common + CFLAGS += -I$(ARCH_SRCDIR)\$(ARCH_SUBDIR) + CFLAGS += -I$(TOPDIR)\sched +else + ARCH_SRCDIR = $(TOPDIR)/arch/$(CONFIG_ARCH)/src +ifeq ($(WINTOOL),y) + NUTTX = "${shell cygpath -w $(TOPDIR)/nuttx$(EXEEXT)}" + CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/chip}" + CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/common}" + CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/$(ARCH_SUBDIR)}" + CFLAGS += -I "${shell cygpath -w $(TOPDIR)/sched}" +else + NUTTX = "$(TOPDIR)/nuttx$(EXEEXT)" + CFLAGS += -I$(ARCH_SRCDIR)/chip + CFLAGS += -I$(ARCH_SRCDIR)/common + CFLAGS += -I$(ARCH_SRCDIR)/$(ARCH_SUBDIR) + CFLAGS += -I$(TOPDIR)/sched +endif +endif + +# The "head" object + +HEAD_OBJ = $(HEAD_ASRC:.S=$(OBJEXT)) +STARTUP_OBJS ?= $(HEAD_OBJ) + +# Flat build or kernel-mode objects + +ASRCS = $(CHIP_ASRCS) $(CMN_ASRCS) +AOBJS = $(ASRCS:.S=$(OBJEXT)) + +CSRCS = $(CHIP_CSRCS) $(CMN_CSRCS) +COBJS = $(CSRCS:.c=$(OBJEXT)) + +SRCS = $(ASRCS) $(CSRCS) +OBJS = $(AOBJS) $(COBJS) + +# User-mode objects + +UASRCS = $(CHIP_UASRCS) $(CMN_UASRCS) +UAOBJS = $(UASRCS:.S=$(OBJEXT)) + +UCSRCS = $(CHIP_UCSRCS) $(CMN_UCSRCS) +UCOBJS = $(UCSRCS:.c=$(OBJEXT)) + +USRCS = $(UASRCS) $(UCSRCS) +UOBJS = $(UAOBJS) $(UCOBJS) + +KBIN = libkarch$(LIBEXT) +UBIN = libuarch$(LIBEXT) +BIN = libarch$(LIBEXT) + +LDFLAGS += $(ARCHSCRIPT) + +EXTRA_LIBS ?= +EXTRA_LIBPATHS ?= +LINKLIBS ?= + +AFLAGS += -I$(TOPDIR)/include + +ifeq ($(CONFIG_WINDOWS_NATIVE),y) + BOARDMAKE = $(if $(wildcard .\board\Makefile),y,) + LIBPATHS += -L"$(TOPDIR)\lib" +ifeq ($(BOARDMAKE),y) + LIBPATHS += -L"$(TOPDIR)\arch\$(CONFIG_ARCH)\src\board" +endif + +else + BOARDMAKE = $(if $(wildcard ./board/Makefile),y,) + +ifeq ($(WINTOOL),y) + LIBPATHS += -L"${shell cygpath -w "$(TOPDIR)/lib"}" +ifeq ($(BOARDMAKE),y) + LIBPATHS += -L"${shell cygpath -w "$(TOPDIR)/arch/$(CONFIG_ARCH)/src/board"}" +endif + +else + LIBPATHS += -L"$(TOPDIR)/lib" +ifeq ($(BOARDMAKE),y) + LIBPATHS += -L"$(TOPDIR)/arch/$(CONFIG_ARCH)/src/board" +endif +endif +endif + +LDLIBS = $(patsubst %.a,%,$(patsubst lib%,-l%,$(LINKLIBS))) +ifeq ($(BOARDMAKE),y) + LDLIBS += -lboard +endif + +LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" +GCC_LIBDIR := ${shell dirname $(LIBGCC)} + +VPATH += chip +VPATH += common +VPATH += $(ARCH_SUBDIR) +VPATH += $(CHIP_DIR) + +all: $(HEAD_OBJ) $(BIN) + +.PHONY: board/libboard$(LIBEXT) + +$(AOBJS) $(UAOBJS) $(HEAD_OBJ): %$(OBJEXT): %.S + $(call ASSEMBLE, $<, $@) + +$(COBJS) $(UCOBJS): %$(OBJEXT): %.c + $(call COMPILE, $<, $@) + +$(BIN) $(KBIN): $(OBJS) + $(call ARCHIVE, $@, $(OBJS)) + @$(MAKE) depend + +$(UBIN): $(UOBJS) + $(call ARCHIVE, $@, $(UOBJS)) + +board/libboard$(LIBEXT): + $(Q) $(MAKE) -C board TOPDIR="$(TOPDIR)" libboard$(LIBEXT) EXTRADEFINES=$(EXTRADEFINES) + +nuttx$(EXEEXT): $(HEAD_OBJ) board/libboard$(LIBEXT) + $(Q) echo "LD: nuttx" + $(Q) $(LD) --entry=__start $(LDFLAGS) $(LIBPATHS) $(EXTRA_LIBPATHS) \ + -o $(NUTTX) $(HEAD_OBJ) $(EXTRA_OBJS) \ + --start-group $(LDLIBS) $(EXTRA_LIBS) $(LIBGCC) --end-group +ifneq ($(CONFIG_WINDOWS_NATIVE),y) + $(Q) $(NM) $(NUTTX) | \ + grep -v '\(compiled\)\|\(\$(OBJEXT)$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \ + sort > $(TOPDIR)/System.map +endif + +# This is part of the top-level export target +# Note that there may not be a head object if layout is handled +# by the linker configuration. + +export_startup: board/libboard$(LIBEXT) $(STARTUP_OBJS) +ifneq ($(STARTUP_OBJS),) + $(Q) if [ -d "$(EXPORT_DIR)/startup" ]; then \ + cp -f $(STARTUP_OBJS) "$(EXPORT_DIR)/startup/."; \ + else \ + echo "$(EXPORT_DIR)/startup does not exist"; \ + exit 1; \ + fi +endif + +# Dependencies + +.depend: Makefile $(SRCS) +ifeq ($(BOARDMAKE),y) + $(Q) $(MAKE) -C board TOPDIR="$(TOPDIR)" depend +endif + $(Q) $(MKDEP) $(patsubst %,--dep-path %,$(subst :, ,$(VPATH))) \ + "$(CC)" -- $(CFLAGS) -- $(SRCS) > Make.dep + $(Q) touch $@ + +depend: .depend + +clean: +ifeq ($(BOARDMAKE),y) + $(Q) $(MAKE) -C board TOPDIR="$(TOPDIR)" clean +endif + $(call DELFILE, $(KBIN)) + $(call DELFILE, $(UBIN)) + $(call DELFILE, $(BIN)) + $(call DELFILE, $(HEAD_OBJ)) + $(call CLEAN) + +distclean: clean +ifeq ($(BOARDMAKE),y) + $(Q) $(MAKE) -C board TOPDIR="$(TOPDIR)" distclean +endif + $(call DELFILE, Make.dep) + $(call DELFILE, .depend) + +info: + @echo $(HEAD_OBJ) + @echo $(ASRCS) + @echo $(CONFIG_ARCH_CHIP) + +#-include Make.dep diff --git a/arch/risc-v/src/common/up_allocateheap.c b/arch/risc-v/src/common/up_allocateheap.c new file mode 100644 index 00000000000..002c853cd06 --- /dev/null +++ b/arch/risc-v/src/common/up_allocateheap.c @@ -0,0 +1,88 @@ +/**************************************************************************** + * arch/risc-v/src/common/up_allocateheap.c + * + * Copyright (C) 2010, 2013, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "up_arch.h" +#include "up_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_allocate_heap + * + * Description: + * This function will be called to dynamically set aside the heap region. + * + * For the kernel build (CONFIG_BUILD_KERNEL=y) with both kernel- and + * user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function provides the + * size of the unprotected, user-space heap. + * + * If a protected kernel-space heap is provided, the kernel heap must be + * allocated (and protected) by an analogous up_allocate_kheap(). + * + ****************************************************************************/ + +void up_allocate_heap(FAR void **heap_start, size_t *heap_size) +{ + board_autoled_on(LED_HEAPALLOCATE); + *heap_start = (FAR void *)g_idle_topstack; + *heap_size = CONFIG_RAM_END - g_idle_topstack; +} diff --git a/arch/risc-v/src/common/up_arch.h b/arch/risc-v/src/common/up_arch.h new file mode 100644 index 00000000000..fc602193450 --- /dev/null +++ b/arch/risc-v/src/common/up_arch.h @@ -0,0 +1,70 @@ +/**************************************************************************** + * arch/risc-v/src/common/up_arch.h + * + * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef ___ARCH_RISCV_SRC_COMMON_UP_ARCH_H +#define ___ARCH_RISCV_SRC_COMMON_UP_ARCH_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +# define getreg8(a) (*(volatile uint8_t *)(a)) +# define putreg8(v,a) (*(volatile uint8_t *)(a) = (v)) +# define getreg16(a) (*(volatile uint16_t *)(a)) +# define putreg16(v,a) (*(volatile uint16_t *)(a) = (v)) +# define getreg32(a) (*(volatile uint32_t *)(a)) +# define putreg32(v,a) (*(volatile uint32_t *)(a) = (v)) + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#endif /* __ASSEMBLY__ */ +#endif /* ___ARCH_ARM_SRC_COMMON_UP_ARCH_H */ diff --git a/arch/risc-v/src/common/up_createstack.c b/arch/risc-v/src/common/up_createstack.c new file mode 100644 index 00000000000..494d54e4abc --- /dev/null +++ b/arch/risc-v/src/common/up_createstack.c @@ -0,0 +1,214 @@ +/**************************************************************************** + * arch/riscv/src/common/up_createstack.c + * + * Copyright (C) 2011, 2013, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "up_arch.h" +#include "up_internal.h" + +/**************************************************************************** + * Pre-processor Macros + ****************************************************************************/ + +/* MIPS requires at least a 4-byte stack alignment. For floating point use, + * however, the stack must be aligned to 8-byte addresses. + */ + +#ifdef CONFIG_LIBC_FLOATINGPOINT +# define STACK_ALIGNMENT 8 +#else +# define STACK_ALIGNMENT 4 +#endif + +/* Stack alignment macros */ + +#define STACK_ALIGN_MASK (STACK_ALIGNMENT-1) +#define STACK_ALIGN_DOWN(a) ((a) & ~STACK_ALIGN_MASK) +#define STACK_ALIGN_UP(a) (((a) + STACK_ALIGN_MASK) & ~STACK_ALIGN_MASK) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_create_stack + * + * Description: + * Allocate a stack for a new thread and setup up stack-related information + * in the TCB. + * + * The following TCB fields must be initialized by this function: + * + * - adj_stack_size: Stack size after adjustment for hardware, processor, + * etc. This value is retained only for debug purposes. + * - stack_alloc_ptr: Pointer to allocated stack + * - adj_stack_ptr: Adjusted stack_alloc_ptr for HW. The initial value of + * the stack pointer. + * + * Inputs: + * - tcb: The TCB of new task + * - stack_size: The requested stack size. At least this much + * must be allocated. + * - ttype: The thread type. This may be one of following (defined in + * include/nuttx/sched.h): + * + * TCB_FLAG_TTYPE_TASK Normal user task + * TCB_FLAG_TTYPE_PTHREAD User pthread + * TCB_FLAG_TTYPE_KERNEL Kernel thread + * + * This thread type is normally available in the flags field of the TCB, + * however, there are certain contexts where the TCB may not be fully + * initialized when up_create_stack is called. + * + * If CONFIG_BUILD_KERNEL is defined, then this thread type may affect + * how the stack is allocated. For example, kernel thread stacks should + * be allocated from protected kernel memory. Stacks for user tasks and + * threads must come from memory that is accessible to user code. + * + ****************************************************************************/ + +int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype) +{ + /* Is there already a stack allocated of a different size? Because of + * alignment issues, stack_size might erroneously appear to be of a + * different size. Fortunately, this is not a critical operation. + */ + + if (tcb->stack_alloc_ptr && tcb->adj_stack_size != stack_size) + { + /* Yes.. Release the old stack */ + + up_release_stack(tcb, ttype); + } + + /* Do we need to allocate a new stack? */ + + if (!tcb->stack_alloc_ptr) + { + /* Allocate the stack. If DEBUG is enabled (but not stack debug), + * then create a zeroed stack to make stack dumps easier to trace. + */ + +#if defined(CONFIG_BUILD_KERNEL) && defined(CONFIG_MM_KERNEL_HEAP) + /* Use the kernel allocator if this is a kernel thread */ + + if (ttype == TCB_FLAG_TTYPE_KERNEL) + { + tcb->stack_alloc_ptr = (uint32_t *)kmm_malloc(stack_size); + } + else +#endif + { + /* Use the user-space allocator if this is a task or pthread */ + + tcb->stack_alloc_ptr = (uint32_t *)kumm_malloc(stack_size); + } + +#ifdef CONFIG_DEBUG_FEATURES + /* Was the allocation successful? */ + + if (!tcb->stack_alloc_ptr) + { + serr("ERROR: Failed to allocate stack, size %d\n", stack_size); + } +#endif + } + + /* Did we successfully allocate a stack? */ + + if (tcb->stack_alloc_ptr) + { + size_t top_of_stack; + size_t size_of_stack; + + /* Yes.. If stack debug is enabled, then fill the stack with a + * recognizable value that we can use later to test for high + * water marks. + */ + +#ifdef CONFIG_STACK_COLORATION + memset(tcb->stack_alloc_ptr, 0xaa, stack_size); +#endif + + /* MIPS uses a push-down stack: the stack grows toward lower + * addresses in memory. The stack pointer register points to the + * lowest, valid working address (the "top" of the stack). Items on + * the stack are referenced as positive word offsets from sp. + */ + + top_of_stack = (uint32_t)tcb->stack_alloc_ptr + stack_size - 4; + + /* The MIPS stack must be aligned at word (4 byte) boundaries; for + * floating point use, the stack must be aligned to 8-byte addresses. + * If necessary top_of_stack must be rounded down to the next + * boundary to meet these alignment requirements. + */ + + top_of_stack = STACK_ALIGN_DOWN(top_of_stack); + size_of_stack = top_of_stack - (uint32_t)tcb->stack_alloc_ptr + 4; + + /* Save the adjusted stack values in the struct tcb_s */ + + tcb->adj_stack_ptr = (FAR uint32_t *)top_of_stack; + tcb->adj_stack_size = size_of_stack; + + board_autoled_on(LED_STACKCREATED); + return OK; + } + + return ERROR; +} diff --git a/arch/risc-v/src/common/up_exit.c b/arch/risc-v/src/common/up_exit.c new file mode 100644 index 00000000000..4345f03f22e --- /dev/null +++ b/arch/risc-v/src/common/up_exit.c @@ -0,0 +1,188 @@ +/**************************************************************************** + * arch/risc-v/src/common/up_exit.c + * + * Copyright (C) 2011, 2013-2014 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#ifdef CONFIG_DUMP_ON_EXIT +#include +#endif + +#include "task/task.h" +#include "sched/sched.h" +#include "group/group.h" +#include "up_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_DEBUG_SCHED_INFO +# undef CONFIG_DUMP_ON_EXIT +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: _up_dumponexit + * + * Description: + * Dump the state of all tasks whenever on task exits. This is debug + * instrumentation that was added to check file-related reference counting + * but could be useful again sometime in the future. + * + ****************************************************************************/ + +#ifdef CONFIG_DUMP_ON_EXIT +static void _up_dumponexit(FAR struct tcb_s *tcb, FAR void *arg) +{ +#if CONFIG_NFILE_DESCRIPTORS > 0 + FAR struct filelist *filelist; +#if CONFIG_NFILE_STREAMS > 0 + FAR struct streamlist *streamlist; +#endif + int i; +#endif + + sinfo(" TCB=%p name=%s pid=%d\n", tcb, tcb->argv[0], tcb->pid); + sinfo(" priority=%d state=%d\n", tcb->sched_priority, tcb->task_state); + +#if CONFIG_NFILE_DESCRIPTORS > 0 + filelist = tcb->group->tg_filelist; + for (i = 0; i < CONFIG_NFILE_DESCRIPTORS; i++) + { + struct inode *inode = filelist->fl_files[i].f_inode; + if (inode) + { + sinfo(" fd=%d refcount=%d\n", + i, inode->i_crefs); + } + } +#endif + +#if CONFIG_NFILE_STREAMS > 0 + streamlist = tcb->group->tg_streamlist; + for (i = 0; i < CONFIG_NFILE_STREAMS; i++) + { + struct file_struct *filep = &streamlist->sl_streams[i]; + if (filep->fs_fd >= 0) + { +#if CONFIG_STDIO_BUFFER_SIZE > 0 + sinfo(" fd=%d nbytes=%d\n", + filep->fs_fd, + filep->fs_bufpos - filep->fs_bufstart); +#else + sinfo(" fd=%d\n", filep->fs_fd); +#endif + } + } +#endif +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: _exit + * + * Description: + * This function causes the currently executing task to cease + * to exist. This is a special case of task_delete() where the task to + * be deleted is the currently executing task. It is more complex because + * a context switch must be perform to the next ready to run task. + * + ****************************************************************************/ + +void _exit(int status) +{ + struct tcb_s *tcb; + + /* Disable interrupts. They will be restored when the next + * task is started. + */ + + (void)up_irq_save(); + + sinfo("TCB=%p exiting\n", this_task()); + +#ifdef CONFIG_DUMP_ON_EXIT + sinfo("Other tasks:\n"); + sched_foreach(_up_dumponexit, NULL); +#endif + + /* Destroy the task at the head of the ready to run list. */ + + (void)task_exit(); + + /* Now, perform the context switch to the new ready-to-run task at the + * head of the list. + */ + + tcb = this_task(); + +#ifdef CONFIG_ARCH_ADDRENV + /* Make sure that the address environment for the previously running + * task is closed down gracefully (data caches dump, MMU flushed) and + * set up the address environment for the new thread at the head of + * the ready-to-run list. + */ + + (void)group_addrenv(tcb); +#endif + + /* Then switch contexts */ + + up_fullcontextrestore(tcb->xcp.regs); + + /* up_fullcontextrestore() should not return but could if the software + * interrupts are disabled. + */ + + PANIC(); +} + diff --git a/arch/risc-v/src/common/up_idle.c b/arch/risc-v/src/common/up_idle.c new file mode 100644 index 00000000000..0c8a867d79f --- /dev/null +++ b/arch/risc-v/src/common/up_idle.c @@ -0,0 +1,95 @@ +/**************************************************************************** + * arch/risc-v/src/common/up_idle.c + * + * Copyright (C) 2011-2012, 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include "up_internal.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_idle + * + * Description: + * up_idle() is the logic that will be executed when their is no other + * ready-to-run task. This is processor idle time and will continue until + * some interrupt occurs to cause a context switch from the idle task. + * + * Processing in this state may be processor-specific. e.g., this is where + * power management operations might be performed. + * + ****************************************************************************/ + +void up_idle(void) +{ +#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS) + /* If the system is idle and there are no timer interrupts, then process + * "fake" timer interrupts. Hopefully, something will wake up. + */ + + sched_process_timer(); +#else + + /* This would be an appropriate place to put some MCU-specific logic to + * sleep in a reduced power mode until an interrupt occurs to save power + */ + + /* This is a kludge that I still don't understand. The call to kmm_trysemaphore() + * in the os_start.c IDLE loop seems necessary for the good health of the IDLE + * loop. When the work queue is enabled, this logic is removed from the IDLE + * loop and it appears that we are somehow left idling with interrupts non- + * functional. The following should be no-op, it just disables then re-enables + * interrupts. But it fixes the problem and will stay here until I understand + * the problem/fix better. + * + * And no, the contents of the CP0 status register are not incorrect. But for + * some reason the status register needs to be re-written again on this thread + * for it to take effect. This might be a PIC32-only issue? + */ + +#ifdef CONFIG_SCHED_WORKQUEUE + irqstate_t flags = enter_critical_section(); + leave_critical_section(flags); +#endif +#endif +} diff --git a/arch/risc-v/src/common/up_initialize.c b/arch/risc-v/src/common/up_initialize.c new file mode 100644 index 00000000000..a31051f3e35 --- /dev/null +++ b/arch/risc-v/src/common/up_initialize.c @@ -0,0 +1,203 @@ +/**************************************************************************** + * arch/risc-v/src/common/up_initialize.c + * + * Copyright (C) 2007-2010, 2012-2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include + +#include "up_arch.h" +#include "up_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_calibratedelay + * + * Description: + * Delay loops are provided for short timing loops. This function, if + * enabled, will just wait for 100 seconds. Using a stopwatch, you can + * can then determine if the timing loops are properly calibrated. + * + ****************************************************************************/ + +#if defined(CONFIG_ARCH_CALIBRATION) && defined(CONFIG_DEBUG) +static void up_calibratedelay(void) +{ + int i; + lldbg("Beginning 100s delay\n"); + for (i = 0; i < 100; i++) + { + up_mdelay(1000); + } + lldbg("End 100s delay\n"); +} +#else +# define up_calibratedelay() +#endif + +/**************************************************************************** + * Name: up_color_intstack + * + * Description: + * Set the interrupt stack to a value so that later we can determine how + * much stack space was used by interrupt handling logic + * + ****************************************************************************/ + +#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3 +static inline void up_color_intstack(void) +{ + uint32_t *ptr = (uint32_t *)&g_intstackalloc; + ssize_t size; + + for (size = (CONFIG_ARCH_INTERRUPTSTACK & ~3); + size > 0; + size -= sizeof(uint32_t)) + { + *ptr++ = INTSTACK_COLOR; + } +} +#else +# define up_color_intstack() +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_initialize + * + * Description: + * up_initialize will be called once during OS initialization after the + * basic OS services have been initialized. The architecture specific + * details of initializing the OS will be handled here. Such things as + * setting up interrupt service routines, starting the clock, and + * registering device drivers are some of the things that are different + * for each processor and hardware platform. + * + * up_initialize is called after the OS initialized but before the user + * initialization logic has been started and before the libraries have + * been initialized. OS services and driver services are available. + * + ****************************************************************************/ + +void up_initialize(void) +{ + /* Calibrate the timing loop */ + + up_calibratedelay(); + + /* Colorize the interrupt stack */ + + up_color_intstack(); + + /* Add any extra memory fragments to the memory manager */ + + up_addregion(); + + /* Initialize the interrupt subsystem */ + + up_irqinitialize(); + + /* Initialize the system timer interrupt */ + +#if !defined(CONFIG_SUPPRESS_INTERRUPTS) && !defined(CONFIG_SUPPRESS_TIMER_INTS) && \ + !defined(CONFIG_SYSTEMTICK_EXTCLK) + up_timer_initialize(); +#endif + + /* Register devices */ + +#if CONFIG_NFILE_DESCRIPTORS > 0 + +#if defined(CONFIG_DEV_NULL) + devnull_register(); /* Standard /dev/null */ +#endif + +#if defined(CONFIG_DEV_ZERO) + devzero_register(); /* Standard /dev/zero */ +#endif + +#endif /* CONFIG_NFILE_DESCRIPTORS */ + + /* Initialize the serial device driver */ + +#ifdef USE_SERIALDRIVER + up_serialinit(); +#endif + + /* Initialize the console device driver (if it is other than the standard + * serial driver). + */ + +#if defined(CONFIG_DEV_LOWCONSOLE) + lowconsole_init(); +#elif defined(CONFIG_SYSLOG_CONSOLE) + syslog_console_init(); +#elif defined(CONFIG_RAMLOG_CONSOLE) + ramlog_consoleinit(); +#endif + + /* Initialize the system logging device */ + +#ifdef CONFIG_SYSLOG_CHAR + syslog_initialize(); +#endif +#ifdef CONFIG_RAMLOG_SYSLOG + ramlog_sysloginit(); +#endif + + board_autoled_on(LED_IRQSENABLED); +} diff --git a/arch/risc-v/src/common/up_internal.h b/arch/risc-v/src/common/up_internal.h new file mode 100644 index 00000000000..f4481a2269a --- /dev/null +++ b/arch/risc-v/src/common/up_internal.h @@ -0,0 +1,160 @@ +/**************************************************************************** + * arch/risc-v/src/common/up_internal.h + * + * Copyright (C) 2007-2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Modified for RISC-V: + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_COMMON_UP_INTERNAL_H +#define __ARCH_RISCV_SRC_COMMON_UP_INTERNAL_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# include +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* This is the value used to mark the stack for subsequent stack monitoring + * logic. + */ + +#define STACK_COLOR 0xdeadbeef +#define INTSTACK_COLOR 0xdeadbeef +#define HEAP_COLOR 'h' + +/* In the RISC_V model, the state is copied from the stack to the TCB, but + * only a referenced is passed to get the state from the TCB. + */ + +#define up_savestate(regs) up_copystate(regs, (uint32_t*)g_current_regs) +#define up_restorestate(regs) (g_current_regs = regs) + +/* Determine which (if any) console driver to use. If a console is enabled + * and no other console device is specified, then a serial console is + * assumed. + */ + +#if !defined(CONFIG_DEV_CONSOLE) || CONFIG_NFILE_DESCRIPTORS <= 0 +# undef USE_SERIALDRIVER +# undef USE_EARLYSERIALINIT +# undef CONFIG_DEV_LOWCONSOLE +# undef CONFIG_RAMLOG_CONSOLE +#else +# if defined(CONFIG_RAMLOG_CONSOLE) +# undef USE_SERIALDRIVER +# undef USE_EARLYSERIALINIT +# undef CONFIG_DEV_LOWCONSOLE +# elif defined(CONFIG_DEV_LOWCONSOLE) +# undef USE_SERIALDRIVER +# undef USE_EARLYSERIALINIT +# else +# define USE_SERIALDRIVER 1 +# define USE_EARLYSERIALINIT 1 +# endif +#endif + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Variables + ****************************************************************************/ + +extern volatile uint32_t *g_current_regs; + +extern uint32_t g_idle_topstack; + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/* Low level initialization provided by board-level logic ******************/ + +void up_boot(void); + +/* Memory allocation ********************************************************/ + +void up_addregion(void); +void up_allocat_eheap(FAR void **heap_start, size_t *heap_size); + +/* IRQ initialization *******************************************************/ + +void up_irqinitialize(void); +void up_copystate(uint32_t *dest, uint32_t *src); +void up_dumpstate(void); +void up_sigdeliver(void); +int up_swint(int irq, FAR void *context); +uint32_t up_get_newintctx(void); + +/* System timer *************************************************************/ + +void up_timer_initialize(void); +int up_timerisr(int irq, void *context); + +/* Low level serial output **************************************************/ + +void up_lowputc(char ch); +void up_puts(const char *str); +void up_lowputs(const char *str); + +/* The OS start routine **************************************************/ + +void os_start(void); + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif /* __ASSEMBLY__ */ + +#endif /* __ARCH_RISCV_SRC_COMMON_UP_INTERNAL_H */ diff --git a/arch/risc-v/src/common/up_interruptcontext.c b/arch/risc-v/src/common/up_interruptcontext.c new file mode 100644 index 00000000000..8bdc595529a --- /dev/null +++ b/arch/risc-v/src/common/up_interruptcontext.c @@ -0,0 +1,70 @@ +/**************************************************************************** + * arch/risc-v/src/common/up_interruptcontext.c + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include "up_internal.h" + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_interrupt_context + * + * Description: Return true is we are currently executing in + * the interrupt handler context. + ****************************************************************************/ + +bool up_interrupt_context(void) +{ + return g_current_regs != NULL; +} diff --git a/arch/risc-v/src/common/up_releasestack.c b/arch/risc-v/src/common/up_releasestack.c new file mode 100644 index 00000000000..15301c49d27 --- /dev/null +++ b/arch/risc-v/src/common/up_releasestack.c @@ -0,0 +1,122 @@ +/**************************************************************************** + * arch/risc-v/src/common/up_releasestack.c + * + * Copyright (C) 2011, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "up_internal.h" + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_release_stack + * + * Description: + * A task has been stopped. Free all stack related resources retained in + * the defunct TCB. + * + * Input Parmeters + * - dtcb: The TCB containing information about the stack to be released + * - ttype: The thread type. This may be one of following (defined in + * include/nuttx/sched.h): + * + * TCB_FLAG_TTYPE_TASK Normal user task + * TCB_FLAG_TTYPE_PTHREAD User pthread + * TCB_FLAG_TTYPE_KERNEL Kernel thread + * + * This thread type is normally available in the flags field of the TCB, + * however, there are certain error recovery contexts where the TCB may + * not be fully initialized when up_release_stack is called. + * + * If CONFIG_BUILD_KERNEL is defined, then this thread type may affect + * how the stack is freed. For example, kernel thread stacks may have + * been allocated from protected kernel memory. Stacks for user tasks + * and threads must have come from memory that is accessible to user + * code. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void up_release_stack(FAR struct tcb_s *dtcb, uint8_t ttype) +{ + /* Is there a stack allocated? */ + + if (dtcb->stack_alloc_ptr) + { +#if defined(CONFIG_BUILD_KERNEL) && defined(CONFIG_MM_KERNEL_HEAP) + /* Use the kernel allocator if this is a kernel thread */ + + if (ttype == TCB_FLAG_TTYPE_KERNEL) + { + sched_kfree(dtcb->stack_alloc_ptr); + } + else +#endif + { + /* Use the user-space allocator if this is a task or pthread */ + + sched_ufree(dtcb->stack_alloc_ptr); + } + + /* Mark the stack freed */ + + dtcb->stack_alloc_ptr = NULL; + } + + /* The size of the allocated stack is now zero */ + + dtcb->adj_stack_size = 0; +} diff --git a/arch/risc-v/src/common/up_stackframe.c b/arch/risc-v/src/common/up_stackframe.c new file mode 100644 index 00000000000..b3cb9801d4d --- /dev/null +++ b/arch/risc-v/src/common/up_stackframe.c @@ -0,0 +1,143 @@ +/**************************************************************************** + * arch/risc-v/src/common/up_stackframe.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "up_internal.h" + +/**************************************************************************** + * Pre-processor Macros + ****************************************************************************/ +/* MIPS requires at least a 4-byte stack alignment. For floating point use, + * however, the stack must be aligned to 8-byte addresses. + */ + +#ifdef CONFIG_LIBC_FLOATINGPOINT +# define STACK_ALIGNMENT 8 +#else +# define STACK_ALIGNMENT 4 +#endif + +/* Stack alignment macros */ + +#define STACK_ALIGN_MASK (STACK_ALIGNMENT-1) +#define STACK_ALIGN_DOWN(a) ((a) & ~STACK_ALIGN_MASK) +#define STACK_ALIGN_UP(a) (((a) + STACK_ALIGN_MASK) & ~STACK_ALIGN_MASK) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_stack_frame + * + * Description: + * Allocate a stack frame in the TCB's stack to hold thread-specific data. + * This function may be called anytime after up_create_stack() or + * up_use_stack() have been called but before the task has been started. + * + * Thread data may be kept in the stack (instead of in the TCB) if it is + * accessed by the user code directly. This includes such things as + * argv[]. The stack memory is guaranteed to be in the same protection + * domain as the thread. + * + * The following TCB fields will be re-initialized: + * + * - adj_stack_size: Stack size after removal of the stack frame from + * the stack + * - adj_stack_ptr: Adjusted initial stack pointer after the frame has + * been removed from the stack. This will still be the initial value + * of the stack pointer when the task is started. + * + * Inputs: + * - tcb: The TCB of new task + * - frame_size: The size of the stack frame to allocate. + * + * Returned Value: + * - A pointer to bottom of the allocated stack frame. NULL will be + * returned on any failures. The alignment of the returned value is + * the same as the alignment of the stack itself. + * + ****************************************************************************/ + +FAR void *up_stack_frame(FAR struct tcb_s *tcb, size_t frame_size) +{ + uintptr_t topaddr; + + /* Align the frame_size */ + + frame_size = STACK_ALIGN_UP(frame_size); + + /* Is there already a stack allocated? Is it big enough? */ + + if (!tcb->stack_alloc_ptr || tcb->adj_stack_size <= frame_size) + { + return NULL; + } + + /* Save the adjusted stack values in the struct tcb_s */ + + topaddr = (uintptr_t)tcb->adj_stack_ptr - frame_size; + tcb->adj_stack_ptr = (FAR void *)topaddr; + tcb->adj_stack_size -= frame_size; + + /* Reset the initial stack pointer */ + + tcb->xcp.regs[REG_SP] = (uint32_t)tcb->adj_stack_ptr; + + /* And return the pointer to the allocated region */ + + return (FAR void *)(topaddr + sizeof(uint32_t)); +} + diff --git a/arch/risc-v/src/common/up_usestack.c b/arch/risc-v/src/common/up_usestack.c new file mode 100644 index 00000000000..605bb79b045 --- /dev/null +++ b/arch/risc-v/src/common/up_usestack.c @@ -0,0 +1,152 @@ +/**************************************************************************** + * arch/risc-v/src/common/up_usestack.c + * + * Copyright (C) 2011, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "up_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* MIPS requires at least a 4-byte stack alignment. For floating point use, + * however, the stack must be aligned to 8-byte addresses. + */ + +#ifdef CONFIG_LIBC_FLOATINGPOINT +# define STACK_ALIGNMENT 8 +#else +# define STACK_ALIGNMENT 4 +#endif + +/* Stack alignment macros */ + +#define STACK_ALIGN_MASK (STACK_ALIGNMENT-1) +#define STACK_ALIGN_DOWN(a) ((a) & ~STACK_ALIGN_MASK) +#define STACK_ALIGN_UP(a) (((a) + STACK_ALIGN_MASK) & ~STACK_ALIGN_MASK) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_use_stack + * + * Description: + * Setup up stack-related information in the TCB using pre-allocated stack + * memory. This function is called only from task_init() when a task or + * kernel thread is started (never for pthreads). + * + * The following TCB fields must be initialized: + * + * - adj_stack_size: Stack size after adjustment for hardware, + * processor, etc. This value is retained only for debug + * purposes. + * - stack_alloc_ptr: Pointer to allocated stack + * - adj_stack_ptr: Adjusted stack_alloc_ptr for HW. The + * initial value of the stack pointer. + * + * Inputs: + * - tcb: The TCB of new task + * - stack_size: The allocated stack size. + * + * NOTE: Unlike up_stack_create() and up_stack_release, this function + * does not require the task type (ttype) parameter. The TCB flags will + * always be set to provide the task type to up_use_stack() if it needs + * that information. + * + ****************************************************************************/ + +int up_use_stack(struct tcb_s *tcb, void *stack, size_t stack_size) +{ + size_t top_of_stack; + size_t size_of_stack; + + /* Is there already a stack allocated? */ + + if (tcb->stack_alloc_ptr) + { + /* Yes.. Release the old stack allocation */ + + up_release_stack(tcb, tcb->flags & TCB_FLAG_TTYPE_MASK); + } + + /* Save the new stack allocation */ + + tcb->stack_alloc_ptr = stack; + + /* MIPS uses a push-down stack: the stack grows toward loweraddresses in + * memory. The stack pointer register, points to the lowest, valid work + * address (the "top" of the stack). Items on the stack are referenced + * as positive word offsets from sp. + */ + + top_of_stack = (uint32_t)tcb->stack_alloc_ptr + stack_size - 4; + + /* The MIPS stack must be aligned at word (4 byte) or double word (8 byte) + * boundaries. If necessary top_of_stack must be rounded down to the + * next boundary + */ + + top_of_stack = STACK_ALIGN_DOWN(top_of_stack); + size_of_stack = top_of_stack - (uint32_t)tcb->stack_alloc_ptr + 4; + + /* Save the adjusted stack values in the struct tcb_s */ + + tcb->adj_stack_ptr = (uint32_t *)top_of_stack; + tcb->adj_stack_size = size_of_stack; + + return OK; +} diff --git a/arch/risc-v/src/nr5m100/Kconfig b/arch/risc-v/src/nr5m100/Kconfig new file mode 100644 index 00000000000..c54f950c627 --- /dev/null +++ b/arch/risc-v/src/nr5m100/Kconfig @@ -0,0 +1,121 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +comment "NanoRisc5 Configuration Options" + +choice + prompt "NR5 Chip Selection" + default ARCH_CHIP_NR5M100 + depends on ARCH_CHIP_NR5 + +config ARCH_CHIP_NR5M100 + bool "NR5M100" + select NR5_HAVE_UART1 + select NR5_HAVE_GPIOA + select NR5_HAVE_GPIOB + select NR5_HAVE_GPIOC + ---help--- + NanoRisc5, RV32IM 128K PROGRAM SRAM, 128K DATA SRAM + +endchoice + +config NR5_NR5M100 + bool + default y + select NR5_NR5M1XX + select NR5_HAVE_UART1 + select NR5_HAVE_TIMER1 + +config NR5_NR5M1XX + bool + default n + +config NR5_EPIC + bool "Has Embedded Priority Interrupt Controller (EPIC)" + ---help--- + NanoRisc5 core can have either single vector interrupts or priority + encoded interrupts. Selects if the core was compiled with EPIC. + +menu "NR5 Peripheral Support" + +# These "hidden" settings determine is a peripheral option is available for the +# selection MCU + +config NR5_HAVE_UART1 + bool + default n + select UART1_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + +config NR5_HAVE_TIMER1 + bool + default n + +config NR5_HAVE_TIM2 + bool + default n + +config NR5_HAVE_I2C1 + bool + default n + +config NR5_HAVE_SPI1 + bool + default n + +# These are the peripheral selections proper + +config NR5_I2C1 + bool "I2C1" + default n + select NR5_I2C + +config NR5_SPI1 + bool "SPI1" + default n + select SPI + select NR5_SPI + +config NR5_TIMER1 + bool "TIMER1" + default n + depends on NR5_HAVE_TIMER1 + +config NR5_TIMER2 + bool "TIMER2" + default n + +config NR5_UART1 + bool "UART1" + default n + select ARCH_HAVE_UART1 + select ARCH_HAVE_SERIAL_TERMIOS + select NR5_UART + +endmenu + +config NR5_SPI + bool + +config NR5_I2C + bool + +config NR5_UART + bool + +config NR5_UART_RX_BUF_SIZE + int "UART RX Bufer size" + default 64 + depends on NR5_UART + ---help--- + Size of RX buffers for NR5 UARTs + +config NR5_UART_TX_BUF_SIZE + int "UART TX Bufer size" + default 64 + depends on NR5_UART + ---help--- + Size of TX buffers for NR5 UARTs + diff --git a/arch/risc-v/src/nr5m100/Make.defs b/arch/risc-v/src/nr5m100/Make.defs new file mode 100644 index 00000000000..8d7b9ee85b4 --- /dev/null +++ b/arch/risc-v/src/nr5m100/Make.defs @@ -0,0 +1,74 @@ +############################################################################ +# arch/risc-v/src/nr5m100/Make.defs +# +# Copyright (C) 2016 Ken Pettit. All rights reserved. +# Author: Ken Pettit +# +# # Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +# Specify our HEAD assembly file. This will be linked as +# the first object file, so it will appear at address 0 +HEAD_ASRC = nr5_vectors.S + +# Specify our general Assembly files +CHIP_ASRCS = nr5_head.S nr5_csr.S up_syscall.S + +# If we are compiling the NELIB library, then specify it +# in AFLAGS so we can change up our startup behavior +ifeq ($(CONFIG_LIB_NEWLIB),y) +AFLAGS += -DCONFIG_LIB_NEWLIB +endif + +# Override the arch to enable hardware MUL during assembly. +# This is to support our hardware mul test. For that test, +# we have to disable hardware mul for C code so the soft +# math libs will be used to compare software mul vs hw mul. +# But hw mul must be enabled to compile the .S file, or we +# will get an illegal instruction error. +ASARCHCPUFLAGS += -march=RV32IMXcustom + +# Specify C code within the common directory to be included +CMN_CSRCS += up_initialize.c up_swint.c +CMN_CSRCS += up_allocateheap.c up_createstack.c up_dumpstate.c up_exit.c up_idle.c +CMN_CSRCS += up_assert.c up_blocktask.c up_copystate.c up_initialstate.c +CMN_CSRCS += up_interruptcontext.c up_releasepending.c up_reprioritizertr.c +CMN_CSRCS += up_releasestack.c up_stackframe.c up_schedulesigaction.c up_sigdeliver.c +CMN_CSRCS += up_unblocktask.c up_usestack.c + +ifeq ($(CONFIG_ARCH_HAVE_VFORK),y) +CMN_CSRCS += up_vfork.c +endif + +# Specify our C code within this directory to be included +CHIP_CSRCS = nr5_init.c nr5_arch.c +CHIP_CSRCS += nr5_lowputc.c nr5_allocateheap.c nr5_serial.c +CHIP_CSRCS += nr5_timerisr.c nr5_irq.c nr5_irq_dispatch.c + +ifeq ($(CONFIG_TIMER),y) +CHIP_CSRCS += nr5_tim_lowerhalf.c +endif + diff --git a/arch/risc-v/src/nr5m100/chip.h b/arch/risc-v/src/nr5m100/chip.h new file mode 100644 index 00000000000..dbe9928c6f6 --- /dev/null +++ b/arch/risc-v/src/nr5m100/chip.h @@ -0,0 +1,67 @@ +/************************************************************************************ + * arch/risc-v/src/nr5m100/chip.h + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_NR5M100_CHIP_H +#define __ARCH_RISCV_SRC_NR5M100_CHIP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/* If the common RV32IM vector handling logic is used, then include the + * required vector definitions as well. + */ + +#ifdef CONFIG_RV32IM_CMNVECTOR +# if defined(CONFIG_NR5_NR5M1XX) +# include "chip/nr5m1xx_vectors.h" +# else +# error "No vector file for this NanoRisc5 family" +# endif +#endif + +/* Include the chip memory map. */ + +#include "nr5_memorymap.h" + +/* Include our custom access routines for ISR masking, priority */ + +#include "nr5_csr.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +#endif /* __ARCH_RISCV_SRC_NR5M100_CHIP_H */ + diff --git a/arch/risc-v/src/nr5m100/chip/nr5m1xx_epic.h b/arch/risc-v/src/nr5m100/chip/nr5m1xx_epic.h new file mode 100644 index 00000000000..3fa13aed104 --- /dev/null +++ b/arch/risc-v/src/nr5m100/chip/nr5m1xx_epic.h @@ -0,0 +1,41 @@ +/************************************************************************************ + * arch/risc-v/src/nr5m100/chip/nr5_epic.h + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef ARCH_RISCV_SRC_NR5M100_CHIP_NR5M1XX_EPIC_H +#define ARCH_RISCV_SRC_NR5M100_CHIP_NR5M1XX_EPIC_H + +#define NR5_EPIC_PRI1_REG 0x7E1 +#define NR5_EPIC_PRI2_REG 0x7E2 +#define NR5_EPIC_PRI3_REG 0x7E3 +#define NR5_EPIC_STAT_REG 0x7E4 + +#endif /* _ARCH_RISCV_SRC_NR5M100_CHIP_NR5M1XX_EPIC_H */ diff --git a/arch/risc-v/src/nr5m100/chip/nr5m1xx_memorymap.h b/arch/risc-v/src/nr5m100/chip/nr5m1xx_memorymap.h new file mode 100644 index 00000000000..4ebc6879d13 --- /dev/null +++ b/arch/risc-v/src/nr5m100/chip/nr5m1xx_memorymap.h @@ -0,0 +1,57 @@ +/************************************************************************************ + * arch/risc-v/src/nr5m100/chip/nr5m1xx_memorymap.h + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_NR5M100_CHIP_NR5M1XX_MEMORYMAP_H +#define __ARCH_RISCV_SRC_NR5M100_CHIP_NR5M1XX_MEMORYMAP_H + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* BOOT ROM, SRAM, PERIPHERALS ******************************************************/ + +#define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */ +#define STM32_SRAM_BASE 0x20000000 /* 0x20000000 - 384Kb SRAM */ +#define STM32_PERIPH_BASE 0x40000000 /* 0x40000000-0x4fffffff: Peripheral block */ + +/* Register Base Address ************************************************************/ + +#define NR5_UART1_BASE 0x40000000 /* 0x40000000 - 0x40000fff: UART0 */ +#define NR5_GPIO1_BASE 0x40001000 /* 0x40001000 - 0x40001fff: GPIO1 */ +#define NR5_GPIO2_BASE 0x40002000 /* 0x40002000 - 0x40002fff: GPIO2 */ +#define NR5_GPIO3_BASE 0x40003000 /* 0x40003000 - 0x40003fff: GPIO3 */ +#define NR5_TIMER1_BASE 0x40004000 /* 0x40004000 - 0x40004fff: TIMER0 timer */ +#define NR5_TIMER2_BASE 0x40005000 /* 0x40005000 - 0x40005fff: TIMER1 timer */ +#define NR5_EXTMEM_BASE 0x40006000 /* 0x40006000 - 0x40006fff: EXTMEM Controller*/ + +#endif /* __ARCH_RISCV_SRC_NR5M100_CHIP_NR5M1XX_MEMORYMAP_H */ + diff --git a/arch/risc-v/src/nr5m100/chip/nr5m1xx_timer.h b/arch/risc-v/src/nr5m100/chip/nr5m1xx_timer.h new file mode 100644 index 00000000000..4739965cf43 --- /dev/null +++ b/arch/risc-v/src/nr5m100/chip/nr5m1xx_timer.h @@ -0,0 +1,190 @@ +/************************************************************************************ + * arch/risc-v/src/nr5m100/chip/nr5_timer.h + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef ARCH_RISCV_SRC_NR5M100_CHIP_NR5M1XX_TIMERA_H +#define ARCH_RISCV_SRC_NR5M100_CHIP_NR5M1XX_TIMERA_H + +#include "nr5m1xx_memorymap.h" + +/* The timers used in the NR5M100 are functionally equivalent to + * Timer A in the MSP430. The hardware peripheral in the FPGA uses the BSD + * licensed RTL code from the OpenMSP430 project on opencores.org. + */ + +/* TimerA offet definitions */ + +#define NR5_TIMERA_TACTL_OFFSET 0x00 +#define NR5_TIMERA_TAR_OFFSET 0x04 +#define NR5_TIMERA_TACCTL0_OFFSET 0x08 +#define NR5_TIMERA_TACCR0_OFFSET 0x0C +#define NR5_TIMERA_TACCTL1_OFFSET 0x10 +#define NR5_TIMERA_TACCR1_OFFSET 0x14 +#define NR5_TIMERA_TACCTL2_OFFSET 0x18 +#define NR5_TIMERA_TACCR2_OFFSET 0x1C +#define NR5_TIMERA_TAIV_OFFSET 0x20 + +/* Timer 1 address definitions */ + +#ifdef CONFIG_NR5_TIMER1 +#define NR5_TIMER1_TACTL_OFFSET (NR5_TIMER1_BASE+NR5_TIMERA_TACTL_OFFSET) +#define NR5_TIMER1_TAR_OFFSET (NR5_TIMER1_BASE+NR5_TIMERA_TAR_OFFSET) +#define NR5_TIMER1_TACCTL0_OFFSET (NR5_TIMER1_BASE+NR5_TIMERA_TACCTL0_OFFSET) +#define NR5_TIMER1_TACCR0_OFFSET (NR5_TIMER1_BASE+NR5_TIMERA_TACCR0_OFFSET) +#define NR5_TIMER1_TACCTL1_OFFSET (NR5_TIMER1_BASE+NR5_TIMERA_TACCTL1_OFFSET) +#define NR5_TIMER1_TACCR1_OFFSET (NR5_TIMER1_BASE+NR5_TIMERA_TACCR1_OFFSET) +#define NR5_TIMER1_TACCTL2_OFFSET (NR5_TIMER1_BASE+NR5_TIMERA_TACCTL2_OFFSET) +#define NR5_TIMER1_TACCR2_OFFSET (NR5_TIMER1_BASE+NR5_TIMERA_TACCR2_OFFSET) +#define NR5_TIMER1_TAIV_OFFSET (NR5_TIMER1_BASE+NR5_TIMERA_TAIV_OFFSET) +#endif + +/* Timer 2 address definitions */ + +#ifdef CONFIG_NR5_TIMER2 +#define NR5_TIMER2_TACTL_OFFSET (NR5_TIMER2_BASE+NR5_TIMERA_TACTL_OFFSET) +#define NR5_TIMER2_TAR_OFFSET (NR5_TIMER2_BASE+NR5_TIMERA_TAR_OFFSET) +#define NR5_TIMER2_TACCTL0_OFFSET (NR5_TIMER2_BASE+NR5_TIMERA_TACCTL0_OFFSET) +#define NR5_TIMER2_TACCR0_OFFSET (NR5_TIMER2_BASE+NR5_TIMERA_TACCR0_OFFSET) +#define NR5_TIMER2_TACCTL1_OFFSET (NR5_TIMER2_BASE+NR5_TIMERA_TACCTL1_OFFSET) +#define NR5_TIMER2_TACCR1_OFFSET (NR5_TIMER2_BASE+NR5_TIMERA_TACCR1_OFFSET) +#define NR5_TIMER2_TACCTL2_OFFSET (NR5_TIMER2_BASE+NR5_TIMERA_TACCTL2_OFFSET) +#define NR5_TIMER2_TACCR2_OFFSET (NR5_TIMER2_BASE+NR5_TIMERA_TACCR2_OFFSET) +#define NR5_TIMER2_TAIV_OFFSET (NR5_TIMER2_BASE+NR5_TIMERA_TAIV_OFFSET) +#endif + +/* Timer 3 address definitions */ + +#ifdef CONFIG_NR5_TIMER3 +#define NR5_TIMER3_TACTL_OFFSET (NR5_TIMER3_BASE+NR5_TIMERA_TACTL_OFFSET) +#define NR5_TIMER3_TAR_OFFSET (NR5_TIMER3_BASE+NR5_TIMERA_TAR_OFFSET) +#define NR5_TIMER3_TACCTL0_OFFSET (NR5_TIMER3_BASE+NR5_TIMERA_TACCTL0_OFFSET) +#define NR5_TIMER3_TACCR0_OFFSET (NR5_TIMER3_BASE+NR5_TIMERA_TACCR0_OFFSET) +#define NR5_TIMER3_TACCTL1_OFFSET (NR5_TIMER3_BASE+NR5_TIMERA_TACCTL1_OFFSET) +#define NR5_TIMER3_TACCR1_OFFSET (NR5_TIMER3_BASE+NR5_TIMERA_TACCR1_OFFSET) +#define NR5_TIMER3_TACCTL2_OFFSET (NR5_TIMER3_BASE+NR5_TIMERA_TACCTL2_OFFSET) +#define NR5_TIMER3_TACCR2_OFFSET (NR5_TIMER3_BASE+NR5_TIMERA_TACCR2_OFFSET) +#define NR5_TIMER3_TAIV_OFFSET (NR5_TIMER3_BASE+NR5_TIMERA_TAIV_OFFSET) +#endif + +/* Timer 4 address definitions */ + +#ifdef CONFIG_NR5_TIMER4 +#define NR5_TIMER4_TACTL_OFFSET (NR5_TIMER4_BASE+NR5_TIMERA_TACTL_OFFSET) +#define NR5_TIMER4_TAR_OFFSET (NR5_TIMER4_BASE+NR5_TIMERA_TAR_OFFSET) +#define NR5_TIMER4_TACCTL0_OFFSET (NR5_TIMER4_BASE+NR5_TIMERA_TACCTL0_OFFSET) +#define NR5_TIMER4_TACCR0_OFFSET (NR5_TIMER4_BASE+NR5_TIMERA_TACCR0_OFFSET) +#define NR5_TIMER4_TACCTL1_OFFSET (NR5_TIMER4_BASE+NR5_TIMERA_TACCTL1_OFFSET) +#define NR5_TIMER4_TACCR1_OFFSET (NR5_TIMER4_BASE+NR5_TIMERA_TACCR1_OFFSET) +#define NR5_TIMER4_TACCTL2_OFFSET (NR5_TIMER4_BASE+NR5_TIMERA_TACCTL2_OFFSET) +#define NR5_TIMER4_TACCR2_OFFSET (NR5_TIMER4_BASE+NR5_TIMERA_TACCR2_OFFSET) +#define NR5_TIMER4_TAIV_OFFSET (NR5_TIMER4_BASE+NR5_TIMERA_TAIV_OFFSET) +#endif + +/* Timer 5 address definitions */ + +#ifdef CONFIG_NR5_TIMER5 +#define NR5_TIMER5_TACTL_OFFSET (NR5_TIMER5_BASE+NR5_TIMERA_TACTL_OFFSET) +#define NR5_TIMER5_TAR_OFFSET (NR5_TIMER5_BASE+NR5_TIMERA_TAR_OFFSET) +#define NR5_TIMER5_TACCTL0_OFFSET (NR5_TIMER5_BASE+NR5_TIMERA_TACCTL0_OFFSET) +#define NR5_TIMER5_TACCR0_OFFSET (NR5_TIMER5_BASE+NR5_TIMERA_TACCR0_OFFSET) +#define NR5_TIMER5_TACCTL1_OFFSET (NR5_TIMER5_BASE+NR5_TIMERA_TACCTL1_OFFSET) +#define NR5_TIMER5_TACCR1_OFFSET (NR5_TIMER5_BASE+NR5_TIMERA_TACCR1_OFFSET) +#define NR5_TIMER5_TACCTL2_OFFSET (NR5_TIMER5_BASE+NR5_TIMERA_TACCTL2_OFFSET) +#define NR5_TIMER5_TACCR2_OFFSET (NR5_TIMER5_BASE+NR5_TIMERA_TACCR2_OFFSET) +#define NR5_TIMER5_TAIV_OFFSET (NR5_TIMER5_BASE+NR5_TIMERA_TAIV_OFFSET) +#endif + +/* Register Bitfield Definitions ********************************************************/ + +/* Control register TACTL Bit definitions */ + +#define TIMERA_TACTL_TAIFG (1 << 0) /* Bit 0: Interrupt Pending Flag */ +#define TIMERA_TACTL_TAIE (1 << 1) /* Bit 1: Interrupt Enable */ +#define TIMERA_TACTL_TACLR (1 << 2) /* Bit 2: TAR counter clear */ +#define TIMERA_TACTL_MC_SHIFT 4 /* Bits 4-5: Mode Control */ +# define TIMERA_TACTL_MC_MASK (3 << TIMERA_TACTL_MC_SHIFT) +# define TIMERA_TACTL_STOP (0 << TIMERA_TACTL_MC_SHIFT) +# define TIMERA_TACTL_UP (1 << TIMERA_TACTL_MC_SHIFT) +# define TIMERA_TACTL_CONTINUOUS (2 << TIMERA_TACTL_MC_SHIFT) +# define TIMERA_TACTL_UPDOWN (3 << TIMERA_TACTL_MC_SHIFT) +#define TIMERA_TACTL_ID_SHIFT 6 /* Bits 6-7: Input Divider */ +# define TIMERA_TACTL_DIV_1 (0 << TIMERA_TACTL_ID_SHIFT) +# define TIMERA_TACTL_DIV_2 (1 << TIMERA_TACTL_ID_SHIFT) +# define TIMERA_TACTL_DIV_4 (2 << TIMERA_TACTL_ID_SHIFT) +# define TIMERA_TACTL_DIV_8 (3 << TIMERA_TACTL_ID_SHIFT) +#define TIMERA_TACTL_TASSEL_SHIFT 8 /* Bits 8-9: Clock Source Select */ +# define TIMERA_TACTL_MED_CLOCK (0 << TIMERA_TACTL_TASSEL_SHIFT) +# define TIMERA_TACTL_SLOW_CLOCK (1 << TIMERA_TACTL_TASSEL_SHIFT) +# define TIMERA_TACTL_SYS_CLOCK (2 << TIMERA_TACTL_TASSEL_SHIFT) +# define TIMERA_TACTL_EXT_CLOCK (3 << TIMERA_TACTL_TASSEL_SHIFT) +#define TIMERA_TACTL_TAPRE_SHIFT 10 /* Bits 10-15: Clock Prescaler */ +#define TIMERA_TACTL_TAPRE_MASK 0x3F +# define TIMERA_TACTL_TAPRE(x) (((x) & TIMERA_TACTL_TAPRE_MASK) << TIMERA_TACTL_TAPRE_SHIFT) + +/* Capture / Compare register bit definitions */ + +#define TIMERA_TACCTL_CCIFG (1 << 0) /* Bit 0: Capture/compare interrupt Flag */ +#define TIMERA_TACCTL_COV (1 << 1) /* Bit 1: Capture overflow */ +#define TIMERA_TACCTL_OUTVAL (1 << 2) /* Bit 2: Output value */ +#define TIMERA_TACCTL_CCI (1 << 3) /* Bit 3: Capture/compare input value */ +#define TIMERA_TACCTL_CCIE (1 << 4) /* Bit 4: Capture/Compare interrupt Enable */ +#define TIMERA_TACCTL_OUTMOD_SHIFT 5 /* Bits 5-7: Output Mode */ +# define TIMERA_TACCTL_OUT (0 << TIMERA_TACCTL_OUTMOD_SHIFT) +# define TIMERA_TACCTL_SET (1 << TIMERA_TACCTL_OUTMOD_SHIFT) +# define TIMERA_TACCTL_TOGGLE_RESET (2 << TIMERA_TACCTL_OUTMOD_SHIFT) +# define TIMERA_TACCTL_SET_RESET (3 << TIMERA_TACCTL_OUTMOD_SHIFT) +# define TIMERA_TACCTL_TOGGLE (4 << TIMERA_TACCTL_OUTMOD_SHIFT) +# define TIMERA_TACCTL_RESET (5 << TIMERA_TACCTL_OUTMOD_SHIFT) +# define TIMERA_TACCTL_TOGGLE_SET (6 << TIMERA_TACCTL_OUTMOD_SHIFT) +# define TIMERA_TACCTL_RESET_SET (7 << TIMERA_TACCTL_OUTMOD_SHIFT) +#define TIMERA_TACCTL_CAP (1 << 8) /* Bit 8: Capture mode select */ +#define TIMERA_TACCTL_SCCI (1 << 10) /* Bit 10: Synchronized capture input */ +#define TIMERA_TACCTL_SCS (1 << 11) /* Bit 11: Syncronize capture source */ +#define TIMERA_TACCTL_CCIS_SHIFT 12 /* Bits 12-13: Capture Input Select */ +# define TIMERA_TACCTL_CCIS_CCIA (0 << TIMERA_TACCTL_CCIS_SHIFT) +# define TIMERA_TACCTL_CCIS_CCIB (1 << TIMERA_TACCTL_CCIS_SHIFT) +# define TIMERA_TACCTL_CCIS_GND (2 << TIMERA_TACCTL_CCIS_SHIFT) +# define TIMERA_TACCTL_CCIS_VCC (3 << TIMERA_TACCTL_CCIS_SHIFT) +#define TIMERA_TACCTL_CM_SHIFT 14 /* Bits 14-15: Capture Mode */ +# define TIMERA_TACCTL_CM_NO_CAPTURE (0 << TIMERA_TACCTL_SM_SHIFT) +# define TIMERA_TACCTL_CM_RISING (1 << TIMERA_TACCTL_SM_SHIFT) +# define TIMERA_TACCTL_CM_FALLING (2 << TIMERA_TACCTL_SM_SHIFT) +# define TIMERA_TACCTL_CM_BOTH (3 << TIMERA_TACCTL_SM_SHIFT) + +/* Interrupt Vector Register */ + +#define TIMERA_TAIV_TAIV_SHIFT 1 /* Bits 1-3: Interrupt Source */ +# define TIMERA_TAIV_TACCR1 (1 << TIMERA_TAIV_TAIV_SHIFT) +# define TIMERA_TAIV_TACCR2 (2 << TIMERA_TAIV_TAIV_SHIFT) +# define TIMERA_TAIV_TAIFG (5 << TIMERA_TAIV_TAIV_SHIFT) + +#endif /* _ARCH_RISCV_SRC_NR5M100_CHIP_NR5M1XX_TIMERA_H */ + diff --git a/arch/risc-v/src/nr5m100/chip/nr5m1xx_uart.h b/arch/risc-v/src/nr5m100/chip/nr5m1xx_uart.h new file mode 100644 index 00000000000..5a790782e98 --- /dev/null +++ b/arch/risc-v/src/nr5m100/chip/nr5m1xx_uart.h @@ -0,0 +1,75 @@ +/************************************************************************************ + * arch/risc-v/src/nr5m100/chip/nr5_uart.h + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef ARCH_RISCV_SRC_NR5M100_CHIP_NR5M1XX_UART_H +#define ARCH_RISCV_SRC_NR5M100_CHIP_NR5M1XX_UART_H + +/* The UART in NR5M100 is a very small (i.e. dumb) peripheral. It + * only supports the most common mode ever used: + * + * 8 Data bits + * 1 Stop bit + * No parity. + * + * It has a programmable baud rate and RX / TX interrupt capability + * and that's about it. The primary goal for the UART is to provide a + * debug console to the part. + */ + +#define NR5_UART_BAUD_RATE_OFFSET 0x000 +#define NR5_UART_TX_REG_OFFSET 0x004 +#define NR5_UART_RX_REG_OFFSET 0x008 +#define NR5_UART_STATUS_REG_OFFSET 0x00C +#define NR5_UART_CTRL_REG_OFFSET 0x010 + +#ifdef CONFIG_NR5_UART1 +# define NR5_UART1_BAUD_RATE_REG (NR5_UART1_BASE+NR5_UART_BAUD_RATE_OFFSET) +# define NR5_UART1_TX_REG (NR5_UART1_BASE+NR5_UART_TX_REG_OFFSET) +# define NR5_UART1_RX_REG (NR5_UART1_BASE+NR5_UART_RX_REG_OFFSET) +# define NR5_UART1_STATUS_REG (NR5_UART1_BASE+NR5_UART_STATUS_REG_OFFSET) +# define NR5_UART1_CTRL_REG (NR5_UART1_BASE+NR5_UART_CTRL_REG_OFFSET) +#endif + +/* Status Register Bit definitions */ + +#define NR5_UART_STATUS_TX_EMPTY 0x01 +#define NR5_UART_STATUS_RX_AVAIL 0x02 +#define NR5_UART_STATUS_RX_OVERRUN 0x04 +#define NR5_UART_RX_IRQ_PENDING 0x08 +#define NR5_UART_TX_IRQ_PENDING 0x10 + +/* Control Register Bit definitions */ + +#define NR5_UART_CTRL_ENABLE_RX_IRQ 0x01 +#define NR5_UART_CTRL_ENABLE_TX_IRQ 0x02 + +#endif /* _ARCH_RISCV_SRC_NR5M100_CHIP_NR5M1XX_UART_H */ diff --git a/arch/risc-v/src/nr5m100/nr5.h b/arch/risc-v/src/nr5m100/nr5.h new file mode 100644 index 00000000000..f6038a76204 --- /dev/null +++ b/arch/risc-v/src/nr5m100/nr5.h @@ -0,0 +1,68 @@ +/************************************************************************************ + * arch/risc-v/src/nr5m100/nr5.h + * + * Copyright (C) 2011 Uros Platise. All rights reserved. + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Authors: Uros Platise + * Gregory Nutt + * Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_NR5M100_NR5_H +#define __ARCH_RISCV_SRC_NR5M100_NR5_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include +#include +#include + +#include +#include "up_internal.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Peripherals **********************************************************************/ + +#include "chip.h" +#include "nr5_csr.h" +#include "nr5_lowputc.h" +#include "nr5_timer.h" +#include "nr5_uart.h" + +#endif /* __ARCH_RISCV_SRC_NR5_NR5_H */ + diff --git a/arch/risc-v/src/nr5m100/nr5_allocateheap.c b/arch/risc-v/src/nr5m100/nr5_allocateheap.c new file mode 100644 index 00000000000..3467cee05cb --- /dev/null +++ b/arch/risc-v/src/nr5m100/nr5_allocateheap.c @@ -0,0 +1,63 @@ +/************************************************************************************ + * arch/risc-v/src/nr5m100/nr5_allocateheap.c + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include + +#include "nr5.h" + +/************************************************************************************ + * Private Types + ************************************************************************************/ + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: up_addregion + * + * Descripton: + * RAM may be added in non-contiguous chunks. This routine adds all chunks + * that may be used for heap. + * + ************************************************************************************/ + +void up_addregion(void) +{ +} + diff --git a/arch/risc-v/src/nr5m100/nr5_arch.c b/arch/risc-v/src/nr5m100/nr5_arch.c new file mode 100644 index 00000000000..0bc09cacb53 --- /dev/null +++ b/arch/risc-v/src/nr5m100/nr5_arch.c @@ -0,0 +1,43 @@ +/************************************************************************************ + * arch/risc-v/src/nr5m100/nr5_arch.c + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#include +#include +#include "nr5.h" + +void up_puts(const char *p) +{ + while (*p != 0) + up_lowputc(*(p++)); + up_lowputc('\n'); +} + diff --git a/arch/risc-v/src/nr5m100/nr5_config.h b/arch/risc-v/src/nr5m100/nr5_config.h new file mode 100644 index 00000000000..36b20d5914b --- /dev/null +++ b/arch/risc-v/src/nr5m100/nr5_config.h @@ -0,0 +1,97 @@ +/************************************************************************************ + * arch/risc-v/src/nr5m100/nr5_config.h + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Modified for RISC-V: + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_NR5M100_NR5_CONFIG_H +#define __ARCH_RISCV_SRC_NR5M100_NR5_CONFIG_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* UARTs ****************************************************************************/ + +/* Are any UARTs enabled? */ + +#undef HAVE_UART_DEVICE +#if defined(CONFIG_NR5_UART1) || defined(CONFIG_NR5_UART2) +# define HAVE_UART_DEVICE 1 +#endif + +/* Is there a serial console? There should be no more than one defined. It + * could be on any UARTn, n=1,.. CHIP_NUARTS + */ + +#if defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_NR5_UART1) +# undef CONFIG_UART2_SERIAL_CONSOLE +# define HAVE_SERIAL_CONSOLE 1 +#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_NR5_UART2) +# undef CONFIG_UART1_SERIAL_CONSOLE +# define HAVE_SERIAL_CONSOLE 1 +#else +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef HAVE_SERIAL_CONSOLE +#endif + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_RISCV_SRC_NR5M100_NR5_CONFIG_H */ diff --git a/arch/risc-v/src/nr5m100/nr5_csr.S b/arch/risc-v/src/nr5m100/nr5_csr.S new file mode 100644 index 00000000000..d586270e09b --- /dev/null +++ b/arch/risc-v/src/nr5m100/nr5_csr.S @@ -0,0 +1,289 @@ +/************************************************************************************ + * arch/risc-v/src/nr5m100/nr5_csr.c + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/* + * Provide C level access function to asm only CSR registers + */ + +#define ENABLE_QREGS +#include "nr5_custom_ops.h" +#include "nr5_csr.h" + + .global up_getmisa + .global up_getarchid + .global up_getimpid + .global up_getvendorid + .global up_gethartid + .global up_getepicprimask + .global up_setepicprimask + .global up_setepicstat + .global up_setsystick + .global up_setpri1bit + .global up_clearpri1bit + .global up_setpri2bit + .global up_clearpri2bit + .global up_setpri3bit + .global up_clearpri3bit + .global up_setirqmaskbit + .global up_clearirqmaskbit + .global up_disableints + .global up_enableints + .global up_getq0 + .global up_getq1 + .global up_getq2 + .global up_setq0 + .global up_setq1 + .global up_setq2 + .global up_lsbenc + + .section .text + +/**************************************************************************** + * Returns the Read Only RV32IM Machine ISA (capabilities) + ****************************************************************************/ + +up_getmisa: + csrr a0, CSR_MISA + ret + +/**************************************************************************** + * Returns the Read Only RV32IM Vendor ID + ****************************************************************************/ + +up_getvendorid: + csrr a0, CSR_MVENDORID + ret + +/**************************************************************************** + * Returns the Read Only RV32IM ARCH ID + ****************************************************************************/ + +up_getarchid: + csrr a0, CSR_MARCHID + ret + +/**************************************************************************** + * Returns the Read Only RV32IM IMP ID + ****************************************************************************/ + +up_getimpid: + csrr a0, CSR_MIMPID + ret + +/**************************************************************************** + * Returns the Read Only RV32IM HART ID + ****************************************************************************/ + +up_gethartid: + csrr a0, CSR_MHARTID + ret + +/**************************************************************************** + * Returns the NR5M100 specific Embedded Priority Interrupt Controller (EPIC) + * IRQ MASK register + ****************************************************************************/ + +up_getepicmask: + csrr a0, NR5_EPIC_IRQ_MASK + ret + +/**************************************************************************** + * Returns the NR5M100 specific EPIC IRQ Priority register + ****************************************************************************/ + +up_getepicpri: + csrr a0, NR5_EPIC_PRIMASK + ret + +/**************************************************************************** + * Sets the NR5M100 specific EPIC IRQ Priority register + ****************************************************************************/ + +up_setepicpri: + csrrw a0, NR5_EPIC_PRIMASK, a0 + ret + +/**************************************************************************** + * Sets the NR5M100 specific SYSTICK control register + ****************************************************************************/ + +up_setsystick: + csrw NR5_MSYSTICK_REG, a0 + ret + +/**************************************************************************** + * Sets bits in the NR5M100 specific PRI1 mask control register + ****************************************************************************/ + +up_setpri1bit: + csrrs a0, NR5_EPIC_PRI1, a0 + ret + +/**************************************************************************** + * Clears bits in the NR5M100 specific PRI1 mask control register + ****************************************************************************/ + +up_clearpri1bit: + csrrc a0, NR5_EPIC_PRI1, a0 + ret + +/**************************************************************************** + * Sets bits in the NR5M100 specific PRI2 mask control register + ****************************************************************************/ + +up_setpri2bit: + csrrs a0, NR5_EPIC_PRI2, a0 + ret + +/**************************************************************************** + * Clears bits in the NR5M100 specific PRI2 mask control register + ****************************************************************************/ + +up_clearpri2bit: + csrrc a0, NR5_EPIC_PRI2, a0 + ret + +/**************************************************************************** + * Sets bits in the NR5M100 specific PRI3 mask control register + ****************************************************************************/ + +up_setpri3bit: + csrrs a0, NR5_EPIC_PRI3, a0 + ret + +/**************************************************************************** + * Clears bits in the NR5M100 specific PRI3 mask control register + ****************************************************************************/ + +up_clearpri3bit: + csrrc a0, NR5_EPIC_PRI3, a0 + ret + +/**************************************************************************** + * Sets bits in the NR5M100 specific IRQ mask control register + ****************************************************************************/ + +up_setirqmaskbit: + csrrs a0, NR5_EPIC_IRQ_MASK, a0 + ret + +/**************************************************************************** + * Clears bits in the NR5M100 specific IRQ mask control register + ****************************************************************************/ + +up_clearirqmaskbit: + csrrc a0, NR5_EPIC_IRQ_MASK, a0 + ret + +/**************************************************************************** + * Disables global interrupts in NR5M100 specific IRQ PRI control register + ****************************************************************************/ + +up_disableints: + csrrc a0, NR5_EPIC_PRIMASK, 1 + ret + +/**************************************************************************** + * Enables global interrupts in NR5M100 specific IRQ PRI control register + ****************************************************************************/ + +up_enableints: + csrrs a0, NR5_EPIC_PRIMASK, 1 + ret + +/**************************************************************************** + * Reads NR5M100 specific Q0 register (used for interrupt processing) + ****************************************************************************/ + +up_getq0: + getq a0, q0 + ret + +/**************************************************************************** + * Reads NR5M100 specific Q1 register (used for interrupt processing) + ****************************************************************************/ + +up_getq1: + getq a0, q1 + ret + +/**************************************************************************** + * Reads NR5M100 specific Q2 register (used for interrupt processing) + ****************************************************************************/ + +up_getq2: + getq a0, q2 + ret + +/**************************************************************************** + * Sets NR5M100 specific Q0 register (used for interrupt processing) + ****************************************************************************/ + +up_setq0: + setq q0, a0 + ret + +/**************************************************************************** + * Sets NR5M100 specific Q1 register (used for interrupt processing) + ****************************************************************************/ + +up_setq1: + setq q1, a0 + ret + +/**************************************************************************** + * Sets NR5M100 specific Q2 register (used for interrupt processing) + ****************************************************************************/ + +up_setq2: + setq q2, a0 + ret + +/**************************************************************************** + * Calls the NR5M100 specific LSBENC opcode. This opcode will find the + * first least significant non-zero bit in a0 and return it's ordinal value. + ****************************************************************************/ + +up_lsbenc: + lsbenc a0, a0 + ret + +/**************************************************************************** + * Modeline to set vim formatting options for ASM file. For this to work, + * you must enable moeline processing in your ~/.vimrc file with: + * + * ~/.vimrc: + * set modeline + * + * vim: noet:ts=4:sw=4 + ****************************************************************************/ + diff --git a/arch/risc-v/src/nr5m100/nr5_csr.h b/arch/risc-v/src/nr5m100/nr5_csr.h new file mode 100644 index 00000000000..025a5098865 --- /dev/null +++ b/arch/risc-v/src/nr5m100/nr5_csr.h @@ -0,0 +1,94 @@ +/************************************************************************************ + * arch/riscv/src/nr5/nr5_csr.h + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/* CSR Definitions */ + +#ifndef __ARCH_RISCV_SRC_NR5_NR5_CSR_H +#define __ARCH_RISCV_SRC_NR5_NR5_CSR_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#ifndef __ASSEMBLY__ +#include +#endif + +#if defined(CONFIG_NR5_NR5M1XX) +# include "chip/nr5m1xx_epic.h" +#endif + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +#define NR5_EPIC_IRQ_MASK 0x7E0 +#define NR5_EPIC_PRI1 0x7E1 +#define NR5_EPIC_PRI2 0x7E2 +#define NR5_EPIC_PRI3 0x7E3 +#define NR5_EPIC_PRIMASK 0x7E4 +#define NR5_MSYSTICK_REG 0x7E5 + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#ifndef __ASSEMBLY__ +void up_setsystick(uint32_t); + +void up_setpri1bit(uint32_t); +void up_setpri2bit(uint32_t); +void up_setpri3bit(uint32_t); + +void up_clearpri1bit(uint32_t); +void up_clearpri2bit(uint32_t); +void up_clearpri3bit(uint32_t); + +void up_setirqmaskbit(uint32_t); +void up_clearirqmaskbit(uint32_t); + +void up_disableints(void); +void up_enableints(void); + +#endif /* __ASSEMBLY__ */ + +#endif /* __ARCH_RISCV_SRC_NR5_NR5_CSR_H */ + diff --git a/arch/risc-v/src/nr5m100/nr5_custom_ops.h b/arch/risc-v/src/nr5m100/nr5_custom_ops.h new file mode 100644 index 00000000000..0c600eccf52 --- /dev/null +++ b/arch/risc-v/src/nr5m100/nr5_custom_ops.h @@ -0,0 +1,61 @@ +/************************************************************************************ + * arch/risc-v/src/nr5m100/nr5_custom_ops.h + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define q0 0 +#define q1 1 +#define q2 2 +#define q3 3 + +/**************************************************************************** + * Assmebler Macros + ****************************************************************************/ + +.macro getq rd qs +custom0 \rd,\qs,0,0 +.endm + +.macro setq qd rs +custom0 \qd,\rs,0,1 +.endm + +.macro lsbenc rd rs +custom0 \rd,\rs,0,2 +.endm + +.macro timer rd rs +custom0 \rd,\rs,0,5 +.endm + diff --git a/arch/risc-v/src/nr5m100/nr5_head.S b/arch/risc-v/src/nr5m100/nr5_head.S new file mode 100644 index 00000000000..aa6eb232645 --- /dev/null +++ b/arch/risc-v/src/nr5m100/nr5_head.S @@ -0,0 +1,611 @@ +/************************************************************************************ + * arch/risc-v/src/nr5m100/nr5_head.S + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#define ENABLE_QREGS + +#include "nr5_custom_ops.h" +#include "nr5_csr.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* Configuration ************************************************************/ + +#define NR5M100_STACK_BASE _ebss +#define NR5M100_STACK_TOP _ebss+CONFIG_IDLETHREAD_STACKSIZE-4 + +#if CONFIG_ARCH_INTERRUPTSTACK > 3 +# define NR5M100_INTSTACK_BASE NR5M100_STACK_TOP +# define NR5M100_INTSTACK_SIZE (CONFIG_ARCH_INTERRUPTSTACK & ~3) +# define NR5M100_INTSTACK_TOP NR5M100_STACK_TOP+NR5M100_INTSTACK_SIZE +# define NR5M100_HEAP_BASE NR5M100_INTSTACK_TOP +#else +# define NR5M100_HEAP_BASE NR5M100_STACK_TOP +#endif + +/**************************************************************************** + * Public Symbols + ****************************************************************************/ + + .global irq_handler + +#ifdef CONFIG_RV32IM_HW_MULDIV + .global time_hard_mul + .global hard_mul + .global hard_mulh + .global hard_mulhsu + .global hard_div + .global hard_divu + .global hard_rem + .global hard_remu + .global hard_mulhu +#endif + + .global g_idle_topstack + + /* Imported symbols */ + + .extern __reset_vec + .extern __trap_vec + .extern __stack_start + .global os_start + +#ifndef CONFIG_LIB_NEWLIB + + .section .text + .global __start + +__start: + + /* Set IRQ regs address */ + + lui x1, %hi(irq_regs) + addi x1, x1, %lo(irq_regs) + lui x2, %hi(irq_regs_addr) + addi x2, x2, %lo(irq_regs_addr) + sw x1, 0(x2) + + /* Set IRQ stack address */ + + lui x1, %hi(irq_stack) + addi x1, x1, %lo(irq_stack) + lui x2, %hi(irq_stack_addr) + addi x2, x2, %lo(irq_stack_addr) + sw x1, 0(x2) + + /* Zero out the registers */ + + addi x1, zero, 0 + addi x2, zero, 0 + addi x3, zero, 0 + addi x4, zero, 0 + addi x5, zero, 0 + addi x6, zero, 0 + addi x7, zero, 0 + addi x8, zero, 0 + addi x9, zero, 0 + addi x10, zero, 0 + addi x11, zero, 0 + addi x12, zero, 0 + addi x13, zero, 0 + addi x14, zero, 0 + addi x15, zero, 0 + addi x16, zero, 0 + addi x17, zero, 0 + addi x18, zero, 0 + addi x19, zero, 0 + addi x20, zero, 0 + addi x21, zero, 0 + addi x22, zero, 0 + addi x23, zero, 0 + addi x24, zero, 0 + addi x25, zero, 0 + addi x26, zero, 0 + addi x27, zero, 0 + addi x28, zero, 0 + addi x29, zero, 0 + addi x30, zero, 0 + addi x31, zero, 0 + + /* Set stack pointer */ + + lui sp,%hi(__stack_start) + + /* Initialize global pointer */ + +1: auipc gp, %pcrel_hi(_gp) + addi gp, gp, %pcrel_lo(1b) + + /* Initialize the Machine Trap Vector */ + + lui t0, %hi(__trap_vec) + addi t0, t0, %lo(__trap_vec) + csrw CSR_MTVEC, t0 + + /* Initialize the Machine Interrupt Table Vector */ + lui t0, %hi(__reset_vec) + csrw CSR_MIVEC, t0 + + /* clear the bss segment */ + + la t0, _fbss + la t1, _end +1: +#ifdef __riscv64 + sd zero,0(t0) + addi t0, t0, 8 +#else + sw zero,0(t0) + addi t0, t0, 4 +#endif + bltu t0, t1, 1b + + /* Call the nr5_init_array routine to initialize C variables */ + + //call __nr5_init_array + + lw a0, 0(sp) # a0 = argc + addi a1, sp, _RISCV_SZPTR/8 # a1 = argv + li a2, 0 # a2 = envp = NULL + + /* Now jump to the main nr5_init routine to setup interrupts, etc. */ + + la t0, __nr5_init + jr t0 + + /* We shouldn't return from __nr5_init */ + + .global _init + .global _fini +_init: +_fini: + # These don't have to do anything since we use init_array/fini_array. + ret + +#endif + +/* +============================================================== +IRQ Handler routine .. save all regs and call the C handler. +============================================================== +*/ + +irq_handler: + + /* save All registers */ + +#ifdef ENABLE_QREGS + + /* Save x1,x2 in the spare q2,q3 registers */ + + setq q2, x1 + setq q3, x2 + + /* Get pointer to our IRQ REGS save region in RAM */ + + lui x2, %hi(irq_regs_addr) + addi x2, x2, %lo(irq_regs_addr) + lw x1, 0(x2) + addi x1, x1, 32*4 + sw x1, 0(x2) + addi x1, x1, -32*4 + + /* Save x3 and x4 to hold regs / stack pointer */ + + sw x3, 3*4(x1) + sw x4, 4*4(x1) + addi x4, x1, 0 + + /* Save the IRQ pending mask to the irq_regs area */ + + getq x2, q1 + sw x2, 33*4(x1) + + /* Save the x1 register (which is in q2) */ + + getq x2, q2 + sw x2, 1*4(x1) + + /* Save the x2 register (which is in q3) */ + + getq x2, q3 + sw x2, 2*4(x1) + + /* Get a stack region in irq stack space */ + + lui x3, %hi(irq_stack_addr) + addi x3, x3, %lo(irq_stack_addr) + lw x2, 0(x3) + addi x2, x2, -128*4 + sw x2, 0(x3) + addi x3, x2, 128*4 + + /* Save the return PC. After the getq of q0, + * the higher priority interrupts will be enabled + * as we are done using the shared resources (Qregs). + */ + + getq x2, q0 + sw x2, 0*4(x1) + + sw x5, 5*4(x1) + sw x6, 6*4(x1) + sw x7, 7*4(x1) + sw x8, 8*4(x1) + sw x9, 9*4(x1) + sw x10, 10*4(x1) + sw x11, 11*4(x1) + sw x12, 12*4(x1) + sw x13, 13*4(x1) + sw x14, 14*4(x1) + sw x15, 15*4(x1) + sw x16, 16*4(x1) + sw x17, 17*4(x1) + sw x18, 18*4(x1) + sw x19, 19*4(x1) + sw x20, 20*4(x1) + sw x21, 21*4(x1) + sw x22, 22*4(x1) + sw x23, 23*4(x1) + sw x24, 24*4(x1) + sw x25, 25*4(x1) + sw x26, 26*4(x1) + sw x27, 27*4(x1) + sw x28, 28*4(x1) + sw x29, 29*4(x1) + sw x30, 30*4(x1) + sw x31, 31*4(x1) + + /* Get the EPIC STATUS */ + + csrr t6, NR5_EPIC_PRIMASK + sw t6, 32*4(x1) + + /* Set ISR Stack pointer */ + + addi sp, x3, 0 # IRQ SP is in x3 from above + +#else // ENABLE_QREGS + + sw gp, 0*4+0x200(zero) + sw x1, 1*4+0x200(zero) + sw x2, 2*4+0x200(zero) + sw x3, 3*4+0x200(zero) + sw x4, 4*4+0x200(zero) + sw x5, 5*4+0x200(zero) + sw x6, 6*4+0x200(zero) + sw x7, 7*4+0x200(zero) + sw x8, 8*4+0x200(zero) + sw x9, 9*4+0x200(zero) + sw x10, 10*4+0x200(zero) + sw x11, 11*4+0x200(zero) + sw x12, 12*4+0x200(zero) + sw x13, 13*4+0x200(zero) + sw x14, 14*4+0x200(zero) + sw x15, 15*4+0x200(zero) + sw x16, 16*4+0x200(zero) + sw x17, 17*4+0x200(zero) + sw x18, 18*4+0x200(zero) + sw x19, 19*4+0x200(zero) + sw x20, 20*4+0x200(zero) + sw x21, 21*4+0x200(zero) + sw x22, 22*4+0x200(zero) + sw x23, 23*4+0x200(zero) + sw x24, 24*4+0x200(zero) + sw x25, 25*4+0x200(zero) + sw x26, 26*4+0x200(zero) + sw x27, 27*4+0x200(zero) + sw x28, 28*4+0x200(zero) + sw x29, 29*4+0x200(zero) + sw x30, 30*4+0x200(zero) + sw x31, 31*4+0x200(zero) + + /* Get the EPIC STATUS */ + + csrr t6, NR5_EPIC_PRIMASK + sw t6, 32*4+0x200(zero) + + /* Set ISR Stack pointer */ + + lui sp, %hi(irq_stack) + addi sp, sp, %lo(irq_stack) + +#endif // ENABLE_QREGS + + /* Set arg0 = address of regs */ + +#ifdef ENABLE_QREGS + addi a0, x4, 0 # REG addr in x4 from above +#else + lui a0, %hi(irq_regs) + addi a0, a0, %lo(irq_regs) +#endif + + /* Set arg1 = interrupt type */ + +#ifdef ENABLE_QREGS + lw a1, 33*4(x1) +#else + addi a1, tp, 0 +#endif + + /* call interrupt handler C function */ + + jal ra, irq_dispatch_all + + /* restore registers */ + +#ifdef ENABLE_QREGS + + /* new irq_regs address returned from C code in a0 */ + + addi x1, a0, 0 + + lw x3, 3*4(x1) + lw x4, 4*4(x1) + lw x5, 5*4(x1) + lw x6, 6*4(x1) + lw x7, 7*4(x1) + lw x8, 8*4(x1) + lw x9, 9*4(x1) + lw x10, 10*4(x1) + lw x11, 11*4(x1) + lw x12, 12*4(x1) + lw x13, 13*4(x1) + lw x14, 14*4(x1) + lw x15, 15*4(x1) + lw x16, 16*4(x1) + lw x17, 17*4(x1) + lw x18, 18*4(x1) + lw x19, 19*4(x1) + lw x20, 20*4(x1) + lw x21, 21*4(x1) + lw x22, 22*4(x1) + lw x23, 23*4(x1) + lw x24, 24*4(x1) + lw x25, 25*4(x1) + lw x26, 26*4(x1) + lw x27, 27*4(x1) + lw x28, 28*4(x1) + lw x29, 29*4(x1) + lw x30, 30*4(x1) + lw x31, 31*4(x1) + + /* Restore return PC to q0. This will cause the + * processor to enter a critical state where + * higher priority IRQs won't happen until after + * the mret, thus protecting our shared QREGS. + */ + + lw x2, 0*4(x1) + setq q0, x2 + + /* Restore EPIC STATUS (it may have changed) */ + + lw x2, 32*4(x1) + csrw NR5_EPIC_PRIMASK, x2 + + /* Restore the IRQ mask so the processor knows + * which interrupts to signal as handled + */ + + lw x2, 33*4(x1) + setq q1, x2 + + /* Put original x1 into q2 */ + + lw x2, 1*4(x1) + setq q2, x2 + + /* Put original x2 into q3 */ + + lw x2, 2*4(x1) + setq q3, x2 + + /* Deallocate the irq_stack space */ + + lui x2, %hi(irq_stack_addr) + addi x2, x2, %lo(irq_stack_addr) + lw x1, 0(x2) + addi x1, x1, 128*4 + sw x1, 0(x2) + + /* Deallocate the irq_regs space */ + + lui x2, %hi(irq_regs_addr) + addi x2, x2, %lo(irq_regs_addr) + lw x1, 0(x2) + addi x1, x1, -32*4 + sw x1, 0(x2) + + /* Now restore original x1,x2 from q2,q3 */ + + getq x1, q2 + getq x2, q3 + +#else // ENABLE_QREGS + + /* new irq_regs address returned from C code in a0 */ + + addi a1, zero, 0x200 + beq a0, a1, 1f + sbreak +1: + + lw gp, 0*4+0x200(zero) + lw x1, 1*4+0x200(zero) + lw x2, 2*4+0x200(zero) + // do not restore x3 (gp) + lw x4, 4*4+0x200(zero) + lw x5, 5*4+0x200(zero) + lw x6, 6*4+0x200(zero) + lw x7, 7*4+0x200(zero) + lw x8, 8*4+0x200(zero) + lw x9, 9*4+0x200(zero) + lw x10, 10*4+0x200(zero) + lw x11, 11*4+0x200(zero) + lw x12, 12*4+0x200(zero) + lw x13, 13*4+0x200(zero) + lw x14, 14*4+0x200(zero) + lw x15, 15*4+0x200(zero) + lw x16, 16*4+0x200(zero) + lw x17, 17*4+0x200(zero) + lw x18, 18*4+0x200(zero) + lw x19, 19*4+0x200(zero) + lw x20, 20*4+0x200(zero) + lw x21, 21*4+0x200(zero) + lw x22, 22*4+0x200(zero) + lw x23, 23*4+0x200(zero) + lw x24, 24*4+0x200(zero) + lw x25, 25*4+0x200(zero) + lw x26, 26*4+0x200(zero) + lw x27, 27*4+0x200(zero) + lw x28, 28*4+0x200(zero) + lw x29, 29*4+0x200(zero) + lw x30, 30*4+0x200(zero) + lw x31, 31*4+0x200(zero) + +#endif // ENABLE_QREGS + + /* Return from Machine Interrupt */ + + mret + +irq_regs: + /* registers are saved to this memory region during interrupt handling + * the program counter is saved as register 0 + */ + + .fill 34*5,4 + + /* stack for the interrupt handler */ + + .fill 128*5,4 +irq_stack: + +irq_regs_addr: + .fill 4,4 +irq_stack_addr: + .fill 4,4 + + +/**************************************************************************** + * Hard mul and div functions for multest. These are C interfaces to + * the MUL / DIV opcodes for performing HARD vs SOFT testing. + ****************************************************************************/ + +#ifdef CONFIG_RV32IM_HW_MULDIV + +/* Multiply, return lower 32 bits */ + +up_hard_mul: + mul a0, a0, a1 + ret + +/* Multiply, return upper 32 bits */ + +up_hard_mulh: + mulh a0, a0, a1 + ret + +/* Multiply unsigned */ + +up_hard_mulhsu: + mulhsu a0, a0, a1 + ret + +up_hard_mulhu: + mulhu a0, a0, a1 + ret + +/* Divide */ + +up_hard_div: + div a0, a0, a1 + ret + +/* Divide, return remainder */ + +up_hard_rem: + rem a0, a0, a1 + ret + +/* Divide, unsigned */ + +up_hard_divu: + divu a0, a0, a1 + ret + +/* Remainder, unsigned */ + +up_hard_remu: + remu a0, a0, a1 + ret + +/* Calculate number of clock cycles requried for MUL */ + +up_time_hard_mul: + rdcycle a3 + mul a0, a0, a1 + rdcycle a4 + sub a1, a4, a3 + sw a1,0(a2) + ret + +#endif + +/**************************************************************************** + * This global variable is unsigned int g_idle_topstack and is exported here only + * because of its coupling to idle thread stack. + ****************************************************************************/ + + .section .data + .type g_idle_topstack, object +g_idle_topstack: + .long NR5M100_HEAP_BASE + .size g_idle_topstack, .-g_idle_topstack + +/**************************************************************************** + * Modeline to set vim formatting options for ASM file. For this to work, + * you must enable moeline processing in your ~/.vimrc file with: + * + * ~/.vimrc: + * set modeline + * + * vim: noet:ts=4:sw=4 + ****************************************************************************/ diff --git a/arch/risc-v/src/nr5m100/nr5_init.c b/arch/risc-v/src/nr5m100/nr5_init.c new file mode 100644 index 00000000000..a296ad5a13c --- /dev/null +++ b/arch/risc-v/src/nr5m100/nr5_init.c @@ -0,0 +1,76 @@ +/************************************************************************************ + * arch/risc-v/src/nr5m100/nr5_init.c + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include + +#include "nr5.h" + +/************************************************************************************ + * Private Types + ************************************************************************************/ + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Function - Initialization + * + * Performs low level board initializaiton tasks. + ************************************************************************************/ + +void __nr5_init(void) +{ + /* Configure the UART so we can get debug output */ + + nr5_lowsetup(); + + /* Do board initialization */ + + nr5_boardinitialize(); + + /* Call os_start() */ + + os_start(); + + /* Shouldn't get here */ + + for (;;); +} + + diff --git a/arch/risc-v/src/nr5m100/nr5_irq.c b/arch/risc-v/src/nr5m100/nr5_irq.c new file mode 100644 index 00000000000..b0d1bfa756e --- /dev/null +++ b/arch/risc-v/src/nr5m100/nr5_irq.c @@ -0,0 +1,320 @@ +/**************************************************************************** + * arch/risc-v/src/nr5m100/nr5_irq.c + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "nr5.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +volatile uint32_t *g_current_regs; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: epic_dump + * + * Description: + * Dump the EPIC priority register settings + * + ****************************************************************************/ + +void epic_dump(void) +{ + uint32_t reg; + char str[40]; + + __asm__ volatile("csrr %0, 0x7e0" : "=r"(reg)); + sprintf(str, "IRQMASK = 0x%08X\r", (int) reg); + up_puts(str); + __asm__ volatile("csrr %0, 0x7e4" : "=r"(reg)); + sprintf(str, "IRQSTACK = 0x%08X\r", (int) reg); + up_puts(str); + __asm__ volatile("csrr %0, 0x7e1" : "=r"(reg)); + sprintf(str, "PRI1 = 0x%08X\r", (int) reg); + up_puts(str); + __asm__ volatile("csrr %0, 0x7e2" : "=r"(reg)); + sprintf(str, "PRI2 = 0x%08X\r", (int) reg); + up_puts(str); + __asm__ volatile("csrr %0, 0x7e3" : "=r"(reg)); + sprintf(str, "PRI3 = 0x%08X\r", (int) reg); + up_puts(str); + __asm__ volatile("csrr %0, 0x7e5" : "=r"(reg)); + sprintf(str, "SYSTICK = 0x%08X\r", (int) reg); + up_puts(str); +} + +/**************************************************************************** + * Name: nr5_trap + * + * Description: + * Handler for execptions. None are handled and all are fatal + * error conditions. The only advantage these provided over the default + * unexpected interrupt handler is that they provide a diagnostic output. + * + ****************************************************************************/ + +#define CONFIG_DEBUG + +int nr5_trap_handler(int irq, void *context) +{ + uint32_t sp; + + /* Print a PANIC message */ + + up_puts("PANIC!!! TRAP received\r\n"); + +#ifdef CONFIG_DEBUG + + /* restore the SP to that of the bad code */ + + sp = g_current_regs[2]; + __asm__ volatile ("addi x2, %0, 0" ::"r"(sp)); + + __asm__ volatile ("ebreak"); +#endif + return 0; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_irqinitialize + ****************************************************************************/ + +void up_irqinitialize(void) +{ + uint32_t mask; + + /* Disable all interrupts */ + + mask = ~0; + __asm__ volatile("csrw %0, %1" :: "i"(NR5_EPIC_IRQ_MASK), "r"(mask)); + + /* Colorize the interrupt stack for debug purposes */ + +#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3 + { + size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~3); + up_stack_color((FAR void *)((uintptr_t)&g_intstackbase - intstack_size), + intstack_size); + } +#endif + + /* Set the location of the vector table */ + + /* Set all interrupts (and exceptions) to the default priority */ + +#ifdef NR5_EPIC_PRI_REG + __asm__ volatile (" \ + csrw %0, 0(zero) \ + csrw %1, 0(zero) \ + csrw %2, 0(zero) " :: + "i"(NR5_EPIC_PRI1_REG), "i"(NR5_EPIC_PRI2_REG), + "i"(NR5_EPIC_PRI3_REG) ); +#endif + + /* Initialize the IRQ stack to Pri level 5 with interrupts disabled */ + + mask = 0x05 << 2; + __asm__ volatile("csrw %0, %1" :: "i"(NR5_EPIC_PRIMASK), "r"(mask)); + + /* currents_regs is non-NULL only while processing an interrupt */ + + g_current_regs = NULL; + + /* Attach the Trap exception handler. */ + + irq_attach(NR5_IRQ_TRAP, nr5_trap_handler); + + /* Attach software interrupt handler */ + + irq_attach(NR5_IRQ_SOFTWARE, up_swint); + up_enable_irq(NR5_IRQ_SOFTWARE); + + /* Set the software interrupt priority higher */ + + up_setpri2bit(1 << NR5_IRQ_SOFTWARE); + +#ifndef CONFIG_SUPPRESS_INTERRUPTS + + /* And finally, enable interrupts */ + + up_enable_irq(NR5_IRQ_TRAP); + +#endif + + /* Now enable Global Interrupts */ + + __asm__ volatile("csrrs a0, %0, 3" :: "i"(NR5_EPIC_PRIMASK)); + +} + +/**************************************************************************** + * Name: up_disable_irq + * + * Description: + * Disable the IRQ specified by 'irq' + * + ****************************************************************************/ + +void up_disable_irq(int irq) +{ + up_setirqmaskbit(1 << irq); +} + +/**************************************************************************** + * Name: up_enable_irq + * + * Description: + * Enable the IRQ specified by 'irq' + * + ****************************************************************************/ + +void up_enable_irq(int irq) +{ + up_clearirqmaskbit(1 << irq); +} + +/**************************************************************************** + * Name: up_ack_irq + * + * Description: + * Acknowledge the IRQ + * + ****************************************************************************/ + +void up_ack_irq(int irq) +{ +} + +/**************************************************************************** + * Name: up_get_newintctx + * + * Description: + * Acknowledge the IRQ + * + ****************************************************************************/ + +uint32_t up_get_newintctx(void) +{ + int32_t regval; + + /* Set priority level 5, enabled upon return from interrupt */ + + regval = ((5 << 2) | 2) << 4; + + return regval; +} + +/**************************************************************************** + * Name: up_prioritize_irq + * + * Description: + * Set the priority of an IRQ. + * + * Since this API is not supported on all architectures, it should be + * avoided in common implementations where possible. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQPRIO +int up_prioritize_irq(int irq, int priority) +{ + return OK; +} +#endif + +/**************************************************************************** + * Name: irqsave + * + * Description: + * Disable IRQs while returning the previous IRQ state + * + ****************************************************************************/ + +irqstate_t up_irq_save(void) +{ + irqstate_t newIrqPri = (2 << 2) | 3; + irqstate_t oldIrqPri; + + /* Set the new IRQ Priority level to level 2, enabled. + * This will allow SW and DEBUG / TRAP interrupts to + * continue to fire, but no general purpose ints. + */ + + __asm__ volatile("csrrw %0, %1, %2" : "=r"(oldIrqPri) : + "i"(NR5_EPIC_PRIMASK), "r"(newIrqPri)); + + return oldIrqPri; +} + +/**************************************************************************** + * Name: irqrestore + * + * Description: + * Restore previous IRQ mask state + * + ****************************************************************************/ + +void up_irq_restore(irqstate_t pri) +{ + __asm__ volatile("csrw %0, %1" :: "i"(NR5_EPIC_PRIMASK), "r"(pri)); +} diff --git a/arch/risc-v/src/nr5m100/nr5_irq_dispatch.c b/arch/risc-v/src/nr5m100/nr5_irq_dispatch.c new file mode 100644 index 00000000000..5271d51abf3 --- /dev/null +++ b/arch/risc-v/src/nr5m100/nr5_irq_dispatch.c @@ -0,0 +1,155 @@ +/************************************************************************************ + * arch/risc-v/src/nr5m100/nr5_irq_dispatch.c + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Modified for RISC-V: + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "group/group.h" + +/**************************************************************************** + * Extern Functions + ****************************************************************************/ + +int up_lsbenc(int); + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +volatile uint32_t * g_current_regs; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * irq_dispatch_all + ****************************************************************************/ + +uint32_t * irq_dispatch_all(uint32_t *regs, uint32_t irqmask) +{ + int next, mask; + mask = irqmask & 0xFFFF; + + board_autoled_on(LED_INIRQ); + +#ifdef CONFIG_SUPPRESS_INTERRUPTS + PANIC(); +#else + /* Current regs non-zero indicates that we are processing an interrupt; + * g_current_regs is also used to manage interrupt level context switches. + * + * Nested interrupts are not supported + */ + + DEBUGASSERT(g_current_regs == NULL); + g_current_regs = regs; + + /* Get ordinal index of interrupt number from mask */ + + next = up_lsbenc(mask); + while (next != -1) + { + /* Deliver the IRQ */ + + irq_dispatch(next, regs); + + /* Clear the IRQ from the mask */ + + mask &= !(1 << next); + next = up_lsbenc(mask); + +#if defined(CONFIG_ARCH_FPU) || defined(CONFIG_ARCH_ADDRENV) + /* Check for a context switch. If a context switch occurred, then + * g_current_regs will have a different value than it did on entry. If an + * interrupt level context switch has occurred, then restore the floating + * point state and the establish the correct address environment before + * returning from the interrupt. + */ + if (regs != g_current_regs) + { +#ifdef CONFIG_ARCH_FPU + /* Restore floating point registers */ + + up_restorefpu((uint32_t *)g_current_regs); +#endif + +#ifdef CONFIG_ARCH_ADDRENV + /* Make sure that the address environment for the previously + * running task is closed down gracefully (data caches dump, + * MMU flushed) and set up the address environment for the new + * thread at the head of the ready-to-run list. + */ + + (void)group_addrenv(NULL); +#endif + } +#endif + } + +#endif + + /* If a context switch occurred while processing the interrupt then + * g_current_regs may have change value. If we return any value different + * from the input regs, then the lower level will know that a context + * switch occurred during interrupt processing. + */ + + regs = (uint32_t *) g_current_regs; + g_current_regs = NULL; + + board_autoled_off(LED_INIRQ); + + /* Return the stack pointer */ + + return regs; +} + diff --git a/arch/risc-v/src/nr5m100/nr5_lowputc.c b/arch/risc-v/src/nr5m100/nr5_lowputc.c new file mode 100644 index 00000000000..87a665be517 --- /dev/null +++ b/arch/risc-v/src/nr5m100/nr5_lowputc.c @@ -0,0 +1,181 @@ +/************************************************************************** + * arch/risc-v/src/nr5m100/nr5_lowputc.c + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Modified for RISC-V: + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************/ + +/************************************************************************** + * Included Files + **************************************************************************/ + +#include + +#include + +#include + +#include "up_internal.h" +#include "up_arch.h" + +#include "nr5_config.h" +#include "nr5.h" + +/************************************************************************** + * Pre-processor Definitions + **************************************************************************/ + +/* Select UART parameters for the selected console */ + +#ifdef HAVE_SERIAL_CONSOLE +# if defined(CONFIG_UART1_SERIAL_CONSOLE) +# define NR5_CONSOLE_BASE NR5_UART1_BASE +# define NR5_CONSOLE_BAUD CONFIG_UART1_BAUD +# define NR5_CONSOLE_BITS CONFIG_UART1_BITS +# define NR5_CONSOLE_PARITY CONFIG_UART1_PARITY +# define NR5_CONSOLE_2STOP CONFIG_UART1_2STOP +# define NR5_CONSOLE_TX GPIO_UART1_TX +# define NR5_CONSOLE_RX GPIO_UART1_RX +# define HAVE_UART +# elif defined(CONFIG_UART2_SERIAL_CONSOLE) +# define NR5_CONSOLE_BASE NR5_UART1_BASE +# define NR5_CONSOLE_BAUD CONFIG_UART1_BAUD +# define NR5_CONSOLE_BITS CONFIG_UART1_BITS +# define NR5_CONSOLE_PARITY CONFIG_UART1_PARITY +# define NR5_CONSOLE_2STOP CONFIG_UART1_2STOP +# define NR5_CONSOLE_TX GPIO_UART1_TX +# define NR5_CONSOLE_RX GPIO_UART1_RX +# define HAVE_UART +# endif + + /* Calculate UART BAUD rate divider */ + +# if defined(CONFIG_NR5_NR5M1XX) + + /* Baud rate for standard UART: + * + * In case of oversampling by 16, the equation is: + * UARTDIV = fCK / 32 / baud + */ + +# define NR5_UARTDIV \ + ((NR5_HCLK_FREQUENCY >> 5) / NR5_CONSOLE_BAUD) + +# endif /* CONFIG_NR5_NR5M1XX */ +#endif /* HAVE_CONSOLE */ + +/************************************************************************** + * Private Types + **************************************************************************/ + +/************************************************************************** + * Private Function Prototypes + **************************************************************************/ + +/************************************************************************** + * Global Variables + **************************************************************************/ + +/************************************************************************** + * Private Variables + **************************************************************************/ + +/************************************************************************** + * Private Functions + **************************************************************************/ + +/************************************************************************** + * Public Functions + **************************************************************************/ + +/************************************************************************** + * Name: up_lowputc + * + * Description: + * Output one byte on the serial console + * + **************************************************************************/ + +void up_lowputc(char ch) +{ +#ifdef HAVE_SERIAL_CONSOLE + /* Wait until the TX data register is empty */ + + while ((getreg32(NR5_CONSOLE_BASE + NR5_UART_STATUS_REG_OFFSET) & NR5_UART_STATUS_TX_EMPTY) == 0) + ; + + /* Then send the character */ + + putreg32((uint32_t)ch, NR5_CONSOLE_BASE + NR5_UART_TX_REG_OFFSET); + +#endif /* HAVE_CONSOLE */ +} + +/************************************************************************** + * Name: nr5_lowsetup + * + * Description: + * This performs basic initialization of the UART used for the serial + * console. Its purpose is to get the console output availabe as soon + * as possible. + * + **************************************************************************/ + +#if defined(CONFIG_NR5_NR5M1XX) + +void nr5_lowsetup(void) +{ +#if defined(HAVE_UART) + + /* Enable and configure the selected console device */ + +#if defined(HAVE_SERIAL_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) + + /* Configure the UART Baud Rate */ + + putreg32(NR5_UARTDIV, NR5_CONSOLE_BASE + NR5_UART_BAUD_RATE_OFFSET); + + /* Configure the RX interrupt */ + + putreg32(NR5_UART_CTRL_ENABLE_RX_IRQ, NR5_CONSOLE_BASE + NR5_UART_CTRL_REG_OFFSET); + +#endif /* HAVE_SERIAL_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */ +#endif /* HAVE_UART */ +} + +#else +# error "Unsupported NR5 chip" +#endif diff --git a/arch/risc-v/src/nr5m100/nr5_lowputc.h b/arch/risc-v/src/nr5m100/nr5_lowputc.h new file mode 100644 index 00000000000..4ab7ce08374 --- /dev/null +++ b/arch/risc-v/src/nr5m100/nr5_lowputc.h @@ -0,0 +1,79 @@ +/************************************************************************************ + * arch/risc-v/src/nr5m100/nr5_lowputc.h + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_NR5M100_NR5_LOWPUTC_H +#define __ARCH_RISCV_SRC_NR5M100_NR5_LOWPUTC_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Name: nr5_lowsetup + * + * Description: + * Called at the very beginning of __nr5_init. Performs low level initialization + * of serial console. + * + ************************************************************************************/ + +EXTERN void nr5_lowsetup(void); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_RISCV_SRC_NR5M100_NR5_LOWPUTC_H */ + diff --git a/arch/risc-v/src/nr5m100/nr5_memorymap.h b/arch/risc-v/src/nr5m100/nr5_memorymap.h new file mode 100644 index 00000000000..8ebcfedd685 --- /dev/null +++ b/arch/risc-v/src/nr5m100/nr5_memorymap.h @@ -0,0 +1,43 @@ +/************************************************************************************ + * arch/risc-v/src/nr5m100/nr5_memorymap.h + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef _ARCH_RISCV_SRC_NR5M100_NR5_MEMORYMAP_H +#define _ARCH_RISCV_SRC_NR5M100_NR5_MEMORYMAP_H + +//#include + +#ifdef CONFIG_NR5_NR5MXXX +#include "chip/nr5m1xx_memorymap.h" +#endif + +#endif /* _ARCH_RISCV_SRC_NR5M100_NR5_MEMORYMAP_H */ + diff --git a/arch/risc-v/src/nr5m100/nr5_serial.c b/arch/risc-v/src/nr5m100/nr5_serial.c new file mode 100644 index 00000000000..44a4cd5d9f0 --- /dev/null +++ b/arch/risc-v/src/nr5m100/nr5_serial.c @@ -0,0 +1,888 @@ +/**************************************************************************** + * arch/risc-v/src/nr5m100/nr5_serial.c + * + * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Modified for RISC-V: + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_SERIAL_TERMIOS +# include +#endif + +#include +#include +#include + +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "nr5_config.h" +#include "chip.h" +#include "nr5.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* If we are not using the serial driver for the console, then we still must + * provide some minimal implementation of up_putc. + */ + +#ifdef USE_SERIALDRIVER + +/* Which UART with be tty0/console and which tty1? The console will always + * be ttyS0. If there is no console then will use the lowest numbered UART. + */ + +#ifdef HAVE_SERIAL_CONSOLE +# if defined(CONFIG_UART1_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart1port /* UART1 is console */ +# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */ +# undef TTYS1_DEV /* No ttyS1 */ +# define SERIAL_CONSOLE 1 +# else +# error "I'm confused... Do we have a serial console or not?" +# endif +#else +# undef CONSOLE_DEV /* No console */ +# undef CONFIG_UART1_SERIAL_CONSOLE +# if defined(CONFIG_NR5_UART1) +# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */ +# undef TTYS1_DEV /* No ttyS1 */ +# define SERIAL_CONSOLE 1 +# else +# undef TTYS0_DEV +# undef TTYS1_DEV +# endif +#endif + +/* Common initialization logic will not not know that the all of the UARTs + * have been disabled. So, as a result, we may still have to provide + * stub implementations of up_earlyserialinit(), up_serialinit(), and + * up_putc(). + */ + +#ifdef HAVE_UART_DEVICE + +/* These values describe the set of enabled interrupts */ + +#define IE_RX (1 << 0) +#define IE_TX (1 << 1) + +#define RX_ENABLED(im) (((im) & IE_RX) != 0) +#define TX_ENABLED(im) (((im) & IE_TX) != 0) + +#define ENABLE_RX(im) do { (im) |= IE_RX; } while (0) +#define ENABLE_TX(im) do { (im) |= IE_TX; } while (0) + +#define DISABLE_RX(im) do { (im) &= ~IE_RX; } while (0) +#define DISABLE_TX(im) do { (im) &= ~IE_TX; } while (0) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct up_dev_s +{ + uintptr_t uartbase; /* Base address of UART registers */ + uint32_t baud; /* Configured baud */ + uint8_t irqrx; /* RX IRQ associated with this UART (for enable) */ + uint8_t irqtx; /* TX IRQ associated with this UART (for enable) */ + uint8_t irqprio; /* Interrupt priority */ + uint8_t im; /* Interrupt mask state */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Low-level helpers */ + +static inline uint32_t up_serialin(struct up_dev_s *priv, int offset); +static inline void up_serialout(struct up_dev_s *priv, int offset, uint32_t value); +static void up_restoreuartint(struct uart_dev_s *dev, uint8_t im); +static void up_disableuartint(struct uart_dev_s *dev, uint8_t *im); + +/* Serial driver methods */ + +static int up_setup(struct uart_dev_s *dev); +static void up_shutdown(struct uart_dev_s *dev); +static int up_attach(struct uart_dev_s *dev); +static void up_detach(struct uart_dev_s *dev); +static int up_interrupt(int irq, void *context); +static int up_ioctl(struct file *filep, int cmd, unsigned long arg); +static int up_receive(struct uart_dev_s *dev, uint32_t *status); +static void up_rxint(struct uart_dev_s *dev, bool enable); +static bool up_rxavailable(struct uart_dev_s *dev); +static void up_send(struct uart_dev_s *dev, int ch); +static void up_txint(struct uart_dev_s *dev, bool enable); +static bool up_txready(struct uart_dev_s *dev); +static bool up_txempty(struct uart_dev_s *dev); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct uart_ops_s g_uart_ops = +{ + .setup = up_setup, + .shutdown = up_shutdown, + .attach = up_attach, + .detach = up_detach, + .ioctl = up_ioctl, + .receive = up_receive, + .rxint = up_rxint, + .rxavailable = up_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = NULL, +#endif + .send = up_send, + .txint = up_txint, + .txready = up_txready, + .txempty = up_txempty, +}; + +/* I/O buffers */ + +#ifdef CONFIG_NR5_UART1 +static char g_uart1rxbuffer[CONFIG_UART1_RXBUFSIZE]; +static char g_uart1txbuffer[CONFIG_UART1_TXBUFSIZE]; +#endif + +/* This describes the state of the NR5 UART1 port. */ + +#ifdef CONFIG_NR5_UART1 +#ifndef CONFIG_NR5_UART1PRIO +# define CONFIG_NR5_UART1PRIO 4 +#endif + +static struct up_dev_s g_uart1priv = +{ + .uartbase = NR5_UART1_BASE, + .baud = CONFIG_UART1_BAUD, + .irqrx = NR5_IRQ_UART1_RX, + .irqtx = NR5_IRQ_UART1_TX, + .irqprio = CONFIG_NR5_UART1PRIO, +}; + +static uart_dev_t g_uart1port = +{ +#if SERIAL_CONSOLE == 1 + .isconsole = 1, +#endif + .recv = + { + .size = CONFIG_UART1_RXBUFSIZE, + .buffer = g_uart1rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART1_TXBUFSIZE, + .buffer = g_uart1txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart1priv, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_serialin + ****************************************************************************/ + +static inline uint32_t up_serialin(struct up_dev_s *priv, int offset) +{ + return getreg32(priv->uartbase + offset); +} + +/**************************************************************************** + * Name: up_serialout + ****************************************************************************/ + +static inline void up_serialout(struct up_dev_s *priv, int offset, uint32_t value) +{ + putreg32(value, priv->uartbase + offset); +} + +/**************************************************************************** + * Name: up_restoreuartint + ****************************************************************************/ + +static void up_restoreuartint(struct uart_dev_s *dev, uint8_t im) +{ + irqstate_t flags; + + /* Re-enable/re-disable interrupts corresponding to the state of bits in im */ + + flags = enter_critical_section(); + up_rxint(dev, RX_ENABLED(im)); + up_txint(dev, TX_ENABLED(im)); + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: up_disableuartint + ****************************************************************************/ + +static void up_disableuartint(struct uart_dev_s *dev, uint8_t *im) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + irqstate_t flags; + + flags = enter_critical_section(); + if (im) + { + *im = priv->im; + } + up_restoreuartint(dev, 0); + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: up_setup + * + * Description: + * Configure the UART baud, bits, parity, etc. This method is called the + * first time that the serial port is opened. + * + ****************************************************************************/ + +static int up_setup(struct uart_dev_s *dev) +{ +#ifndef CONFIG_SUPPRESS_UART_CONFIG +// struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + + /* Configure the UART as an RS-232 UART */ + + //pic32mx_uartconfigure(priv->uartbase, priv->baud, priv->parity, + // priv->bits, priv->stopbits2); +#endif + +#ifdef CONFIG_ARCH_IRQPRIO + /* Set up the interrupt priority */ + + up_prioritize_irq(priv->irq, priv->irqprio); +#endif + + return OK; +} + +/**************************************************************************** + * Name: up_shutdown + * + * Description: + * Disable the UART. This method is called when the serial + * port is closed + * + ****************************************************************************/ + +static void up_shutdown(struct uart_dev_s *dev) +{ + //struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + + /* Disable interrupts */ + + up_disableuartint(dev, NULL); + + /* Reset hardware and disable Rx and Tx */ + + //nr5_uartreset(priv->uartbase); +} + +/**************************************************************************** + * Name: up_attach + * + * Description: + * Configure the UART to operation in interrupt driven mode. This method is + * called when the serial port is opened. Normally, this is just after the + * the setup() method is called, however, the serial console may operate in + * a non-interrupt driven mode during the boot phase. + * + * RX and TX interrupts are not enabled by the attach method (unless the + * hardware supports multiple levels of interrupt enabling). The RX and TX + * interrupts are not enabled until the txint() and rxint() methods are called. + * + ****************************************************************************/ + +static int up_attach(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + + /* Initialize interrupt generation on the peripheral */ + + up_serialout(priv, NR5_UART_CTRL_REG_OFFSET, IE_RX | IE_TX); + irq_attach(priv->irqrx, up_interrupt); + irq_attach(priv->irqtx, up_interrupt); + + /* Indicate no interrupts active in EPIC */ + + priv->im = 0; + + return OK; +} + +/**************************************************************************** + * Name: up_detach + * + * Description: + * Detach UART interrupts. This method is called when the serial port is + * closed normally just before the shutdown method is called. The exception + * is the serial console which is never shutdown. + * + ****************************************************************************/ + +static void up_detach(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + + /* Disable interrupts */ + + up_disableuartint(dev, NULL); + + /* Disable interrupt generation on the peripheral */ + + up_serialout(priv, NR5_UART_CTRL_REG_OFFSET, 0); + + /* Detach from the interrupt */ + + irq_detach(priv->irqrx); + irq_detach(priv->irqtx); +} + +/**************************************************************************** + * Name: up_interrupt + * + * Description: + * This is the UART interrupt handler. It will be invoked when an + * interrupt received on the 'irq' It should call uart_transmitchars or + * uart_receivechar to perform the appropriate data transfers. The + * interrupt handling logic must be able to map the 'irq' number into the + * approprite uart_dev_s structure in order to call these functions. + * + ****************************************************************************/ + +static int up_interrupt(int irq, void *context) +{ + struct uart_dev_s *dev = NULL; + struct up_dev_s *priv; + int passes; + uint32_t status; + bool handled; + +#ifdef CONFIG_NR5_UART1 + if (g_uart1priv.irqrx == irq || g_uart1priv.irqtx == irq) + { + dev = &g_uart1port; + } + else +#endif +#ifdef CONFIG_NR5_UART2 + if (g_uart2priv.irqrx == irq || g_uart2priv.irqtx == irq) + { + dev = &g_uart2port; + } + else +#endif + { + PANIC(); + } + priv = (struct up_dev_s *)dev->priv; + DEBUGASSERT(priv); + + /* Loop until there are no characters to be transferred or, + * until we have been looping for a long time. + */ + + handled = true; + for (passes = 0; passes < 256 && handled; passes++) + { + handled = false; + + status = up_serialin(priv, NR5_UART_STATUS_REG_OFFSET); + + /* Handle incoming, received bytes. The RX FIFO is configured to + * interrupt when the RX FIFO is 75% full (that is 6 of 8 for 8-deep + * FIFOs or 3 of 4 for 4-deep FIFOS. + */ + + if (status & NR5_UART_RX_IRQ_PENDING) + { + /* Process incoming bytes */ + + uart_recvchars(dev); + handled = true; + } + + /* Handle outgoing, transmit bytes The RT FIFO is configured to + * interrupt only when the TX FIFO is empty. There are not many + * options on trigger TX interrupts. The FIFO-not-full might generate + * better through-put but with a higher interrupt rate. FIFO-empty should + * lower the interrupt rate but result in a burstier output. If + * you change this, You will probably need to change the conditions for + * clearing the pending TX interrupt below. + * + * NOTE: When I tried using the FIFO-not-full interrupt trigger, I + * had either lost interrupts, or else a window where I might get + * infinite interrupts. The problem is that there is a race condition + * with trying to clearing the pending interrupt based on the FIFO + * full condition. + */ + + if (status & NR5_UART_TX_IRQ_PENDING) + { + /* Process outgoing bytes */ + + uart_xmitchars(dev); + handled = true; + } + } + + return OK; +} + +/**************************************************************************** + * Name: up_ioctl + * + * Description: + * All ioctl calls will be routed through this method + * + ****************************************************************************/ + +static int up_ioctl(struct file *filep, int cmd, unsigned long arg) +{ +#ifdef CONFIG_SERIAL_TERMIOS + struct inode *inode; + struct uart_dev_s *dev; + struct up_dev_s *priv; + int ret = OK; + + DEBUGASSERT(filep, filep->f_inode); + inode = filep->f_inode; + dev = inode->i_private; + + DEBUGASSERT(dev, dev->priv); + priv = (struct up_dev_s *)dev->priv; + + switch (cmd) + { + case xxx: /* Add commands here */ + break; + + case TCGETS: + { + struct termios *termiosp = (struct termios *)arg; + + if (!termiosp) + { + ret = -EINVAL; + break; + } + + /* TODO: Other termios fields are not yet returned. + * Note that only cfsetospeed is not necessary because we have + * knowledge that only one speed is supported. + */ + + cfsetispeed(termiosp, priv->baud); + } + break; + + case TCSETS: + { + struct termios *termiosp = (struct termios *)arg; + + if (!termiosp) + { + ret = -EINVAL; + break; + } + + /* TODO: Handle other termios settings. + * Note that only cfgetispeed is used besued we have knowledge + * that only one speed is supported. + */ + + priv->baud = cfgetispeed(termiosp); + //pic32mx_uartconfigure(priv->uartbase, priv->baud, priv->parity, + // priv->bits, priv->stopbits2); + } + break; + + default: + ret = -ENOTTY; + break; + } + + return ret; +#else + return -ENOTTY; +#endif +} + +/**************************************************************************** + * Name: up_receive + * + * Description: + * Called (usually) from the interrupt level to receive one + * character from the UART. Error bits associated with the + * receipt are provided in the return 'status'. + * + ****************************************************************************/ + +static int up_receive(struct uart_dev_s *dev, uint32_t *status) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + + /* Return status information */ + + if (status) + { + *status = 0; /* We are not yet tracking serial errors */ + } + + /* Then return the actual received byte */ + + return (int)(up_serialin(priv, NR5_UART_RX_REG_OFFSET)); +} + +/**************************************************************************** + * Name: up_rxint + * + * Description: + * Call to enable or disable RX interrupts + * + ****************************************************************************/ + +static void up_rxint(struct uart_dev_s *dev, bool enable) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + irqstate_t flags; + uint8_t im; + + flags = enter_critical_section(); + im = priv->im; + if (enable) + { + /* Receive an interrupt when their is anything in the Rx data register (or an Rx + * timeout occurs). + */ + +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + up_enable_irq(priv->irqrx); + ENABLE_RX(im); +#endif + } + else + { + up_disable_irq(priv->irqrx); + DISABLE_RX(im); + } + priv->im = im; + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: up_rxavailable + * + * Description: + * Return true if the receive register is not empty + * + ****************************************************************************/ + +static bool up_rxavailable(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + + /* Return true is data is available in the receive data buffer */ + + return (up_serialin(priv, NR5_UART_STATUS_REG_OFFSET) & NR5_UART_STATUS_RX_AVAIL) != 0; +} + +/**************************************************************************** + * Name: up_send + * + * Description: + * This method will send one byte on the UART. + * + ****************************************************************************/ + +static void up_send(struct uart_dev_s *dev, int ch) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + up_serialout(priv, NR5_UART_TX_REG_OFFSET, (uint32_t)ch); +} + +/**************************************************************************** + * Name: up_txint + * + * Description: + * Call to enable or disable TX interrupts + * + ****************************************************************************/ + +static void up_txint(struct uart_dev_s *dev, bool enable) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + irqstate_t flags; + uint8_t im; + + flags = enter_critical_section(); + im = priv->im; + if (enable) + { + /* Enable the TX interrupt */ + +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + up_enable_irq(priv->irqtx); + ENABLE_TX(im); + + /* Fake a TX interrupt here by just calling uart_xmitchars() with + * interrupts disabled (note this may recurse). + */ + + uart_xmitchars(dev); +#endif + } + else + { + /* Disable the TX interrupt */ + + up_disable_irq(priv->irqtx); + DISABLE_TX(im); + } + + priv->im = im; + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: up_txready + * + * Description: + * Return true if the tranmsit data register is empty + * + ****************************************************************************/ + +static bool up_txready(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + + /* Return TRUE if the Transmit buffer register is not full */ + + return (up_serialin(priv, NR5_UART_STATUS_REG_OFFSET) & NR5_UART_STATUS_TX_EMPTY) != 0; +} + +/**************************************************************************** + * Name: up_txempty + * + * Description: + * Return true if the tranmsit data register is empty + * + ****************************************************************************/ + +static bool up_txempty(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + + /* Return TRUE if the Transmit shift register is empty */ + + return (up_serialin(priv, NR5_UART_STATUS_REG_OFFSET) & NR5_UART_STATUS_TX_EMPTY) != 0; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_earlyserialinit + * + * Description: + * Performs the low level UART initialization early in debug so that the + * serial console will be available during bootup. This must be called + * before up_serialinit. NOTE: This function depends on GPIO pin + * configuration performed in up_consoleinit() and main clock iniialization + * performed in up_clkinitialize(). + * + ****************************************************************************/ + +void up_earlyserialinit(void) +{ + /* Disable interrupts from all UARTS. The console is enabled in + * nr5_consoleinit(). + */ + + up_disableuartint(&TTYS0_DEV, NULL); +#ifdef TTYS1_DEV + up_disableuartint(&TTYS1_DEV, NULL); +#endif + + /* Configuration whichever one is the console */ + +#ifdef HAVE_SERIAL_CONSOLE + CONSOLE_DEV.isconsole = true; + up_setup(&CONSOLE_DEV); +#endif +} + +/**************************************************************************** + * Name: up_serialinit + * + * Description: + * Register serial console and serial ports. This assumes + * that up_earlyserialinit was called previously. + * + ****************************************************************************/ + +void up_serialinit(void) +{ + /* Register the console */ + +#ifdef HAVE_SERIAL_CONSOLE + (void)uart_register("/dev/console", &CONSOLE_DEV); +#endif + + /* Register all UARTs */ + + (void)uart_register("/dev/ttyS0", &TTYS0_DEV); +#ifdef TTYS1_DEV + (void)uart_register("/dev/ttyS1", &TTYS1_DEV); +#endif +} + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +int up_putc(int ch) +{ +#ifdef HAVE_SERIAL_CONSOLE + struct uart_dev_s *dev = (struct uart_dev_s *)&CONSOLE_DEV; + uint8_t imr; + + up_disableuartint(dev, &imr); + + /* Check for LF */ + + if (ch == '\n') + { + /* Add CR */ + + up_lowputc('\r'); + } + + up_lowputc(ch); + up_restoreuartint(dev, imr); +#endif + return ch; +} + +/**************************************************************************** + * Name: up_earlyserialinit, up_serialinit, and up_putc + * + * Description: + * stubs that may be needed. These stubs would be used if all UARTs are + * disabled. In that case, the logic in common/up_initialize() is not + * smart enough to know that there are not UARTs and will still expect + * these interfaces to be provided. + * + ****************************************************************************/ +#else /* HAVE_UART_DEVICE */ +void up_earlyserialinit(void) +{ +} + +void up_serialinit(void) +{ +} + +int up_putc(int ch) +{ + return ch; +} + +#endif /* HAVE_UART_DEVICE */ +#else /* USE_SERIALDRIVER */ + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +int up_putc(int ch) +{ +#ifdef HAVE_SERIAL_CONSOLE + /* Check for LF */ + + if (ch == '\n') + { + /* Add CR */ + + up_lowputc('\r'); + } + + up_lowputc(ch); +#endif + return ch; +} + +#endif /* USE_SERIALDRIVER */ + diff --git a/arch/risc-v/src/nr5m100/nr5_timer.c b/arch/risc-v/src/nr5m100/nr5_timer.c new file mode 100644 index 00000000000..132cb9e9849 --- /dev/null +++ b/arch/risc-v/src/nr5m100/nr5_timer.c @@ -0,0 +1,512 @@ +/************************************************************************************ + * arm/risc-v/src/nr5m100/nr5_timer.c + * + * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Modified for RISC-V: + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include + +#include +#include +#include +#include +#include + +#include "chip.h" +#include "up_internal.h" +#include "up_arch.h" + +#include "nr5.h" + +/************************************************************************************ + * Private Types + ************************************************************************************/ +/* Configuration ********************************************************************/ + +/* This module then only compiles if there are enabled timers that are not intended for + * some other purpose. + */ + +#if defined(CONFIG_NR5_TIMER0) || defined(CONFIG_NR5_TIMER1) || defined(CONFIG_NR5_TIMER2) || \ + defined(CONFIG_NR5_TIMER3) || defined(CONFIG_NR5_TIMER4) || defined(CONFIG_NR5_TIMER5) + +/************************************************************************************ + * Private Types + ************************************************************************************/ + +/* Timer Device Structure */ + +struct nr5_timer_priv_s +{ + struct nr5_timer_ops_s *ops; + nr5_timer_mode_t mode; + uint32_t base; /* TIMERn base address */ +}; + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/* Get a 16-bit register value by offset */ + +static inline uint16_t nr5_getreg16(FAR struct nr5_timer_dev_s *dev, + uint8_t offset) +{ + uint16_t *p16 = (uint16_t *) (((struct nr5_timer_priv_s *)dev)->base + offset); + return *p16; +} + +/* Put a 16-bit register value by offset */ + +static inline void nr5_putreg16(FAR struct nr5_timer_dev_s *dev, uint8_t offset, + uint16_t value) +{ + uint16_t *p16 = (uint16_t *) (((struct nr5_timer_priv_s *)dev)->base + offset); + *p16 = value; +} + +/* Modify a 16-bit register value by offset */ + +static inline void nr5_modifyreg16(FAR struct nr5_timer_dev_s *dev, + uint8_t offset, uint16_t clearbits, + uint16_t setbits) +{ + modifyreg16(((struct nr5_timer_priv_s *)dev)->base + offset, clearbits, setbits); +} + +/* Clear the TAR counter */ + +static void nr5_timer_clear_counter(FAR struct nr5_timer_dev_s *dev) +{ + uint16_t val = nr5_getreg16(dev, NR5_TIMERA_TACTL_OFFSET); + val |= TIMERA_TACTL_TACLR; + nr5_putreg16(dev, NR5_TIMERA_TACTL_OFFSET, val); +} + +static void nr5_timer_enable(FAR struct nr5_timer_dev_s *dev) +{ + uint16_t val = nr5_getreg16(dev, NR5_BTIM_CR1_OFFSET); + nr5_timer_clear_counter(dev); + val |= ATIM_CR1_CEN; + nr5_putreg16(dev, NR5_BTIM_CR1_OFFSET, val); +} + +/* Disable the timer by setting the mode to STOP */ + +static void nr5_timer_disable(FAR struct nr5_timer_dev_s *dev) +{ + uint16_t val = nr5_getreg16(dev, NR5_TIMERA_TACTL_OFFSET); + val &= ~TIMERA_TACTL_MC_MASK; + nr5_putreg16(dev, NR5_TIMERA_TACTL_OFFSET, val); +} + +/* Reset timer into system default state, but do not affect output/input pins */ + +static void nr5_timer_reset(FAR struct nr5_timer_dev_s *dev) +{ + ((struct nr5_timer_priv_s *)dev)->mode = NR5_TIMER_MODE_DISABLED; + nr5_timer_disable(dev); +} + +/************************************************************************************ + * Basic Functions + ************************************************************************************/ + +static int nr5_timer_setclock(FAR struct nr5_timer_dev_s *dev, uint32_t freq) +{ + int prescaler; + + ASSERT(dev); + + /* Disable Timer? */ + + if (freq == 0) + { + nr5_timer_disable(dev); + return 0; + } + +#if NR5_NATIM > 0 + if (((struct nr5_timer_priv_s *)dev)->base == NR5_TIM1_BASE || + ((struct nr5_timer_priv_s *)dev)->base == NR5_TIM8_BASE) + { + prescaler = NR5_TIM18_FREQUENCY / freq; + } + else +#endif + { + prescaler = NR5_TIM27_FREQUENCY / freq; + } + + /* We need to decrement value for '1', but only, if we are allowed to + * not to cause underflow. Check for overflow. + */ + + if (prescaler > 0) + { + prescaler--; + } + + if (prescaler > 0xffff) + { + prescaler = 0xffff; + } + + nr5_putreg16(dev, NR5_BTIM_PSC_OFFSET, prescaler); + nr5_timer_enable(dev); + + return prescaler; +} + +static void nr5_timer_setperiod(FAR struct nr5_timer_dev_s *dev, + uint32_t period) +{ + ASSERT(dev); + nr5_putreg32(dev, NR5_BTIM_ARR_OFFSET, period); +} + +static int nr5_timer_setisr(FAR struct nr5_timer_dev_s *dev, + int (*handler)(int irq, void *context), + int source) +{ + int vectorno; + + ASSERT(dev); + ASSERT(source == 0); + + switch (((struct nr5_timer_priv_s *)dev)->base) + { +#ifdef CONFIG_NR5_TIM2 + case NR5_TIM2_BASE: + vectorno = NR5_IRQ_TIM2; + break; +#endif +#ifdef CONFIG_NR5_TIM3 + case NR5_TIM3_BASE: + vectorno = NR5_IRQ_TIM3; + break; +#endif +#ifdef CONFIG_NR5_TIM4 + case NR5_TIM4_BASE: + vectorno = NR5_IRQ_TIM4; + break; +#endif +#ifdef CONFIG_NR5_TIM5 + case NR5_TIM5_BASE: + vectorno = NR5_IRQ_TIM5; + break; +#endif +#if NR5_NBTIM > 0 +#ifdef CONFIG_NR5_TIM6 + case NR5_TIM6_BASE: + vectorno = NR5_IRQ_TIM6; + break; +#endif +#endif +#if NR5_NBTIM > 1 +#ifdef CONFIG_NR5_TIM7 + case NR5_TIM7_BASE: + vectorno = NR5_IRQ_TIM7; + break; +#endif +#endif +#if NR5_NATIM > 0 + /* TODO: add support for multiple sources and callbacks */ + +#ifdef CONFIG_NR5_TIM1 + case NR5_TIM1_BASE: + vectorno = NR5_IRQ_TIM1UP; + break; +#endif +#ifdef CONFIG_NR5_TIM8 + case NR5_TIM8_BASE: + vectorno = NR5_IRQ_TIM8UP; + break; +#endif +#endif + default: + return ERROR; + } + + /* Disable interrupt when callback is removed */ + + if (!handler) + { + up_disable_irq(vectorno); + irq_detach(vectorno); + return OK; + } + + /* Otherwise set callback and enable interrupt */ + + irq_attach(vectorno, handler); + up_enable_irq(vectorno); + +#ifdef CONFIG_ARCH_IRQPRIO + /* Set the interrupt priority */ + + up_prioritize_irq(vectorno, NVIC_SYSH_PRIORITY_DEFAULT); +#endif + + return OK; +} + +static void nr5_timer_enableint(FAR struct nr5_timer_dev_s *dev, int source) +{ + ASSERT(dev); + nr5_modifyreg16(dev, NR5_BTIM_DIER_OFFSET, 0, ATIM_DIER_UIE); +} + +static void nr5_timer_disableint(FAR struct nr5_timer_dev_s *dev, int source) +{ + ASSERT(dev); + nr5_modifyreg16(dev, NR5_BTIM_DIER_OFFSET, ATIM_DIER_UIE, 0); +} + +static void nr5_timer_ackint(FAR struct nr5_timer_dev_s *dev, int source) +{ + nr5_putreg16(dev, NR5_BTIM_SR_OFFSET, ~ATIM_SR_UIF); +} + +/************************************************************************************ + * General Functions + ************************************************************************************/ + +static int nr5_timer_setmode(FAR struct nr5_timer_dev_s *dev, nr5_timer_mode_t mode) +{ + uint16_t val = ATIM_CR1_CEN | ATIM_CR1_ARPE; + + ASSERT(dev); + + /* Decode operational modes */ + + switch (mode & NR5_TIMER_MODE_MASK) + { + case NR5_TIMER_MODE_DISABLED: + val = 0; + break; + + case NR5_TIMER_MODE_DOWN: + val |= ATIM_CR1_DIR; + + case NR5_TIMER_MODE_UP: + break; + + case NR5_TIMER_MODE_UPDOWN: + val |= ATIM_CR1_CENTER1; + // Our default: Interrupts are generated on compare, when counting down + break; + + case NR5_TIMER_MODE_PULSE: + val |= ATIM_CR1_OPM; + break; + + default: return ERROR; + } + + nr5_timer_clear_counter(dev); + nr5_putreg16(dev, NR5_BTIM_CR1_OFFSET, val); + + return OK; +} + +/************************************************************************************ + * Device Structures, Instantiation + ************************************************************************************/ + +struct nr5_timer_ops_s nr5_timer_ops = +{ + .setmode = &nr5_timer_setmode, + .setclock = &nr5_timer_setclock, + .setperiod = &nr5_timer_setperiod, + .setisr = &nr5_timer_setisr, + .enableint = &nr5_timer_enableint, + .disableint = &nr5_timer_disableint, + .ackint = &nr5_timer_ackint +}; + +#ifdef CONFIG_NR5_TIMER1 +struct nr5_timer_priv_s nr5_timer1_priv = +{ + .ops = &nr5_timer_ops, + .mode = NR5_TIMER_MODE_UNUSED, + .base = NR5_TIMER1_BASE, +}; +#endif + +#ifdef CONFIG_NR5_TIMER2 +struct nr5_timer_priv_s nr5_timer2_priv = +{ + .ops = &nr5_timer_ops, + .mode = NR5_TIMER_MODE_UNUSED, + .base = NR5_TIMER2_BASE, +}; +#endif + +#ifdef CONFIG_NR5_TIMER3 +struct nr5_timer_priv_s nr5_timer3_priv = +{ + .ops = &nr5_timer_ops, + .mode = NR5_TIMER_MODE_UNUSED, + .base = NR5_TIMER3_BASE, +}; +#endif + +#ifdef CONFIG_NR5_TIMER4 +struct nr5_timer_priv_s nr5_timer4_priv = +{ + .ops = &nr5_timer_ops, + .mode = NR5_TIMER_MODE_UNUSED, + .base = NR5_TIMER4_BASE, +}; +#endif + +#ifdef CONFIG_NR5_TIMER5 +struct nr5_timer_priv_s nr5_timer5_priv = +{ + .ops = &nr5_timer_ops, + .mode = NR5_TIMER_MODE_UNUSED, + .base = NR5_TIMER5_BASE, +}; +#endif + +/************************************************************************************ + * Public Function - Initialization + ************************************************************************************/ + +FAR struct nr5_timer_dev_s *nr5_timer_init(int timer) +{ + struct nr5_timer_dev_s *dev = NULL; + + /* Get structure pointer */ + + switch (timer) + { +#ifdef CONFIG_NR5_TIMER1 + case 1: + dev = (struct nr5_timer_dev_s *)&nr5_timer1_priv; + break; +#endif +#ifdef CONFIG_NR5_TIMER2 + case 2: + dev = (struct nr5_timer_dev_s *)&nr5_timer2_priv; + break; +#endif +#ifdef CONFIG_NR5_TIMER3 + case 3: + dev = (struct nr5_timer_dev_s *)&nr5_timer3_priv; + break; +#endif +#ifdef CONFIG_NR5_TIMER4 + case 4: + dev = (struct nr5_timer_dev_s *)&nr5_timer4_priv; + break; +#endif +#ifdef CONFIG_NR5_TIMER5 + case 5: + dev = (struct nr5_timer_dev_s *)&nr5_timer5_priv; + break; +#endif + + default: + return NULL; + } + + /* Is device already allocated */ + + if (((struct nr5_timer_priv_s *)dev)->mode != NR5_TIMER_MODE_UNUSED) + { + return NULL; + } + + nr5_timer_reset(dev); + + return dev; +} + +/* TODO: Detach interrupts, and close down all TIM Channels */ + +int nr5_timer_deinit(FAR struct nr5_timer_dev_s * dev) +{ + ASSERT(dev); + + /* Set timer mode to STOP */ + + switch (((struct nr5_timer_priv_s *)dev)->base) + { +#if NR5_NATIM > 0 +#ifdef CONFIG_NR5_TIM1 + case NR5_TIMER1_BASE: + modifyreg32(NR5_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); + break; +#endif +#ifdef CONFIG_NR5_TIM2 + case NR5_TIMER2_BASE: + modifyreg32(NR5_RCC_APB1ENR, RCC_APB1ENR_TIM2EN, 0); + break; +#endif +#ifdef CONFIG_NR5_TIM3 + case NR5_TIMER3_BASE: + modifyreg32(NR5_RCC_APB1ENR, RCC_APB1ENR_TIM3EN, 0); + break; +#endif +#ifdef CONFIG_NR5_TIM4 + case NR5_TIMER4_BASE: + modifyreg32(NR5_RCC_APB1ENR, RCC_APB1ENR_TIM4EN, 0); + break; +#endif +#ifdef CONFIG_NR5_TIM5 + case NR5_TIMER5_BASE: + modifyreg32(NR5_RCC_APB1ENR, RCC_APB1ENR_TIM5EN, 0); + break; +#endif +#endif + + default: + return ERROR; + } + + /* Mark it as free */ + + ((struct nr5_timer_priv_s *)dev)->mode = NR5_TIMER_MODE_UNUSED; + + return OK; +} + +#endif /* defined(CONFIG_NR5_TIM1 || ... || TIM8) */ diff --git a/arch/risc-v/src/nr5m100/nr5_timer.h b/arch/risc-v/src/nr5m100/nr5_timer.h new file mode 100644 index 00000000000..b1c76cc911f --- /dev/null +++ b/arch/risc-v/src/nr5m100/nr5_timer.h @@ -0,0 +1,168 @@ +/************************************************************************************ + * arch/risc-v/src/nr5m100/nr5_timer.h + * + * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Modified for RISC-V: + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_NR5M100_NR5_TIMER_H +#define __ARCH_RISCV_SRC_NR5M100_NR5_TIMER_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "chip/nr5m1xx_timer.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* Helpers **************************************************************************/ + +#define NR5_TIMER_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) +#define NR5_TIMER_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) +#define NR5_TIMER_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) +#define NR5_TIMER_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) +#define NR5_TIMER_SETISR(d,hnd,s) ((d)->ops->setisr(d,hnd,s)) +#define NR5_TIMER_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) +#define NR5_TIMER_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) +#define NR5_TIMER_ACKINT(d,s) ((d)->ops->ackint(d,s)) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/* Timer Modes of Operation */ + +typedef enum +{ + NR5_TIMER_MODE_UNUSED = -1, + + /* One of the following */ + + NR5_TIMER_MODE_DISABLED = 0x0000, + NR5_TIMER_MODE_UP = 0x0001, + NR5_TIMER_MODE_CONTINUOUS = 0x0002, + NR5_TIMER_MODE_UPDOWN = 0x0003, + + /* One of the following */ + + NR5_TIM_MODE_CK_SLOW = 0x0000, + NR5_TIM_MODE_CK_MED = 0x0010, + NR5_TIM_MODE_CK_SYS = 0x0020, + NR5_TIM_MODE_CK_EXT = 0x0030, + +} nr5_timer_mode_t; + +/* Timer Operations */ + +struct nr5_timer_dev_s; + +struct nr5_timer_ops_s +{ + /* Basic Timer Operations */ + + int (*setmode)(FAR struct nr5_timer_dev_s *dev, nr5_timer_mode_t mode); + int (*setclock)(FAR struct nr5_timer_dev_s *dev, uint32_t freq); + void (*setperiod)(FAR struct nr5_timer_dev_s *dev, uint32_t period); + + /* Timer Interrupt Operations */ + + int (*setisr)(FAR struct nr5_timer_dev_s *dev, int (*handler)(int irq, void *context), int source); + void (*enableint)(FAR struct nr5_timer_dev_s *dev, int source); + void (*disableint)(FAR struct nr5_timer_dev_s *dev, int source); + void (*ackint)(FAR struct nr5_timer_dev_s *dev, int source); +}; + +/* Timer Device Structure */ + +struct nr5_timer_dev_s +{ + struct nr5_timer_ops_s *ops; +}; + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/* Power-up timer and get its structure */ + +FAR struct nr5_timer_dev_s *nr5_timer_init(int timer); + +/* Power-down timer, mark it as unused */ + +int nr5_timer_deinit(FAR struct nr5_timer_dev_s * dev); + +/**************************************************************************** + * Name: nr5_timer_initialize + * + * Description: + * Bind the configuration timer to a timer lower half instance and + * register the timer drivers at 'devpath' + * + * Input Parameters: + * devpath - The full path to the timer device. This should be of the form /dev/timer0 + * timer - the timer number. + * + * Returned Values: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_TIMER +int nr5_timer_initialize(FAR const char *devpath, int timer); +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_RISCV_SRC_NR5M100_NR5_TIMER_H */ + diff --git a/arch/risc-v/src/nr5m100/nr5_timerisr.c b/arch/risc-v/src/nr5m100/nr5_timerisr.c new file mode 100644 index 00000000000..5406b0f851b --- /dev/null +++ b/arch/risc-v/src/nr5m100/nr5_timerisr.c @@ -0,0 +1,159 @@ +/**************************************************************************** + * arch/risc-v/src/nr5m100/nr5_timerisr.c + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Modified for RISC-V: + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include "up_arch.h" + +#include "nr5.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The desired timer interrupt frequency is provided by the definition + * CLK_TCK (see include/time.h). CLK_TCK defines the desired number of + * system clock ticks per second. That value is a user configurable setting + * that defaults to 100 (100 ticks per second = 10 MS interval). + * + * The RCC feeds the Cortex System Timer (SysTick) with the AHB clock (HCLK) + * divided by 8. The SysTick can work either with this clock or with the + * Cortex clock (HCLK), configurable in the SysTick Control and Status + * register. + */ + +#ifdef CONFIG_NR5_SYSTICK_SCLK +# define SYSTICK_RELOAD ((NR5_SCLK_FREQUENCY / CLOCKS_PER_SEC) - 1) +#else +# define SYSTICK_RELOAD ((NR5_HCLK_FREQUENCY / CLOCKS_PER_SEC) - 1) +#endif + +/* The size of the reload field is 30 bits. Verify that the reload value + * will fit in the reload register. + */ + +#if SYSTICK_RELOAD > 0x3fffffff +# error SYSTICK_RELOAD exceeds the range of the RELOAD register +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Global Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: up_timerisr + * + * Description: + * The timer ISR will perform a variety of services for various portions + * of the systems. + * + ****************************************************************************/ + +static uint64_t g_systick = 0; + +int up_timerisr(int irq, void *context) +{ + /* Process timer interrupt */ + + sched_process_timer(); + return 0; +} + +/**************************************************************************** + * Function: up_get_systick + * + * Description: + * Returns the current value of systick. + * + ****************************************************************************/ + +uint64_t up_get_systick(void) +{ + return g_systick; +} + +/**************************************************************************** + * Function: up_timer_initialize + * + * Description: + * This function is called during start-up to initialize + * the timer interrupt. + * + ****************************************************************************/ + +void up_timer_initialize(void) +{ + /* Set the SysTick interrupt to the default priority */ + + up_clearpri1bit(NR5_IRQ_SYSTICK); + up_clearpri2bit(NR5_IRQ_SYSTICK); + up_clearpri3bit(NR5_IRQ_SYSTICK); + + /* Attach the timer interrupt vector */ + + (void)irq_attach(NR5_IRQ_SYSTICK, up_timerisr); + + /* Configure and enable SysTick to interrupt at the requested rate */ + + up_setsystick(0x80000000 | SYSTICK_RELOAD); + + /* And enable the timer interrupt */ + + up_enable_irq(NR5_IRQ_SYSTICK); +} + diff --git a/arch/risc-v/src/nr5m100/nr5_uart.c b/arch/risc-v/src/nr5m100/nr5_uart.c new file mode 100644 index 00000000000..4497e70d3e9 --- /dev/null +++ b/arch/risc-v/src/nr5m100/nr5_uart.c @@ -0,0 +1,254 @@ +/************************************************************************************ + * arch/risc-v/src/nr5m100/nr5_uart.c + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#include +#include +#include + +#include "nr5.h" + +#define MAKE_UINT32(a,b,c,d) (((a) << 24) | ((b) << 16) | ((c) << 8) | d) + +struct nr5_uart_buffer_s +{ + uint16_t head; + uint16_t tail; + uint16_t size; + char * buffer; +}; + +struct nr5_uart_regs_s +{ + uint32_t* pBaud; // Data status port + uint32_t* pStat; // Data status port + uint8_t* pTx; // Data TX port + uint8_t* pRx; // Data RX port + uint32_t* pIntCtrl; // Interrupt enable control + int rx_irq; // IRQ number + int tx_irq; // IRQ number +}; + +struct nr5_uart_s +{ + volatile struct nr5_uart_regs_s * regs; + struct nr5_uart_buffer_s * tx_buf; + struct nr5_uart_buffer_s * rx_buf; +}; + +/* +============================================================================== +Static global pointers to access the hardware +============================================================================== +*/ + +#ifdef CONFIG_NR5_HAVE_UART1 +static char g_uart1_rx_buf[CONFIG_NR5_UART_RX_BUF_SIZE]; +static char g_uart1_tx_buf[CONFIG_NR5_UART_TX_BUF_SIZE]; + +static struct nr5_uart_buffer_s g_nr5_uart1_rx_buf = +{ + .head = 0, + .tail = 0, + .size = CONFIG_NR5_UART_RX_BUF_SIZE, + .buffer = g_uart1_rx_buf, +}; + +static struct nr5_uart_buffer_s g_nr5_uart1_tx_buf = +{ + .head = 0, + .tail = 0, + .size = CONFIG_NR5_UART_TX_BUF_SIZE, + .buffer = g_uart1_tx_buf, +}; + +static volatile struct nr5_uart_regs_s g_nr5_uart1_regs = +{ + .pBaud = (uint32_t *) NR5_UART1_BAUD_RATE_REG, + .pStat = (uint32_t *) NR5_UART1_STATUS_REG, + .pRx = (uint8_t *) NR5_UART1_RX_REG, + .pTx = (uint8_t *) NR5_UART1_TX_REG, + .pIntCtrl = (uint32_t *) NR5_UART1_CTRL_REG, + .rx_irq = NR5_IRQ_UART1_RX, + .tx_irq = NR5_IRQ_UART1_TX, +}; + +static struct nr5_uart_s g_nr5_uart1 = +{ + .regs = &g_nr5_uart1_regs, + .rx_buf = &g_nr5_uart1_rx_buf, + .tx_buf = &g_nr5_uart1_tx_buf, +}; +#endif + +/* +============================================================================== +ISR for NanoRisc5 UART RX availalbe. +============================================================================== +*/ +int nr5_uart_rx_isr(int irq_num, void *context) +{ + struct nr5_uart_s *dev = NULL; + char rxdata; + +#ifdef CONFIG_NR5_HAVE_UART1 + if (irq_num == g_nr5_uart1_regs.rx_irq) + { + dev = &g_nr5_uart1; + } +#endif + + /* Process the data */ + + if (dev != NULL) + { + /* Read the RX byte */ + + rxdata = *dev->regs->pRx; + *dev->regs->pTx = rxdata; + + dev->rx_buf->buffer[dev->rx_buf->head++] = rxdata; + if (dev->rx_buf->head == dev->rx_buf->size) + dev->rx_buf->head = 0; + } + + return 0; +} + +/* +============================================================================== +Routine to initialize the HAL layer. Must be called prior to any other +HAL function. +============================================================================== +*/ +void nr5_uart_init(int uart) +{ + volatile struct nr5_uart_s *dev = NULL; + uint32_t cmpval = MAKE_UINT32('F', 'P', 'G', 'A'); + + switch (uart) + { +#ifdef CONFIG_NR5_HAVE_UART1 + case 1: + dev = &g_nr5_uart1; +#endif + } + + // If a device was selected above, then initilize it + // + if (dev != NULL) + { + /* Attache the ISR and enable the IRQ with the EPIC */ + + //irq_attach(dev->regs->rx_irq, &nr5_uart_rx_isr); + //up_enable_irq(dev->regs->rx_irq); + + // Set the baud rate + + if (up_getimpid() == cmpval) + { + *dev->regs->pBaud = 0x0d; + } + + /* Now enable the RX IRQ in the UART peripheral */ + + //*dev->regs->pIntCtrl = NR5_UART_CTRL_ENABLE_RX_IRQ; + } +} + +/* +============================================================================== +Routine to get RX byte from console UART +============================================================================== +*/ +uint8_t nr5_uart_get_rx() +{ + uint8_t rxdata = 0; + + up_disableints(); + if (g_nr5_uart1.rx_buf->head != g_nr5_uart1.rx_buf->tail) + { + struct nr5_uart_buffer_s *pBuf = g_nr5_uart1.rx_buf; + + rxdata = pBuf->buffer[pBuf->tail++]; + if (pBuf->tail == pBuf->size) + pBuf->tail = 0; + } + up_enableints(); + return rxdata; +} + +/* +============================================================================== +Routine to test if RX byte available at console UART +============================================================================== +*/ +int nr5_uart_test_rx_avail() +{ + struct nr5_uart_buffer_s *pBuf = g_nr5_uart1.rx_buf; + int avail; + + up_disableints(); + avail= !(pBuf->head == pBuf->tail); + up_enableints(); + + /* If no RX data available then halt the processor until an interrupt */ + if (!avail) + __asm__ volatile ("wfi"); + + return avail; +} + +/* +============================================================================== +Routine to test if RX byte available at console UART +============================================================================== +*/ +int nr5_uart_test_tx_empty() +{ + return *g_nr5_uart1.regs->pStat & NR5_UART_STATUS_TX_EMPTY; +} + +/* +============================================================================== +Routine to send TX byte to console UART +============================================================================== +*/ +void nr5_uart_put_tx(uint8_t ch) +{ + // Wait for TX to be empty + while (!(*g_nr5_uart1.regs->pStat & NR5_UART_STATUS_TX_EMPTY)) + ; + + // Write to TX + *g_nr5_uart1.regs->pTx = ch; +} + diff --git a/arch/risc-v/src/nr5m100/nr5_uart.h b/arch/risc-v/src/nr5m100/nr5_uart.h new file mode 100644 index 00000000000..7f40dfc0ab3 --- /dev/null +++ b/arch/risc-v/src/nr5m100/nr5_uart.h @@ -0,0 +1,49 @@ +/************************************************************************************ + * arch/riscv/src/nr5/nr5_uart.h + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef _ARCH_RISCV_SRC_NR5_NR5_UART_H +#define _ARCH_RISCV_SRC_NR5_NR5_UART_H + +#include + +#ifdef CONFIG_NR5_NR5M1XX +#include "chip/nr5m1xx_uart.h" +#endif + +void nr5_uart_init(int uart_num); +uint8_t nr5_uart_get_rx(void); +int nr5_uart_test_rx_avail(void); +int nr5_uart_test_tx_empty(void); +void nr5_uart_put_tx(uint8_t ch); + +#endif /* _ARCH_RISCV_SRC_NR5_NR5_UART_H */ + diff --git a/arch/risc-v/src/nr5m100/nr5_vectors.S b/arch/risc-v/src/nr5m100/nr5_vectors.S new file mode 100644 index 00000000000..ea239d91ce7 --- /dev/null +++ b/arch/risc-v/src/nr5m100/nr5_vectors.S @@ -0,0 +1,101 @@ +/************************************************************************************ + * arch/risc-v/src/nr5m100/nr5_vectors.S + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include "nr5_csr.h" + + .section .text.vec + .global __reset_vec + .global __trap_vec + + +/************************************************************************************ + * ADDR: 00h - RESET + ************************************************************************************/ + +__reset_vec: + csrw NR5_EPIC_PRIMASK, 7 + j __start + +/************************************************************************************ + * ADDR: 08h - PRI0 (Illegal Instruction, Bus Error) + ************************************************************************************/ + +__trap_vec: +__pri0_vec: + j irq_handler + nop + +/************************************************************************************ + * ADDR: 10h - PRI1 Interrupt Handler + ************************************************************************************/ + +__pri1_vec: + j irq_handler + nop + +/************************************************************************************ + * ADDR: 18h - PRI2 Interrupt Handler + ************************************************************************************/ + +__pri2_vec: + j irq_handler + nop + +/************************************************************************************ + * ADDR: 20h - PRI3 Interrupt Handler + ************************************************************************************/ + +__pri3_vec: + j irq_handler + nop + +/************************************************************************************ + * ADDR: 28h - PRI4 Interrupt Handler + ************************************************************************************/ + +__pri4_vec: + j irq_handler + nop + +/**************************************************************************** + * Modeline to set vim formatting options for ASM file. For this to work, + * you must enable moeline processing in your ~/.vimrc file with: + * + * ~/.vimrc: + * set modeline + * + * vim: noet:ts=4:sw=4 + ****************************************************************************/ diff --git a/arch/risc-v/src/nr5m100/up_schedulesigaction.c b/arch/risc-v/src/nr5m100/up_schedulesigaction.c new file mode 100644 index 00000000000..d7b8698a56c --- /dev/null +++ b/arch/risc-v/src/nr5m100/up_schedulesigaction.c @@ -0,0 +1,213 @@ +/**************************************************************************** + * arch/risc-v/src/nr5m100/up_schedulesigaction.c + * + * Copyright (C) 2011, 2015-2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Modified for RISC-V: + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "sched/sched.h" +#include "up_internal.h" +#include "up_arch.h" + +#ifndef CONFIG_DISABLE_SIGNALS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_schedule_sigaction + * + * Description: + * This function is called by the OS when one or more + * signal handling actions have been queued for execution. + * The architecture specific code must configure things so + * that the 'igdeliver' callback is executed on the thread + * specified by 'tcb' as soon as possible. + * + * This function may be called from interrupt handling logic. + * + * This operation should not cause the task to be unblocked + * nor should it cause any immediate execution of sigdeliver. + * Typically, a few cases need to be considered: + * + * (1) This function may be called from an interrupt handler + * During interrupt processing, all xcptcontext structures + * should be valid for all tasks. That structure should + * be modified to invoke sigdeliver() either on return + * from (this) interrupt or on some subsequent context + * switch to the recipient task. + * (2) If not in an interrupt handler and the tcb is NOT + * the currently executing task, then again just modify + * the saved xcptcontext structure for the recipient + * task so it will invoke sigdeliver when that task is + * later resumed. + * (3) If not in an interrupt handler and the tcb IS the + * currently executing task -- just call the signal + * handler now. + * + ****************************************************************************/ + +void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver) +{ + irqstate_t flags; + uint32_t int_ctx; + + sinfo("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver); + + /* Make sure that interrupts are disabled */ + + flags = enter_critical_section(); + + /* Refuse to handle nested signal actions */ + + if (!tcb->xcp.sigdeliver) + { + /* First, handle some special cases when the signal is + * being delivered to the currently executing task. + */ + + sinfo("rtcb=0x%p g_current_regs=0x%p\n", + this_task(), g_current_regs); + + if (tcb == this_task()) + { + /* CASE 1: We are not in an interrupt handler and + * a task is signalling itself for some reason. + */ + + if (!g_current_regs) + { + /* In this case just deliver the signal now. */ + + sigdeliver(tcb); + } + + /* CASE 2: We are in an interrupt handler AND the + * interrupted task is the same as the one that + * must receive the signal, then we will have to modify + * the return state as well as the state in the TCB. + * + * Hmmm... there looks like a latent bug here: The following + * logic would fail in the strange case where we are in an + * interrupt handler, the thread is signalling itself, but + * a context switch to another task has occurred so that + * g_current_regs does not refer to the thread of this_task()! + */ + + else + { + /* Save the return EPC and STATUS registers. These will be + * restored by the signal trampoline after the signals have + * been delivered. + */ + + tcb->xcp.sigdeliver = sigdeliver; + tcb->xcp.saved_epc = g_current_regs[REG_EPC]; + + /* Then set up to vector to the trampoline with interrupts + * disabled + */ + + g_current_regs[REG_EPC] = (uint32_t)up_sigdeliver; + int_ctx = g_current_regs[REG_INT_CTX]; + int_ctx &= ~EPIC_STATUS_INT_PRI_MASK; + int_ctx |= EPIC_STATUS_INT_PRI1; + g_current_regs[REG_INT_CTX] = int_ctx; + + /* And make sure that the saved context in the TCB + * is the same as the interrupt return context. + */ + + up_savestate(tcb->xcp.regs); + + sinfo("PC/STATUS Saved: %08x/%08x New: %08x/%08x\n", + tcb->xcp.saved_epc, tcb->xcp.saved_status, + g_current_regs[REG_EPC], g_current_regs[REG_STATUS]); + } + } + + /* Otherwise, we are (1) signaling a task is not running + * from an interrupt handler or (2) we are not in an + * interrupt handler and the running task is signalling + * some non-running task. + */ + + else + { + /* Save the return EPC and STATUS registers. These will be + * restored by the signal trampoline after the signals have + * been delivered. + */ + + tcb->xcp.sigdeliver = sigdeliver; + tcb->xcp.saved_epc = tcb->xcp.regs[REG_EPC]; + tcb->xcp.saved_int_ctx = tcb->xcp.regs[REG_INT_CTX]; + + /* Then set up to vector to the trampoline with interrupts + * disabled + */ + + tcb->xcp.regs[REG_EPC] = (uint32_t)up_sigdeliver; + int_ctx = tcb->xcp.regs[REG_INT_CTX]; + int_ctx &= ~EPIC_STATUS_INT_PRI_MASK; + int_ctx |= EPIC_STATUS_INT_PRI1; + tcb->xcp.regs[REG_INT_CTX] = int_ctx; + + sinfo("PC/STATUS Saved: %08x/%08x New: %08x/%08x\n", + tcb->xcp.saved_epc, tcb->xcp.saved_status, + tcb->xcp.regs[REG_EPC], tcb->xcp.regs[REG_STATUS]); + } + } + + leave_critical_section(flags); +} + +#endif /* !CONFIG_DISABLE_SIGNALS */ diff --git a/arch/risc-v/src/rv32im/Kconfig b/arch/risc-v/src/rv32im/Kconfig new file mode 100644 index 00000000000..9bc4b560f52 --- /dev/null +++ b/arch/risc-v/src/rv32im/Kconfig @@ -0,0 +1,51 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +comment "RV32IM Configuration Options" + +choice + prompt "Toolchain Selection" + default RV32IM_TOOLCHAIN_GNU_RVGW if HOST_WINDOWS + default RV32IM_TOOLCHAIN_GNU_RVGL if !HOST_WINDOWS + +config RV32IM_TOOLCHAIN_GNU_RVGL + bool "Generic GNU RVG toolchain under Linux (or other POSIX environment)" + ---help--- + This option should work for any modern GNU toolchain (GCC 5.2 or newer) + configured for riscv32-unknown-elf. + +config RV32IM_TOOLCHAIN_GNU_RVGW + bool "Generic GNU RVG toolchain under Windows" + depends on HOST_WINDOWS + ---help--- + This option should work for any modern GNU toolchain (GCC 5.2 or newer) + configured for riscv32-unknown-elf. + +endchoice + +config RV32IM_HW_MULDIV + bool "Supports Hardware MUL and DIV" + default n + ---help--- + Specifies if the architecture supports hardware multiply and + hardware division instructions. Selecting this will cause the + generated code to natively use mul / div instructions for any + math operations. + +config RV32IM_SYSTEM_CSRRS_SUPPORT + bool "Supports RV core feature identification via CSRRS opcode" + default n + ---help--- + Specifies if the architecture supports the SYSTEM opcode for reading + Control Status Registers to obtain the RV core option flags. + +config RV32IM_CUSTOM_IRQ_SUPPORT + bool "Has custom implementation for IRQ handling" + default n + ---help--- + Allows overriding the standard IRQ processing as described + in the RISC-V architecture documents. This allows architecture + specific code to support non-standard IRQ processing in the core. + diff --git a/arch/risc-v/src/rv32im/Toolchain.defs b/arch/risc-v/src/rv32im/Toolchain.defs new file mode 100644 index 00000000000..a89cf6cb266 --- /dev/null +++ b/arch/risc-v/src/rv32im/Toolchain.defs @@ -0,0 +1,104 @@ +############################################################################ +# arch/risc-v/src/rv32im/Toolchain.defs +# +# Copyright (C) 2012-2013, 2015 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# modified for RISC-V: +# +# Copyright (C) 2016 Ken Pettit. All rights reserved. +# Author: Ken Pettit +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +# Setup for the selected toolchain + +# +# Handle old-style chip-specific toolchain names in the absence of +# a new-style toolchain specification, force the selection of a single +# toolchain and allow the selected toolchain to be overridden by a +# command-line selection. +# + +ifeq ($(filter y, $(CONFIG_RV32IM_TOOLCHAIN_GNU_RVGL)),y) + CONFIG_RISCV_TOOLCHAIN ?= GNU_RVGL +endif + +ifeq ($(filter y, $(CONFIG_RV32IM_TOOLCHAIN_GNU_RVGW)),y) + CONFIG_RISCV_TOOLCHAIN ?= GNU_RVGW +endif + +# +# Supported toolchains +# +# Each toolchain definition should set: +# +# CROSSDEV The GNU toolchain triple (command prefix) +# ARCROSSDEV If required, an alternative prefix used when +# invoking ar and nm. +# ARCHCPUFLAGS CPU-specific flags selecting the instruction set +# options, etc. +# MAXOPTIMIZATION The maximum optimization level that results in +# reliable code generation. +# + +ifeq ($(CONFIG_DEBUG_CUSTOMOPT),y) + MAXOPTIMIZATION := $(CONFIG_DEBUG_OPTLEVEL) +endif + +# Generic GNU RVG toolchain on OS X, Linux or any typical Posix system + +ifeq ($(CONFIG_RISCV_TOOLCHAIN),GNU_RVGL) + CROSSDEV ?= riscv64-unknown-elf- + ARCROSSDEV ?= riscv64-unknown-elf- +ifeq ($(CONFIG_RV32IM_HW_MULDIV),y) + ARCHCPUFLAGS = -march=RV32IMXcustom -m32 +else + ARCHCPUFLAGS = -march=RV32IXcustom -m32 +endif +endif + +ifeq ($(CONFIG_RISCV_TOOLCHAIN),GNU_RVGW) + CROSSDEV ?= riscv32-unknown-elf- + ARCROSSDEV ?= riscv32-unknown-elf- + ifneq ($(CONFIG_WINDOWS_NATIVE),y) + WINTOOL = y + endif +ifeq ($(CONFIG_RV32IM_HW_MULDIV),y) + ARCHCPUFLAGS = -march=RV32IMXcustom -m32 +else + ARCHCPUFLAGS = -march=RV32IXcustom -m32 +endif +endif + +# Individual tools may limit the optimizatin level but, by default, the +# optimization level will be set to to -Os + +ifeq ($(CONFIG_DEBUG_SYMBOLS),) +MAXOPTIMIZATION ?= -Os +endif + diff --git a/arch/risc-v/src/rv32im/up_assert.c b/arch/risc-v/src/rv32im/up_assert.c new file mode 100644 index 00000000000..a5edaa54d18 --- /dev/null +++ b/arch/risc-v/src/rv32im/up_assert.c @@ -0,0 +1,161 @@ +/**************************************************************************** + * arch/risc-v/src/rv32im/up_assert.c + * + * Copyright (C) 2011-2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include "up_arch.h" +#include "sched/sched.h" +#include "up_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* USB trace dumping */ + +#ifndef CONFIG_USBDEV_TRACE +# undef CONFIG_ARCH_USBDUMP +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: _up_assert + ****************************************************************************/ + +static void _up_assert(int errorcode) noreturn_function; +static void _up_assert(int errorcode) +{ + /* Are we in an interrupt handler or the idle task? */ + + if (g_current_regs || this_task()->pid == 0) + { + (void)up_irq_save(); + for (; ; ) + { +#ifdef CONFIG_ARCH_LEDS + board_autoled_on(LED_PANIC); + up_mdelay(250); + board_autoled_off(LED_PANIC); + up_mdelay(250); +#endif + } + } + else + { + exit(errorcode); + } +} + +/**************************************************************************** + * Name: assert_tracecallback + ****************************************************************************/ + +#ifdef CONFIG_ARCH_USBDUMP +static int usbtrace_syslog(FAR const char *fmt, ...) +{ + va_list ap; + int ret; + + /* Let vsyslog do the real work */ + + va_start(ap, fmt); + ret = vsyslog(LOG_EMERG, fmt, ap); + va_end(ap); + return ret; +} + +static int assert_tracecallback(FAR struct usbtrace_s *trace, FAR void *arg) +{ + usbtrace_trprintf(usbtrace_syslog, trace->event, trace->value); + return 0; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_assert + ****************************************************************************/ + +void up_assert(const uint8_t *filename, int lineno) +{ +#if CONFIG_TASK_NAME_SIZE > 0 && defined(CONFIG_DEBUG_ALERT) + struct tcb_s *rtcb = this_task(); +#endif + + board_autoled_on(LED_ASSERTION); + +#if CONFIG_TASK_NAME_SIZE > 0 + _alert("Assertion failed at file:%s line: %d task: %s\n", + filename, lineno, rtcb->name); +#else + _alert("Assertion failed at file:%s line: %d\n", + filename, lineno); +#endif + + up_dumpstate(); + +#ifdef CONFIG_ARCH_USBDUMP + /* Dump USB trace data */ + + (void)usbtrace_enumerate(assert_tracecallback, NULL); +#endif + +#ifdef CONFIG_BOARD_CRASHDUMP + board_crashdump(up_getsp(), this_task(), filename, lineno); +#endif + + _up_assert(EXIT_FAILURE); +} diff --git a/arch/risc-v/src/rv32im/up_blocktask.c b/arch/risc-v/src/rv32im/up_blocktask.c new file mode 100644 index 00000000000..530797da2b1 --- /dev/null +++ b/arch/risc-v/src/rv32im/up_blocktask.c @@ -0,0 +1,179 @@ +/**************************************************************************** + * arch/risc-v/src/rv32im/up_blocktask.c + * + * Copyright (C) 2011, 2013-2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "sched/sched.h" +#include "group/group.h" +#include "up_internal.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_block_task + * + * Description: + * The currently executing task at the head of + * the ready to run list must be stopped. Save its context + * and move it to the inactive list specified by task_state. + * + * Inputs: + * tcb: Refers to a task in the ready-to-run list (normally + * the task at the head of the list). It most be + * stopped, its context saved and moved into one of the + * waiting task lists. It it was the task at the head + * of the ready-to-run list, then a context to the new + * ready to run task must be performed. + * task_state: Specifies which waiting task list should be + * hold the blocked task TCB. + * + ****************************************************************************/ + +void up_block_task(struct tcb_s *tcb, tstate_t task_state) +{ + struct tcb_s *rtcb = this_task(); + bool switch_needed; + + /* Verify that the context switch can be performed */ + + ASSERT((tcb->task_state >= FIRST_READY_TO_RUN_STATE) && + (tcb->task_state <= LAST_READY_TO_RUN_STATE)); + + /* Remove the tcb task from the ready-to-run list. If we + * are blocking the task at the head of the task list (the + * most likely case), then a context switch to the next + * ready-to-run task is needed. In this case, it should + * also be true that rtcb == tcb. + */ + + switch_needed = sched_removereadytorun(tcb); + + /* Add the task to the specified blocked task list */ + + sched_addblocked(tcb, (tstate_t)task_state); + + /* If there are any pending tasks, then add them to the ready-to-run + * task list now + */ + + if (g_pendingtasks.head) + { + switch_needed |= sched_mergepending(); + } + + /* Now, perform the context switch if one is needed */ + + if (switch_needed) + { + /* Update scheduler parameters */ + + sched_suspend_scheduler(rtcb); + + /* Are we in an interrupt handler? */ + + if (g_current_regs) + { + /* Yes, then we have to do things differently. + * Just copy the g_current_regs into the OLD rtcb. + */ + + up_savestate(rtcb->xcp.regs); + + /* Restore the exception context of the rtcb at the (new) head + * of the ready-to-run task list. + */ + + rtcb = this_task(); + + /* Reset scheduler parameters */ + + sched_resume_scheduler(rtcb); + + /* Then switch contexts. Any necessary address environment + * changes will be made when the interrupt returns. + */ + + up_restorestate(rtcb->xcp.regs); + } + + /* No, then we will need to perform the user context switch */ + + else + { + /* Get the context of the task at the head of the ready to + * run list. + */ + + struct tcb_s *nexttcb = this_task(); + +#ifdef CONFIG_ARCH_ADDRENV + /* Make sure that the address environment for the previously + * running task is closed down gracefully (data caches dump, + * MMU flushed) and set up the address environment for the new + * thread at the head of the ready-to-run list. + */ + + (void)group_addrenv(nexttcb); +#endif + /* Reset scheduler parameters */ + + sched_resume_scheduler(nexttcb); + + /* Then switch contexts */ + + up_switchcontext(rtcb->xcp.regs, nexttcb->xcp.regs); + + /* up_switchcontext forces a context switch to the task at the + * head of the ready-to-run list. It does not 'return' in the + * normal sense. When it does return, it is because the blocked + * task is again ready to run and has execution priority. + */ + } + } +} diff --git a/arch/risc-v/src/rv32im/up_copystate.c b/arch/risc-v/src/rv32im/up_copystate.c new file mode 100644 index 00000000000..ca0fa98019a --- /dev/null +++ b/arch/risc-v/src/rv32im/up_copystate.c @@ -0,0 +1,86 @@ +/**************************************************************************** + * arch/risc-v/src/rv32im/up_copystate.c + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "up_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_copystate + ****************************************************************************/ + +/* A little faster than most memcpy's */ + +void up_copystate(uint32_t *dest, uint32_t *src) +{ + int i; + + /* In the MIPS model, the state is copied from the stack to the TCB, + * but only a reference is passed to get the state from the TCB. So the + * following check avoids copying the TCB save area onto itself: + */ + + if (src != dest) + { + for (i = 0; i < XCPTCONTEXT_REGS; i++) + { + *dest++ = *src++; + } + } +} + diff --git a/arch/risc-v/src/rv32im/up_doirq.c b/arch/risc-v/src/rv32im/up_doirq.c new file mode 100644 index 00000000000..70966d12f96 --- /dev/null +++ b/arch/risc-v/src/rv32im/up_doirq.c @@ -0,0 +1,148 @@ +/**************************************************************************** + * arch/risc-v/src/rv32im/up_doirq.c + * + * Copyright (C) 2011, 2014-2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "group/group.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +uint32_t *up_doirq(int irq, uint32_t *regs) +{ + board_autoled_on(LED_INIRQ); +#ifdef CONFIG_SUPPRESS_INTERRUPTS + PANIC(); +#else + /* Current regs non-zero indicates that we are processing an interrupt; + * g_current_regs is also used to manage interrupt level context switches. + * + * Nested interrupts are not supported + */ + + DEBUGASSERT(g_current_regs == NULL); + g_current_regs = regs; + + /* Disable further occurrences of this interrupt (until the interrupt sources + * have been clear by the driver). + */ + + up_disable_irq(irq); + + /* Deliver the IRQ */ + + irq_dispatch(irq, regs); + +#if defined(CONFIG_ARCH_FPU) || defined(CONFIG_ARCH_ADDRENV) + /* Check for a context switch. If a context switch occurred, then + * g_current_regs will have a different value than it did on entry. If an + * interrupt level context switch has occurred, then restore the floating + * point state and the establish the correct address environment before + * returning from the interrupt. + */ + + if (regs != g_current_regs) + { +#ifdef CONFIG_ARCH_FPU + /* Restore floating point registers */ + + up_restorefpu((uint32_t *)g_current_regs); +#endif + +#ifdef CONFIG_ARCH_ADDRENV + /* Make sure that the address environment for the previously + * running task is closed down gracefully (data caches dump, + * MMU flushed) and set up the address environment for the new + * thread at the head of the ready-to-run list. + */ + + (void)group_addrenv(NULL); +#endif + } +#endif + + /* If a context switch occurred while processing the interrupt then + * g_current_regs may have change value. If we return any value different + * from the input regs, then the lower level will know that a context + * switch occurred during interrupt processing. + */ + + regs = (uint32_t *)g_current_regs; + + /* Set g_current_regs to NULL to indicate that we are no longer in an + * interrupt handler. + */ + + g_current_regs = NULL; + + /* Unmask the last interrupt (global interrupts are still disabled) */ + + up_enable_irq(irq); +#endif + board_autoled_off(LED_INIRQ); + return regs; +} diff --git a/arch/risc-v/src/rv32im/up_dumpstate.c b/arch/risc-v/src/rv32im/up_dumpstate.c new file mode 100644 index 00000000000..97f74c64110 --- /dev/null +++ b/arch/risc-v/src/rv32im/up_dumpstate.c @@ -0,0 +1,231 @@ +/**************************************************************************** + * arch/risc-v/src/rv32im/up_dumpstate.c + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Updated for RISC-V: + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include "up_arch.h" +#include "sched/sched.h" +#include "up_internal.h" + +#ifdef CONFIG_ARCH_STACKDUMP + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_getsp + ****************************************************************************/ + +static inline uint32_t up_getsp(void) +{ + register uint32_t sp; + __asm__ + ( + "\tadd %0, x0, x2\n" + : "=r"(sp) + ); + return sp; +} + +/**************************************************************************** + * Name: up_stackdump + ****************************************************************************/ + +static void up_stackdump(uint32_t sp, uint32_t stack_base) +{ + uint32_t stack ; + + for (stack = sp & ~0x1f; stack < stack_base; stack += 32) + { + uint32_t *ptr = (uint32_t *)stack; + _alert("%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n", + stack, ptr[0], ptr[1], ptr[2], ptr[3], + ptr[4], ptr[5], ptr[6], ptr[7]); + } +} + +/**************************************************************************** + * Name: up_registerdump + ****************************************************************************/ + +static inline void up_registerdump(void) +{ + /* Are user registers available from interrupt processing? */ + + if (g_current_regs) + { + _alert("EPC:%08x \n", + g_current_regs[REG_EPC]); + _alert("A0:%08x A1:%08x A2:%08x A3:%08x A4:%08x A5:%08x A6:%08x A7:%08x\n", + g_current_regs[REG_A0], g_current_regs[REG_A1], g_current_regs[REG_A2], + g_current_regs[REG_A3], g_current_regs[REG_A4], g_current_regs[REG_A5], + g_current_regs[REG_A6], g_current_regs[REG_A7]); + _alert("T0:%08x T1:%08x T2:%08x T3:%08x T4:%08x T5:%08x T6:%08x\n", + g_current_regs[REG_T0], g_current_regs[REG_T1], g_current_regs[REG_T2], + g_current_regs[REG_T3], g_current_regs[REG_T4], g_current_regs[REG_T5], + g_current_regs[REG_T6]); + _alert("S0:%08x S1:%08x S2:%08x S3:%08x S4:%08x S5:%08x S6:%08x S7:%08x\n", + g_current_regs[REG_S0], g_current_regs[REG_S1], g_current_regs[REG_S2], + g_current_regs[REG_S3], g_current_regs[REG_S4], g_current_regs[REG_S5], + g_current_regs[REG_S6], g_current_regs[REG_S7]); + _alert("S8:%08x S9:%08x S10:%08x S11:%08x\n", + g_current_regs[REG_S8], g_current_regs[REG_S9], g_current_regs[REG_S10], + g_current_regs[REG_S11]); +#ifdef RISCV_SAVE_GP + _alert("GP:%08x SP:%08x FP:%08x TP:%08x RA:%08x\n", + g_current_regs[REG_GP], g_current_regs[REG_SP], g_current_regs[REG_FP], + g_current_regs[REG_TP], g_current_regs[REG_RA]); +#else + _alert("SP:%08x FP:%08x TP:%08x RA:%08x\n", + g_current_regs[REG_SP], g_current_regs[REG_FP], g_current_regs[REG_TP], + g_current_regs[REG_RA]); +#endif + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_dumpstate + ****************************************************************************/ + +void up_dumpstate(void) +{ + struct tcb_s *rtcb = this_task(); + uint32_t sp = up_getsp(); + uint32_t ustackbase; + uint32_t ustacksize; +#if CONFIG_ARCH_INTERRUPTSTACK > 3 + uint32_t istackbase; + uint32_t istacksize; +#endif + + /* Get the limits on the user stack memory */ + + if (rtcb->pid == 0) + { + ustackbase = g_idle_topstack - 4; + ustacksize = CONFIG_IDLETHREAD_STACKSIZE; + } + else + { + ustackbase = (uint32_t)rtcb->adj_stack_ptr; + ustacksize = (uint32_t)rtcb->adj_stack_size; + } + + /* Get the limits on the interrupt stack memory */ + +#if CONFIG_ARCH_INTERRUPTSTACK > 3 + istackbase = (uint32_t)&g_intstackbase; + istacksize = (CONFIG_ARCH_INTERRUPTSTACK & ~3) - 4; + + /* Show interrupt stack info */ + + _alert("sp: %08x\n", sp); + _alert("IRQ stack:\n"); + _alert(" base: %08x\n", istackbase); + _alert(" size: %08x\n", istacksize); + + /* Does the current stack pointer lie within the interrupt + * stack? + */ + + if (sp <= istackbase && sp > istackbase - istacksize) + { + /* Yes.. dump the interrupt stack */ + + up_stackdump(sp, istackbase); + + /* Extract the user stack pointer which should lie + * at the base of the interrupt stack. + */ + + sp = g_intstackbase; + _alert("sp: %08x\n", sp); + } + + /* Show user stack info */ + + _alert("User stack:\n"); + _alert(" base: %08x\n", ustackbase); + _alert(" size: %08x\n", ustacksize); +#else + _alert("sp: %08x\n", sp); + _alert("stack base: %08x\n", ustackbase); + _alert("stack size: %08x\n", ustacksize); +#endif + + /* Dump the user stack if the stack pointer lies within the allocated user + * stack memory. + */ + + if (sp > ustackbase || sp <= ustackbase - ustacksize) + { +#if !defined(CONFIG_ARCH_INTERRUPTSTACK) || CONFIG_ARCH_INTERRUPTSTACK < 4 + _alert("ERROR: Stack pointer is not within allocated stack\n"); +#endif + } + else + { + up_stackdump(sp, ustackbase); + } + + /* Then dump the registers (if available) */ + + up_registerdump(); +} + +#endif /* CONFIG_ARCH_STACKDUMP */ diff --git a/arch/risc-v/src/rv32im/up_initialstate.c b/arch/risc-v/src/rv32im/up_initialstate.c new file mode 100644 index 00000000000..492f9f10860 --- /dev/null +++ b/arch/risc-v/src/rv32im/up_initialstate.c @@ -0,0 +1,133 @@ +/**************************************************************************** + * arch/risc-v/src/rv32im/up_initialstate.c + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "up_internal.h" +#include "up_arch.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_initial_state + * + * Description: + * A new thread is being started and a new TCB + * has been created. This function is called to initialize + * the processor specific portions of the new TCB. + * + * This function must setup the intial architecture registers + * and/or stack so that execution will begin at tcb->start + * on the next context switch. + * + ****************************************************************************/ + +void up_initial_state(struct tcb_s *tcb) +{ + struct xcptcontext *xcp = &tcb->xcp; + uint32_t regval; + + /* Initialize the initial exception register context structure */ + + memset(xcp, 0, sizeof(struct xcptcontext)); + + /* Save the initial stack pointer. Hmmm.. the stack is set to the very + * beginning of the stack region. Some functions may want to store data on + * the caller's stack and it might be good to reserve some space. However, + * only the start function would do that and we have control over that one + */ + + xcp->regs[REG_SP] = (uint32_t)tcb->adj_stack_ptr; + + /* Save the task entry point */ + + xcp->regs[REG_EPC] = (uint32_t)tcb->start; + + /* If this task is running PIC, then set the PIC base register to the + * address of the allocated D-Space region. + */ + +#ifdef CONFIG_PIC +# warning "Missing logic" +#endif + + /* Set privileged- or unprivileged-mode, depending on how NuttX is + * configured and what kind of thread is being started. + * + * If the kernel build is not selected, then all threads run in + * privileged thread mode. + */ + +#ifdef CONFIG_BUILD_KERNEL +# warning "Missing logic" +#endif + + /* Set the initial value of the interrupt context register. + * + * Since various RISC-V platforms use different interrupt + * methodologies, the value of the interrupt context is + * part specific. + * + */ + + regval = up_get_newintctx(); + xcp->regs[REG_INT_CTX] = regval; +} + diff --git a/arch/risc-v/src/rv32im/up_releasepending.c b/arch/risc-v/src/rv32im/up_releasepending.c new file mode 100644 index 00000000000..e3fa22d47ed --- /dev/null +++ b/arch/risc-v/src/rv32im/up_releasepending.c @@ -0,0 +1,148 @@ +/**************************************************************************** + * arch/risc-v/src/rv32im/up_releasepending.c + * + * Copyright (C) 2011, 2014-2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "sched/sched.h" +#include "group/group.h" +#include "up_internal.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_release_pending + * + * Description: + * Release and ready-to-run tasks that have + * collected in the pending task list. This can call a + * context switch if a new task is placed at the head of + * the ready to run list. + * + ****************************************************************************/ + +void up_release_pending(void) +{ + struct tcb_s *rtcb = this_task(); + + sinfo("From TCB=%p\n", rtcb); + + /* Merge the g_pendingtasks list into the ready-to-run task list */ + + /* sched_lock(); */ + if (sched_mergepending()) + { + /* The currently active task has changed! We will need to switch + * contexts. + * + * Update scheduler parameters. + */ + + sched_suspend_scheduler(rtcb); + + /* Are we operating in interrupt context? */ + + if (g_current_regs) + { + /* Yes, then we have to do things differently. + * Just copy the g_current_regs into the OLD rtcb. + */ + + up_savestate(rtcb->xcp.regs); + + /* Restore the exception context of the rtcb at the (new) head + * of the ready-to-run task list. + */ + + rtcb = this_task(); + + /* Update scheduler parameters */ + + sched_resume_scheduler(rtcb); + + /* Then switch contexts. Any necessary address environment + * changes will be made when the interrupt returns. + */ + + up_restorestate(rtcb->xcp.regs); + } + + /* No, then we will need to perform the user context switch */ + + else + { + /* Switch context to the context of the task at the head of the + * ready to run list. + */ + + struct tcb_s *nexttcb = this_task(); + +#ifdef CONFIG_ARCH_ADDRENV + /* Make sure that the address environment for the previously + * running task is closed down gracefully (data caches dump, + * MMU flushed) and set up the address environment for the new + * thread at the head of the ready-to-run list. + */ + + (void)group_addrenv(nexttcb); +#endif + /* Update scheduler parameters */ + + sched_resume_scheduler(nexttcb); + + /* Then switch contexts */ + + up_switchcontext(rtcb->xcp.regs, nexttcb->xcp.regs); + + /* up_switchcontext forces a context switch to the task at the + * head of the ready-to-run list. It does not 'return' in the + * normal sense. When it does return, it is because the blocked + * task is again ready to run and has execution priority. + */ + } + } +} diff --git a/arch/risc-v/src/rv32im/up_reprioritizertr.c b/arch/risc-v/src/rv32im/up_reprioritizertr.c new file mode 100644 index 00000000000..26ed4ab2d10 --- /dev/null +++ b/arch/risc-v/src/rv32im/up_reprioritizertr.c @@ -0,0 +1,203 @@ +/**************************************************************************** + * arch/risc-v/src/rv32im/up_reprioritizertr.c + * + * Copyright (C) 2011, 2013-2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include + +#include "sched/sched.h" +#include "group/group.h" +#include "up_internal.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_reprioritize_rtr + * + * Description: + * Called when the priority of a running or + * ready-to-run task changes and the reprioritization will + * cause a context switch. Two cases: + * + * 1) The priority of the currently running task drops and the next + * task in the ready to run list has priority. + * 2) An idle, ready to run task's priority has been raised above the + * the priority of the current, running task and it now has the + * priority. + * + * Inputs: + * tcb: The TCB of the task that has been reprioritized + * priority: The new task priority + * + ****************************************************************************/ + +void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority) +{ + /* Verify that the caller is sane */ + + if (tcb->task_state < FIRST_READY_TO_RUN_STATE || + tcb->task_state > LAST_READY_TO_RUN_STATE +#if SCHED_PRIORITY_MIN > 0 + || priority < SCHED_PRIORITY_MIN +#endif +#if SCHED_PRIORITY_MAX < UINT8_MAX + || priority > SCHED_PRIORITY_MAX +#endif + ) + { + PANIC(); + } + else + { + struct tcb_s *rtcb = this_task(); + bool switch_needed; + + sinfo("TCB=%p PRI=%d\n", tcb, priority); + + /* Remove the tcb task from the ready-to-run list. + * sched_removereadytorun will return true if we just + * remove the head of the ready to run list. + */ + + switch_needed = sched_removereadytorun(tcb); + + /* Setup up the new task priority */ + + tcb->sched_priority = (uint8_t)priority; + + /* Return the task to the specified blocked task list. + * sched_addreadytorun will return true if the task was + * added to the new list. We will need to perform a context + * switch only if the EXCLUSIVE or of the two calls is non-zero + * (i.e., one and only one the calls changes the head of the + * ready-to-run list). + */ + + switch_needed ^= sched_addreadytorun(tcb); + + /* Now, perform the context switch if one is needed */ + + if (switch_needed) + { + /* If we are going to do a context switch, then now is the right + * time to add any pending tasks back into the ready-to-run list. + * task list now + */ + + if (g_pendingtasks.head) + { + sched_mergepending(); + } + + /* Update scheduler parameters */ + + sched_suspend_scheduler(rtcb); + + /* Are we in an interrupt handler? */ + + if (g_current_regs) + { + /* Yes, then we have to do things differently. + * Just copy the g_current_regs into the OLD rtcb. + */ + + up_savestate(rtcb->xcp.regs); + + /* Restore the exception context of the rtcb at the (new) head + * of the ready-to-run task list. + */ + + rtcb = this_task(); + + /* Update scheduler parameters */ + + sched_resume_scheduler(rtcb); + + /* Then switch contexts. Any necessary address environment + * changes will be made when the interrupt returns. + */ + + up_restorestate(rtcb->xcp.regs); + } + + /* No, then we will need to perform the user context switch */ + + else + { + /* Switch context to the context of the task at the head of the + * ready to run list. + */ + + struct tcb_s *nexttcb = this_task(); + +#ifdef CONFIG_ARCH_ADDRENV + /* Make sure that the address environment for the previously + * running task is closed down gracefully (data caches dump, + * MMU flushed) and set up the address environment for the new + * thread at the head of the ready-to-run list. + */ + + (void)group_addrenv(nexttcb); +#endif + /* Update scheduler parameters */ + + sched_resume_scheduler(nexttcb); + + /* Then switch contexts */ + + up_switchcontext(rtcb->xcp.regs, nexttcb->xcp.regs); + + /* up_switchcontext forces a context switch to the task at the + * head of the ready-to-run list. It does not 'return' in the + * normal sense. When it does return, it is because the blocked + * task is again ready to run and has execution priority. + */ + } + } + } +} diff --git a/arch/risc-v/src/rv32im/up_sigdeliver.c b/arch/risc-v/src/rv32im/up_sigdeliver.c new file mode 100644 index 00000000000..6d57a2b4a36 --- /dev/null +++ b/arch/risc-v/src/rv32im/up_sigdeliver.c @@ -0,0 +1,155 @@ +/**************************************************************************** + * arch/risc-v/src/rv32im/up_sigdeliver.c + * + * Copyright (C) 2011, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Modified for RISC-V: + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "sched/sched.h" +#include "up_internal.h" +#include "up_arch.h" + +#ifndef CONFIG_DISABLE_SIGNALS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_sigdeliver + * + * Description: + * This is the a signal handling trampoline. When a signal action was + * posted. The task context was mucked with and forced to branch to this + * location with interrupts disabled. + * + ****************************************************************************/ + +void up_sigdeliver(void) +{ + struct tcb_s *rtcb = this_task(); + uint32_t regs[XCPTCONTEXT_REGS]; + sig_deliver_t sigdeliver; + + /* Save the errno. This must be preserved throughout the signal handling + * so that the user code final gets the correct errno value (probably + * EINTR). + */ + + int saved_errno = rtcb->pterrno; + + board_autoled_on(LED_SIGNAL); + + sinfo("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n", + rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head); + ASSERT(rtcb->xcp.sigdeliver != NULL); + + /* Save the real return state on the stack. */ + + up_copystate(regs, rtcb->xcp.regs); + regs[REG_EPC] = rtcb->xcp.saved_epc; + regs[REG_INT_CTX] = rtcb->xcp.saved_int_ctx; + + /* Get a local copy of the sigdeliver function pointer. We do this so that + * we can nullify the sigdeliver function pointer in the TCB and accept + * more signal deliveries while processing the current pending signals. + */ + + sigdeliver = rtcb->xcp.sigdeliver; + rtcb->xcp.sigdeliver = NULL; + + /* Then restore the task interrupt state */ + + up_irq_restore((irqstate_t)regs[REG_INT_CTX]); + + /* Deliver the signals */ + + sigdeliver(rtcb); + + /* Output any debug messages BEFORE restoring errno (because they may + * alter errno), then disable interrupts again and restore the original + * errno that is needed by the user logic (it is probably EINTR). + */ + + sinfo("Resuming EPC: %08x INT_CTX: %08x\n", regs[REG_EPC], regs[REG_INT_CTX]); + + (void)up_irq_save(); + rtcb->pterrno = saved_errno; + + /* Then restore the correct state for this thread of + * execution. + */ + + board_autoled_off(LED_SIGNAL); + up_fullcontextrestore(regs); + + /* up_fullcontextrestore() should not return but could if the software + * interrupts are disabled. + */ + + PANIC(); +} + +#endif /* !CONFIG_DISABLE_SIGNALS */ + diff --git a/arch/risc-v/src/rv32im/up_swint.c b/arch/risc-v/src/rv32im/up_swint.c new file mode 100644 index 00000000000..61f3afefacf --- /dev/null +++ b/arch/risc-v/src/rv32im/up_swint.c @@ -0,0 +1,285 @@ +/**************************************************************************** + * arch/riscv/src/rv32im/up_swint.c + * + * Copyright (C) 2011-2012, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include + +#include + +#include "up_internal.h" + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_registerdump + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_SYSCALL_INFO +static void up_registerdump(const uint32_t *regs) +{ + svcinfo("EPC:%08x\n", + regs[REG_EPC]); + svcinfo("A0:%08x A1:%08x A2:%08x A3:%08x A4:%08x A5:%08x A6:%08x A7:%08x\n", + regs[REG_A0], regs[REG_A1], regs[REG_A2], regs[REG_A3], + regs[REG_A4], regs[REG_A5], regs[REG_A6], regs[REG_A7]); + svcinfo("T0:%08x T1:%08x T2:%08x T3:%08x T4:%08x T5:%08x T6:%08x\n", + regs[REG_T0], regs[REG_T1], regs[REG_T2], regs[REG_T3], + regs[REG_T4], regs[REG_T5], regs[REG_T6]); + svcinfo("S0:%08x S1:%08x S2:%08x S3:%08x S4:%08x S5:%08x S6:%08x S7:%08x\n", + regs[REG_S0], regs[REG_S1], regs[REG_S2], regs[REG_S3], + regs[REG_S4], regs[REG_S5], regs[REG_S6], regs[REG_S7]); + svcinfo("S8:%08x S9:%08x S10:%08x S11:%08x\n", + regs[REG_S8], regs[REG_S9], regs[REG_S10], regs[REG_S11]); +#ifdef MIPS32_SAVE_GP + svcinfo("GP:%08x SP:%08x FP:%08x TP:%08x RA:%08x\n", + regs[REG_GP], regs[REG_SP], regs[REG_FP], regs[REG_TP], regs[REG_RA]); +#else + svcinfo("SP:%08x FP:%08x TP:%08x RA:%08x\n", + regs[REG_SP], regs[REG_FP], regs[REG_TP], regs[REG_RA]); +#endif +} +#else +# define up_registerdump(regs) +#endif + +/**************************************************************************** + * Name: dispatch_syscall + * + * Description: + * Call the stub function corresponding to the system call. + * + ****************************************************************************/ + +#ifdef CONFIG_BUILD_KERNEL +static void dispatch_syscall(void) naked_function; +static void dispatch_syscall(void) +{ +# error "Missing logic" + +/* Refer to arch/arm/src/armv7-m/up_svcall.h for how this is done for ARM */ +/* __asm__ __volatile__ */ +/* ( */ +/* Save registers */ +/* Get the base of the stub lookup table */ +/* Get the offset of the stub for this syscall */ +/* Load the entry of the stub for this syscall */ +/* Call the stub */ +/* Restore regsisters */ +/* Return from the syscall */ +/* ); */ +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_swint + * + * Description: + * This is software interrupt exception handler that performs context + * switching and manages system calls + * + ****************************************************************************/ + +int up_swint(int irq, FAR void *context) +{ + uint32_t *regs = (uint32_t *)context; + + DEBUGASSERT(regs && regs == g_current_regs); + + /* Software interrupt 0 is invoked with REG_A0 (REG_X10) = system call + * command and REG_A1-6 = variable number of + * arguments depending on the system call. + */ + +#ifdef CONFIG_DEBUG_SYSCALL_INFO + svcinfo("Entry: regs: %p cmd: %d\n", regs, regs[REG_A0]); + up_registerdump(regs); +#endif + + /* Handle the SWInt according to the command in $a0 */ + + switch (regs[REG_A0]) + { + /* A0=SYS_restore_context: This a restore context command: + * + * void up_fullcontextrestore(uint32_t *restoreregs) noreturn_function; + * + * At this point, the following values are saved in context: + * + * A0 = SYS_restore_context + * A1 = restoreregs + * + * In this case, we simply need to set g_current_regs to restore register + * area referenced in the saved R1. context == g_current_regs is the normal + * exception return. By setting g_current_regs = context[R1], we force + * the return to the saved context referenced in $a1. + */ + + case SYS_restore_context: + { + DEBUGASSERT(regs[REG_A1] != 0); + g_current_regs = (uint32_t *)regs[REG_A1]; + } + break; + + /* A0=SYS_switch_context: This a switch context command: + * + * void up_switchcontext(uint32_t *saveregs, uint32_t *restoreregs); + * + * At this point, the following values are saved in context: + * + * A0 = SYS_switch_context + * A1 = saveregs + * A2 = restoreregs + * + * In this case, we save the context registers to the save register + * area reference by the saved contents of R5 and then set + * g_current_regs to to the save register area referenced by the saved + * contents of R6. + */ + + case SYS_switch_context: + { + DEBUGASSERT(regs[REG_A1] != 0 && regs[REG_A2] != 0); + up_copystate((uint32_t *)regs[REG_A1], regs); + g_current_regs = (uint32_t *)regs[REG_A2]; + } + break; + + /* A0=SYS_syscall_return: This a switch context command: + * + * void up_sycall_return(void); + * + * At this point, the following values are saved in context: + * + * A0 = SYS_syscall_return + * + * We need to restore the saved return address and return in + * unprivileged thread mode. + */ + +#ifdef CONFIG_BUILD_KERNEL + case SYS_syscall_return: + { + struct tcb_s *rtcb = sched_self(); + int index = (int)rtcb->xcp.nsyscalls - 1; + + /* Make sure that there is a saved syscall return address. */ + + DEBUGASSERT(index >= 0); + + /* Setup to return to the saved syscall return address in + * the original mode. + */ + + g_current_regs[REG_EPC] = rtcb->xcp.syscall[index].sysreturn; +#error "Missing logic -- need to restore the original mode" + rtcb->xcp.nsyscalls = index; + } + break; +#endif + + /* This is not an architecture-specify system call. If NuttX is built + * as a standalone kernel with a system call interface, then all of the + * additional system calls must be handled as in the default case. + */ + + default: + { +#ifdef CONFIG_BUILD_KERNEL + FAR struct tcb_s *rtcb = sched_self(); + int index = rtcb->xcp.nsyscalls; + + /* Verify that the SYS call number is within range */ + + DEBUGASSERT(g_current_regs[REG_A0] < SYS_maxsyscall); + + /* Make sure that we got here that there is a no saved syscall + * return address. We cannot yet handle nested system calls. + */ + + DEBUGASSERT(index < CONFIG_SYS_NNEST); + + /* Setup to return to dispatch_syscall in privileged mode. */ + + rtcb->xcpsyscall[index].sysreturn = regs[REG_EPC]; +#error "Missing logic -- Need to save mode" + rtcb->xcp.nsyscalls = index + 1; + + regs[REG_EPC] = (uint32_t)dispatch_syscall; +#error "Missing logic -- Need to set privileged mode" + + /* Offset R0 to account for the reserved values */ + + g_current_regs[REG_A0] -= CONFIG_SYS_RESERVED; +#else + svcerr("ERROR: Bad SYS call: %d\n", regs[REG_A0]); +#endif + } + break; + } + + /* Report what happened. That might difficult in the case of a context switch */ + +#ifdef CONFIG_DEBUG_SYSCALL_INFO + if (regs != g_current_regs) + { + svcinfo("SWInt Return: Context switch!\n"); + up_registerdump((const uint32_t *)g_current_regs); + } + else + { + svcinfo("SWInt Return: %d\n", regs[REG_A0]); + } +#endif + + return OK; +} diff --git a/arch/risc-v/src/rv32im/up_syscall.S b/arch/risc-v/src/rv32im/up_syscall.S new file mode 100644 index 00000000000..1c110db6295 --- /dev/null +++ b/arch/risc-v/src/rv32im/up_syscall.S @@ -0,0 +1,112 @@ +/**************************************************************************** + * arch/riscv/src/rv32im/up_syscall.S + * + * Copyright (C) 2011, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Modified for RISC-V: + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Symbols + ****************************************************************************/ + + .file "up_syscall0.S" + .global sys_call0 + .global sys_call1 + .global sys_call2 + .global sys_call3 + .global sys_call4 + .global sys_call5 + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_syscall0, up_syscall1, up_syscall2, up_syscall3 + * + * Description: + * up_syscall0 - System call SYS_ argument and no additional parameters. + * up_syscall1 - System call SYS_ argument and one additional parameter. + * up_syscall2 - System call SYS_ argument and two additional parameters. + * up_syscall3 - System call SYS_ argument and three additional parameters. + * up_syscall4 - System call SYS_ argument and four additional parameters. + * up_syscall5 - System call SYS_ argument and five additional parameters. + * + * Assumption: + * All interrupts are disabled except for the software interrupts. + * + ****************************************************************************/ + + .text + +sys_call0: /* a0 holds the syscall number */ +sys_call1: /* a0 holds the syscall number, argument in a1 */ +sys_call2: /* a0 holds the syscall number, arguments in a1 and a2 */ +sys_call3: /* a0 holds the syscall number, arguments in a1, a2, and a3 */ +sys_call4: /* a0 holds the syscall number, arguments in a1, a2, a3 and a4 */ +sys_call5: /* a0 holds the syscall number, arguments in a1, a2, a3, a4 and a5 */ + + /* Issue the ECALL opcode to perform a SW interrupt to the OS */ + + ecall + + /* The actual interrupt may not a occur for a few more cycles. Let's + * put a few nop's here in hope that the SW interrupt occurs during + * the sequence of nops. + */ + + nop + nop + + /* Then return with the result of the software interrupt in v0 */ + + ret + nop + diff --git a/arch/risc-v/src/rv32im/up_unblocktask.c b/arch/risc-v/src/rv32im/up_unblocktask.c new file mode 100644 index 00000000000..1b7350e05b1 --- /dev/null +++ b/arch/risc-v/src/rv32im/up_unblocktask.c @@ -0,0 +1,163 @@ +/**************************************************************************** + * arch/risc-v/src/rv32im/up_unblocktask.c + * + * Copyright (C) 2011, 2013-2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "sched/sched.h" +#include "group/group.h" +#include "clock/clock.h" +#include "up_internal.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_unblock_task + * + * Description: + * A task is currently in an inactive task list + * but has been prepped to execute. Move the TCB to the + * ready-to-run list, restore its context, and start execution. + * + * Inputs: + * tcb: Refers to the tcb to be unblocked. This tcb is + * in one of the waiting tasks lists. It must be moved to + * the ready-to-run list and, if it is the highest priority + * ready to run task, executed. + * + ****************************************************************************/ + +void up_unblock_task(struct tcb_s *tcb) +{ + struct tcb_s *rtcb = this_task(); + + /* Verify that the context switch can be performed */ + + ASSERT((tcb->task_state >= FIRST_BLOCKED_STATE) && + (tcb->task_state <= LAST_BLOCKED_STATE)); + + /* Remove the task from the blocked task list */ + + sched_removeblocked(tcb); + + /* Add the task in the correct location in the prioritized + * ready-to-run task list + */ + + if (sched_addreadytorun(tcb)) + { + /* The currently active task has changed! We need to do + * a context switch to the new task. + */ + + /* Update scheduler parameters */ + + sched_suspend_scheduler(rtcb); + + /* Are we in an interrupt handler? */ + + if (g_current_regs) + { + /* Yes, then we have to do things differently. + * Just copy the g_current_regs into the OLD rtcb. + */ + + up_savestate(rtcb->xcp.regs); + + /* Restore the exception context of the rtcb at the (new) head + * of the ready-to-run task list. + */ + + rtcb = this_task(); + + /* Update scheduler parameters */ + + sched_resume_scheduler(rtcb); + + /* Then switch contexts. Any necessary address environment + * changes will be made when the interrupt returns. + */ + + up_restorestate(rtcb->xcp.regs); + } + + /* No, then we will need to perform the user context switch */ + + else + { + /* Restore the exception context of the new task that is ready to + * run (probably tcb). This is the new rtcb at the head of the + * ready-to-run task list. + */ + + struct tcb_s *nexttcb = this_task(); + +#ifdef CONFIG_ARCH_ADDRENV + /* Make sure that the address environment for the previously + * running task is closed down gracefully (data caches dump, + * MMU flushed) and set up the address environment for the new + * thread at the head of the ready-to-run list. + */ + + (void)group_addrenv(nexttcb); +#endif + /* Update scheduler parameters */ + + sched_resume_scheduler(nexttcb); + + /* Then switch contexts */ + + up_switchcontext(rtcb->xcp.regs, nexttcb->xcp.regs); + + /* up_switchcontext forces a context switch to the task at the + * head of the ready-to-run list. It does not 'return' in the + * normal sense. When it does return, it is because the blocked + * task is again ready to run and has execution priority. + */ + } + } +} diff --git a/arch/risc-v/src/rv32im/up_vfork.c b/arch/risc-v/src/rv32im/up_vfork.c new file mode 100644 index 00000000000..f2f5332bece --- /dev/null +++ b/arch/risc-v/src/rv32im/up_vfork.c @@ -0,0 +1,262 @@ +/**************************************************************************** + * arch/mips/src/mips32/up_vfork.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "up_vfork.h" +#include "sched/sched.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_STACK_ALIGNMENT +# define CONFIG_STACK_ALIGNMENT 4 +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_vfork + * + * Description: + * The vfork() function has the same effect as fork(), except that the + * behavior is undefined if the process created by vfork() either modifies + * any data other than a variable of type pid_t used to store the return + * value from vfork(), or returns from the function in which vfork() was + * called, or calls any other function before successfully calling _exit() + * or one of the exec family of functions. + * + * The overall sequence is: + * + * 1) User code calls vfork(). vfork() collects context information and + * transfers control up up_vfork(). + * 2) up_vfork()and calls task_vforksetup(). + * 3) task_vforksetup() allocates and configures the child task's TCB. This + * consists of: + * - Allocation of the child task's TCB. + * - Initialization of file descriptors and streams + * - Configuration of environment variables + * - Setup the intput parameters for the task. + * - Initialization of the TCB (including call to up_initial_state() + * 4) up_vfork() provides any additional operating context. up_vfork must: + * - Allocate and initialize the stack + * - Initialize special values in any CPU registers that were not + * already configured by up_initial_state() + * 5) up_vfork() then calls task_vforkstart() + * 6) task_vforkstart() then executes the child thread. + * + * task_vforkabort() may be called if an error occurs between steps 3 and 6. + * + * Input Paremeters: + * context - Caller context information saved by vfork() + * + * Return: + * Upon successful completion, vfork() returns 0 to the child process and + * returns the process ID of the child process to the parent process. + * Otherwise, -1 is returned to the parent, no child process is created, + * and errno is set to indicate the error. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_HAVE_VFORK + +#error This part of the port is not done yet!! + +pid_t up_vfork(const struct vfork_s *context) +{ + struct tcb_s *parent = this_task(); + struct task_tcb_s *child; + size_t stacksize; + uint32_t newsp; +#ifdef CONFIG_MIPS32_FRAMEPOINTER + uint32_t newfp; +#endif + uint32_t stackutil; + int ret; + + sinfo("s0:%08x s1:%08x s2:%08x s3:%08x s4:%08x\n", + context->s0, context->s1, context->s2, context->s3, context->s4); +#ifdef CONFIG_MIPS32_FRAMEPOINTER + sinfo("s5:%08x s6:%08x s7:%08x\n", + context->s5, context->s6, context->s7); +#ifdef MIPS32_SAVE_GP + sinfo("fp:%08x sp:%08x ra:%08x gp:%08x\n", + context->fp, context->sp, context->ra, context->gp); +#else + sinfo("fp:%08x sp:%08x ra:%08x\n", + context->fp context->sp, context->ra); +#endif +#else + sinfo("s5:%08x s6:%08x s7:%08x s8:%08x\n", + context->s5, context->s6, context->s7, context->s8); +#ifdef MIPS32_SAVE_GP + sinfo("sp:%08x ra:%08x gp:%08x\n", + context->sp, context->ra, context->gp); +#else + sinfo("sp:%08x ra:%08x\n", + context->sp, context->ra); +#endif +#endif + + /* Allocate and initialize a TCB for the child task. */ + + child = task_vforksetup((start_t)context->ra); + if (!child) + { + sinfo("task_vforksetup failed\n"); + return (pid_t)ERROR; + } + + sinfo("Parent=%p Child=%p\n", parent, child); + + /* Get the size of the parent task's stack. Due to alignment operations, + * the adjusted stack size may be smaller than the stack size originally + * requrested. + */ + + stacksize = parent->adj_stack_size + CONFIG_STACK_ALIGNMENT - 1; + + /* Allocate the stack for the TCB */ + + ret = up_create_stack((FAR struct tcb_s *)child, stacksize, + parent->flags & TCB_FLAG_TTYPE_MASK); + if (ret != OK) + { + serr("ERROR: up_create_stack failed: %d\n", ret); + task_vforkabort(child, -ret); + return (pid_t)ERROR; + } + + /* How much of the parent's stack was utilized? The MIPS uses + * a push-down stack so that the current stack pointer should + * be lower than the initial, adjusted stack pointer. The + * stack usage should be the difference between those two. + */ + + DEBUGASSERT((uint32_t)parent->adj_stack_ptr > context->sp); + stackutil = (uint32_t)parent->adj_stack_ptr - context->sp; + + sinfo("stacksize:%d stackutil:%d\n", stacksize, stackutil); + + /* Make some feeble effort to perserve the stack contents. This is + * feeble because the stack surely contains invalid pointers and other + * content that will not work in the child context. However, if the + * user follows all of the caveats of vfork() usage, even this feeble + * effort is overkill. + */ + + newsp = (uint32_t)child->cmn.adj_stack_ptr - stackutil; + memcpy((void *)newsp, (const void *)context->sp, stackutil); + + /* Was there a frame pointer in place before? */ + +#ifdef CONFIG_MIPS32_FRAMEPOINTER + if (context->fp <= (uint32_t)parent->adj_stack_ptr && + context->fp >= (uint32_t)parent->adj_stack_ptr - stacksize) + { + uint32_t frameutil = (uint32_t)parent->adj_stack_ptr - context->fp; + newfp = (uint32_t)child->cmn.adj_stack_ptr - frameutil; + } + else + { + newfp = context->fp; + } + + sinfo("Old stack base:%08x SP:%08x FP:%08x\n", + parent->adj_stack_ptr, context->sp, context->fp); + sinfo("New stack base:%08x SP:%08x FP:%08x\n", + child->cmn.adj_stack_ptr, newsp, newfp); +#else + sinfo("Old stack base:%08x SP:%08x\n", + parent->adj_stack_ptr, context->sp); + sinfo("New stack base:%08x SP:%08x\n", + child->cmn.adj_stack_ptr, newsp); +#endif + + /* Update the stack pointer, frame pointer, global pointer and saved + * registers. When the child TCB was initialized, all of the values + * were set to zero. up_initial_state() altered a few values, but the + * return value in v0 should be cleared to zero, providing the + * indication to the newly started child thread. + */ + + child->cmn.xcp.regs[REG_S0] = context->s0; /* Saved register s0 */ + child->cmn.xcp.regs[REG_S1] = context->s1; /* Saved register s1 */ + child->cmn.xcp.regs[REG_S2] = context->s2; /* Saved register s2 */ + child->cmn.xcp.regs[REG_S3] = context->s3; /* Volatile register s3 */ + child->cmn.xcp.regs[REG_S4] = context->s4; /* Volatile register s4 */ + child->cmn.xcp.regs[REG_S5] = context->s5; /* Volatile register s5 */ + child->cmn.xcp.regs[REG_S6] = context->s6; /* Volatile register s6 */ + child->cmn.xcp.regs[REG_S7] = context->s7; /* Volatile register s7 */ +#ifdef CONFIG_MIPS32_FRAMEPOINTER + child->cmn.xcp.regs[REG_FP] = newfp; /* Frame pointer */ +#else + child->cmn.xcp.regs[REG_S8] = context->s8; /* Volatile register s8 */ +#endif + child->cmn.xcp.regs[REG_SP] = newsp; /* Stack pointer */ +#ifdef MIPS32_SAVE_GP + child->cmn.xcp.regs[REG_GP] = newsp; /* Global pointer */ +#endif + + /* And, finally, start the child task. On a failure, task_vforkstart() + * will discard the TCB by calling task_vforkabort(). + */ + + return task_vforkstart(child); +} + +#endif /* CONFIG_ARCH_HAVE_VFORK */ + diff --git a/arch/risc-v/src/rv32im/up_vfork.h b/arch/risc-v/src/rv32im/up_vfork.h new file mode 100644 index 00000000000..079a744c830 --- /dev/null +++ b/arch/risc-v/src/rv32im/up_vfork.h @@ -0,0 +1,132 @@ +/**************************************************************************** + * arch/mips/src/mips/up_vfork.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_MIPS_SRC_MIPS32_VFORK_H +#define __ARCH_MIPS_SRC_MIPS32_VFORK_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* Register r30 may be a frame pointer in some ABIs. Or may just be saved + * register s8. It makes a difference for vfork handling. + */ + +#undef VFORK_HAVE_FP + +/* r0 zero Always has the value 0. + * r1 at Temporary generally used by assembler. + * r2-r3 v0-v1 Used for expression evaluations and to hold the integer and + * pointer type function return values. + * r4-r7 a0-a3 Used for passing arguments to functions; values are not + * preserved across function calls. + * r8-r15 t0-t7 Temporary registers used for expression evaluation; values + * are not preserved across function calls. + * r16-r23 s0-s7 Saved registers; values are preserved across function calls. + * r24-r25 t8-t9 Temporary registers used for expression evaluations; values + * are not preserved across function calls. When calling + * position independent functions r25 must contain the address + * of the called function. + * r26-r27 k0-k1 Used only by the operating system. + * r28 gp Global pointer and context pointer. + * r29 sp Stack pointer. + * r30 s8 Saved register (like s0-s7). If a frame pointer is used, + * then this is the frame pointer. + * r31 ra Return address. + */ + +#define VFORK_S0_OFFSET (0*4) /* Saved register s0 */ +#define VFORK_S1_OFFSET (1*4) /* Saved register s1 */ +#define VFORK_S2_OFFSET (2*4) /* Saved register s2 */ +#define VFORK_S3_OFFSET (3*4) /* Saved register s3 */ +#define VFORK_S4_OFFSET (4*4) /* Saved register s4 */ +#define VFORK_S5_OFFSET (5*4) /* Saved register s5 */ +#define VFORK_S6_OFFSET (6*4) /* Saved register s6 */ +#define VFORK_S7_OFFSET (7*4) /* Saved register s7 */ + +#ifdef CONFIG_MIPS32_FRAMEPOINTER +# define VFORK_FP_OFFSET (8*4) /* Frame pointer */ +#else +# define VFORK_S8_OFFSET (8*4) /* Saved register s8 */ +#endif + +#define VFORK_SP_OFFSET (9*4) /* Stack pointer*/ +#define VFORK_RA_OFFSET (10*4) /* Return address*/ +#ifdef MIPS32_SAVE_GP +# define VFORK_GP_OFFSET (11*4) /* Global pointer */ +# define VFORK_SIZEOF (12*4) +#else +# define VFORK_SIZEOF (11*4) +#endif + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +struct vfork_s +{ + /* CPU registers */ + + uint32_t s0; /* Saved register s0 */ + uint32_t s1; /* Saved register s1 */ + uint32_t s2; /* Saved register s2 */ + uint32_t s3; /* Saved register s3 */ + uint32_t s4; /* Saved register s4 */ + uint32_t s5; /* Saved register s5 */ + uint32_t s6; /* Saved register s6 */ + uint32_t s7; /* Saved register s7 */ +#ifdef CONFIG_MIPS32_FRAMEPOINTER + uint32_t fp; /* Frame pointer */ +#else + uint32_t s8; /* Saved register s8 */ +#endif + uint32_t sp; /* Stack pointer*/ + uint32_t ra; /* Return address*/ +#ifdef MIPS32_SAVE_GP + uint32_t gp; /* Global pointer */ +#endif + + /* Floating point registers (not yet) */ +}; +#endif + +#endif /* __ARCH_MIPS_SRC_MIPS32_VFORK_H */ diff --git a/configs/Kconfig b/configs/Kconfig index 2b629c1a4f1..3e08a0dba49 100644 --- a/configs/Kconfig +++ b/configs/Kconfig @@ -673,6 +673,14 @@ config ARCH_BOARD_PIRELLI_DPL10 This directory contains the board support for Pirelli dpl10 phones. The additions were made by Craig Comstock (with help form Alan Carvalho de Assis). +config ARCH_BOARD_NR5M100_NEXYS4 + bool "NEXT RISC-V NR5M100 on Nexys-4 board" + depends on ARCH_CHIP_NR5M100 + select UART_SERIALDRIVER + ---help--- + This is the port NuttX to the NEXT RISC-V processor runnining on a Digilent + Nexys-4 (non DDR version) FPGA board. + config ARCH_BOARD_NUCLEO_144 bool "STMicro NUCLEO-144" depends on ARCH_CHIP_STM32F746ZG || ARCH_CHIP_STM32F767ZI @@ -1413,6 +1421,7 @@ config ARCH_BOARD default "ne64badge" if ARCH_BOARD_NE64BADGE default "ntosd-dm320" if ARCH_BOARD_NTOSD_DM320 default "nutiny-nuc120" if ARCH_BOARD_NUTINY_NUC120 + default "nr5m100-nexys4" if ARCH_BOARD_NR5M100_NEXYS4 default "olimex-efm32g880f128-stk" if ARCH_BOARD_OLIMEX_EFM32G880F128_STK default "olimex-lpc1766stk" if ARCH_BOARD_LPC1766STK default "olimex-lpc2378" if ARCH_BOARD_OLIMEXLPC2378 diff --git a/configs/README.txt b/configs/README.txt index 8bf546a298d..9bd796ffa77 100644 --- a/configs/README.txt +++ b/configs/README.txt @@ -551,6 +551,9 @@ configs/rgmp See http://rgmp.sourceforge.net/wiki/index.php/Main_Page for further information about RGMP. +configs/nr5m100-nexys4 + Port of NuttX to RISC-V platform on IQ-Analog NR5M100 RISC-V FPGA platform. + configs/sabre-6quad This directory holds a port of NuttX to the NXP/Freescale Sabre board featuring the iMX 6Quad CPU. diff --git a/configs/nr5m100-nexys4/Kconfig b/configs/nr5m100-nexys4/Kconfig new file mode 100644 index 00000000000..8824428a4d5 --- /dev/null +++ b/configs/nr5m100-nexys4/Kconfig @@ -0,0 +1,9 @@ +# +# For a description of the syntax of this configuration file, +# see misc/tools/kconfig-language.txt. +# + +if ARCH_BOARD_NR5M100_NEXYS4 + + +endif diff --git a/configs/nr5m100-nexys4/README.txt b/configs/nr5m100-nexys4/README.txt new file mode 100644 index 00000000000..fc939aa4c60 --- /dev/null +++ b/configs/nr5m100-nexys4/README.txt @@ -0,0 +1,251 @@ +README +====== + +This README discusses issues unique to NuttX configurations for the +IQ-Analog NR5M100 FPGA implementation of a RISC-V core on the Digilent +Nexys4 FPGA board. + +The port is currently very minimal, though additional support may be +added in the future to address more of the board peripherals supplied +on the FPGA board. Those peripherals include: + + Supported: + - USB UART (console port) + - 16 single color LEDs + - 16 slide switch inputs + - Two tri-color LEDs + - 5 Joystick style pushbuttons + - 16 GPIO pins on 2 of the PMOD expansion connectors + + Not supported: + - VGA display port + - 8 digit 7-segement display + - SD card slot + - SPI FLASH memory (shared with FPGA configuration data). + - USB HID (single device) connector serviced by external PIC uC + - Non-DDR (older version): 16 MB Cellular SRAM + - DDR (newer version): 128 MB DDR2 SDRAM + - Microphone + - 10/100 Ethernet PHY + - 3-Axis accelerometer + - Temperature sensor + +See http://store.digilentinc.com/nexys-4-ddr-artix-7-fpga-trainer-board-recommended-for-ece-curriculum/ +or http://store.digilentinc.com/nexys-4-artix-7-fpga-trainer-board-limited-time-see-nexys4-ddr/ +for more information about these boards. + +Contents +======== + + - NR5M100 Overview + - Development Environment + - GNU Toolchain Options + - Debugger + - IDEs + - LEDs + - PWM + - UARTs + - Timer Inputs/Outputs + - FSMC SRAM + - SSD1289 + - Mikroe-STM32F4-specific Configuration Options + - Configurations + +Development Environment +======================= + The NR5M100 RISC-V core was designed as a low gate count / low performance micro controller + for inclusion in an ASIC. It is based on a Verilog RISC-V called picorv32, but has many + additions beyond that baseline. The design running on the Digilent Nexys4 FPGA is a + validation platform for the core and is presented as an open source project. + + The reason NR5M100 is "low performance" is that it is a state machine based core (like the + picorv32) and not a multi-stage pipeline core. This means that it requires an average of + 4.5 clock cycles to execute each instruction. On a multi-stage pipeline architecure, this + average would be closer to 1 clock cycle per instruction (though a bit higher due to + pipeline branch misses). The tradeoff for lower performance is a simpler design. There + is a single memory bus interface for both instructions and data. Multi-stage pipeline + cores require a separate I and D bus with cache SRAM and an external memory cache controller, + etc. This in addition to the pipeline registers adds additional gate count. + + The nr5m100-nexys4 core runs at 83.333 Mhz which provides about 18 Mhz effective operating + speed with the multi-clock per instruction architecture. If you are looking for a higher + performance platform, you should check out the PULP Platform ( http://www.pulp-platform.org ). + That is an FPGA design with a 4-stage pipeline RISC-V core, though not currently supported + by NuttX. The NR5M100 project will likely pull in the RISC-V core from that design next, + though this will probably not be available soon. With a bit of work, it is possible to + run the nr5m100-nexys4 core at 170 Mhz with a 6.5 clocks-per-instruction state machine. + This would give an effective performance of about 26Mhz. + +Development Environment +======================= + + Linux is the best choice for development, though Cygwin on Windows may work. + The source has been built only using the GNU toolchain (see below) under a Linux + environment. Other toolchains will likely cause problems or not be available yet. + +RISC-V GNU Toolchain +==================== + + To compile the code, you must first build a RISC-V GNU Toolchain from the sources at + https://github.com/riscv/riscv-gnu-toolchain. I don't know of any sources for pre-compiled + toolchains (though there may be some out there). + + To build this toolchain, follow these instructions (tested on Ubuntu 12.04): + + 1. Create a working directory in your home folder: + + mkdir ~/riscv + cd ~/riscv + + 2. Clone the GNU source tree: + + git clone --recursive https://github.com/riscv/riscv-gnu-toolchain + + 3. Ensure the following packages are installed: + + sudo apt-get install texinfo bison flex autoconf automake libgmp-dev libmpfr-dev libmpc-dev + + 4. Configure and build the toolchain: + + cd riscv-gnu-toolchain + ./configure --with-xlen=64 --with-arch=I --disable-float --disable-atomic --enable-multilib --prefix=~/riscv + make -j4 (or -j8 based on how many cores you have) + + 5. Setup your PATH environment variable to include the toolchain (you may want to add this to + your shell login script, such as .bash_profile, etc.): + + export PATH=~/riscv/bin:$PATH + + Windows based toolchain + ----------------------- + May be possible to compile the GNU toolchain described above using Cygwin, but havne't tried it. + +Debugger +======== + The Debug Module within the NR5M100 RISC-V has been designed to work with the RISC-V gdb + debugger interfaced with the SiFive implementation of OpenOCD. The interface has been tested + with a J-LINK JTAG probe connected to PMOD header B on the FPGA using an adapter board + that I designed and fabbed at OSHPark. I will update this README.txt file soon with a link + to the shared project for anyone who wishes to build one. + + To build OpenOCD, perform the following: + + 1. Ensure the proper packages are installed: + + sudo apt-get install autoconf automake libtool libusb-1.0-0-dev + + 2. Download the latest OpenOCD sources from the SiFive github repo: + + cd ~/riscv + git clone --recursive https://github.com/sifive/openocd.git + + 3. Configure and build OpenOCD. The x86_64 GCC compilers will give errors because of + shadowed variable warnings, so diable the -Werror flag also: + + cd openocd + sed -i 's/ -Werror//g' configure.ac + ./bootstrap + ./configure --enable-jlink --enable-maintainer-mode --enable-ftdi --prefix=~/riscv CFLAGS=-g + + The configuration scripts for openocd and nr5m100-nexys4 have been provided in the + nuttx/configs/nr5m100-nexys4/scripts directory. They are configured to use a J-LINK JTAG + probe and to search for the IQ-Analog (the company I work for) IDCODE and part number for + the FPGA board (7a10 for Artix xc7a100 part on the Digilent Nexys4 board). With FPGA + source directly from the nr5m100 github site (to be provided), this ID will match the + hardware. If changes are made to the JEDEC ID and/or part number, then the nr5m100.cfg + file will need to be modified with the proper CPUID value. + +IDEs +==== + + NuttX is built using command-line make. It can be used with an IDE, but some + effort will be required to create the project. While I haven't tried it as + I am not an IDE guy, the team at SiFive have reported that they now have + Eclipse working with the RISC-V gdb debugger. + + NOTE: The notes below are taken from an ARM build of NuttX, not RISC-V, so + they may or may not work. Try it and see I suppose. + + Makefile Build + -------------- + Under Eclipse, it is pretty easy to set up an "empty makefile project" and + simply use the NuttX makefile to build the system. That is almost for free + under Linux. Under Windows, you will need to set up the "Cygwin GCC" empty + makefile project in order to work with Windows (Google for "Eclipse Cygwin" - + there is a lot of help on the internet). + + Native Build + ------------ + Here are a few tips before you start that effort: + + 1) Select the toolchain that you will be using in your .config file + 2) Start the NuttX build at least one time from the Cygwin command line + before trying to create your project. This is necessary to create + certain auto-generated files and directories that will be needed. + 3) Set up include pathes: You will need include/, arch/risc-v/src/rv32im, + arch/risc-v/src/common, arch/risc-v/src/nr5m100, and sched/. + 4) All assembly files need to have the definition option -D __ASSEMBLY__ + on the command line. + + Startup files will probably cause you some headaches. The NuttX startup file + is arch/risc-v/src/nr5m100/nr5_vectors.S. With RIDE, I build NuttX + one time from the Cygwin command line in order to obtain the pre-built + startup object needed by RIDE. + +LEDs +==== + +The Nexys4 board has 16 single-color LEDs onboard, as well as 2 tri-color LEDs. +These are supported using GPIO Ports A (16-single color) and B (tri-color). +Additionally the tri-color LEDs can be driven from the Timer 1 or 2 PWM output +signals. + +PWM +=== + +The nr5m100-nexys4 design has PWM capabilities within the Timer 1 and Timer 2 +modules. These PWM signals can be muxed to the tri-color LEDs or to I/O +pins on one of the PMOD expansion headers. + +UARTs +===== + +The nr5m100-nexys4 design has an onboard USB-UART providing an RS-232 interface +via the same USB cable that is used to program the FPGA. The core proivdes a +fixed 8-Data bit, 1 stop bit, no parity UART connected to this intrface. + +UART PINS +--------- + +UART1 + RX FPGA C4 (USB UART device) + TX FPGA D4 (USB UART device) + +Default USART/UART Configuration +-------------------------------- + +UART1 is enabled in all configurations (see */defconfig). + +Configurations +============== + +Each nr5m100-nexys4 configuration is maintained in a sub-directory and +can be selected as follow: + + cd tools + ./configure.sh nr5m100-nexys4/ + cd - + . ./setenv.sh + +If this is a Windows native build, then configure.bat should be used +instead of configure.sh: + + configure.bat nr5m100-nexys4\ + +Where is one of the following: + + nsh + --- + This is an NSH example that uses UART1 as the console. UART1 is connected + to the USB UART bridge on the FPGA board. + diff --git a/configs/nr5m100-nexys4/include/board.h b/configs/nr5m100-nexys4/include/board.h new file mode 100644 index 00000000000..366c3007d1f --- /dev/null +++ b/configs/nr5m100-nexys4/include/board.h @@ -0,0 +1,178 @@ +/************************************************************************************ + * configs/nr5m100-nexys4/include/board.h + * include/arch/board/board.h + * + * Copyright (C) 2012-2013, 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Modified for NR5M100: + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __CONFIG_NR5M100_NEXYS4_INCLUDE_BOARD_H +#define __CONFIG_NR5M100_NEXYS4_INCLUDE_BOARD_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +#include "nr5.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Clocking *************************************************************************/ +/* The NR5M100_Nexys4 system uses a 100 MHz main oscillator */ + +#define NR5_HCLK_FREQUENCY 100000000ul +#define NR5_SCLK_FREQUENCY 100000000ul + +//#define STM32_SYSCLK_FREQUENCY 168000000ul + +/* Timer Frequencies are the same as the HCLK frequency + */ + +#define NR5_TIMER_FREQUENCY NR5_HCLK_FREQUENCY + +/* LED definitions ******************************************************************/ +/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in any + * way. The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with stm32_setled() */ + +#if 0 +#define BOARD_LED1 0 +#define BOARD_LED2 1 +#define BOARD_LED3 2 +#define BOARD_LED4 3 +#endif +#define BOARD_NLEDS 0 + +#if 1 +#define BOARD_LED_GREEN BOARD_LED1 +#define BOARD_LED_ORANGE BOARD_LED2 +#define BOARD_LED_RED BOARD_LED3 +#define BOARD_LED_BLUE BOARD_LED4 + +/* LED bits for use with nr5_setleds() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) +#define BOARD_LED2_BIT (1 << BOARD_LED2) +#define BOARD_LED3_BIT (1 << BOARD_LED3) +#define BOARD_LED4_BIT (1 << BOARD_LED4) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 LEDs on board the + * stm32f4discovery. The following definitions describe how NuttX controls the LEDs: + */ + +#define LED_STARTED 0 /* LED1 */ +#define LED_HEAPALLOCATE 1 /* LED2 */ +#define LED_IRQSENABLED 2 /* LED1 + LED2 */ +#define LED_STACKCREATED 3 /* LED3 */ +#define LED_INIRQ 4 /* LED1 + LED3 */ +#define LED_SIGNAL 5 /* LED2 + LED3 */ +#define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */ +#define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */ + +/* Button definitions ***************************************************************/ +/* The STM32F4 Discovery supports one button: */ + +#define BUTTON_USER 0 + +#define NUM_BUTTONS 5 + +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +#endif /* 0 */ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ +/************************************************************************************ + * Name: nr5_boardinitialize + * + * Description: + * All NR5 architectures must provide the following entry point. This entry point + * is called early in the intitialization -- after all memory has been configured + * and mapped but before any devices have been initialized. + * + ************************************************************************************/ + +void nr5_boardinitialize(void); + +/************************************************************************************ + * Name: nr5_ledinit, nr5_setled, and nr5_setleds + * + * Description: + * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board LEDs. If + * CONFIG_ARCH_LEDS is not defined, then the following interfacesare available to + * control the LEDs from user applications. + * + ************************************************************************************/ + +#ifndef CONFIG_ARCH_LEDS +void nr5_ledinit(void); +void nr5_setled(int led, bool ledon); +void nr5_setleds(uint8_t ledset); +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif +#endif /* __ASSEMBLY__ */ +#endif /* __CONFIG_NR5M100_NEXYS4_INCLUDE_BOARD_H */ + diff --git a/configs/nr5m100-nexys4/nsh/Make.defs b/configs/nr5m100-nexys4/nsh/Make.defs new file mode 100644 index 00000000000..190f6def749 --- /dev/null +++ b/configs/nr5m100-nexys4/nsh/Make.defs @@ -0,0 +1,114 @@ +############################################################################ +# configs/stm32f4discovery/nsh/Make.defs +# +# Copyright (C) 2011-2013 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/risc-v/src/rv32im/Toolchain.defs + +LDSCRIPT = ld.script + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mkwindeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" +else + # Linux/Cygwin-native toolchain + MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT) +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +AR = $(ARCROSSDEV)ar rcs +NM = $(ARCROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g + ASARCHCPUFLAGS += -Wa,-g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS += $(CFLAGS) -D__ASSEMBLY__ $(ASARCHCPUFLAGS) + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +ASMEXT = .S +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs -melf32lriscv +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g -melf32lriscv +endif + + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe +HOSTLDFLAGS = + diff --git a/configs/nr5m100-nexys4/nsh/defconfig b/configs/nr5m100-nexys4/nsh/defconfig new file mode 100644 index 00000000000..bfd3fc4fc2e --- /dev/null +++ b/configs/nr5m100-nexys4/nsh/defconfig @@ -0,0 +1,800 @@ +# +# Automatically generated file; DO NOT EDIT. +# Nuttx/ Configuration +# + +# +# Build Setup +# +# CONFIG_EXPERIMENTAL is not set +# CONFIG_DEFAULT_SMALL is not set +CONFIG_HOST_LINUX=y +# CONFIG_HOST_OSX is not set +# CONFIG_HOST_WINDOWS is not set +# CONFIG_HOST_OTHER is not set + +# +# Build Configuration +# +CONFIG_APPS_DIR="../apps" +CONFIG_BUILD_FLAT=y +# CONFIG_BUILD_2PASS is not set + +# +# Binary Output Formats +# +# CONFIG_RRLOAD_BINARY is not set +CONFIG_INTELHEX_BINARY=y +# CONFIG_MOTOROLA_SREC is not set +CONFIG_RAW_BINARY=y +# CONFIG_UBOOT_UIMAGE is not set + +# +# Customize Header Files +# +# CONFIG_ARCH_STDINT_H is not set +# CONFIG_ARCH_STDBOOL_H is not set +# CONFIG_ARCH_MATH_H is not set +# CONFIG_ARCH_FLOAT_H is not set +# CONFIG_ARCH_STDARG_H is not set +# CONFIG_ARCH_DEBUG_H is not set + +# +# Debug Options +# +CONFIG_DEBUG_ALERT=y +# CONFIG_DEBUG_FEATURES is not set +# CONFIG_ARCH_HAVE_STACKCHECK is not set +# CONFIG_ARCH_HAVE_HEAPCHECK is not set +CONFIG_DEBUG_SYMBOLS=y +CONFIG_ARCH_HAVE_CUSTOMOPT=y +# CONFIG_DEBUG_NOOPT is not set +# CONFIG_DEBUG_CUSTOMOPT is not set +CONFIG_DEBUG_FULLOPT=y + +# +# System Type +# +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_AVR is not set +# CONFIG_ARCH_HC is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_RGMP is not set +# CONFIG_ARCH_RENESAS is not set +CONFIG_ARCH_RISCV=y +# CONFIG_ARCH_SIM is not set +# CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_Z16 is not set +# CONFIG_ARCH_Z80 is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_CHIP="nr5m100" +# CONFIG_SERIAL_TERMIOS is not set + +# +# RISC-V Options +# +CONFIG_ARCH_CHIP_NR5M100=y +# CONFIG_ARCH_RV32I is not set +CONFIG_ARCH_RV32IM=y + +# +# RV32IM Configuration Options +# +CONFIG_RV32IM_TOOLCHAIN_GNU_RVGL=y +CONFIG_RV32IM_HW_MULDIV=y +CONFIG_RV32IM_SYSTEM_CSRRS_SUPPORT=y +# CONFIG_RV32IM_CUSTOM_IRQ_SUPPORT is not set + +# +# NanoRisc5 Configuration Options +# +CONFIG_NR5_NR5M100=y +CONFIG_NR5_NR5M1XX=y +# CONFIG_NR5_EPIC is not set + +# +# NR5 Peripheral Support +# +CONFIG_NR5_HAVE_UART1=y +CONFIG_NR5_HAVE_TIMER1=y +# CONFIG_NR5_HAVE_TIM2 is not set +# CONFIG_NR5_HAVE_I2C1 is not set +# CONFIG_NR5_HAVE_SPI1 is not set +# CONFIG_NR5_I2C1 is not set +# CONFIG_NR5_SPI1 is not set +CONFIG_NR5_TIMER1=y +CONFIG_NR5_TIMER2=y +CONFIG_NR5_UART1=y +CONFIG_NR5_UART=y +CONFIG_NR5_UART_RX_BUF_SIZE=64 +CONFIG_NR5_UART_TX_BUF_SIZE=64 + +# +# Architecture Options +# +# CONFIG_ARCH_NOINTC is not set +# CONFIG_ARCH_VECNOTIRQ is not set +# CONFIG_ARCH_DMA is not set +# CONFIG_ARCH_HAVE_IRQPRIO is not set +# CONFIG_ARCH_L2CACHE is not set +# CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set +# CONFIG_ARCH_HAVE_ADDRENV is not set +# CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set +# CONFIG_ARCH_HAVE_MULTICPU is not set +# CONFIG_ARCH_HAVE_VFORK is not set +# CONFIG_ARCH_HAVE_MMU is not set +# CONFIG_ARCH_HAVE_MPU is not set +# CONFIG_ARCH_NAND_HWECC is not set +# CONFIG_ARCH_HAVE_EXTCLK is not set +# CONFIG_ARCH_HAVE_POWEROFF is not set +# CONFIG_ARCH_HAVE_RESET is not set +CONFIG_ARCH_STACKDUMP=y +# CONFIG_ARCH_IDLE_CUSTOM is not set +# CONFIG_ARCH_HAVE_RAMFUNCS is not set +# CONFIG_ARCH_HAVE_RAMVECTORS is not set + +# +# Board Settings +# +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_ARCH_CALIBRATION=y + +# +# Interrupt options +# +CONFIG_ARCH_HAVE_INTERRUPTSTACK=y +CONFIG_ARCH_INTERRUPTSTACK=0 +# CONFIG_ARCH_HAVE_HIPRI_INTERRUPT is not set + +# +# Boot options +# +# CONFIG_BOOT_RUNFROMEXTSRAM is not set +CONFIG_BOOT_RUNFROMFLASH=y +# CONFIG_BOOT_RUNFROMISRAM is not set +# CONFIG_BOOT_RUNFROMSDRAM is not set +# CONFIG_BOOT_COPYTORAM is not set + +# +# Boot Memory Configuration +# +CONFIG_RAM_START=0x20000000 +CONFIG_RAM_SIZE=114688 +# CONFIG_ARCH_HAVE_SDRAM is not set + +# +# Board Selection +# +CONFIG_ARCH_BOARD_NR5M100_NEXYS4=y +# CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD="nr5m100-nexys4" + +# +# Common Board Options +# + +# +# Board-Specific Options +# +# CONFIG_BOARD_CRASHDUMP is not set +CONFIG_LIB_BOARDCTL=y +# CONFIG_BOARDCTL_UNIQUEID is not set +# CONFIG_BOARDCTL_TSCTEST is not set +# CONFIG_BOARDCTL_ADCTEST is not set +# CONFIG_BOARDCTL_PWMTEST is not set +# CONFIG_BOARDCTL_GRAPHICS is not set +# CONFIG_BOARDCTL_IOCTL is not set + +# +# RTOS Features +# +CONFIG_DISABLE_OS_API=y +# CONFIG_DISABLE_POSIX_TIMERS is not set +# CONFIG_DISABLE_PTHREAD is not set +# CONFIG_DISABLE_SIGNALS is not set +# CONFIG_DISABLE_MQUEUE is not set +# CONFIG_DISABLE_ENVIRON is not set + +# +# Clocks and Timers +# +CONFIG_USEC_PER_TICK=10000 +# CONFIG_SYSTEM_TIME64 is not set +# CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set +# CONFIG_JULIAN_TIME is not set +CONFIG_START_YEAR=2013 +CONFIG_START_MONTH=1 +CONFIG_START_DAY=27 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_PREALLOC_WDOGS=4 +CONFIG_WDOG_INTRESERVE=0 +CONFIG_PREALLOC_TIMERS=4 + +# +# Tasks and Scheduling +# +# CONFIG_INIT_NONE is not set +CONFIG_INIT_ENTRYPOINT=y +# CONFIG_INIT_FILEPATH is not set +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_RR_INTERVAL=200 +# CONFIG_SCHED_SPORADIC is not set +CONFIG_TASK_NAME_SIZE=0 +CONFIG_MAX_TASKS=16 +# CONFIG_SCHED_HAVE_PARENT is not set +# CONFIG_SCHED_WAITPID is not set + +# +# Pthread Options +# +# CONFIG_MUTEX_TYPES is not set +CONFIG_NPTHREAD_KEYS=4 + +# +# Performance Monitoring +# +# CONFIG_SCHED_CPULOAD is not set +# CONFIG_SCHED_INSTRUMENTATION is not set + +# +# Files and I/O +# +CONFIG_DEV_CONSOLE=y +# CONFIG_FDCLONE_DISABLE is not set +# CONFIG_FDCLONE_STDIO is not set +# CONFIG_SDCLONE_DISABLE is not set +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NAME_MAX=32 +# CONFIG_PRIORITY_INHERITANCE is not set + +# +# RTOS hooks +# +# CONFIG_BOARD_INITIALIZE is not set +# CONFIG_SCHED_STARTHOOK is not set +# CONFIG_SCHED_ATEXIT is not set +# CONFIG_SCHED_ONEXIT is not set + +# +# Signal Numbers +# +CONFIG_SIG_SIGUSR1=1 +CONFIG_SIG_SIGUSR2=2 +CONFIG_SIG_SIGALARM=3 +CONFIG_SIG_SIGCONDTIMEDOUT=16 + +# +# POSIX Message Queue Options +# +CONFIG_PREALLOC_MQ_MSGS=32 +CONFIG_MQ_MAXMSGSIZE=32 +# CONFIG_MODULE is not set + +# +# Work queue support +# +# CONFIG_SCHED_WORKQUEUE is not set +# CONFIG_SCHED_HPWORK is not set +# CONFIG_SCHED_LPWORK is not set + +# +# Stack and heap information +# +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_USERMAIN_STACKSIZE=2048 +CONFIG_PTHREAD_STACK_MIN=256 +CONFIG_PTHREAD_STACK_DEFAULT=2048 +# CONFIG_LIB_SYSCALL is not set + +# +# Device Drivers +# +CONFIG_DISABLE_POLL=y +CONFIG_DEV_NULL=y +CONFIG_DEV_ZERO=y +# CONFIG_DEV_URANDOM is not set +# CONFIG_DEV_LOOP is not set + +# +# Buffering +# +# CONFIG_DRVR_WRITEBUFFER is not set +# CONFIG_DRVR_READAHEAD is not set +# CONFIG_RAMDISK is not set +# CONFIG_CAN is not set +# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set +# CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set +# CONFIG_PWM is not set +# CONFIG_ARCH_HAVE_I2CRESET is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set +# CONFIG_I2S is not set + +# +# Timer Driver Support +# +# CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set +# CONFIG_RTC is not set +# CONFIG_WATCHDOG is not set +# CONFIG_ANALOG is not set +# CONFIG_AUDIO_DEVICES is not set +# CONFIG_VIDEO_DEVICES is not set +# CONFIG_BCH is not set +# CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# +# CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set + +# +# LCD Driver Support +# +# CONFIG_LCD is not set +# CONFIG_SLCD is not set + +# +# LED Support +# +# CONFIG_RGBLED is not set +# CONFIG_PCA9635PW is not set +# CONFIG_NCP5623C is not set +# CONFIG_MMCSD is not set +# CONFIG_MODEM is not set +# CONFIG_MTD is not set +# CONFIG_EEPROM is not set +# CONFIG_PIPES is not set +# CONFIG_PM is not set +# CONFIG_POWER is not set +# CONFIG_SENSORS is not set +# CONFIG_SERCOMM_CONSOLE is not set +CONFIG_SERIAL=y +# CONFIG_DEV_LOWCONSOLE is not set +# CONFIG_SERIAL_REMOVABLE is not set +CONFIG_SERIAL_CONSOLE=y +# CONFIG_16550_UART is not set +CONFIG_UART_SERIALDRIVER=y +# CONFIG_UART0_SERIALDRIVER is not set +CONFIG_UART1_SERIALDRIVER=y +# CONFIG_UART2_SERIALDRIVER is not set +# CONFIG_UART3_SERIALDRIVER is not set +# CONFIG_UART4_SERIALDRIVER is not set +# CONFIG_UART5_SERIALDRIVER is not set +# CONFIG_UART6_SERIALDRIVER is not set +# CONFIG_UART7_SERIALDRIVER is not set +# CONFIG_UART8_SERIALDRIVER is not set +# CONFIG_SCI0_SERIALDRIVER is not set +# CONFIG_SCI1_SERIALDRIVER is not set +# CONFIG_USART0_SERIALDRIVER is not set +# CONFIG_USART1_SERIALDRIVER is not set +# CONFIG_USART2_SERIALDRIVER is not set +# CONFIG_USART3_SERIALDRIVER is not set +# CONFIG_USART4_SERIALDRIVER is not set +# CONFIG_USART5_SERIALDRIVER is not set +# CONFIG_USART6_SERIALDRIVER is not set +# CONFIG_USART7_SERIALDRIVER is not set +# CONFIG_USART8_SERIALDRIVER is not set +# CONFIG_OTHER_UART_SERIALDRIVER is not set +CONFIG_MCU_SERIAL=y +# CONFIG_STANDARD_SERIAL is not set +# CONFIG_SERIAL_IFLOWCONTROL is not set +# CONFIG_SERIAL_OFLOWCONTROL is not set +# CONFIG_SERIAL_DMA is not set +CONFIG_ARCH_HAVE_SERIAL_TERMIOS=y +# CONFIG_UART_SERIAL_CONSOLE is not set +CONFIG_UART1_SERIAL_CONSOLE=y +# CONFIG_OTHER_SERIAL_CONSOLE is not set +# CONFIG_NO_SERIAL_CONSOLE is not set + +# +# UART Configuration +# +CONFIG_UART_RXBUFSIZE=256 +CONFIG_UART_TXBUFSIZE=256 +CONFIG_UART_BAUD=115200 +CONFIG_UART_BITS=8 +CONFIG_UART_PARITY=0 +CONFIG_UART_2STOP=0 +# CONFIG_UART_IFLOWCONTROL is not set +# CONFIG_UART_OFLOWCONTROL is not set +# CONFIG_UART_DMA is not set + +# +# UART1 Configuration +# +CONFIG_UART1_RXBUFSIZE=256 +CONFIG_UART1_TXBUFSIZE=256 +CONFIG_UART1_BAUD=115200 +CONFIG_UART1_BITS=8 +CONFIG_UART1_PARITY=0 +CONFIG_UART1_2STOP=0 +# CONFIG_UART1_IFLOWCONTROL is not set +# CONFIG_UART1_OFLOWCONTROL is not set +# CONFIG_UART1_DMA is not set +# CONFIG_PSEUDOTERM is not set +# CONFIG_USBDEV is not set +# CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set +# CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set + +# +# System Logging +# +# CONFIG_ARCH_SYSLOG is not set +# CONFIG_RAMLOG is not set +# CONFIG_SYSLOG_INTBUFFER is not set +# CONFIG_SYSLOG_TIMESTAMP is not set +# CONFIG_SYSLOG_SERIAL_CONSOLE is not set +# CONFIG_SYSLOG_CHAR is not set +# CONFIG_SYSLOG_CONSOLE is not set +CONFIG_SYSLOG_NONE=y +# CONFIG_SYSLOG_FILE is not set +# CONFIG_CONSOLE_SYSLOG is not set +# CONFIG_SYSLOG_CHARDEV is not set + +# +# Networking Support +# +# CONFIG_ARCH_HAVE_NET is not set +# CONFIG_ARCH_HAVE_PHY is not set +# CONFIG_NET is not set + +# +# Crypto API +# +# CONFIG_CRYPTO is not set + +# +# File Systems +# + +# +# File system configuration +# +# CONFIG_DISABLE_MOUNTPOINT is not set +# CONFIG_FS_AUTOMOUNTER is not set +# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set +# CONFIG_FS_READABLE is not set +CONFIG_FS_WRITABLE=y +# CONFIG_FS_NAMED_SEMAPHORES is not set +CONFIG_FS_MQUEUE_MPATH="/var/mqueue" +# CONFIG_FS_RAMMAP is not set +# CONFIG_FS_FAT is not set +# CONFIG_FS_NXFFS is not set +# CONFIG_FS_ROMFS is not set +# CONFIG_FS_TMPFS is not set +# CONFIG_FS_SMARTFS is not set +# CONFIG_FS_BINFS is not set +# CONFIG_FS_PROCFS is not set +# CONFIG_FS_UNIONFS is not set + +# +# Graphics Support +# +# CONFIG_NX is not set + +# +# Memory Management +# +# CONFIG_MM_SMALL is not set +CONFIG_MM_REGIONS=1 +# CONFIG_ARCH_HAVE_HEAP2 is not set +# CONFIG_GRAN is not set + +# +# Audio Support +# +# CONFIG_AUDIO is not set + +# +# Wireless Support +# + +# +# Binary Loader +# +# CONFIG_BINFMT_DISABLE is not set +# CONFIG_BINFMT_EXEPATH is not set +# CONFIG_NXFLAT is not set +# CONFIG_ELF is not set +CONFIG_BUILTIN=y +# CONFIG_PIC is not set +# CONFIG_SYMTAB_ORDEREDBYNAME is not set + +# +# Library Routines +# + +# +# Standard C Library Options +# +CONFIG_STDIO_BUFFER_SIZE=64 +CONFIG_STDIO_LINEBUFFER=y +CONFIG_NUNGET_CHARS=2 +CONFIG_LIB_HOMEDIR="/" +# CONFIG_LIBM is not set +# CONFIG_NOPRINTF_FIELDWIDTH is not set +# CONFIG_LIBC_FLOATINGPOINT is not set +CONFIG_LIBC_LONG_LONG=y +# CONFIG_LIBC_IOCTL_VARIADIC is not set +CONFIG_LIB_RAND_ORDER=1 +# CONFIG_EOL_IS_CR is not set +# CONFIG_EOL_IS_LF is not set +# CONFIG_EOL_IS_BOTH_CRLF is not set +CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_LIBC_EXECFUNCS is not set +CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 +CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 +CONFIG_LIBC_STRERROR=y +# CONFIG_LIBC_STRERROR_SHORT is not set +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_TMPDIR="/tmp" +CONFIG_LIBC_MAX_TMPFILE=32 +CONFIG_ARCH_LOWPUTC=y +# CONFIG_LIBC_LOCALTIME is not set +# CONFIG_TIME_EXTENDED is not set +CONFIG_LIB_SENDFILE_BUFSIZE=512 +# CONFIG_ARCH_ROMGETC is not set +# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set +# CONFIG_ARCH_HAVE_TLS is not set +# CONFIG_LIBC_NETDB is not set + +# +# Non-standard Library Support +# +# CONFIG_LIB_CRC64_FAST is not set +# CONFIG_LIB_KBDCODEC is not set +# CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set + +# +# Basic CXX Support +# +# CONFIG_C99_BOOL8 is not set +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +# CONFIG_CXX_NEWLONG is not set + +# +# uClibc++ Standard C++ Library +# +# CONFIG_UCLIBCXX is not set + +# +# Application Configuration +# + +# +# Built-In Applications +# +CONFIG_BUILTIN_PROXY_STACKSIZE=1024 + +# +# CAN Utilities +# + +# +# Examples +# +# CONFIG_EXAMPLES_CHAT is not set +# CONFIG_EXAMPLES_CONFIGDATA is not set +# CONFIG_EXAMPLES_CXXTEST is not set +# CONFIG_EXAMPLES_DHCPD is not set +# CONFIG_EXAMPLES_ELF is not set +# CONFIG_EXAMPLES_FTPC is not set +# CONFIG_EXAMPLES_FTPD is not set +# CONFIG_EXAMPLES_HELLO is not set +# CONFIG_EXAMPLES_HELLOXX is not set +# CONFIG_EXAMPLES_HIDKBD is not set +# CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_KEYPADTEST is not set +# CONFIG_EXAMPLES_MEDIA is not set +# CONFIG_EXAMPLES_MM is not set +# CONFIG_EXAMPLES_MODBUS is not set +# CONFIG_EXAMPLES_MOUNT is not set +# CONFIG_EXAMPLES_NRF24L01TERM is not set +CONFIG_EXAMPLES_NSH=y +CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y +# CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NXFFS is not set +# CONFIG_EXAMPLES_NXHELLO is not set +# CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NX is not set +# CONFIG_EXAMPLES_NXLINES is not set +# CONFIG_EXAMPLES_NXTERM is not set +# CONFIG_EXAMPLES_NXTEXT is not set +# CONFIG_EXAMPLES_OSTEST is not set +# CONFIG_EXAMPLES_PCA9635 is not set +# CONFIG_EXAMPLES_POSIXSPAWN is not set +# CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set +# CONFIG_EXAMPLES_RGBLED is not set +# CONFIG_EXAMPLES_RGMP is not set +# CONFIG_EXAMPLES_SENDMAIL is not set +# CONFIG_EXAMPLES_SERIALBLASTER is not set +# CONFIG_EXAMPLES_SERIALRX is not set +# CONFIG_EXAMPLES_SERLOOP is not set +# CONFIG_EXAMPLES_SLCD is not set +# CONFIG_EXAMPLES_SMART is not set +# CONFIG_EXAMPLES_SMART_TEST is not set +# CONFIG_EXAMPLES_SMP is not set +# CONFIG_EXAMPLES_TCPECHO is not set +# CONFIG_EXAMPLES_TELNETD is not set +# CONFIG_EXAMPLES_TIFF is not set +# CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_USBSERIAL is not set +# CONFIG_EXAMPLES_USBTERM is not set +# CONFIG_EXAMPLES_WATCHDOG is not set +# CONFIG_EXAMPLES_WEBSERVER is not set + +# +# File System Utilities +# +# CONFIG_FSUTILS_INIFILE is not set + +# +# GPS Utilities +# +# CONFIG_GPSUTILS_MINMEA_LIB is not set + +# +# Graphics Support +# +# CONFIG_TIFF is not set +# CONFIG_GRAPHICS_TRAVELER is not set + +# +# Interpreters +# +# CONFIG_INTERPRETERS_FICL is not set +# CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set +# CONFIG_INTERPRETERS_PCODE is not set + +# +# FreeModBus +# +# CONFIG_MODBUS is not set + +# +# Network Utilities +# +# CONFIG_NETUTILS_CODECS is not set +# CONFIG_NETUTILS_ESP8266 is not set +# CONFIG_NETUTILS_FTPC is not set +# CONFIG_NETUTILS_JSON is not set +# CONFIG_NETUTILS_SMTP is not set + +# +# NSH Library +# +CONFIG_NSH_LIBRARY=y +# CONFIG_NSH_MOTD is not set + +# +# Command Line Configuration +# +CONFIG_NSH_READLINE=y +# CONFIG_NSH_CLE is not set +CONFIG_NSH_LINELEN=64 +# CONFIG_NSH_DISABLE_SEMICOLON is not set +CONFIG_NSH_CMDPARMS=y +CONFIG_NSH_MAXARGUMENTS=6 +CONFIG_NSH_ARGCAT=y +CONFIG_NSH_NESTDEPTH=3 +# CONFIG_NSH_DISABLEBG is not set +CONFIG_NSH_BUILTIN_APPS=y + +# +# Disable Individual commands +# +# CONFIG_NSH_DISABLE_ADDROUTE is not set +# CONFIG_NSH_DISABLE_BASENAME is not set +# CONFIG_NSH_DISABLE_CAT is not set +# CONFIG_NSH_DISABLE_CD is not set +# CONFIG_NSH_DISABLE_CP is not set +# CONFIG_NSH_DISABLE_CMP is not set +CONFIG_NSH_DISABLE_DATE=y +# CONFIG_NSH_DISABLE_DD is not set +# CONFIG_NSH_DISABLE_DF is not set +# CONFIG_NSH_DISABLE_DELROUTE is not set +# CONFIG_NSH_DISABLE_DIRNAME is not set +# CONFIG_NSH_DISABLE_ECHO is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_FREE is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HELP is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +CONFIG_NSH_DISABLE_IFUPDOWN=y +# CONFIG_NSH_DISABLE_KILL is not set +# CONFIG_NSH_DISABLE_LOSETUP is not set +# CONFIG_NSH_DISABLE_LOSMART is not set +# CONFIG_NSH_DISABLE_LS is not set +# CONFIG_NSH_DISABLE_MB is not set +# CONFIG_NSH_DISABLE_MKDIR is not set +CONFIG_NSH_DISABLE_MKRD=y +# CONFIG_NSH_DISABLE_MH is not set +# CONFIG_NSH_DISABLE_MOUNT is not set +# CONFIG_NSH_DISABLE_MV is not set +# CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_PWD is not set +# CONFIG_NSH_DISABLE_RM is not set +# CONFIG_NSH_DISABLE_RMDIR is not set +# CONFIG_NSH_DISABLE_SET is not set +# CONFIG_NSH_DISABLE_SH is not set +# CONFIG_NSH_DISABLE_SLEEP is not set +# CONFIG_NSH_DISABLE_TIME is not set +# CONFIG_NSH_DISABLE_TEST is not set +# CONFIG_NSH_DISABLE_UMOUNT is not set +# CONFIG_NSH_DISABLE_UNAME is not set +# CONFIG_NSH_DISABLE_UNSET is not set +# CONFIG_NSH_DISABLE_USLEEP is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 + +# +# Configure Command Options +# +CONFIG_NSH_CMDOPT_DF_H=y +CONFIG_NSH_CODECS_BUFSIZE=128 +CONFIG_NSH_CMDOPT_HEXDUMP=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_STRERROR=y + +# +# Scripting Support +# +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_ITEF is not set +# CONFIG_NSH_DISABLE_LOOPS is not set + +# +# Console Configuration +# +CONFIG_NSH_CONSOLE=y +# CONFIG_NSH_ALTCONDEV is not set +CONFIG_NSH_ARCHINIT=y +# CONFIG_NSH_LOGIN is not set +# CONFIG_NSH_CONSOLE_LOGIN is not set + +# +# NxWidgets/NxWM +# + +# +# Platform-specific Support +# +# CONFIG_PLATFORM_CONFIGDATA is not set + +# +# System Libraries and NSH Add-Ons +# +# CONFIG_SYSTEM_CLE is not set +# CONFIG_SYSTEM_CUTERM is not set +# CONFIG_SYSTEM_FREE is not set +# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_SYSTEM_HEXED is not set +# CONFIG_SYSTEM_INSTALL is not set +# CONFIG_SYSTEM_RAMTEST is not set +CONFIG_READLINE_HAVE_EXTMATCH=y +CONFIG_SYSTEM_READLINE=y +CONFIG_READLINE_ECHO=y +# CONFIG_READLINE_TABCOMPLETION is not set +# CONFIG_READLINE_CMD_HISTORY is not set +# CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set +# CONFIG_SYSTEM_UBLOXMODEM is not set +# CONFIG_SYSTEM_VI is not set +# CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/nr5m100-nexys4/nsh/setenv.sh b/configs/nr5m100-nexys4/nsh/setenv.sh new file mode 100644 index 00000000000..83220855967 --- /dev/null +++ b/configs/nr5m100-nexys4/nsh/setenv.sh @@ -0,0 +1,45 @@ +#!/bin/bash +# configs/nr5m100-nexys4/nsh/setenv.sh +# +# Copyright (C) 2008 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +if [ "$(basename $0)" = "setenv.sh" ] ; then + echo "You must source this script, not run it!" 1>&2 + exit 1 +fi + +if [ -z ${PATH_ORIG} ]; then export PATH_ORIG=${PATH}; fi + +#export NUTTX_BIN= +#export PATH=${NUTTX_BIN}:/sbin:/usr/sbin:${PATH_ORIG} + +echo "PATH : ${PATH}" diff --git a/configs/nr5m100-nexys4/scripts/ld.script b/configs/nr5m100-nexys4/scripts/ld.script new file mode 100644 index 00000000000..df856beb23d --- /dev/null +++ b/configs/nr5m100-nexys4/scripts/ld.script @@ -0,0 +1,305 @@ +/**************************************************************************** + * configs/nr5m100-nexys4/scripts/ld.script + * + * Copyright (C) 2011-2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2016 Ken Pettit. + * Author: Gregory Nutt + * Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/*======================================================================*/ +/* Linker script for nr5m100_nexys board */ +/*======================================================================*/ + +/*----------------------------------------------------------------------*/ +/* Setup */ +/*----------------------------------------------------------------------*/ + +/* The OUTPUT_ARCH command specifies the machine architecture where the + argument is one of the names used in the BFD library. More + specifically one of the entires in bfd/cpu-mips.c */ + +OUTPUT_ARCH( "riscv" ) + +/* Define the memory regions were we put stuff */ +MEMORY +{ + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 384K +} + +stack_size = 4096; + +/* Define the beginning and ending stack */ +__stack_start = ORIGIN(sram) + LENGTH(sram); +__stack_end = __stack_start - stack_size; + + +/* The ENTRY command specifies the entry point (ie. first instruction to + execute). The symbol _start is defined in crt0.S */ + +ENTRY( __reset ) + +/* The GROUP command is special since the listed archives will be + searched repeatedly until there are no new undefined references. We + need this since -lc depends on -lgloss and -lgloss depends on -lc. I + thought gcc would automatically include -lgcc when needed, but + idt32.ld includes it explicitly here and I was seeing link errors + without it. */ + +/*GROUP( -lc -lgloss -lgcc ) */ +GROUP( -lc ) + +/*----------------------------------------------------------------------*/ +/* Sections */ +/*----------------------------------------------------------------------*/ +/* This is where we specify how the input sections map to output + sections. The .= commands set the location counter, and the + sections are inserted in increasing address order according to the + location counter. The following statement will take all of the .bar + input sections and reloate them into the .foo output section which + starts at address 0x1000. + + . = 0.x1000; + .foo : { *(.bar) } + + If we wrap an input specification with a KEEP command then it + prevents it from being eliminted during "link-time garbage + collection". I'm not sure what this is, so I just followed what was + done in idt32.ld. + + We can also set a global external symbol to a specific address in the + output binary with this syntax: + + _etext = .; + PROVIDE( etext = . ); + + This will set the global symbol _ftext to the current location. If we + wrap this in a PROVIDE commad, the symbol will only be set if it is + not defined. We do this with symbols which don't begin with an + underscore since technically in ansi C someone might have a function + with the same name (eg. etext). + + If we need to label the beginning of a section we need to make sure + that the linker doesn't insert an orphan section inbetween where we + set the symbol and the actual begining of the section. We can do that + by assigning the location dot to itself. + + . = . + _ftext = .; + .text : + { } + + */ + +SECTIONS +{ + + /*--------------------------------------------------------------------*/ + /* Startup vectors + /*--------------------------------------------------------------------*/ + . = 0x20000000; + _vectors = .; + + /* vectors: Program code section */ + .vectors : + { + *(.text.vec) + *(.text.vec.*) + *(.gnu.linkonce.t.*) + } + _evectors = .; + + /*--------------------------------------------------------------------*/ + /* Code and read-only segment */ + /*--------------------------------------------------------------------*/ + + /* Begining of code and text segment */ + . = 0x20000030; + _ftext = .; + PROVIDE( eprol = . ); + + /* text: Program code section */ + .text : + { + _stext = ABSOLUTE(.); + *(.text) + *(.text.*) + *(.gnu.linkonce.t.*) + } + + /* init: Code to execute before main (called by crt0.S) */ + .init : + { + KEEP( *(.init) ) + } + + /* fini: Code to execute after main (called by crt0.S) */ + .fini : + { + KEEP( *(.fini) ) + } + + /* rodata: Read-only data */ + _rodata = .; + .rodata : + { + *(.rdata) + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r.*) + } + + /* End of code and read-only segment */ + PROVIDE( etext = . ); + _etext = .; + + /*--------------------------------------------------------------------*/ + /* Global constructor/destructor segement */ + /*--------------------------------------------------------------------*/ + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array )) + PROVIDE_HIDDEN (__init_array_end = .); + } + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array )) + PROVIDE_HIDDEN (__fini_array_end = .); + } + + /*--------------------------------------------------------------------*/ + /* Other misc gcc segments (this was in idt32.ld) */ + /*--------------------------------------------------------------------*/ + /* I am not quite sure about these sections but it seems they are for + C++ exception handling. I think .jcr is for "Java Class + Registration" but it seems to end up in C++ binaries as well. */ + + .eh_frame_hdr : { *(.eh_frame_hdr) } + .eh_frame : { KEEP( *(.eh_frame) ) } + .gcc_except_table : { *(.gcc_except_table) } + .jcr : { KEEP (*(.jcr)) } + + /*--------------------------------------------------------------------*/ + /* Initialized data segment */ + /*--------------------------------------------------------------------*/ + + /* Start of initialized data segment */ + . = ALIGN(16); + _fdata = .; + + /* data: Writable data */ + _sdata = .; + .data : + { + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + } + + /* End of initialized data segment */ + PROVIDE( edata = . ); + _edata = .; + + /* Have _gp point to middle of sdata/sbss to maximize displacement range */ + . = ALIGN(16); + _gp = . + 0x7FF0; + + /* Writable small data segment */ + .sdata : + { + *(.sdata) + *(.sdata.*) + *(.srodata.*) + . = ALIGN(16); + *(.gnu.linkonce.s.*) + } + + /*--------------------------------------------------------------------*/ + /* Uninitialized data segment */ + /*--------------------------------------------------------------------*/ + + /* Start of uninitialized data segment */ + . = ALIGN(8); + _fbss = .; + + /* Writable uninitialized small data segment */ + .sbss : + { + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + } + + /* bss: Uninitialized writeable data section */ + . = .; + _bss_start = .; + .bss : + { + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + } + _bss_end = .; + _ebss = .; + + /* End of uninitialized data segment (used by syscalls.c for heap) */ + . = ALIGN(16); + PROVIDE( end = . ); + _end = ALIGN(16); + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/configs/nr5m100-nexys4/scripts/nr5m1xx.cfg b/configs/nr5m100-nexys4/scripts/nr5m1xx.cfg new file mode 100644 index 00000000000..9218333b820 --- /dev/null +++ b/configs/nr5m100-nexys4/scripts/nr5m1xx.cfg @@ -0,0 +1,64 @@ +############################################################################ +# configs/nr5m100-nexys4/scripts/nr5m1xx.cfg +# +# Copyright (C) 2016 Ken Pettit. All rights reserved. +# Author: Ken Pettit +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +proc init_board {} { + reset_config srst_only +} + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME nr5m1xx +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x1f40092d +} + +jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x5 -irmask 0x1f -expected-id $_CPUTAPID +set _TARGETNAME $_CHIPNAME.cpu + +target create $_TARGETNAME riscv -endian $_ENDIAN -chain-position $_TARGETNAME + +$_TARGETNAME configure -work-area-phys 0x20018000 -work-area-size 0x2000 -work-area-backup 0 + diff --git a/configs/nr5m100-nexys4/scripts/openocd.cfg b/configs/nr5m100-nexys4/scripts/openocd.cfg new file mode 100644 index 00000000000..ea4564d84e0 --- /dev/null +++ b/configs/nr5m100-nexys4/scripts/openocd.cfg @@ -0,0 +1,61 @@ +############################################################################ +# configs/nr5m100-nexys4/scripts/openocd.cfg +# +# Copyright (C) 2016 Ken Pettit. All rights reserved. +# Author: Ken Pettit +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +#====================================== +# +# Define the interface +# +#===================================== + +interface jlink +adapter_khz 2000 + +#====================================== +# +# Define the target +# +#===================================== + +source [find nr5m1xx.cfg] + +#====================================== +# +# Init and halt the processor +# +#===================================== + +init +reset halt + diff --git a/configs/nr5m100-nexys4/src/Makefile b/configs/nr5m100-nexys4/src/Makefile new file mode 100644 index 00000000000..66a28f1b001 --- /dev/null +++ b/configs/nr5m100-nexys4/src/Makefile @@ -0,0 +1,90 @@ +############################################################################ +# configs/nr5m100-nexys4/src/Makefile +# +# Copyright (C) 2016 Ken Pettit. All rights reserved. +# Author: Ken Pettit +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +-include $(TOPDIR)/Make.defs + +ASRCS = +AOBJS = $(ASRCS:.S=$(OBJEXT)) + +CSRCS = nr5_appinit.c nr5_boot.c nr5_autoleds.c + +ifeq ($(CONFIG_ARCH_BOARD_NR5_CUSTOM_CLOCKCONFIG),y) +CSRCS += nr5_clockconfig.c +endif + +COBJS = $(CSRCS:.c=$(OBJEXT)) + +SRCS = $(ASRCS) $(CSRCS) +OBJS = $(AOBJS) $(COBJS) + +ARCH_SRCDIR = $(TOPDIR)/arch/$(CONFIG_ARCH)/src +ifeq ($(CONFIG_WINDOWS_NATIVE),y) + CFLAGS += -I$(ARCH_SRCDIR) -I$(ARCH_SRCDIR)\common -I$(ARCH_SRCDIR)\rv32im +else +ifeq ($(WINTOOL),y) + CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/chip}" \ + -I "${shell cygpath -w $(ARCH_SRCDIR)/common}" \ + -I "${shell cygpath -w $(ARCH_SRCDIR)/armv7-m}" +else + CFLAGS += -I$(ARCH_SRCDIR)/$(CONFIG_ARCH_CHIP) -I$(ARCH_SRCDIR)/common -I$(ARCH_SRCDIR)/rv32im +endif +endif + +all: libboard$(LIBEXT) + +$(AOBJS): %$(OBJEXT): %.S + $(call ASSEMBLE, $<, $@) + +$(COBJS) $(LINKOBJS): %$(OBJEXT): %.c + $(call COMPILE, $<, $@) + +libboard$(LIBEXT): $(OBJS) + $(call ARCHIVE, $@, $(OBJS)) + +.depend: Makefile $(SRCS) + $(Q) $(MKDEP) $(CC) -- $(CFLAGS) -- $(SRCS) >Make.dep + $(Q) touch $@ + +depend: .depend + +clean: + $(call DELFILE, libboard$(LIBEXT)) + $(call CLEAN) + +distclean: clean + $(call DELFILE, Make.dep) + $(call DELFILE, .depend) + +-include Make.dep diff --git a/configs/nr5m100-nexys4/src/nr5_appinit.c b/configs/nr5m100-nexys4/src/nr5_appinit.c new file mode 100644 index 00000000000..861f1d44a8a --- /dev/null +++ b/configs/nr5m100-nexys4/src/nr5_appinit.c @@ -0,0 +1,86 @@ +/**************************************************************************** + * config/nr5m100-nexys4/src/nr5_appinit.c + * + * Copyright (C) 2012-2013, 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "nr5.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform architecture specific initialization + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initalization logic and the the + * matching application logic. The value cold be such things as a + * mode enumeration value, a set of DIP switch switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ + + return OK; +} diff --git a/configs/nr5m100-nexys4/src/nr5_autoleds.c b/configs/nr5m100-nexys4/src/nr5_autoleds.c new file mode 100644 index 00000000000..a35a6331cc5 --- /dev/null +++ b/configs/nr5m100-nexys4/src/nr5_autoleds.c @@ -0,0 +1,71 @@ +/************************************************************************************ + * configs/nr5m100_nexys4/src/nr5_autoleds.c + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: board_autoled_on + * + * Description: + * All NR5 architectures must provide the following entry point. This entry point + * is called early in the intitialization -- after all memory has been configured + * and mapped but before any devices have been initialized. + * + ************************************************************************************/ + +void board_autoled_on(int led) +{ + +} diff --git a/configs/nr5m100-nexys4/src/nr5_boot.c b/configs/nr5m100-nexys4/src/nr5_boot.c new file mode 100644 index 00000000000..a98722566c4 --- /dev/null +++ b/configs/nr5m100-nexys4/src/nr5_boot.c @@ -0,0 +1,70 @@ +/************************************************************************************ + * configs/nr5m100_nexys4/src/nr5_boot.c + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: nr5_boardinitialize + * + * Description: + * All NR5 architectures must provide the following entry point. This entry point + * is called early in the intitialization -- after all memory has been configured + * and mapped but before any devices have been initialized. + * + ************************************************************************************/ + +void nr5_boardinitialize(void) +{ +}