From 1ea22b680d7ed5a87412128103e9ec88c74e7d23 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 21 Oct 2016 13:23:28 -0600 Subject: [PATCH] Xtensa: Add timer dispatch logic --- arch/xtensa/include/esp32/irq.h | 150 ++++++++++---------- arch/xtensa/src/common/xtensa_inthandlers.S | 24 ++-- 2 files changed, 88 insertions(+), 86 deletions(-) diff --git a/arch/xtensa/include/esp32/irq.h b/arch/xtensa/include/esp32/irq.h index 1dadb66b89c..b394e8d6ba6 100644 --- a/arch/xtensa/include/esp32/irq.h +++ b/arch/xtensa/include/esp32/irq.h @@ -69,6 +69,10 @@ * is still to be determined what will be done for the the ESP32. */ +#define XTENSA_IRQ_TIMER0 0 /* INTERRUPT, bit 6 */ +#define XTENSA_IRQ_TIMER1 1 /* INTERRUPT, bit 15 */ +#define XTENSA_IRQ_TIMER2 2 /* INTERRUPT, bit 16 */ + /* Interrupt Matrix * * The Interrupt Matrix embedded in the ESP32 independently allocates @@ -98,94 +102,94 @@ /* PRO_INTR_STATUS_REG_0 / APP_INTR_STATUS_REG_0 */ -#define XTENSA_IRQ_SREG0 0 -#define XTENSA_IRQ_MAC 0 /* INTR_STATUS_REG_0, bit 0 */ -#define XTENSA_IRQ_MAC_NMI 1 /* INTR_STATUS_REG_0, bit 1 */ -#define XTENSA_IRQ_BB 2 /* INTR_STATUS_REG_0, bit 2 */ -#define XTENSA_IRQ_BB_MAC 3 /* INTR_STATUS_REG_0, bit 3 */ -#define XTENSA_IRQ_BT_BB 4 /* INTR_STATUS_REG_0, bit 4 */ -#define XTENSA_IRQ_BT_BB_NMI 5 /* INTR_STATUS_REG_0, bit 5 */ -#define XTENSA_IRQ_RWBT_IRQ 6 /* INTR_STATUS_REG_0, bit 6 */ -#define XTENSA_IRQ_RWBLE_IRQ 7 /* INTR_STATUS_REG_0, bit 7 */ -#define XTENSA_IRQ_RWBT_NMI 8 /* INTR_STATUS_REG_0, bit 8 */ -#define XTENSA_IRQ_RWBLE_NMI 9 /* INTR_STATUS_REG_0, bit 9 */ +#define XTENSA_IRQ_SREG0 3 +#define XTENSA_IRQ_MAC 3 /* INTR_STATUS_REG_0, bit 0 */ +#define XTENSA_IRQ_MAC_NMI 4 /* INTR_STATUS_REG_0, bit 1 */ +#define XTENSA_IRQ_BB 5 /* INTR_STATUS_REG_0, bit 2 */ +#define XTENSA_IRQ_BB_MAC 6 /* INTR_STATUS_REG_0, bit 3 */ +#define XTENSA_IRQ_BT_BB 7 /* INTR_STATUS_REG_0, bit 4 */ +#define XTENSA_IRQ_BT_BB_NMI 8 /* INTR_STATUS_REG_0, bit 5 */ +#define XTENSA_IRQ_RWBT_IRQ 9 /* INTR_STATUS_REG_0, bit 6 */ +#define XTENSA_IRQ_RWBLE_IRQ 10 /* INTR_STATUS_REG_0, bit 7 */ +#define XTENSA_IRQ_RWBT_NMI 11 /* INTR_STATUS_REG_0, bit 8 */ +#define XTENSA_IRQ_RWBLE_NMI 12 /* INTR_STATUS_REG_0, bit 9 */ -#define XTENSA_IRQ_SLC0 10 /* INTR_STATUS_REG_0, bit 10 */ -#define XTENSA_IRQ_SLC1 11 /* INTR_STATUS_REG_0, bit 11 */ -#define XTENSA_IRQ_UHCI0 12 /* INTR_STATUS_REG_0, bit 12 */ -#define XTENSA_IRQ_UHCI1 13 /* INTR_STATUS_REG_0, bit 13 */ -#define XTENSA_IRQ_TG_T0_LEVEL 14 /* INTR_STATUS_REG_0, bit 14 */ -#define XTENSA_IRQ_TG_T1_LEVEL 15 /* INTR_STATUS_REG_0, bit 15 */ -#define XTENSA_IRQ_TG_WDT_LEVEL 16 /* INTR_STATUS_REG_0, bit 16 */ -#define XTENSA_IRQ_TG_LACT_LEVEL 17 /* INTR_STATUS_REG_0, bit 17 */ -#define XTENSA_IRQ_TG1_T0_LEVEL 18 /* INTR_STATUS_REG_0, bit 18 */ -#define XTENSA_IRQ_TG1_T1_LEVEL 19 /* INTR_STATUS_REG_0, bit 19 */ +#define XTENSA_IRQ_SLC0 13 /* INTR_STATUS_REG_0, bit 10 */ +#define XTENSA_IRQ_SLC1 14 /* INTR_STATUS_REG_0, bit 11 */ +#define XTENSA_IRQ_UHCI0 15 /* INTR_STATUS_REG_0, bit 12 */ +#define XTENSA_IRQ_UHCI1 16 /* INTR_STATUS_REG_0, bit 13 */ +#define XTENSA_IRQ_TG_T0_LEVEL 17 /* INTR_STATUS_REG_0, bit 14 */ +#define XTENSA_IRQ_TG_T1_LEVEL 18 /* INTR_STATUS_REG_0, bit 15 */ +#define XTENSA_IRQ_TG_WDT_LEVEL 19 /* INTR_STATUS_REG_0, bit 16 */ +#define XTENSA_IRQ_TG_LACT_LEVEL 20 /* INTR_STATUS_REG_0, bit 17 */ +#define XTENSA_IRQ_TG1_T0_LEVEL 21 /* INTR_STATUS_REG_0, bit 18 */ +#define XTENSA_IRQ_TG1_T1_LEVEL 22 /* INTR_STATUS_REG_0, bit 19 */ -#define XTENSA_IRQ_TG1_WDT_LEVEL 20 /* INTR_STATUS_REG_0, bit 20 */ -#define XTENSA_IRQ_G1_LACT_LEVEL 21 /* INTR_STATUS_REG_0, bit 21 */ -#define XTENSA_IRQ_CPU_GPIO 22 /* INTR_STATUS_REG_0, bit 22 */ -#define XTENSA_IRQ_CPU_NMI 23 /* INTR_STATUS_REG_0, bit 23 */ -#define XTENSA_IRQ_CPU_CPU0 24 /* INTR_STATUS_REG_0, bit 24 */ -#define XTENSA_IRQ_CPU_CPU1 25 /* INTR_STATUS_REG_0, bit 25 */ -#define XTENSA_IRQ_CPU_CPU2 26 /* INTR_STATUS_REG_0, bit 26 */ -#define XTENSA_IRQ_CPU_CPU3 27 /* INTR_STATUS_REG_0, bit 27 */ -#define XTENSA_IRQ_SPI0 28 /* INTR_STATUS_REG_0, bit 28 */ -#define XTENSA_IRQ_SPI1 29 /* INTR_STATUS_REG_0, bit 29 */ +#define XTENSA_IRQ_TG1_WDT_LEVEL 23 /* INTR_STATUS_REG_0, bit 20 */ +#define XTENSA_IRQ_G1_LACT_LEVEL 24 /* INTR_STATUS_REG_0, bit 21 */ +#define XTENSA_IRQ_CPU_GPIO 25 /* INTR_STATUS_REG_0, bit 22 */ +#define XTENSA_IRQ_CPU_NMI 26 /* INTR_STATUS_REG_0, bit 23 */ +#define XTENSA_IRQ_CPU_CPU0 27 /* INTR_STATUS_REG_0, bit 24 */ +#define XTENSA_IRQ_CPU_CPU1 28 /* INTR_STATUS_REG_0, bit 25 */ +#define XTENSA_IRQ_CPU_CPU2 29 /* INTR_STATUS_REG_0, bit 26 */ +#define XTENSA_IRQ_CPU_CPU3 30 /* INTR_STATUS_REG_0, bit 27 */ +#define XTENSA_IRQ_SPI0 31 /* INTR_STATUS_REG_0, bit 28 */ +#define XTENSA_IRQ_SPI1 32 /* INTR_STATUS_REG_0, bit 29 */ -#define XTENSA_IRQ_SPI2 30 /* INTR_STATUS_REG_0, bit 30 */ -#define XTENSA_IRQ_SPI3 31 /* INTR_STATUS_REG_0, bit 31 */ +#define XTENSA_IRQ_SPI2 33 /* INTR_STATUS_REG_0, bit 30 */ +#define XTENSA_IRQ_SPI3 34 /* INTR_STATUS_REG_0, bit 31 */ /* PRO_INTR_STATUS_REG_1 / APP_INTR_STATUS_REG_1 */ -#define XTENSA_IRQ_SREG1 32 -#define XTENSA_IRQ_I2S0 32 /* INTR_STATUS_REG_1, bit 0 */ -#define XTENSA_IRQ_I2S1 33 /* INTR_STATUS_REG_1, bit 1 */ -#define XTENSA_IRQ_UART 34 /* INTR_STATUS_REG_1, bit 2 */ -#define XTENSA_IRQ_UART1 35 /* INTR_STATUS_REG_1, bit 3 */ -#define XTENSA_IRQ_UART2 36 /* INTR_STATUS_REG_1, bit 4 */ -#define XTENSA_IRQ_SDIO_HOST 37 /* INTR_STATUS_REG_1, bit 5 */ -#define XTENSA_IRQ_EMAC 38 /* INTR_STATUS_REG_1, bit 6 */ -#define XTENSA_IRQ_PWM0 39 /* INTR_STATUS_REG_1, bit 7 */ -#define XTENSA_IRQ_PWM1 40 /* INTR_STATUS_REG_1, bit 8 */ -#define XTENSA_IRQ_PWM2 41 /* INTR_STATUS_REG_1, bit 9 */ +#define XTENSA_IRQ_SREG1 35 +#define XTENSA_IRQ_I2S0 35 /* INTR_STATUS_REG_1, bit 0 */ +#define XTENSA_IRQ_I2S1 36 /* INTR_STATUS_REG_1, bit 1 */ +#define XTENSA_IRQ_UART 37 /* INTR_STATUS_REG_1, bit 2 */ +#define XTENSA_IRQ_UART1 38 /* INTR_STATUS_REG_1, bit 3 */ +#define XTENSA_IRQ_UART2 39 /* INTR_STATUS_REG_1, bit 4 */ +#define XTENSA_IRQ_SDIO_HOST 40 /* INTR_STATUS_REG_1, bit 5 */ +#define XTENSA_IRQ_EMAC 41 /* INTR_STATUS_REG_1, bit 6 */ +#define XTENSA_IRQ_PWM0 42 /* INTR_STATUS_REG_1, bit 7 */ +#define XTENSA_IRQ_PWM1 43 /* INTR_STATUS_REG_1, bit 8 */ +#define XTENSA_IRQ_PWM2 44 /* INTR_STATUS_REG_1, bit 9 */ -#define XTENSA_IRQ_PWM3 42 /* INTR_STATUS_REG_1, bit 10 */ -#define XTENSA_IRQ_LEDC 43 /* INTR_STATUS_REG_1, bit 11 */ -#define XTENSA_IRQ_EFUSE 44 /* INTR_STATUS_REG_1, bit 12 */ -#define XTENSA_IRQ_CAN 45 /* INTR_STATUS_REG_1, bit 13 */ -#define XTENSA_IRQ_RTC_CORE 46 /* INTR_STATUS_REG_1, bit 14 */ -#define XTENSA_IRQ_RMT 47 /* INTR_STATUS_REG_1, bit 15 */ -#define XTENSA_IRQ_PCNT 48 /* INTR_STATUS_REG_1, bit 16 */ -#define XTENSA_IRQ_I2C_EXT0 49 /* INTR_STATUS_REG_1, bit 17 */ -#define XTENSA_IRQ_I2C_EXT1 50 /* INTR_STATUS_REG_1, bit 18 */ -#define XTENSA_IRQ_RSA 51 /* INTR_STATUS_REG_1, bit 19 */ +#define XTENSA_IRQ_PWM3 45 /* INTR_STATUS_REG_1, bit 10 */ +#define XTENSA_IRQ_LEDC 46 /* INTR_STATUS_REG_1, bit 11 */ +#define XTENSA_IRQ_EFUSE 47 /* INTR_STATUS_REG_1, bit 12 */ +#define XTENSA_IRQ_CAN 48 /* INTR_STATUS_REG_1, bit 13 */ +#define XTENSA_IRQ_RTC_CORE 49 /* INTR_STATUS_REG_1, bit 14 */ +#define XTENSA_IRQ_RMT 50 /* INTR_STATUS_REG_1, bit 15 */ +#define XTENSA_IRQ_PCNT 51 /* INTR_STATUS_REG_1, bit 16 */ +#define XTENSA_IRQ_I2C_EXT0 52 /* INTR_STATUS_REG_1, bit 17 */ +#define XTENSA_IRQ_I2C_EXT1 53 /* INTR_STATUS_REG_1, bit 18 */ +#define XTENSA_IRQ_RSA 54 /* INTR_STATUS_REG_1, bit 19 */ -#define XTENSA_IRQ_SPI1_DMA 52 /* INTR_STATUS_REG_1, bit 20 */ -#define XTENSA_IRQ_SPI2_DMA 53 /* INTR_STATUS_REG_1, bit 21 */ -#define XTENSA_IRQ_SPI3_DMA 54 /* INTR_STATUS_REG_1, bit 22 */ -#define XTENSA_IRQ_WDG 55 /* INTR_STATUS_REG_1, bit 23 */ -#define XTENSA_IRQ_TIMER1 56 /* INTR_STATUS_REG_1, bit 24 */ -#define XTENSA_IRQ_TIMER2 57 /* INTR_STATUS_REG_1, bit 25 */ -#define XTENSA_IRQ_TG_T0_EDGE 58 /* INTR_STATUS_REG_1, bit 26 */ -#define XTENSA_IRQ_TG_T1_EDGE 59 /* INTR_STATUS_REG_1, bit 27 */ -#define XTENSA_IRQ_TG_WDT_EDGE 60 /* INTR_STATUS_REG_1, bit 28 */ -#define XTENSA_IRQ_TG_LACT_EDGE 61 /* INTR_STATUS_REG_1, bit 29 */ +#define XTENSA_IRQ_SPI1_DMA 55 /* INTR_STATUS_REG_1, bit 20 */ +#define XTENSA_IRQ_SPI2_DMA 56 /* INTR_STATUS_REG_1, bit 21 */ +#define XTENSA_IRQ_SPI3_DMA 57 /* INTR_STATUS_REG_1, bit 22 */ +#define XTENSA_IRQ_WDG 58 /* INTR_STATUS_REG_1, bit 23 */ +#define XTENSA_IRQ_TIMER1 59 /* INTR_STATUS_REG_1, bit 24 */ +#define XTENSA_IRQ_TIMER2 60 /* INTR_STATUS_REG_1, bit 25 */ +#define XTENSA_IRQ_TG_T0_EDGE 61 /* INTR_STATUS_REG_1, bit 26 */ +#define XTENSA_IRQ_TG_T1_EDGE 62 /* INTR_STATUS_REG_1, bit 27 */ +#define XTENSA_IRQ_TG_WDT_EDGE 63 /* INTR_STATUS_REG_1, bit 28 */ +#define XTENSA_IRQ_TG_LACT_EDGE 64 /* INTR_STATUS_REG_1, bit 29 */ -#define XTENSA_IRQ_TG1_T0_EDGE 62 /* INTR_STATUS_REG_1, bit 30 */ -#define XTENSA_IRQ_TG1_T1_EDGE 63 /* INTR_STATUS_REG_1, bit 31 */ +#define XTENSA_IRQ_TG1_T0_EDGE 65 /* INTR_STATUS_REG_1, bit 30 */ +#define XTENSA_IRQ_TG1_T1_EDGE 66 /* INTR_STATUS_REG_1, bit 31 */ /* PRO_INTR_STATUS_REG_2 / APP_INTR_STATUS_REG_2 */ -#define XTENSA_IRQ_SREG0 64 -#define XTENSA_IRQ_TG1_WDT_EDGE 64 /* INTR_STATUS_REG_2, bit 0 */ -#define XTENSA_IRQ_TG1_LACT_EDGE 65 /* INTR_STATUS_REG_2, bit 1 */ -#define XTENSA_IRQ_MMU_IA 66 /* INTR_STATUS_REG_2, bit 2 */ -#define XTENSA_IRQ_MPU_IA 67 /* INTR_STATUS_REG_2, bit 3 */ -#define XTENSA_IRQ_CACHE_IA 68 /* INTR_STATUS_REG_2, bit 4 */ +#define XTENSA_IRQ_SREG2 67 +#define XTENSA_IRQ_TG1_WDT_EDGE 67 /* INTR_STATUS_REG_2, bit 0 */ +#define XTENSA_IRQ_TG1_LACT_EDGE 68 /* INTR_STATUS_REG_2, bit 1 */ +#define XTENSA_IRQ_MMU_IA 69 /* INTR_STATUS_REG_2, bit 2 */ +#define XTENSA_IRQ_MPU_IA 70 /* INTR_STATUS_REG_2, bit 3 */ +#define XTENSA_IRQ_CACHE_IA 71 /* INTR_STATUS_REG_2, bit 4 */ /* Total number of interrupts */ -#define NR_IRQS 69 +#define NR_IRQS 72 /**************************************************************************** * Public Types diff --git a/arch/xtensa/src/common/xtensa_inthandlers.S b/arch/xtensa/src/common/xtensa_inthandlers.S index fbd3e6b08c2..cb18aec95b0 100644 --- a/arch/xtensa/src/common/xtensa_inthandlers.S +++ b/arch/xtensa/src/common/xtensa_inthandlers.S @@ -60,6 +60,7 @@ #include #include +#include #include "xtensa_specregs.h" #include "xtensa_macros.h" @@ -209,20 +210,17 @@ 7: .ifeq XT_TIMER_INTPRI - \level -.L_xt_user_int_timer_&level&: - /* Interrupt handler for the RTOS tick timer if at this level. - We'll be reading the interrupt state again after this call - so no need to preserve any registers except a6 (vpri_mask). - */ -#ifdef CONFIG_XTENSA_CALL0_ABI - mov a12, a6 - call0 XT_RTOS_TIMER_INT - mov a2, a12 -#else - mov a2, a6 - call4 XT_RTOS_TIMER_INT -#endif + /* Interrupt handler for the RTOS tick timer if at this level. + * We'll be reading the interrupt state again after this call + * so no need to preserve any registers except a6 (vpri_mask). + */ + + mov a12, a6 /* Preserve a6 */ + movi a2, XTENSA_IRQ_TIMER&level& /* Arg 1: IRQ number */ + mov a3, sp /* Arg 2: Top of stack = register save area */ + call0 xtensa_irq_dispatch /* Call xtensa_int_decode */ + mov a6, a12 /* Preserve a6 */ .endif #ifdef CONFIG_XTENSA_USE_SWPRI