diff --git a/arch/Kconfig b/arch/Kconfig index 1efa5d52c2a..65d730dc7f0 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -202,6 +202,10 @@ config ARCH_HAVE_RESET bool default n +config ARCH_HAVE_FETCHADD + bool + default n + config ARCH_HAVE_RTC_SUBSECONDS bool default n diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 63ca64635c4..642325162df 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -16,6 +16,7 @@ config ARCH_CHIP_A1X select ARCH_HAVE_FPU select ARCH_HAVE_IRQPRIO select ARCH_HAVE_LOWVECTORS + select ARCH_HAVE_FETCHADD select ARCH_HAVE_SDRAM select BOOT_RUNFROMSDRAM select ARCH_HAVE_ADDRENV @@ -51,6 +52,7 @@ config ARCH_CHIP_EFM32 select ARCH_HAVE_CMNVECTOR select ARCH_HAVE_SPI_BITORDER select ARMV7M_CMNVECTOR + select ARCH_HAVE_FETCHADD ---help--- Energy Micro EFM32 microcontrollers (ARM Cortex-M). @@ -69,6 +71,7 @@ config ARCH_CHIP_IMX6 select ARCH_HAVE_FPU select ARCH_HAVE_TRUSTZONE select ARCH_HAVE_LOWVECTORS + select ARCH_HAVE_FETCHADD select ARCH_HAVE_SDRAM select BOOT_RUNFROMSDRAM select ARCH_HAVE_ADDRENV @@ -82,6 +85,7 @@ config ARCH_CHIP_KINETIS select ARCH_HAVE_MPU select ARM_HAVE_MPU_UNIFIED select ARCH_HAVE_FPU + select ARCH_HAVE_FETCHADD select ARCH_HAVE_RAMFUNCS select ARCH_HAVE_CMNVECTOR select ARCH_HAVE_I2CRESET @@ -114,15 +118,6 @@ config ARCH_CHIP_LM ---help--- TI/Luminary Stellaris LMS3 and LM4F architectures (ARM Cortex-M3/4) -config ARCH_CHIP_TIVA - bool "TI Tiva" - select ARCH_HAVE_CMNVECTOR - select ARCH_HAVE_MPU - select ARM_HAVE_MPU_UNIFIED - select ARCH_HAVE_FPU - ---help--- - TI Tiva TM4C architectures (ARM Cortex-M4) - config ARCH_CHIP_LPC11XX bool "NXP LPC11xx" select ARCH_CORTEXM0 @@ -136,6 +131,7 @@ config ARCH_CHIP_LPC17XX select ARCH_HAVE_CMNVECTOR select ARCH_HAVE_MPU select ARM_HAVE_MPU_UNIFIED + select ARCH_HAVE_FETCHADD ---help--- NXP LPC17xx architectures (ARM Cortex-M3) @@ -168,6 +164,7 @@ config ARCH_CHIP_LPC43XX select ARCH_HAVE_MPU select ARM_HAVE_MPU_UNIFIED select ARCH_HAVE_FPU + select ARCH_HAVE_FETCHADD ---help--- NPX LPC43XX architectures (ARM Cortex-M4). @@ -179,6 +176,7 @@ config ARCH_CHIP_LPC54XX select ARCH_HAVE_MPU select ARM_HAVE_MPU_UNIFIED select ARCH_HAVE_FPU + select ARCH_HAVE_FETCHADD ---help--- NPX LPC54XX architectures (ARM Cortex-M4). @@ -203,6 +201,7 @@ config ARCH_CHIP_SAMA5 select ARCH_HAVE_FPU select ARCH_HAVE_IRQPRIO select ARCH_HAVE_LOWVECTORS + select ARCH_HAVE_FETCHADD select ARCH_HAVE_I2CRESET select ARCH_HAVE_TICKLESS select ARCH_HAVE_ADDRENV @@ -229,6 +228,7 @@ config ARCH_CHIP_SAM34 select ARCH_HAVE_CMNVECTOR select ARCH_HAVE_MPU select ARM_HAVE_MPU_UNIFIED + select ARCH_HAVE_FETCHADD select ARCH_HAVE_RAMFUNCS select ARMV7M_HAVE_STACKCHECK ---help--- @@ -239,6 +239,7 @@ config ARCH_CHIP_SAMV7 select ARCH_HAVE_CMNVECTOR select ARCH_CORTEXM7 select ARCH_HAVE_MPU + select ARCH_HAVE_FETCHADD select ARCH_HAVE_RAMFUNCS select ARCH_HAVE_TICKLESS select ARCH_HAVE_I2CRESET @@ -253,6 +254,7 @@ config ARCH_CHIP_STM32 bool "STMicro STM32 F1/F2/F3/F4" select ARCH_HAVE_CMNVECTOR select ARCH_HAVE_MPU + select ARCH_HAVE_FETCHADD select ARCH_HAVE_I2CRESET select ARCH_HAVE_HEAPCHECK select ARCH_HAVE_PROGMEM @@ -276,6 +278,7 @@ config ARCH_CHIP_STM32F7 select ARCH_HAVE_CMNVECTOR select ARCH_CORTEXM7 select ARCH_HAVE_MPU + select ARCH_HAVE_FETCHADD select ARCH_HAVE_I2CRESET select ARCH_HAVE_HEAPCHECK select ARCH_HAVE_SPI_BITORDER @@ -312,17 +315,29 @@ config ARCH_CHIP_TMS570 bool "TI TMS570" select ENDIAN_BIG select ARCH_HAVE_LOWVECTORS + select ARCH_HAVE_FETCHADD select ARCH_HAVE_RAMFUNCS select ARMV7R_MEMINIT select ARMV7R_HAVE_DECODEFIQ ---help--- TI TMS570 family +config ARCH_CHIP_TIVA + bool "TI Tiva" + select ARCH_HAVE_CMNVECTOR + select ARCH_HAVE_MPU + select ARM_HAVE_MPU_UNIFIED + select ARCH_HAVE_FPU + select ARCH_HAVE_FETCHADD + ---help--- + TI Tiva TM4C architectures (ARM Cortex-M4) + config ARCH_CHIP_XMC4 bool "Infineon XMC4xxx" select ARCH_HAVE_CMNVECTOR select ARCH_CORTEXM4 select ARCH_HAVE_MPU + select ARCH_HAVE_FETCHADD select ARCH_HAVE_RAMFUNCS select ARCH_HAVE_I2CRESET select ARM_HAVE_MPU_UNIFIED diff --git a/arch/arm/include/spinlock.h b/arch/arm/include/spinlock.h index 16079cc81a3..4a129faccab 100644 --- a/arch/arm/include/spinlock.h +++ b/arch/arm/include/spinlock.h @@ -130,7 +130,7 @@ typedef uint8_t spinlock_t; * Description: * Perform an atomic test and set operation on the provided spinlock. * - * This function must be provided via the architecture-specific logoic. + * This function must be provided via the architecture-specific logic. * * Input Parameters: * lock - The address of spinlock object. diff --git a/arch/arm/src/a1x/Make.defs b/arch/arm/src/a1x/Make.defs index 7ffb41537e9..2697e5363d4 100644 --- a/arch/arm/src/a1x/Make.defs +++ b/arch/arm/src/a1x/Make.defs @@ -55,7 +55,7 @@ endif CMN_ASRCS += arm_vectors.S arm_fpuconfig.S arm_fullcontextrestore.S CMN_ASRCS += arm_saveusercontext.S arm_vectoraddrexcptn.S arm_vfork.S -CMN_ASRCS += arm_testset.S +CMN_ASRCS += arm_testset.S arm_fetchadd.S CMN_ASRCS += cp15_coherent_dcache.S cp15_invalidate_dcache.S CMN_ASRCS += cp15_clean_dcache.S cp15_flush_dcache.S cp15_invalidate_dcache_all.S diff --git a/arch/arm/src/armv7-a/arm_fetchadd.S b/arch/arm/src/armv7-a/arm_fetchadd.S new file mode 100644 index 00000000000..143c38e5163 --- /dev/null +++ b/arch/arm/src/armv7-a/arm_fetchadd.S @@ -0,0 +1,257 @@ +/**************************************************************************** + * arch/arm/src/armv7-m/gnu/up_fetchadd.S + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + + .syntax unified + .thumb + .file "up_fetchadd.S" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + + .text + +/**************************************************************************** + * Name: up_fetchadd32 + * + * Description: + * Perform an atomic fetch add operation on the provided 32-bit value. + * + * This function must be provided via the architecture-specific logic. + * + * Input Parameters: + * addr - The address of 32-bit value to be incremented. + * value - The 32-bit addend + * + * Returned Value: + * The incremented value (volatile!) + * + ****************************************************************************/ + + .globl up_fetchadd32 + .type up_fetchadd32, %function + +up_fetchadd32: + +1: + ldrex r2, [r0] /* Fetch the value to be incremented */ + add r2, r2, r1 /* Add the addend */ + + strex r3, r2, [r0] /* Attempt to save the result */ + teq r3, #0 /* r2 will be 1 is strex failed */ + bne 1b /* Failed to lock... try again */ + + mov r0, r2 /* Return the incremented value */ + bx lr /* Successful! */ + .size up_fetchadd32, . - up_fetchadd32 + +/**************************************************************************** + * Name: up_fetchsub32 + * + * Description: + * Perform an atomic fetch subtract operation on the provided 32-bit value. + * + * This function must be provided via the architecture-specific logic. + * + * Input Parameters: + * addr - The address of 32-bit value to be decremented. + * value - The 32-bit subtrahend + * + * Returned Value: + * The decremented value (volatile!) + * + ****************************************************************************/ + + .globl up_fetchsub32 + .type up_fetchsub32, %function + +up_fetchsub32: + +1: + ldrex r2, [r0] /* Fetch the value to be decremented */ + sub r2, r2, r1 /* Subtract the subtrahend */ + + strex r3, r2, [r0] /* Attempt to save the result */ + teq r3, #0 /* r2 will be 1 is strex failed */ + bne 1b /* Failed to lock... try again */ + + mov r0, r2 /* Return the decremented value */ + bx lr /* Successful! */ + .size up_fetchsub32, . - up_fetchsub32 + +/**************************************************************************** + * Name: up_fetchadd16 + * + * Description: + * Perform an atomic fetch add operation on the provided 16-bit value. + * + * This function must be provided via the architecture-specific logic. + * + * Input Parameters: + * addr - The address of 16-bit value to be incremented. + * value - The 16-bit addend + * + * Returned Value: + * The incremented value (volatile!) + * + ****************************************************************************/ + + .globl up_fetchadd16 + .type up_fetchadd16, %function + +up_fetchadd16: + +1: + ldrexh r2, [r0] /* Fetch the value to be incremented */ + add r2, r2, r1 /* Add the addend */ + + strexh r3, r2, [r0] /* Attempt to save the result */ + teq r3, #0 /* r2 will be 1 is strexh failed */ + bne 1b /* Failed to lock... try again */ + + mov r0, r2 /* Return the incremented value */ + bx lr /* Successful! */ + .size up_fetchadd16, . - up_fetchadd16 + +/**************************************************************************** + * Name: up_fetchsub16 + * + * Description: + * Perform an atomic fetch subtract operation on the provided 16-bit value. + * + * This function must be provided via the architecture-specific logic. + * + * Input Parameters: + * addr - The address of 16-bit value to be decremented. + * value - The 16-bit subtrahend + * + * Returned Value: + * The decremented value (volatile!) + * + ****************************************************************************/ + + .globl up_fetchsub16 + .type up_fetchsub16, %function + +up_fetchsub16: + +1: + ldrexh r2, [r0] /* Fetch the value to be decremented */ + sub r2, r2, r1 /* Subtract the subtrahend */ + + /* Attempt to save the decremented value */ + + strexh r3, r2, [r0] /* Attempt to save the result */ + teq r3, #0 /* r2 will be 1 is strexh failed */ + bne 1b /* Failed to lock... try again */ + + mov r0, r2 /* Return the decremented value */ + bx lr /* Successful! */ + .size up_fetchsub16, . - up_fetchsub16 + +/**************************************************************************** + * Name: up_fetchadd8 + * + * Description: + * Perform an atomic fetch add operation on the provided 8-bit value. + * + * This function must be provided via the architecture-specific logic. + * + * Input Parameters: + * addr - The address of 8-bit value to be incremented. + * value - The 8-bit addend + * + * Returned Value: + * The incremented value (volatile!) + * + ****************************************************************************/ + + .globl up_fetchadd8 + .type up_fetchadd8, %function + +up_fetchadd8: + +1: + ldrexb r2, [r0] /* Fetch the value to be incremented */ + add r2, r2, r1 /* Add the addend */ + + strexb r3, r2, [r0] /* Attempt to save the result */ + teq r3, #0 /* r2 will be 1 is strexb failed */ + bne 1b /* Failed to lock... try again */ + + mov r0, r2 /* Return the incremented value */ + bx lr /* Successful! */ + .size up_fetchadd8, . - up_fetchadd8 + +/**************************************************************************** + * Name: up_fetchsub8 + * + * Description: + * Perform an atomic fetch subtract operation on the provided 8-bit value. + * + * This function must be provided via the architecture-specific logic. + * + * Input Parameters: + * addr - The address of 8-bit value to be decremented. + * value - The 8-bit subtrahend + * + * Returned Value: + * The decremented value (volatile!) + * + ****************************************************************************/ + + .globl up_fetchsub8 + .type up_fetchsub8, %function + +up_fetchsub8: + +1: + ldrexb r2, [r0] /* Fetch the value to be decremented */ + sub r2, r2, r1 /* Subtract the subtrahend */ + + strexb r3, r2, [r0] /* Attempt to save the result */ + teq r3, #0 /* r2 will be 1 is strexb failed */ + bne 1b /* Failed to lock... try again */ + + mov r0, r2 /* Return the decremented value */ + bx lr /* Successful! */ + .size up_fetchsub8, . - up_fetchsub8 + .end diff --git a/arch/arm/src/armv7-a/arm_testset.S b/arch/arm/src/armv7-a/arm_testset.S index 638736e4d67..feb3ea3df46 100644 --- a/arch/arm/src/armv7-a/arm_testset.S +++ b/arch/arm/src/armv7-a/arm_testset.S @@ -72,7 +72,7 @@ * Description: * Perform an atomic test and set operation on the provided spinlock. * - * This function must be provided via the architecture-specific logoic. + * This function must be provided via the architecture-specific logic. * * Input Parameters: * lock - The address of spinlock object (r0). diff --git a/arch/arm/src/armv7-m/gnu/up_fetchadd.S b/arch/arm/src/armv7-m/gnu/up_fetchadd.S new file mode 100644 index 00000000000..143c38e5163 --- /dev/null +++ b/arch/arm/src/armv7-m/gnu/up_fetchadd.S @@ -0,0 +1,257 @@ +/**************************************************************************** + * arch/arm/src/armv7-m/gnu/up_fetchadd.S + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + + .syntax unified + .thumb + .file "up_fetchadd.S" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + + .text + +/**************************************************************************** + * Name: up_fetchadd32 + * + * Description: + * Perform an atomic fetch add operation on the provided 32-bit value. + * + * This function must be provided via the architecture-specific logic. + * + * Input Parameters: + * addr - The address of 32-bit value to be incremented. + * value - The 32-bit addend + * + * Returned Value: + * The incremented value (volatile!) + * + ****************************************************************************/ + + .globl up_fetchadd32 + .type up_fetchadd32, %function + +up_fetchadd32: + +1: + ldrex r2, [r0] /* Fetch the value to be incremented */ + add r2, r2, r1 /* Add the addend */ + + strex r3, r2, [r0] /* Attempt to save the result */ + teq r3, #0 /* r2 will be 1 is strex failed */ + bne 1b /* Failed to lock... try again */ + + mov r0, r2 /* Return the incremented value */ + bx lr /* Successful! */ + .size up_fetchadd32, . - up_fetchadd32 + +/**************************************************************************** + * Name: up_fetchsub32 + * + * Description: + * Perform an atomic fetch subtract operation on the provided 32-bit value. + * + * This function must be provided via the architecture-specific logic. + * + * Input Parameters: + * addr - The address of 32-bit value to be decremented. + * value - The 32-bit subtrahend + * + * Returned Value: + * The decremented value (volatile!) + * + ****************************************************************************/ + + .globl up_fetchsub32 + .type up_fetchsub32, %function + +up_fetchsub32: + +1: + ldrex r2, [r0] /* Fetch the value to be decremented */ + sub r2, r2, r1 /* Subtract the subtrahend */ + + strex r3, r2, [r0] /* Attempt to save the result */ + teq r3, #0 /* r2 will be 1 is strex failed */ + bne 1b /* Failed to lock... try again */ + + mov r0, r2 /* Return the decremented value */ + bx lr /* Successful! */ + .size up_fetchsub32, . - up_fetchsub32 + +/**************************************************************************** + * Name: up_fetchadd16 + * + * Description: + * Perform an atomic fetch add operation on the provided 16-bit value. + * + * This function must be provided via the architecture-specific logic. + * + * Input Parameters: + * addr - The address of 16-bit value to be incremented. + * value - The 16-bit addend + * + * Returned Value: + * The incremented value (volatile!) + * + ****************************************************************************/ + + .globl up_fetchadd16 + .type up_fetchadd16, %function + +up_fetchadd16: + +1: + ldrexh r2, [r0] /* Fetch the value to be incremented */ + add r2, r2, r1 /* Add the addend */ + + strexh r3, r2, [r0] /* Attempt to save the result */ + teq r3, #0 /* r2 will be 1 is strexh failed */ + bne 1b /* Failed to lock... try again */ + + mov r0, r2 /* Return the incremented value */ + bx lr /* Successful! */ + .size up_fetchadd16, . - up_fetchadd16 + +/**************************************************************************** + * Name: up_fetchsub16 + * + * Description: + * Perform an atomic fetch subtract operation on the provided 16-bit value. + * + * This function must be provided via the architecture-specific logic. + * + * Input Parameters: + * addr - The address of 16-bit value to be decremented. + * value - The 16-bit subtrahend + * + * Returned Value: + * The decremented value (volatile!) + * + ****************************************************************************/ + + .globl up_fetchsub16 + .type up_fetchsub16, %function + +up_fetchsub16: + +1: + ldrexh r2, [r0] /* Fetch the value to be decremented */ + sub r2, r2, r1 /* Subtract the subtrahend */ + + /* Attempt to save the decremented value */ + + strexh r3, r2, [r0] /* Attempt to save the result */ + teq r3, #0 /* r2 will be 1 is strexh failed */ + bne 1b /* Failed to lock... try again */ + + mov r0, r2 /* Return the decremented value */ + bx lr /* Successful! */ + .size up_fetchsub16, . - up_fetchsub16 + +/**************************************************************************** + * Name: up_fetchadd8 + * + * Description: + * Perform an atomic fetch add operation on the provided 8-bit value. + * + * This function must be provided via the architecture-specific logic. + * + * Input Parameters: + * addr - The address of 8-bit value to be incremented. + * value - The 8-bit addend + * + * Returned Value: + * The incremented value (volatile!) + * + ****************************************************************************/ + + .globl up_fetchadd8 + .type up_fetchadd8, %function + +up_fetchadd8: + +1: + ldrexb r2, [r0] /* Fetch the value to be incremented */ + add r2, r2, r1 /* Add the addend */ + + strexb r3, r2, [r0] /* Attempt to save the result */ + teq r3, #0 /* r2 will be 1 is strexb failed */ + bne 1b /* Failed to lock... try again */ + + mov r0, r2 /* Return the incremented value */ + bx lr /* Successful! */ + .size up_fetchadd8, . - up_fetchadd8 + +/**************************************************************************** + * Name: up_fetchsub8 + * + * Description: + * Perform an atomic fetch subtract operation on the provided 8-bit value. + * + * This function must be provided via the architecture-specific logic. + * + * Input Parameters: + * addr - The address of 8-bit value to be decremented. + * value - The 8-bit subtrahend + * + * Returned Value: + * The decremented value (volatile!) + * + ****************************************************************************/ + + .globl up_fetchsub8 + .type up_fetchsub8, %function + +up_fetchsub8: + +1: + ldrexb r2, [r0] /* Fetch the value to be decremented */ + sub r2, r2, r1 /* Subtract the subtrahend */ + + strexb r3, r2, [r0] /* Attempt to save the result */ + teq r3, #0 /* r2 will be 1 is strexb failed */ + bne 1b /* Failed to lock... try again */ + + mov r0, r2 /* Return the decremented value */ + bx lr /* Successful! */ + .size up_fetchsub8, . - up_fetchsub8 + .end diff --git a/arch/arm/src/armv7-m/gnu/up_testset.S b/arch/arm/src/armv7-m/gnu/up_testset.S index c1888c56a98..10929b0780d 100644 --- a/arch/arm/src/armv7-m/gnu/up_testset.S +++ b/arch/arm/src/armv7-m/gnu/up_testset.S @@ -74,7 +74,7 @@ * Description: * Perform an atomic test and set operation on the provided spinlock. * - * This function must be provided via the architecture-specific logoic. + * This function must be provided via the architecture-specific logic. * * Input Parameters: * lock - The address of spinlock object. diff --git a/arch/arm/src/armv7-m/iar/up_fetchadd.S b/arch/arm/src/armv7-m/iar/up_fetchadd.S new file mode 100644 index 00000000000..f5db1837f64 --- /dev/null +++ b/arch/arm/src/armv7-m/iar/up_fetchadd.S @@ -0,0 +1,238 @@ +/**************************************************************************** + * arch/arm/src/armv7-m/iar/up_fetchadd.S + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + + MODULE up_testset + SECTION .text:CODE:NOROOT(2) + +/**************************************************************************** + * Public Symbols + ****************************************************************************/ + + PUBLIC up_fetchadd32 + PUBLIC up_fetchsub32 + PUBLIC up_fetchadd16 + PUBLIC up_fetchsub16 + PUBLIC up_fetchadd8 + PUBLIC up_fetchsub8 + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + + THUMB + +/**************************************************************************** + * Name: up_fetchadd32 + * + * Description: + * Perform an atomic fetch add operation on the provided 32-bit value. + * + * This function must be provided via the architecture-specific logic. + * + * Input Parameters: + * addr - The address of 32-bit value to be incremented. + * value - The 32-bit addend + * + * Returned Value: + * The incremented value (volatile!) + * + ****************************************************************************/ + +up_fetchadd32: + + ldrex r2, [r0] /* Fetch the value to be incremented */ + add r2, r2, r1 /* Add the addend */ + + strex r3, r2, [r0] /* Attempt to save the result */ + teq r3, #0 /* r2 will be 1 is strex failed */ + bne up_fetchadd32 /* Failed to lock... try again */ + + mov r0, r2 /* Return the incremented value */ + bx lr /* Successful! */ + +/**************************************************************************** + * Name: up_fetchsub32 + * + * Description: + * Perform an atomic fetch subtract operation on the provided 32-bit value. + * + * This function must be provided via the architecture-specific logic. + * + * Input Parameters: + * addr - The address of 32-bit value to be decremented. + * value - The 32-bit subtrahend + * + * Returned Value: + * The decremented value (volatile!) + * + ****************************************************************************/ + +up_fetchsub32: + + ldrex r2, [r0] /* Fetch the value to be decremented */ + sub r2, r2, r1 /* Subtract the subtrahend */ + + strex r3, r2, [r0] /* Attempt to save the result */ + teq r3, #0 /* r2 will be 1 is strex failed */ + bne up_fetchsub32 /* Failed to lock... try again */ + + mov r0, r2 /* Return the decremented value */ + bx lr /* Successful! */ + +/**************************************************************************** + * Name: up_fetchadd16 + * + * Description: + * Perform an atomic fetch add operation on the provided 16-bit value. + * + * This function must be provided via the architecture-specific logic. + * + * Input Parameters: + * addr - The address of 16-bit value to be incremented. + * value - The 16-bit addend + * + * Returned Value: + * The incremented value (volatile!) + * + ****************************************************************************/ + +up_fetchadd16: + + ldrexh r2, [r0] /* Fetch the value to be incremented */ + add r2, r2, r1 /* Add the addend */ + + strexh r3, r2, [r0] /* Attempt to save the result */ + teq r3, #0 /* r2 will be 1 is strexh failed */ + bne up_fetchadd16 /* Failed to lock... try again */ + + mov r0, r2 /* Return the incremented value */ + bx lr /* Successful! */ + +/**************************************************************************** + * Name: up_fetchsub16 + * + * Description: + * Perform an atomic fetch subtract operation on the provided 16-bit value. + * + * This function must be provided via the architecture-specific logic. + * + * Input Parameters: + * addr - The address of 16-bit value to be decremented. + * value - The 16-bit subtrahend + * + * Returned Value: + * The decremented value (volatile!) + * + ****************************************************************************/ + +up_fetchsub16: + + ldrexh r2, [r0] /* Fetch the value to be decremented */ + sub r2, r2, r1 /* Subtract the subtrahend */ + + /* Attempt to save the decremented value */ + + strexh r3, r2, [r0] /* Attempt to save the result */ + teq r3, #0 /* r2 will be 1 is strexh failed */ + bne up_fetchsub16 /* Failed to lock... try again */ + + mov r0, r2 /* Return the decremented value */ + bx lr /* Successful! */ + +/**************************************************************************** + * Name: up_fetchadd8 + * + * Description: + * Perform an atomic fetch add operation on the provided 8-bit value. + * + * This function must be provided via the architecture-specific logic. + * + * Input Parameters: + * addr - The address of 8-bit value to be incremented. + * value - The 8-bit addend + * + * Returned Value: + * The incremented value (volatile!) + * + ****************************************************************************/ + +up_fetchadd8: + + ldrexb r2, [r0] /* Fetch the value to be incremented */ + add r2, r2, r1 /* Add the addend */ + + strexb r3, r2, [r0] /* Attempt to save the result */ + teq r3, #0 /* r2 will be 1 is strexb failed */ + bne up_fetchadd8 /* Failed to lock... try again */ + + mov r0, r2 /* Return the incremented value */ + bx lr /* Successful! */ + +/**************************************************************************** + * Name: up_fetchsub8 + * + * Description: + * Perform an atomic fetch subtract operation on the provided 8-bit value. + * + * This function must be provided via the architecture-specific logic. + * + * Input Parameters: + * addr - The address of 8-bit value to be decremented. + * value - The 8-bit subtrahend + * + * Returned Value: + * The decremented value (volatile!) + * + ****************************************************************************/ + +up_fetchsub8: + + ldrexb r2, [r0] /* Fetch the value to be decremented */ + sub r2, r2, r1 /* Subtract the subtrahend */ + + strexb r3, r2, [r0] /* Attempt to save the result */ + teq r3, #0 /* r2 will be 1 is strexb failed */ + bne up_fetchsub8 /* Failed to lock... try again */ + + mov r0, r2 /* Return the decremented value */ + bx lr /* Successful! */ + + END diff --git a/arch/arm/src/armv7-m/iar/up_testset.S b/arch/arm/src/armv7-m/iar/up_testset.S index e690aed3de9..72874dff336 100644 --- a/arch/arm/src/armv7-m/iar/up_testset.S +++ b/arch/arm/src/armv7-m/iar/up_testset.S @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/armv7-m/gnu/up_testset.S + * arch/arm/src/armv7-m/iar/up_testset.S * * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -59,7 +59,7 @@ * Description: * Perform an atomic test and set operation on the provided spinlock. * - * This function must be provided via the architecture-specific logoic. + * This function must be provided via the architecture-specific logic. * * Input Parameters: * lock - The address of spinlock object. diff --git a/arch/arm/src/armv7-r/arm_fetchadd.S b/arch/arm/src/armv7-r/arm_fetchadd.S new file mode 100644 index 00000000000..ccdd42df52d --- /dev/null +++ b/arch/arm/src/armv7-r/arm_fetchadd.S @@ -0,0 +1,257 @@ +/**************************************************************************** + * arch/arm/src/armv7-r/gnu/up_fetchadd.S + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + + .syntax unified + .thumb + .file "up_fetchadd.S" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + + .text + +/**************************************************************************** + * Name: up_fetchadd32 + * + * Description: + * Perform an atomic fetch add operation on the provided 32-bit value. + * + * This function must be provided via the architecture-specific logic. + * + * Input Parameters: + * addr - The address of 32-bit value to be incremented. + * value - The 32-bit addend + * + * Returned Value: + * The incremented value (volatile!) + * + ****************************************************************************/ + + .globl up_fetchadd32 + .type up_fetchadd32, %function + +up_fetchadd32: + +1: + ldrex r2, [r0] /* Fetch the value to be incremented */ + add r2, r2, r1 /* Add the addend */ + + strex r3, r2, [r0] /* Attempt to save the result */ + teq r3, #0 /* r2 will be 1 is strex failed */ + bne 1b /* Failed to lock... try again */ + + mov r0, r2 /* Return the incremented value */ + bx lr /* Successful! */ + .size up_fetchadd32, . - up_fetchadd32 + +/**************************************************************************** + * Name: up_fetchsub32 + * + * Description: + * Perform an atomic fetch subtract operation on the provided 32-bit value. + * + * This function must be provided via the architecture-specific logic. + * + * Input Parameters: + * addr - The address of 32-bit value to be decremented. + * value - The 32-bit subtrahend + * + * Returned Value: + * The decremented value (volatile!) + * + ****************************************************************************/ + + .globl up_fetchsub32 + .type up_fetchsub32, %function + +up_fetchsub32: + +1: + ldrex r2, [r0] /* Fetch the value to be decremented */ + sub r2, r2, r1 /* Subtract the subtrahend */ + + strex r3, r2, [r0] /* Attempt to save the result */ + teq r3, #0 /* r2 will be 1 is strex failed */ + bne 1b /* Failed to lock... try again */ + + mov r0, r2 /* Return the decremented value */ + bx lr /* Successful! */ + .size up_fetchsub32, . - up_fetchsub32 + +/**************************************************************************** + * Name: up_fetchadd16 + * + * Description: + * Perform an atomic fetch add operation on the provided 16-bit value. + * + * This function must be provided via the architecture-specific logic. + * + * Input Parameters: + * addr - The address of 16-bit value to be incremented. + * value - The 16-bit addend + * + * Returned Value: + * The incremented value (volatile!) + * + ****************************************************************************/ + + .globl up_fetchadd16 + .type up_fetchadd16, %function + +up_fetchadd16: + +1: + ldrexh r2, [r0] /* Fetch the value to be incremented */ + add r2, r2, r1 /* Add the addend */ + + strexh r3, r2, [r0] /* Attempt to save the result */ + teq r3, #0 /* r2 will be 1 is strexh failed */ + bne 1b /* Failed to lock... try again */ + + mov r0, r2 /* Return the incremented value */ + bx lr /* Successful! */ + .size up_fetchadd16, . - up_fetchadd16 + +/**************************************************************************** + * Name: up_fetchsub16 + * + * Description: + * Perform an atomic fetch subtract operation on the provided 16-bit value. + * + * This function must be provided via the architecture-specific logic. + * + * Input Parameters: + * addr - The address of 16-bit value to be decremented. + * value - The 16-bit subtrahend + * + * Returned Value: + * The decremented value (volatile!) + * + ****************************************************************************/ + + .globl up_fetchsub16 + .type up_fetchsub16, %function + +up_fetchsub16: + +1: + ldrexh r2, [r0] /* Fetch the value to be decremented */ + sub r2, r2, r1 /* Subtract the subtrahend */ + + /* Attempt to save the decremented value */ + + strexh r3, r2, [r0] /* Attempt to save the result */ + teq r3, #0 /* r2 will be 1 is strexh failed */ + bne 1b /* Failed to lock... try again */ + + mov r0, r2 /* Return the decremented value */ + bx lr /* Successful! */ + .size up_fetchsub16, . - up_fetchsub16 + +/**************************************************************************** + * Name: up_fetchadd8 + * + * Description: + * Perform an atomic fetch add operation on the provided 8-bit value. + * + * This function must be provided via the architecture-specific logic. + * + * Input Parameters: + * addr - The address of 8-bit value to be incremented. + * value - The 8-bit addend + * + * Returned Value: + * The incremented value (volatile!) + * + ****************************************************************************/ + + .globl up_fetchadd8 + .type up_fetchadd8, %function + +up_fetchadd8: + +1: + ldrexb r2, [r0] /* Fetch the value to be incremented */ + add r2, r2, r1 /* Add the addend */ + + strexb r3, r2, [r0] /* Attempt to save the result */ + teq r3, #0 /* r2 will be 1 is strexb failed */ + bne 1b /* Failed to lock... try again */ + + mov r0, r2 /* Return the incremented value */ + bx lr /* Successful! */ + .size up_fetchadd8, . - up_fetchadd8 + +/**************************************************************************** + * Name: up_fetchsub8 + * + * Description: + * Perform an atomic fetch subtract operation on the provided 8-bit value. + * + * This function must be provided via the architecture-specific logic. + * + * Input Parameters: + * addr - The address of 8-bit value to be decremented. + * value - The 8-bit subtrahend + * + * Returned Value: + * The decremented value (volatile!) + * + ****************************************************************************/ + + .globl up_fetchsub8 + .type up_fetchsub8, %function + +up_fetchsub8: + +1: + ldrexb r2, [r0] /* Fetch the value to be decremented */ + sub r2, r2, r1 /* Subtract the subtrahend */ + + strexb r3, r2, [r0] /* Attempt to save the result */ + teq r3, #0 /* r2 will be 1 is strexb failed */ + bne 1b /* Failed to lock... try again */ + + mov r0, r2 /* Return the decremented value */ + bx lr /* Successful! */ + .size up_fetchsub8, . - up_fetchsub8 + .end diff --git a/arch/arm/src/armv7-r/arm_testset.S b/arch/arm/src/armv7-r/arm_testset.S index f82837d5fe8..703f466b198 100644 --- a/arch/arm/src/armv7-r/arm_testset.S +++ b/arch/arm/src/armv7-r/arm_testset.S @@ -72,7 +72,7 @@ * Description: * Perform an atomic test and set operation on the provided spinlock. * - * This function must be provided via the architecture-specific logoic. + * This function must be provided via the architecture-specific logic. * * Input Parameters: * lock - The address of spinlock object. diff --git a/arch/arm/src/efm32/Make.defs b/arch/arm/src/efm32/Make.defs index e02561c77bb..9d24cd2c37b 100644 --- a/arch/arm/src/efm32/Make.defs +++ b/arch/arm/src/efm32/Make.defs @@ -39,7 +39,7 @@ CMN_UASRCS = CMN_UCSRCS = CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S -CMN_ASRCS += up_testset.S vfork.S +CMN_ASRCS += up_testset.S up_fetchadd.S vfork.S CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copyfullstate.c CMN_CSRCS += up_createstack.c up_doirq.c up_exit.c up_hardfault.c diff --git a/arch/arm/src/imx6/Make.defs b/arch/arm/src/imx6/Make.defs index c551c22d97b..3950f54a98d 100644 --- a/arch/arm/src/imx6/Make.defs +++ b/arch/arm/src/imx6/Make.defs @@ -58,7 +58,7 @@ endif CMN_ASRCS += arm_vectors.S arm_fpuconfig.S arm_fullcontextrestore.S CMN_ASRCS += arm_saveusercontext.S arm_vectoraddrexcptn.S arm_vfork.S -CMN_ASRCS += arm_testset.S +CMN_ASRCS += arm_testset.S arm_fetchadd.S CMN_ASRCS += cp15_coherent_dcache.S cp15_invalidate_dcache.S CMN_ASRCS += cp15_clean_dcache.S cp15_flush_dcache.S cp15_invalidate_dcache_all.S diff --git a/arch/arm/src/kinetis/Make.defs b/arch/arm/src/kinetis/Make.defs index 4d9907907ed..7e47c09e035 100644 --- a/arch/arm/src/kinetis/Make.defs +++ b/arch/arm/src/kinetis/Make.defs @@ -43,7 +43,7 @@ CMN_UASRCS = CMN_UCSRCS = CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S -CMN_ASRCS += up_testset.S vfork.S +CMN_ASRCS += up_testset.S up_fetchadd.S vfork.S CMN_CSRCS = up_assert.c up_blocktask.c up_copyfullstate.c up_createstack.c CMN_CSRCS += up_mdelay.c up_udelay.c up_exit.c up_initialize.c up_memfault.c diff --git a/arch/arm/src/lpc17xx/Make.defs b/arch/arm/src/lpc17xx/Make.defs index 115a3222a2b..c164c95f13f 100644 --- a/arch/arm/src/lpc17xx/Make.defs +++ b/arch/arm/src/lpc17xx/Make.defs @@ -47,7 +47,7 @@ CMN_UASRCS = CMN_UCSRCS = CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S -CMN_ASRCS += up_testset.S vfork.S +CMN_ASRCS += up_testset.S up_fetchadd.S vfork.S CMN_CSRCS = up_assert.c up_blocktask.c up_copyfullstate.c up_createstack.c CMN_CSRCS += up_mdelay.c up_udelay.c up_exit.c up_initialize.c up_memfault.c diff --git a/arch/arm/src/lpc43xx/Make.defs b/arch/arm/src/lpc43xx/Make.defs index d5bd8912372..744768142c0 100644 --- a/arch/arm/src/lpc43xx/Make.defs +++ b/arch/arm/src/lpc43xx/Make.defs @@ -36,7 +36,7 @@ HEAD_ASRC = CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S -CMN_ASRCS += up_testset.S vfork.S +CMN_ASRCS += up_testset.S up_fetchadd.S vfork.S CMN_CSRCS = up_assert.c up_blocktask.c up_copyfullstate.c CMN_CSRCS += up_createstack.c up_mdelay.c up_udelay.c up_exit.c diff --git a/arch/arm/src/lpc54xx/Make.defs b/arch/arm/src/lpc54xx/Make.defs index 4ba8c0d6f8f..0df41b51b82 100644 --- a/arch/arm/src/lpc54xx/Make.defs +++ b/arch/arm/src/lpc54xx/Make.defs @@ -36,7 +36,7 @@ HEAD_ASRC = CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S -CMN_ASRCS += up_testset.S vfork.S +CMN_ASRCS += up_testset.S up_fetchadd.S vfork.S CMN_CSRCS = up_assert.c up_blocktask.c up_copyfullstate.c CMN_CSRCS += up_createstack.c up_mdelay.c up_udelay.c up_exit.c diff --git a/arch/arm/src/sam34/Make.defs b/arch/arm/src/sam34/Make.defs index 9ca94574306..12a35528fb6 100644 --- a/arch/arm/src/sam34/Make.defs +++ b/arch/arm/src/sam34/Make.defs @@ -47,7 +47,7 @@ CMN_UASRCS = CMN_UCSRCS = CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S -CMN_ASRCS += up_testset.S vfork.S +CMN_ASRCS += up_testset.S up_fetchadd.S vfork.S CMN_CSRCS = up_assert.c up_blocktask.c up_copyfullstate.c up_createstack.c CMN_CSRCS += up_mdelay.c up_udelay.c up_exit.c up_initialize.c diff --git a/arch/arm/src/sama5/Make.defs b/arch/arm/src/sama5/Make.defs index 716f5581d25..3c447aae1f0 100644 --- a/arch/arm/src/sama5/Make.defs +++ b/arch/arm/src/sama5/Make.defs @@ -55,7 +55,7 @@ endif CMN_ASRCS += arm_vectors.S arm_fpuconfig.S arm_fullcontextrestore.S CMN_ASRCS += arm_saveusercontext.S arm_vectoraddrexcptn.S arm_vfork.S -CMN_ASRCS += arm_testset.S +CMN_ASRCS += arm_testset.S arm_fetchadd.S CMN_ASRCS += cp15_coherent_dcache.S cp15_invalidate_dcache.S CMN_ASRCS += cp15_clean_dcache.S cp15_flush_dcache.S cp15_invalidate_dcache_all.S diff --git a/arch/arm/src/samv7/Make.defs b/arch/arm/src/samv7/Make.defs index fe5ab20b2c6..f7d4f3fb6b0 100644 --- a/arch/arm/src/samv7/Make.defs +++ b/arch/arm/src/samv7/Make.defs @@ -44,7 +44,7 @@ CMN_UASRCS = CMN_UCSRCS = CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S -CMN_ASRCS += up_testset.S vfork.S +CMN_ASRCS += up_testset.S up_fetchadd.S vfork.S CMN_CSRCS = up_assert.c up_blocktask.c up_copyfullstate.c up_createstack.c CMN_CSRCS += up_mdelay.c up_udelay.c up_exit.c up_idle.c up_initialize.c CMN_CSRCS += up_initialstate.c up_interruptcontext.c up_memfault.c up_modifyreg8.c diff --git a/arch/arm/src/stm32/Make.defs b/arch/arm/src/stm32/Make.defs index e4402d0bfb1..898a6986b18 100644 --- a/arch/arm/src/stm32/Make.defs +++ b/arch/arm/src/stm32/Make.defs @@ -43,7 +43,7 @@ CMN_UASRCS = CMN_UCSRCS = CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S -CMN_ASRCS += up_testset.S vfork.S +CMN_ASRCS += up_testset.S up_fetchadd.S vfork.S CMN_CSRCS = up_assert.c up_blocktask.c up_copyfullstate.c CMN_CSRCS += up_createstack.c up_mdelay.c up_udelay.c up_exit.c diff --git a/arch/arm/src/stm32f7/Make.defs b/arch/arm/src/stm32f7/Make.defs index ccb0fe66549..fb05fecf339 100644 --- a/arch/arm/src/stm32f7/Make.defs +++ b/arch/arm/src/stm32f7/Make.defs @@ -44,7 +44,7 @@ CMN_UASRCS = CMN_UCSRCS = CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S -CMN_ASRCS += up_testset.S vfork.S +CMN_ASRCS += up_testset.S up_fetchadd.S vfork.S CMN_CSRCS = up_assert.c up_blocktask.c up_copyfullstate.c up_createstack.c CMN_CSRCS += up_mdelay.c up_udelay.c up_exit.c up_initialize.c diff --git a/arch/arm/src/tiva/Make.defs b/arch/arm/src/tiva/Make.defs index d65294d6c51..6e5c862d96e 100644 --- a/arch/arm/src/tiva/Make.defs +++ b/arch/arm/src/tiva/Make.defs @@ -36,7 +36,7 @@ HEAD_ASRC = tiva_vectors.S CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S -CMN_ASRCS += up_testset.S vfork.S +CMN_ASRCS += up_testset.S up_fetchadd.S vfork.S CMN_CSRCS = up_assert.c up_blocktask.c up_copyfullstate.c up_createstack.c CMN_CSRCS += up_mdelay.c up_udelay.c up_exit.c up_idle.c up_initialize.c diff --git a/arch/arm/src/tms570/Make.defs b/arch/arm/src/tms570/Make.defs index 9d1d32f627b..c1103a2f012 100644 --- a/arch/arm/src/tms570/Make.defs +++ b/arch/arm/src/tms570/Make.defs @@ -42,7 +42,7 @@ HEAD_ASRC = arm_vectortab.S CMN_ASRCS += arm_vectors.S arm_head.S arm_fullcontextrestore.S CMN_ASRCS += arm_saveusercontext.S arm_vectoraddrexcptn.S arm_vfork.S -CMN_ASRCS += arm_testset.S +CMN_ASRCS += arm_testset.S arm_fetchadd.S CMN_ASRCS += cp15_coherent_dcache.S cp15_invalidate_dcache.S CMN_ASRCS += cp15_clean_dcache.S cp15_flush_dcache.S CMN_ASRCS += cp15_invalidate_dcache_all.S diff --git a/arch/arm/src/xmc4/Make.defs b/arch/arm/src/xmc4/Make.defs index 76ddb95391e..2b6fb0c62c3 100644 --- a/arch/arm/src/xmc4/Make.defs +++ b/arch/arm/src/xmc4/Make.defs @@ -43,7 +43,7 @@ CMN_UASRCS = CMN_UCSRCS = CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S -CMN_ASRCS += up_testset.S vfork.S +CMN_ASRCS += up_testset.S up_fetchadd.S vfork.S CMN_CSRCS = up_assert.c up_blocktask.c up_copyfullstate.c up_createstack.c CMN_CSRCS += up_mdelay.c up_udelay.c up_exit.c up_initialize.c up_memfault.c diff --git a/arch/sim/include/spinlock.h b/arch/sim/include/spinlock.h index 85333276b12..9bfc5f40a87 100644 --- a/arch/sim/include/spinlock.h +++ b/arch/sim/include/spinlock.h @@ -69,7 +69,7 @@ typedef bool spinlock_t; * Description: * Perform an atomic test and set operation on the provided spinlock. * - * This function must be provided via the architecture-specific logoic. + * This function must be provided via the architecture-specific logic. * * Input Parameters: * lock - The address of spinlock object. diff --git a/arch/sim/src/up_testset.c b/arch/sim/src/up_testset.c index d1b754bca06..1f825e64154 100644 --- a/arch/sim/src/up_testset.c +++ b/arch/sim/src/up_testset.c @@ -73,7 +73,7 @@ static pthread_mutex_t g_tsmutex = PTHREAD_MUTEX_INITIALIZER; * Description: * Perform an atomic test and set operation on the provided spinlock. * - * This function must be provided via the architecture-specific logoic. + * This function must be provided via the architecture-specific logic. * * Input Parameters: * lock - The address of spinlock object. diff --git a/arch/xtensa/include/spinlock.h b/arch/xtensa/include/spinlock.h index 9d0ef213d01..644253f8543 100644 --- a/arch/xtensa/include/spinlock.h +++ b/arch/xtensa/include/spinlock.h @@ -79,7 +79,7 @@ typedef uint32_t spinlock_t; * Description: * Perform an atomic test and set operation on the provided spinlock. * - * This function must be provided via the architecture-specific logoic. + * This function must be provided via the architecture-specific logic. * * Input Parameters: * lock - The address of spinlock object. diff --git a/arch/xtensa/src/common/xtensa_testset.c b/arch/xtensa/src/common/xtensa_testset.c index d8fdec3c00b..480a61052f5 100644 --- a/arch/xtensa/src/common/xtensa_testset.c +++ b/arch/xtensa/src/common/xtensa_testset.c @@ -91,7 +91,7 @@ static inline uint32_t xtensa_compareset(FAR volatile uint32_t *addr, * Description: * Perform an atomic test and set operation on the provided spinlock. * - * This function must be provided via the architecture-specific logoic. + * This function must be provided via the architecture-specific logic. * * Input Parameters: * lock - The address of spinlock object. diff --git a/include/nuttx/arch.h b/include/nuttx/arch.h index 9e52a6b0197..b5ec933ac0b 100644 --- a/include/nuttx/arch.h +++ b/include/nuttx/arch.h @@ -1686,6 +1686,54 @@ int up_timer_start(FAR const struct timespec *ts); /* See prototype in include/nuttx/spinlock.h */ +/**************************************************************************** + * Name: up_fetchadd8, up_fetchadd16, and up_fetchadd32 + * + * Description: + * Perform an atomic fetch add operation on the provided 8-, 16-, or 32- + * bit value. + * + * This function must be provided via the architecture-specific logic. + * + * Input Parameters: + * addr - The address of value to be incremented. + * value - The addend + * + * Returned Value: + * The incremented value (volatile!) + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_HAVE_FETCHADD +int32_t up_fetchadd32(FAR int32_t *addr, int32_t value); +int16_t up_fetchadd16(FAR int16_t *addr, int16_t value); +int8_t up_fetchadd8(FAR int8_t *addr, int8_t value); +#endif + +/**************************************************************************** + * Name: up_fetchsub8 + * + * Description: + * Perform an atomic fetch subtract operation on the provided 8-, 16-, or + * 32-bit value. + * + * This function must be provided via the architecture-specific logic. + * + * Input Parameters: + * addr - The address of value to be decremented. + * value - The subtrahend + * + * Returned Value: + * The decremented value (volatile!) + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_HAVE_FETCHADD +int32_t up_fetchsub32(FAR int32_t *addr, int32_t value); +int16_t up_fetchsub16(FAR int16_t *addr, int16_t value); +int8_t up_fetchsub8(FAR int8_t *addr, int8_t value); +#endif + /**************************************************************************** * Name: up_cpu_index * diff --git a/include/nuttx/spinlock.h b/include/nuttx/spinlock.h index 7ce1c1594e0..dc551e6d2b7 100644 --- a/include/nuttx/spinlock.h +++ b/include/nuttx/spinlock.h @@ -122,7 +122,7 @@ struct spinlock_s * Description: * Perform an atomic test and set operation on the provided spinlock. * - * This function must be provided via the architecture-specific logoic. + * This function must be provided via the architecture-specific logic. * * Input Parameters: * lock - The address of spinlock object.