diff --git a/arch/arm/src/nrf91/Kconfig b/arch/arm/src/nrf91/Kconfig
index 53c535b605f..4e01fe34813 100644
--- a/arch/arm/src/nrf91/Kconfig
+++ b/arch/arm/src/nrf91/Kconfig
@@ -241,84 +241,88 @@ endchoice # SPU configuration
 
 if NRF91_SPU_NONSECURE
 
+config NRF91_REGULATORS_NS
+	bool "REGULATORS non-secure"
+	default n
+
 config NRF91_POWERCLOCK_NS
-	bool "IPC POWER/CLOCK non-secure"
+	bool "POWER/CLOCK non-secure"
 	default n
 
 config NRF91_GPIO0_NS
-	bool "IPC GPIO0 non-secure"
+	bool "GPIO0 non-secure"
 	default n
 
 config NRF91_NVMC_NS
-	bool "IPC NVMC non-secure"
+	bool "NVMC non-secure"
 	default n
 
 config NRF91_SERIAL0_NS
-	bool "IPC SERIAL0 non-secure"
+	bool "SERIAL0 non-secure"
 	default n
 
 config NRF91_SERIAL1_NS
-	bool "IPC SERIAL1 non-secure"
+	bool "SERIAL1 non-secure"
 	default n
 
 config NRF91_SERIAL2_NS
-	bool "IPC SERIAL2 non-secure"
+	bool "SERIAL2 non-secure"
 	default n
 
 config NRF91_SERIAL3_NS
-	bool "IPC SERIAL3 non-secure"
+	bool "SERIAL3 non-secure"
 	default n
 
 config NRF91_SERIAL4_NS
-	bool "IPC SERIAL4 non-secure"
+	bool "SERIAL4 non-secure"
 	default n
 
 config NRF91_TIMER0_NS
-	bool "IPC TIMER0 non-secure"
+	bool "TIMER0 non-secure"
 	default n
 
 config NRF91_TIMER1_NS
-	bool "IPC TIMER1 non-secure"
+	bool "TIMER1 non-secure"
 	default n
 
 config NRF91_TIMER2_NS
-	bool "IPC TIMER2 non-secure"
+	bool "TIMER2 non-secure"
 	default n
 
 config NRF91_RTC0_NS
-	bool "IPC RTC0 non-secure"
+	bool "RTC0 non-secure"
 	default n
 
 config NRF91_WDT0_NS
-	bool "IPC WDT0 non-secure"
+	bool "WDT0 non-secure"
 	default n
 
 config NRF91_WDT1_NS
-	bool "IPC WDT1 non-secure"
+	bool "WDT1 non-secure"
 	default n
 
 config NRF91_RTC0_NS
-	bool "IPC RTC0 non-secure"
+	bool "RTC0 non-secure"
 	default n
 
 config NRF91_RTC1_NS
-	bool "IPC RTC1 non-secure"
+	bool "RTC1 non-secure"
 	default n
 
 config NRF91_PWM0_NS
-	bool "IPC PWM0 non-secure"
+	bool "PWM0 non-secure"
 	default n
 
 config NRF91_PWM1_NS
-	bool "IPC PWM1 non-secure"
+	bool "PWM1 non-secure"
 	default n
 
 config NRF91_PWM2_NS
-	bool "IPC PWM2 non-secure"
+	bool "PWM2 non-secure"
 	default n
 
 config NRF91_PWM3_NS
-	bool "IPC PWM3 non-secure"
+	bool "PWM3 non-secure"
 	default n
 
 config NRF91_IPC_NS
@@ -441,6 +445,7 @@ endmenu # System Timer
 config NRF91_FLASH_PREFETCH
 	bool "Enable FLASH Pre-fetch"
 	default y
+	depends on !ARCH_TRUSTZONE_NONSECURE
 	---help---
 		Enable FLASH prefetch
 
diff --git a/arch/arm/src/nrf91/hardware/nrf91_spu.h b/arch/arm/src/nrf91/hardware/nrf91_spu.h
index a7771169c2e..01dd48290ff 100644
--- a/arch/arm/src/nrf91/hardware/nrf91_spu.h
+++ b/arch/arm/src/nrf91/hardware/nrf91_spu.h
@@ -109,6 +109,13 @@
 #define SPU_RAMREGION_PERM_SECATTR           (1 << 4)
 #define SPU_RAMREGION_PERM_LOCK              (1 << 8)
 
-#define SPU_PERM_SECATTR                     (1 << 4)
+#define SPU_PERIPHID_SECUREMAPPING_SHIFT     (0)
+#define SPU_PERIPHID_SECUREMAPPING_MASK      (3 << SPU_PERIPHID_SECUREMAPPING_SHIFT)
+#  define SPU_PERIPHID_SECUREMAPPING_NONSEC  (0 << SPU_PERIPHID_SECUREMAPPING_SHIFT)
+#  define SPU_PERIPHID_SECUREMAPPING_SEC     (1 << SPU_PERIPHID_SECUREMAPPING_SHIFT)
+#  define SPU_PERIPHID_SECUREMAPPING_USER    (2 << SPU_PERIPHID_SECUREMAPPING_SHIFT)
+#  define SPU_PERIPHID_SECUREMAPPING_SPLIT   (3 << SPU_PERIPHID_SECUREMAPPING_SHIFT)
+#define SPU_PERIPHID_PERM_SECATTR            (1 << 4)
+#define SPU_PERIPHID_PERM_DMASEC             (1 << 5)
 
 #endif /* __ARCH_ARM_SRC_NRF91_HARDWARE_NRF91_SPU_H */
diff --git a/arch/arm/src/nrf91/nrf91_spu.c b/arch/arm/src/nrf91/nrf91_spu.c
index 89f974d7946..58fea6c6220 100644
--- a/arch/arm/src/nrf91/nrf91_spu.c
+++ b/arch/arm/src/nrf91/nrf91_spu.c
@@ -26,6 +26,8 @@
 
 #include "arm_internal.h"
 
+#include "sau.h"
+
 #include "hardware/nrf91_spu.h"
 
 /****************************************************************************
@@ -36,7 +38,7 @@
  * Private Functions
  ****************************************************************************/
 
-#if defined(NRF91_SPU_NONSECURE)
+#if defined(CONFIG_NRF91_SPU_NONSECURE)
 /****************************************************************************
  * Name: nrf91_spu_mem_default
  ****************************************************************************/
@@ -50,15 +52,15 @@ static void nrf91_spu_mem_default(void)
   for (i = CONFIG_NRF91_FLASH_NS_START; i < SPU_FLASH_REGIONS; i++)
     {
       modifyreg32(NRF91_SPU_FLASHREGIONPERM(i),
-                  SPU_FLASHREGION_PERM_SECATTR, SPU_PERM_SECATTR);
+                  SPU_FLASHREGION_PERM_SECATTR, 0);
     }
 
   /* Security attribute for RAM */
 
-  for (i = CONFIG_NRF91_FLASH_NS_START; i < SPU_RAM_REGIONS; i++)
+  for (i = CONFIG_NRF91_RAM_NS_START; i < SPU_RAM_REGIONS; i++)
     {
       modifyreg32(NRF91_SPU_RAMREGIONPERM(i),
-                  SPU_RAMREGION_PERM_SECATTR, SPU_PERM_SECATTR);
+                  SPU_RAMREGION_PERM_SECATTR, 0);
     }
 }
 
@@ -68,94 +70,99 @@ static void nrf91_spu_mem_default(void)
 
 static void nrf91_spu_periph(void)
 {
+#ifdef CONFIG_NRF91_REGULATORS_NS
+  modifyreg32(NRF91_SPU_PERIPHIDPERM(NRF91_REGULATORS_ID),
+              SPU_PERIPHID_PERM_SECATTR, 0);
+#endif
+
 #ifdef CONFIG_NRF91_POWERCLOCK_NS
   modifyreg32(NRF91_SPU_PERIPHIDPERM(NRF91_POWER_CLOCK_ID),
-              SPU_PERIPHID_PERM_SECATTR, SPU_PERM_SECATTR);
+              SPU_PERIPHID_PERM_SECATTR, 0);
 #endif
 
 #ifdef CONFIG_NRF91_GPIO0_NS
   modifyreg32(NRF91_SPU_PERIPHIDPERM(NRF91_GPIO0_ID),
-              SPU_PERIPHID_PERM_SECATTR, SPU_PERM_SECATTR);
+              SPU_PERIPHID_PERM_SECATTR, 0);
 #endif
 
 #ifdef CONFIG_NRF91_NVMC_NS
   modifyreg32(NRF91_SPU_PERIPHIDPERM(NRF91_NVMC_ID),
-              SPU_PERIPHID_PERM_SECATTR, SPU_PERM_SECATTR);
+              SPU_PERIPHID_PERM_SECATTR, 0);
 #endif
 
 #ifdef CONFIG_NRF91_SERIAL0_NS
   modifyreg32(NRF91_SPU_PERIPHIDPERM(NRF91_SERIAL0_ID),
-              SPU_PERIPHID_PERM_SECATTR, SPU_PERM_SECATTR);
+              SPU_PERIPHID_PERM_SECATTR, 0);
 #endif
 
 #ifdef CONFIG_NRF91_SERIAL1_NS
   modifyreg32(NRF91_SPU_PERIPHIDPERM(NRF91_SERIAL1_ID),
-              SPU_PERIPHID_PERM_SECATTR, SPU_PERM_SECATTR);
+              SPU_PERIPHID_PERM_SECATTR, 0);
 #endif
 
 #ifdef CONFIG_NRF91_SERIAL2_NS
   modifyreg32(NRF91_SPU_PERIPHIDPERM(NRF91_SERIAL2_ID),
-              SPU_PERIPHID_PERM_SECATTR, SPU_PERM_SECATTR);
+              SPU_PERIPHID_PERM_SECATTR, 0);
 #endif
 
 #ifdef CONFIG_NRF91_SERIAL3_NS
   modifyreg32(NRF91_SPU_PERIPHIDPERM(NRF91_SERIAL3_ID),
-              SPU_PERIPHID_PERM_SECATTR, SPU_PERM_SECATTR);
+              SPU_PERIPHID_PERM_SECATTR, 0);
 #endif
 
 #ifdef CONFIG_NRF91_TIMER0_NS
   modifyreg32(NRF91_SPU_PERIPHIDPERM(NRF91_TIMER0_ID),
-              SPU_PERIPHID_PERM_SECATTR, SPU_PERM_SECATTR);
+              SPU_PERIPHID_PERM_SECATTR, 0);
 #endif
 
 #ifdef CONFIG_NRF91_TIMER1_NS
   modifyreg32(NRF91_SPU_PERIPHIDPERM(NRF91_TIMER1_ID),
-              SPU_PERIPHID_PERM_SECATTR, SPU_PERM_SECATTR);
+              SPU_PERIPHID_PERM_SECATTR, 0);
 #endif
 
 #ifdef CONFIG_NRF91_TIMER2_NS
   modifyreg32(NRF91_SPU_PERIPHIDPERM(NRF91_TIMER2_ID),
-              SPU_PERIPHID_PERM_SECATTR, SPU_PERM_SECATTR);
+              SPU_PERIPHID_PERM_SECATTR, 0);
 #endif
 
 #ifdef CONFIG_NRF91_RTC0_NS
   modifyreg32(NRF91_SPU_PERIPHIDPERM(NRF91_RTC0_ID),
-              SPU_PERIPHID_PERM_SECATTR, SPU_PERM_SECATTR);
+              SPU_PERIPHID_PERM_SECATTR, 0);
 #endif
 
 #ifdef CONFIG_NRF91_RTC1_NS
   modifyreg32(NRF91_SPU_PERIPHIDPERM(NRF91_RTC1_ID),
-              SPU_PERIPHID_PERM_SECATTR, SPU_PERM_SECATTR);
+              SPU_PERIPHID_PERM_SECATTR, 0);
 #endif
 
 #ifdef CONFIG_NRF91_WDT0_NS
   modifyreg32(NRF91_SPU_PERIPHIDPERM(NRF91_WDT0_ID),
-              SPU_PERIPHID_PERM_SECATTR, SPU_PERM_SECATTR);
+              SPU_PERIPHID_PERM_SECATTR, 0);
 #endif
 
 #ifdef CONFIG_NRF91_WDT1_NS
   modifyreg32(NRF91_SPU_PERIPHIDPERM(NRF91_WDT1_ID),
-              SPU_PERIPHID_PERM_SECATTR, SPU_PERM_SECATTR);
+              SPU_PERIPHID_PERM_SECATTR, 0);
 #endif
 
 #ifdef CONFIG_NRF91_PWM0_NS
   modifyreg32(NRF91_SPU_PERIPHIDPERM(NRF91_PWM0_ID),
-              SPU_PERIPHID_PERM_SECATTR, SPU_PERM_SECATTR);
+              SPU_PERIPHID_PERM_SECATTR, 0);
 #endif
 
 #ifdef CONFIG_NRF91_PWM1_NS
   modifyreg32(NRF91_SPU_PERIPHIDPERM(NRF91_PWM1_ID),
-              SPU_PERIPHID_PERM_SECATTR, SPU_PERM_SECATTR);
+              SPU_PERIPHID_PERM_SECATTR, 0);
 #endif
 
 #ifdef CONFIG_NRF91_PWM2_NS
   modifyreg32(NRF91_SPU_PERIPHIDPERM(NRF91_PWM2_ID),
-              SPU_PERIPHID_PERM_SECATTR, SPU_PERM_SECATTR);
+              SPU_PERIPHID_PERM_SECATTR, 0);
 #endif
 
 #ifdef CONFIG_NRF91_IPC_NS
   modifyreg32(NRF91_SPU_PERIPHIDPERM(NRF91_IPC_ID),
-              SPU_PERIPHID_PERM_SECATTR, SPU_PERM_SECATTR);
+              SPU_PERIPHID_PERM_SECATTR, 0);
 #endif
 
   /* Make all GPIO non-secure */
@@ -174,7 +181,13 @@ static void nrf91_spu_periph(void)
 
 void nrf91_spu_configure(void)
 {
-#if defined(NRF91_SPU_NONSECURE)
+  /* Allow the security attribution to be set by the Nordic SPU */
+
+  sau_control(false, true);
+
+  up_secure_irq_all(false);
+
+#if defined(CONFIG_NRF91_SPU_NONSECURE)
   /* Peripheral configuration */
 
   nrf91_spu_periph();