diff --git a/arch/arm/src/samdl/chip/samd_gclk.h b/arch/arm/src/samdl/chip/samd_gclk.h
index bb2e3620212..67517a5eaa5 100644
--- a/arch/arm/src/samdl/chip/samd_gclk.h
+++ b/arch/arm/src/samdl/chip/samd_gclk.h
@@ -1,12 +1,14 @@
 /********************************************************************************************
  * arch/arm/src/samdl/chip/samd_gclk.h
  *
- *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * References:
  *   "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
  *   Datasheet", 42129J–SAM–12/2013
+ *   "Atmel SAM D21E / SAM D21G / SAM D21J SMART ARM-Based Microcontroller
+ *   Datasheet", Atmel-42181E–SAM-D21_Datasheet–02/2015
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -48,7 +50,7 @@
 
 #include "chip.h"
 
-#ifdef CONFIG_ARCH_FAMILY_SAMD20
+#if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21)
 
 /********************************************************************************************
  * Pre-processor Definitions
@@ -84,6 +86,8 @@
 #define GCLK_CLKCTRL_ID_SHIFT   (0)       /* Bits 0-5: Generic Clock Selection ID */
 #define GCLK_CLKCTRL_ID_MASK    (0x3f << GCLK_CLKCTRL_ID_SHIFT)
 #  define GCLK_CLKCTRL_ID(n)    ((n) << GCLK_CLKCTRL_ID_SHIFT)
+
+#ifdef CONFIG_ARCH_FAMILY_SAMD20
 #  define GCLK_CLKCTRL_ID_DFLL48M    (0 << GCLK_CLKCTRL_ID_SHIFT)  /* DFLL48M Reference */
 #  define GCLK_CLKCTRL_ID_WDT        (1 << GCLK_CLKCTRL_ID_SHIFT)  /* WDT */
 #  define GCLK_CLKCTRL_ID_RTC        (2 << GCLK_CLKCTRL_ID_SHIFT)  /* RTC */
@@ -114,6 +118,49 @@
 #  define GCLK_CLKCTRL_ID_ACANA      (25 << GCLK_CLKCTRL_ID_SHIFT) /* AC_ANA */
 #  define GCLK_CLKCTRL_ID_DAC        (26 << GCLK_CLKCTRL_ID_SHIFT) /* DAC */
 #  define GCLK_CLKCTRL_ID_PTC        (27 << GCLK_CLKCTRL_ID_SHIFT) /* PTC */
+#endif
+
+#ifdef CONFIG_ARCH_FAMILY_SAMD21
+#  define GCLK_CLKCTRL_ID_DFLL48M    (0 << GCLK_CLKCTRL_ID_SHIFT)  /* DFLL48M Reference */
+#  define GCLK_CLKCTRL_ID_DPLL       (1 << GCLK_CLKCTRL_ID_SHIFT)  /* FDPLL96M input clock source for reference */
+#  define GCLK_CLKCTRL_ID_DPLL32K    (2 << GCLK_CLKCTRL_ID_SHIFT)  /* FDPLL96M 32kHz clock for FDPLL96M internal lock timer */
+#  define GCLK_CLKCTRL_ID_WDT        (3 << GCLK_CLKCTRL_ID_SHIFT)  /* WDT */
+#  define GCLK_CLKCTRL_ID_RTC        (4 << GCLK_CLKCTRL_ID_SHIFT)  /* RTC */
+#  define GCLK_CLKCTRL_ID_EIC        (5 << GCLK_CLKCTRL_ID_SHIFT)  /* EIC */
+#  define GCLK_CLKCTRL_ID_EVSYS(n)   (((n)+7) << GCLK_CLKCTRL_ID_SHIFT)
+#  define GCLK_CLKCTRL_ID_EVSYS0     (7 << GCLK_CLKCTRL_ID_SHIFT)  /* EVSYS_CHANNEL_0 */
+#  define GCLK_CLKCTRL_ID_EVSYS1     (8 << GCLK_CLKCTRL_ID_SHIFT)  /* EVSYS_CHANNEL_1 */
+#  define GCLK_CLKCTRL_ID_EVSYS2     (9 << GCLK_CLKCTRL_ID_SHIFT) /* EVSYS_CHANNEL_2 */
+#  define GCLK_CLKCTRL_ID_EVSYS3     (10 << GCLK_CLKCTRL_ID_SHIFT) /* EVSYS_CHANNEL_3 */
+#  define GCLK_CLKCTRL_ID_EVSYS4     (11 << GCLK_CLKCTRL_ID_SHIFT) /* EVSYS_CHANNEL_4 */
+#  define GCLK_CLKCTRL_ID_EVSYS5     (12 << GCLK_CLKCTRL_ID_SHIFT) /* EVSYS_CHANNEL_5 */
+#  define GCLK_CLKCTRL_ID_EVSYS6     (13 << GCLK_CLKCTRL_ID_SHIFT) /* EVSYS_CHANNEL_6 */
+#  define GCLK_CLKCTRL_ID_EVSYS7     (14 << GCLK_CLKCTRL_ID_SHIFT) /* EVSYS_CHANNEL_7 */
+#  define GCLK_CLKCTRL_ID_EVSYS8     (15 << GCLK_CLKCTRL_ID_SHIFT) /* EVSYS_CHANNEL_8 */
+#  define GCLK_CLKCTRL_ID_EVSYS9     (16 << GCLK_CLKCTRL_ID_SHIFT) /* EVSYS_CHANNEL_9 */
+#  define GCLK_CLKCTRL_ID_EVSYS10    (17 << GCLK_CLKCTRL_ID_SHIFT) /* EVSYS_CHANNEL_10 */
+#  define GCLK_CLKCTRL_ID_EVSYS11    (18 << GCLK_CLKCTRL_ID_SHIFT) /* EVSYS_CHANNEL_11 */
+#  define GCLK_CLKCTRL_ID_SERCOMS    (19 << GCLK_CLKCTRL_ID_SHIFT) /* SERCOMx_SLOW */
+#  define GCLK_CLKCTRL_ID_SERCOMC(n) (((n)+20) << GCLK_CLKCTRL_ID_SHIFT)
+#  define GCLK_CLKCTRL_ID_SERCOM0C   (20 << GCLK_CLKCTRL_ID_SHIFT) /* SERCOM0_CORE */
+#  define GCLK_CLKCTRL_ID_SERCOM1C   (21 << GCLK_CLKCTRL_ID_SHIFT) /* SERCOM1_CORE */
+#  define GCLK_CLKCTRL_ID_SERCOM2C   (22 << GCLK_CLKCTRL_ID_SHIFT) /* SERCOM2_CORE */
+#  define GCLK_CLKCTRL_ID_SERCOM3C   (23 << GCLK_CLKCTRL_ID_SHIFT) /* SERCOM3_CORE */
+#  define GCLK_CLKCTRL_ID_SERCOM4C   (24 << GCLK_CLKCTRL_ID_SHIFT) /* SERCOM4_CORE */
+#  define GCLK_CLKCTRL_ID_SERCOM5C   (25 << GCLK_CLKCTRL_ID_SHIFT) /* SERCOM5_CORE */
+#  define GCLK_CLKCTRL_ID_TCC01      (26 << GCLK_CLKCTRL_ID_SHIFT) /* TCC0,TCC1 */
+#  define GCLK_CLKCTRL_ID_TCC23      (27 << GCLK_CLKCTRL_ID_SHIFT) /* TCC2,TC3 */
+#  define GCLK_CLKCTRL_ID_TC45       (28 << GCLK_CLKCTRL_ID_SHIFT) /* TC4,TC5 */
+#  define GCLK_CLKCTRL_ID_TC67       (29 << GCLK_CLKCTRL_ID_SHIFT) /* TC6,TC7 */
+#  define GCLK_CLKCTRL_ID_ADC        (30 << GCLK_CLKCTRL_ID_SHIFT) /* ADC */
+#  define GCLK_CLKCTRL_ID_ACDIG      (31 << GCLK_CLKCTRL_ID_SHIFT) /* AC_DIG */
+#  define GCLK_CLKCTRL_ID_ACANA      (32 << GCLK_CLKCTRL_ID_SHIFT) /* AC_ANA */
+#  define GCLK_CLKCTRL_ID_DAC        (33 << GCLK_CLKCTRL_ID_SHIFT) /* DAC */
+#  define GCLK_CLKCTRL_ID_PTC        (34 << GCLK_CLKCTRL_ID_SHIFT) /* PTC */
+#  define GCLK_CLKCTRL_I2S0_PTC      (35 << GCLK_CLKCTRL_ID_SHIFT) /* I2S0 */
+#  define GCLK_CLKCTRL_I2S1_PTC      (36 << GCLK_CLKCTRL_ID_SHIFT) /* I2S1 */
+#endif
+
 #define GCLK_CLKCTRL_GEN_SHIFT  (8)       /* Bits 8-11: Generic Clock Generator */
 #define GCLK_CLKCTRL_GEN_MASK   (15 << GCLK_CLKCTRL_GEN_SHIFT)
 #  define GCLK_CLKCTRL_GEN(n)   ((n) << GCLK_CLKCTRL_GEN_SHIFT) /* Generic clock generator n */
@@ -125,6 +172,11 @@
 #  define GCLK_CLKCTRL_GEN5     (5 << GCLK_CLKCTRL_GEN_SHIFT)   /* Generic clock generator 5 */
 #  define GCLK_CLKCTRL_GEN6     (6 << GCLK_CLKCTRL_GEN_SHIFT)   /* Generic clock generator 6 */
 #  define GCLK_CLKCTRL_GEN7     (7 << GCLK_CLKCTRL_GEN_SHIFT)   /* Generic clock generator 7 */
+
+#ifdef CONFIG_ARCH_FAMILY_SAMD21
+#  define GCLK_CLKCTRL_GEN8     (8 << GCLK_CLKCTRL_GEN_SHIFT)   /* Generic clock generator 8 */
+#endif
+
 #define GCLK_CLKCTRL_CLKEN      (1 << 14) /* Bit 14: Clock Enable */
 #define GCLK_CLKCTRL_WRTLOCK    (1 << 15) /* Bit 15: Write Lock */
 
@@ -141,6 +193,11 @@
 #  define GCLK_GENCTRL_ID5      (5 << GCLK_GENCTRL_ID_SHIFT)   /* Generic clock generator 5 */
 #  define GCLK_GENCTRL_ID6      (6 << GCLK_GENCTRL_ID_SHIFT)   /* Generic clock generator 6 */
 #  define GCLK_GENCTRL_ID7      (7 << GCLK_GENCTRL_ID_SHIFT)   /* Generic clock generator 7 */
+
+#ifdef CONFIG_ARCH_FAMILY_SAMD21
+#  define GCLK_GENCTRL_ID8      (78<< GCLK_GENCTRL_ID_SHIFT)   /* Generic clock generator 8 */
+#endif
+
 #define GCLK_GENCTRL_SRC_SHIFT  (8)       /* Bits 8-12: Source Select */
 #define GCLK_GENCTRL_SRC_MASK   (31 << GCLK_GENCTRL_SRC_SHIFT)
 #  define GCLK_GENCTRL_SRC_XOSC      (0 << GCLK_GENCTRL_SRC_SHIFT) /* XOSC oscillator output */
@@ -187,5 +244,5 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* CONFIG_ARCH_FAMILY_SAMD20 */
+#endif /* CONFIG_ARCH_FAMILY_SAMD20 || CONFIG_ARCH_FAMILY_SAMD21 */
 #endif /* __ARCH_ARM_SRC_SAMDL_CHIP_SAMD_GCLK_H */
diff --git a/arch/arm/src/samdl/chip/samd_pm.h b/arch/arm/src/samdl/chip/samd_pm.h
index 066eef5279a..828b45dd642 100644
--- a/arch/arm/src/samdl/chip/samd_pm.h
+++ b/arch/arm/src/samdl/chip/samd_pm.h
@@ -7,6 +7,8 @@
  * References:
  *   "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
  *   Datasheet", 42129J–SAM–12/2013
+ *   "Atmel SAM D21E / SAM D21G / SAM D21J SMART ARM-Based Microcontroller
+ *   Datasheet", Atmel-42181E–SAM-D21_Datasheet–02/2015
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
diff --git a/arch/arm/src/samdl/samd_clockconfig.c b/arch/arm/src/samdl/samd_clockconfig.c
index 704245468db..d44122719c1 100644
--- a/arch/arm/src/samdl/samd_clockconfig.c
+++ b/arch/arm/src/samdl/samd_clockconfig.c
@@ -1,13 +1,15 @@
 /****************************************************************************
  * arch/arm/src/samdl/samd_clockconfig.c
  *
- *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * References:
  *   1. "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
  *      Datasheet", 42129J–SAM–12/2013
- *   2. Atmel sample code for the SAMD20.  This code has an ASF license
+ *   2. "Atmel SAM D21E / SAM D21G / SAM D21J SMART ARM-Based Microcontroller
+ *      Datasheet", Atmel-42181E–SAM-D21_Datasheet–02/2015
+ *   3. Atmel sample code for the SAMD20.  This code has an ASF license
  *      with is compatible with the NuttX BSD license, but includes the
  *      provision that this code not be used in non-Atmel products.  That
  *      sample code was used only as a reference so I believe that only the
@@ -66,7 +68,7 @@
 #include "samd_periphclks.h"
 #include "sam_clockconfig.h"
 
-#ifdef CONFIG_ARCH_FAMILY_SAMD20
+#if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21)
 
 /****************************************************************************
  * Pre-processor Definitions
@@ -216,6 +218,23 @@ static const struct sam_gclkconfig_s g_gclkconfig[] =
     .clksrc     = (uint8_t)(BOARD_GCLK7_CLOCK_SOURCE >> GCLK_GENCTRL_SRC_SHIFT),
   }
 #endif
+
+  /* GCLK generator 8 */
+
+#ifdef BOARD_GCLK8_ENABLE
+  ,
+  {
+    .gclk       = 8,
+#ifdef BOARD_GCLK8_RUN_IN_STANDBY
+    .runstandby = true;
+#endif
+#ifdef BOARD_GCLK8_OUTPUT_ENABLE
+    .output     = true;
+#endif
+    .prescaler  = BOARD_GCLK8_PRESCALER,
+    .clksrc     = (uint8_t)(BOARD_GCLK8_CLOCK_SOURCE >> GCLK_GENCTRL_SRC_SHIFT),
+  }
+#endif
 };
 
 #define NGCLKS_ENABLED (sizeof(g_gclkconfig) / sizeof(struct sam_gclkconfig_s))
@@ -869,4 +888,4 @@ void sam_clockconfig(void)
   sam_dividers();
 }
 
-#endif /* CONFIG_ARCH_FAMILY_SAMD20 */
+#endif /* CONFIG_ARCH_FAMILY_SAMD20 || CONFIG_ARCH_FAMILY_SAMD21*/