diff --git a/arch/arm/include/stm32l4/chip.h b/arch/arm/include/stm32l4/chip.h index 99f13d2baa0..585d8605e5c 100644 --- a/arch/arm/include/stm32l4/chip.h +++ b/arch/arm/include/stm32l4/chip.h @@ -55,7 +55,7 @@ * - L486 has AES * - L496, L4A6 has 320 Kib SRAM, 2xCAN and CameraIF. Most (all?) of these have I2C4. * - L4A6 has AES and HASH - * + * * ----------- ---------------- ----- ------ ------ ---- ---- ----- * PART PACKAGE GPIOs LCD Tamper FSMC CapS AdcCh * ----------- ---------------- ----- ------ ------ ---- ---- ----- diff --git a/arch/arm/src/armv7-a/gtm.h b/arch/arm/src/armv7-a/gtm.h index 054d37f1784..347085f6737 100644 --- a/arch/arm/src/armv7-a/gtm.h +++ b/arch/arm/src/armv7-a/gtm.h @@ -112,7 +112,7 @@ extern "C" #endif /**************************************************************************** - * Name: + * Name: * * Description: * diff --git a/arch/arm/src/armv7-m/arch_clean_dcache.c b/arch/arm/src/armv7-m/arch_clean_dcache.c index 735623b4cda..0c2828d2b58 100644 --- a/arch/arm/src/armv7-m/arch_clean_dcache.c +++ b/arch/arm/src/armv7-m/arch_clean_dcache.c @@ -119,7 +119,7 @@ void arch_clean_dcache(uintptr_t start, uintptr_t end) int32_t tmpways = ways; /* Isolate the cache line associated with this address. For example - * if the cache line size is 32 bytes and the cache size is 16KB, then + * if the cache line size is 32 bytes and the cache size is 16KB, then * * sshift = 5 : Offset to the beginning of the set field * smask = 0x007f : Mask of the set field diff --git a/arch/arm/src/armv7-m/arch_flush_dcache.c b/arch/arm/src/armv7-m/arch_flush_dcache.c index c884eec041e..28ab2a00a04 100644 --- a/arch/arm/src/armv7-m/arch_flush_dcache.c +++ b/arch/arm/src/armv7-m/arch_flush_dcache.c @@ -119,7 +119,7 @@ void arch_flush_dcache(uintptr_t start, uintptr_t end) int32_t tmpways = ways; /* Isolate the cache line associated with this address. For example - * if the cache line size is 32 bytes and the cache size is 16KB, then + * if the cache line size is 32 bytes and the cache size is 16KB, then * * sshift = 5 : Offset to the beginning of the set field * smask = 0x007f : Mask of the set field diff --git a/arch/arm/src/armv7-m/arch_invalidate_dcache.c b/arch/arm/src/armv7-m/arch_invalidate_dcache.c index 899252cde7f..d6175f2d100 100644 --- a/arch/arm/src/armv7-m/arch_invalidate_dcache.c +++ b/arch/arm/src/armv7-m/arch_invalidate_dcache.c @@ -120,7 +120,7 @@ void arch_invalidate_dcache(uintptr_t start, uintptr_t end) int32_t tmpways = ways; /* Isolate the cache line associated with this address. For example - * if the cache line size is 32 bytes and the cache size is 16KB, then + * if the cache line size is 32 bytes and the cache size is 16KB, then * * sshift = 5 : Offset to the beginning of the set field * smask = 0x007f : Mask of the set field diff --git a/arch/arm/src/armv7-m/dwt.h b/arch/arm/src/armv7-m/dwt.h index 6cd66c9594d..0d15a613c67 100644 --- a/arch/arm/src/armv7-m/dwt.h +++ b/arch/arm/src/armv7-m/dwt.h @@ -26,7 +26,7 @@ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. - * + * * Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved. * Author: Pierre-noel Bouteville * diff --git a/arch/arm/src/armv7-m/iar/up_fullcontextrestore.S b/arch/arm/src/armv7-m/iar/up_fullcontextrestore.S index 9a50acb2064..045c903a32a 100644 --- a/arch/arm/src/armv7-m/iar/up_fullcontextrestore.S +++ b/arch/arm/src/armv7-m/iar/up_fullcontextrestore.S @@ -78,7 +78,7 @@ ************************************************************************************/ THUMB - + up_fullcontextrestore: /* Perform the System call with R0=1 and R1=regs */ @@ -90,5 +90,5 @@ up_fullcontextrestore: /* This call should not return */ bx lr /* Unnecessary ... will not return */ - + END diff --git a/arch/arm/src/armv7-m/up_itm.c b/arch/arm/src/armv7-m/up_itm.c index 695360a1e70..c3774ac6f5c 100644 --- a/arch/arm/src/armv7-m/up_itm.c +++ b/arch/arm/src/armv7-m/up_itm.c @@ -111,7 +111,7 @@ uint32_t itm_sendchar(uint32_t ch) /**************************************************************************** * Name: itm_receivechar - * + * * Description: * * Input Parameters: @@ -122,7 +122,7 @@ uint32_t itm_sendchar(uint32_t ch) * ****************************************************************************/ -int32_t itm_receivechar(void) +int32_t itm_receivechar(void) { int32_t ch = -1; /* Assume no character available */ @@ -150,7 +150,7 @@ int32_t itm_receivechar(void) * ****************************************************************************/ -int32_t itm_checkchar (void) +int32_t itm_checkchar (void) { return (g_itm_rxbuffer != ITM_RXBUFFER_EMPTY); } diff --git a/arch/arm/src/common/up_createstack.c b/arch/arm/src/common/up_createstack.c index 4503e15532e..6643f94def7 100644 --- a/arch/arm/src/common/up_createstack.c +++ b/arch/arm/src/common/up_createstack.c @@ -223,7 +223,7 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype) top_of_stack = (uint32_t)tcb->stack_alloc_ptr + stack_size - 4; /* The ARM stack must be aligned to 8-byte alignment for EABI. - * If necessary top_of_stack must be rounded down to the next + * If necessary top_of_stack must be rounded down to the next * boundary */ diff --git a/arch/arm/src/common/up_usestack.c b/arch/arm/src/common/up_usestack.c index f8072a66d4e..55c6a0526f5 100644 --- a/arch/arm/src/common/up_usestack.c +++ b/arch/arm/src/common/up_usestack.c @@ -133,7 +133,7 @@ int up_use_stack(struct tcb_s *tcb, void *stack, size_t stack_size) top_of_stack = (uint32_t)tcb->stack_alloc_ptr + stack_size - 4; /* The ARM stack must be aligned to 8-byte alignment for EABI. - * If necessary top_of_stack must be rounded down to the next + * If necessary top_of_stack must be rounded down to the next * boundary */ diff --git a/arch/arm/src/efm32/Make.defs b/arch/arm/src/efm32/Make.defs index 0b5ae3819fd..e02561c77bb 100644 --- a/arch/arm/src/efm32/Make.defs +++ b/arch/arm/src/efm32/Make.defs @@ -98,7 +98,7 @@ CHIP_CSRCS = efm32_start.c efm32_clockconfig.c efm32_irq.c efm32_timerisr.c CHIP_CSRCS += efm32_gpio.c efm32_lowputc.c efm32_timer.c efm32_i2c.c ifeq ($(CONFIG_EFM32_FLASHPROG),y) -CHIP_CSRCS += efm32_flash.c +CHIP_CSRCS += efm32_flash.c endif ifeq ($(CONFIG_EFM32_BITBAND),y) diff --git a/arch/arm/src/efm32/chip/efm32_calibrate.h b/arch/arm/src/efm32/chip/efm32_calibrate.h index 7fb84d1e310..508d0b56e98 100644 --- a/arch/arm/src/efm32/chip/efm32_calibrate.h +++ b/arch/arm/src/efm32/chip/efm32_calibrate.h @@ -88,6 +88,6 @@ struct efm32_calibrate_s { const uint32_t address; /* Address of calibration register */ const uint32_t value; /* Default value for calibration register */ -}; +}; #endif /* __ARCH_ARM_SRC_EFM32_CHIP_EFM32_CALIBRATE_H */ diff --git a/arch/arm/src/efm32/chip/efm32_devinfo.h b/arch/arm/src/efm32/chip/efm32_devinfo.h index 501e34741cc..024b5b2674a 100644 --- a/arch/arm/src/efm32/chip/efm32_devinfo.h +++ b/arch/arm/src/efm32/chip/efm32_devinfo.h @@ -79,16 +79,16 @@ /* MSC Register Offsets ********************************************************************************************************/ -#define EFM32_DEVINFO_CAL_OFFSET 0x0000 -#define EFM32_DEVINFO_ADC0CALn_OFFSET(n) (0x0004+(n)*4) -#define EFM32_DEVINFO_DAC0CALn_OFFSET(n) (0x0018+(n)*4) -#define EFM32_DEVINFO_AUXHFRCOCALn_OFFSET(n) (0x0024+(n)*4) -#define EFM32_DEVINFO_HFRCOCALn_OFFSET(n) (0x002c+(n)*4) -#define EFM32_DEVINFO_MEMINFO_PAGE_SIZE_OFFSET 0x0034 -#define EFM32_DEVINFO_UNIQUEL_OFFSET 0x0040 -#define EFM32_DEVINFO_UNIQUEH_OFFSET 0x0044 -#define EFM32_DEVINFO_MEMINFO_SIZE_OFFSET 0x0048 -#define EFM32_DEVINFO_PART_OFFSET 0x004c +#define EFM32_DEVINFO_CAL_OFFSET 0x0000 +#define EFM32_DEVINFO_ADC0CALn_OFFSET(n) (0x0004+(n)*4) +#define EFM32_DEVINFO_DAC0CALn_OFFSET(n) (0x0018+(n)*4) +#define EFM32_DEVINFO_AUXHFRCOCALn_OFFSET(n) (0x0024+(n)*4) +#define EFM32_DEVINFO_HFRCOCALn_OFFSET(n) (0x002c+(n)*4) +#define EFM32_DEVINFO_MEMINFO_PAGE_SIZE_OFFSET 0x0034 +#define EFM32_DEVINFO_UNIQUEL_OFFSET 0x0040 +#define EFM32_DEVINFO_UNIQUEH_OFFSET 0x0044 +#define EFM32_DEVINFO_MEMINFO_SIZE_OFFSET 0x0048 +#define EFM32_DEVINFO_PART_OFFSET 0x004c /* MSC Register Addresses ******************************************************************************************************/ @@ -121,7 +121,7 @@ #define _DEVINFO_CAL_CRC_SHIFT 0 /* Integrity CRC checksum shift */ #define _DEVINFO_CAL_TEMP_MASK 0x00FF0000UL /* Calibration temperature, DegC, mask */ #define _DEVINFO_CAL_TEMP_SHIFT 16 /* Calibration temperature shift */ - + #define _DEVINFO_ADC0CAL0_1V25_GAIN_MASK 0x00007F00UL /* Gain for 1V25 reference, mask */ #define _DEVINFO_ADC0CAL0_1V25_GAIN_SHIFT 8 /* Gain for 1V25 reference, shift */ #define _DEVINFO_ADC0CAL0_1V25_OFFSET_MASK 0x0000007FUL /* Offset for 1V25 reference, mask */ @@ -130,7 +130,7 @@ #define _DEVINFO_ADC0CAL0_2V5_GAIN_SHIFT 24 /* Gain for 2V5 reference, shift */ #define _DEVINFO_ADC0CAL0_2V5_OFFSET_MASK 0x007F0000UL /* Offset for 2V5 reference, mask */ #define _DEVINFO_ADC0CAL0_2V5_OFFSET_SHIFT 16 /* Offset for 2V5 reference, shift */ - + #define _DEVINFO_ADC0CAL1_VDD_GAIN_MASK 0x00007F00UL /* Gain for VDD reference, mask */ #define _DEVINFO_ADC0CAL1_VDD_GAIN_SHIFT 8 /* Gain for VDD reference, shift */ #define _DEVINFO_ADC0CAL1_VDD_OFFSET_MASK 0x0000007FUL /* Offset for VDD reference, mask */ @@ -139,33 +139,33 @@ #define _DEVINFO_ADC0CAL1_5VDIFF_GAIN_SHIFT 24 /* Gain for 5VDIFF reference, mask */ #define _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_MASK 0x007F0000UL /* Offset for 5VDIFF reference, mask */ #define _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_SHIFT 16 /* Offset for 5VDIFF reference, shift */ - + #define _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_MASK 0x0000007FUL /* Offset for 2XVDDVSS reference, mask */ #define _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_SHIFT 0 /* Offset for 2XVDDVSS reference, shift */ #define _DEVINFO_ADC0CAL2_TEMP1V25_MASK 0xFFF00000UL /* Temperature reading at 1V25 reference, mask */ #define _DEVINFO_ADC0CAL2_TEMP1V25_SHIFT 20 /* Temperature reading at 1V25 reference, DegC */ - + #define _DEVINFO_DAC0CAL0_1V25_GAIN_MASK 0x007F0000UL /* Gain for 1V25 reference, mask */ #define _DEVINFO_DAC0CAL0_1V25_GAIN_SHIFT 16 /* Gain for 1V25 reference, shift */ #define _DEVINFO_DAC0CAL0_1V25_CH1_OFFSET_MASK 0x00003F00UL /* Channel 1 offset for 1V25 reference, mask */ #define _DEVINFO_DAC0CAL0_1V25_CH1_OFFSET_SHIFT 8 /* Channel 1 offset for 1V25 reference, shift */ #define _DEVINFO_DAC0CAL0_1V25_CH0_OFFSET_MASK 0x0000003FUL /* Channel 0 offset for 1V25 reference, mask */ #define _DEVINFO_DAC0CAL0_1V25_CH0_OFFSET_SHIFT 0 /* Channel 0 offset for 1V25 reference, shift */ - + #define _DEVINFO_DAC0CAL1_2V5_GAIN_MASK 0x007F0000UL /* Gain for 2V5 reference, mask */ #define _DEVINFO_DAC0CAL1_2V5_GAIN_SHIFT 16 /* Gain for 2V5 reference, shift */ #define _DEVINFO_DAC0CAL1_2V5_CH1_OFFSET_MASK 0x00003F00UL /* Channel 1 offset for 2V5 reference, mask */ #define _DEVINFO_DAC0CAL1_2V5_CH1_OFFSET_SHIFT 8 /* Channel 1 offset for 2V5 reference, shift */ #define _DEVINFO_DAC0CAL1_2V5_CH0_OFFSET_MASK 0x0000003FUL /* Channel 0 offset for 2V5 reference, mask */ #define _DEVINFO_DAC0CAL1_2V5_CH0_OFFSET_SHIFT 0 /* Channel 0 offset for 2V5 reference, shift */ - + #define _DEVINFO_DAC0CAL2_VDD_GAIN_MASK 0x007F0000UL /* Gain for VDD reference, mask */ #define _DEVINFO_DAC0CAL2_VDD_GAIN_SHIFT 16 /* Gain for VDD reference, shift */ #define _DEVINFO_DAC0CAL2_VDD_CH1_OFFSET_MASK 0x00003F00UL /* Channel 1 offset for VDD reference, mask */ #define _DEVINFO_DAC0CAL2_VDD_CH1_OFFSET_SHIFT 8 /* Channel 1 offset for VDD reference, shift */ #define _DEVINFO_DAC0CAL2_VDD_CH0_OFFSET_MASK 0x0000003FUL /* Channel 0 offset for VDD reference, mask */ #define _DEVINFO_DAC0CAL2_VDD_CH0_OFFSET_SHIFT 0 /* Channel 0 offset for VDD reference, shift*/ - + #define _DEVINFO_AUXHFRCOCAL0_BAND1_MASK 0x000000FFUL /* 1MHz tuning value for AUXHFRCO, mask */ #define _DEVINFO_AUXHFRCOCAL0_BAND1_SHIFT 0 /* 1MHz tuning value for AUXHFRCO, shift */ #define _DEVINFO_AUXHFRCOCAL0_BAND7_MASK 0x0000FF00UL /* 7MHz tuning value for AUXHFRCO, mask */ @@ -174,12 +174,12 @@ #define _DEVINFO_AUXHFRCOCAL0_BAND11_SHIFT 16 /* 11MHz tuning value for AUXHFRCO, shift */ #define _DEVINFO_AUXHFRCOCAL0_BAND14_MASK 0xFF000000UL /* 14MHz tuning value for AUXHFRCO, mask */ #define _DEVINFO_AUXHFRCOCAL0_BAND14_SHIFT 24 /* 14MHz tuning value for AUXHFRCO, shift */ - + #define _DEVINFO_AUXHFRCOCAL1_BAND21_MASK 0x000000FFUL /* 21MHz tuning value for AUXHFRCO, mask */ #define _DEVINFO_AUXHFRCOCAL1_BAND21_SHIFT 0 /* 21MHz tuning value for AUXHFRCO, shift */ #define _DEVINFO_AUXHFRCOCAL1_BAND28_MASK 0x0000FF00UL /* 28MHz tuning value for AUXHFRCO, shift */ #define _DEVINFO_AUXHFRCOCAL1_BAND28_SHIFT 8 /* 28MHz tuning value for AUXHFRCO, mask */ - + #define _DEVINFO_HFRCOCAL0_BAND1_MASK 0x000000FFUL /* 1MHz tuning value for HFRCO, mask */ #define _DEVINFO_HFRCOCAL0_BAND1_SHIFT 0 /* 1MHz tuning value for HFRCO, shift */ #define _DEVINFO_HFRCOCAL0_BAND7_MASK 0x0000FF00UL /* 7MHz tuning value for HFRCO, mask */ @@ -188,26 +188,26 @@ #define _DEVINFO_HFRCOCAL0_BAND11_SHIFT 16 /* 11MHz tuning value for HFRCO, shift */ #define _DEVINFO_HFRCOCAL0_BAND14_MASK 0xFF000000UL /* 14MHz tuning value for HFRCO, mask */ #define _DEVINFO_HFRCOCAL0_BAND14_SHIFT 24 /* 14MHz tuning value for HFRCO, shift */ - + #define _DEVINFO_HFRCOCAL1_BAND21_MASK 0x000000FFUL /* 21MHz tuning value for HFRCO, mask */ #define _DEVINFO_HFRCOCAL1_BAND21_SHIFT 0 /* 21MHz tuning value for HFRCO, shift */ #define _DEVINFO_HFRCOCAL1_BAND28_MASK 0x0000FF00UL /* 28MHz tuning value for HFRCO, shift */ #define _DEVINFO_HFRCOCAL1_BAND28_SHIFT 8 /* 28MHz tuning value for HFRCO, mask */ - + #define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK 0xFF000000UL /* Flash page size (refer to ref.man for encoding) mask */ #define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_SHIFT 24 /* Flash page size shift */ - + #define _DEVINFO_UNIQUEL_MASK 0xFFFFFFFFUL /* Lower part of 64-bit device unique number */ #define _DEVINFO_UNIQUEL_SHIFT 0 /* Unique Low 32-bit shift */ - + #define _DEVINFO_UNIQUEH_MASK 0xFFFFFFFFUL /* High part of 64-bit device unique number */ #define _DEVINFO_UNIQUEH_SHIFT 0 /* Unique High 32-bit shift */ - + #define _DEVINFO_MEMINFO_SIZE_SRAM_MASK 0xFFFF0000UL /* Flash size in kilobytes */ #define _DEVINFO_MEMINFO_SIZE_SRAM_SHIFT 16 /* Bit position for flash size */ #define _DEVINFO_MEMINFO_SIZE_FLASH_MASK 0x0000FFFFUL /* SRAM size in kilobytes */ #define _DEVINFO_MEMINFO_SIZE_FLASH_SHIFT 0 /* Bit position for SRAM size */ - + #define _DEVINFO_PART_PROD_REV_MASK 0xFF000000UL /* Production revision */ #define _DEVINFO_PART_PROD_REV_SHIFT 24 /* Bit position for production revision */ #define _DEVINFO_PART_DEVICE_FAMILY_MASK 0x00FF0000UL /* Device Family, 0x47 for Gecko */ diff --git a/arch/arm/src/efm32/chip/efm32_flash.h b/arch/arm/src/efm32/chip/efm32_flash.h index 5c9f153be07..48cd8ee9e01 100644 --- a/arch/arm/src/efm32/chip/efm32_flash.h +++ b/arch/arm/src/efm32/chip/efm32_flash.h @@ -52,6 +52,6 @@ # define EFM32_FLASH_PAGESIZE 512 #elif defined(CONFIG_EFM32_EFM32TG) # define EFM32_FLASH_PAGESIZE 512 -#endif +#endif #endif /* __ARCH_ARM_SRC_EFM32_CHIP_EFM32_FLASH_H */ diff --git a/arch/arm/src/efm32/chip/efm32_gpio.h b/arch/arm/src/efm32/chip/efm32_gpio.h index ba3b7ebc0bf..f631de0409e 100644 --- a/arch/arm/src/efm32/chip/efm32_gpio.h +++ b/arch/arm/src/efm32/chip/efm32_gpio.h @@ -284,7 +284,7 @@ #endif /* GPIO Register Bit Field Definitions *****************************************************************************************/ - + /* Bit fields for GPIO P_CTRL */ #define _GPIO_P_CTRL_RESETVALUE 0x00000000UL /* Default value for GPIO_P_CTRL */ diff --git a/arch/arm/src/efm32/chip/efm32_romtable.h b/arch/arm/src/efm32/chip/efm32_romtable.h index 209fbd7d8d1..42ed83cbc84 100644 --- a/arch/arm/src/efm32/chip/efm32_romtable.h +++ b/arch/arm/src/efm32/chip/efm32_romtable.h @@ -109,6 +109,6 @@ struct efm32_romtable_s const uint32_t pid2; /* Chip minor rev MSB, JEP_106_PRESENT, JEP_106_NO */ const uint32_t pid3; /* Chip minor rev LSB */ const uint32_t cid0; /* Unused */ -}; +}; #endif /* __ARCH_ARM_SRC_EFM32_CHIP_EFM32_ROMTABLE_H */ diff --git a/arch/arm/src/efm32/efm32_leserial.c b/arch/arm/src/efm32/efm32_leserial.c index de8d157c8ab..2303f7ce72a 100644 --- a/arch/arm/src/efm32/efm32_leserial.c +++ b/arch/arm/src/efm32/efm32_leserial.c @@ -152,7 +152,7 @@ struct efm32_leuart_s ****************************************************************************/ static inline uint32_t efm32_serialin(struct efm32_leuart_s *priv, int offset); -static inline void efm32_serialout(struct efm32_leuart_s *priv, int offset, +static inline void efm32_serialout(struct efm32_leuart_s *priv, int offset, uint32_t value); static inline void efm32_setuartint(struct efm32_leuart_s *priv); diff --git a/arch/arm/src/efm32/efm32_pwm.c b/arch/arm/src/efm32/efm32_pwm.c index 180fe04e00c..b9c7bd0271d 100644 --- a/arch/arm/src/efm32/efm32_pwm.c +++ b/arch/arm/src/efm32/efm32_pwm.c @@ -66,7 +66,7 @@ #if defined(CONFIG_EFM32_TIMER0_PWM) || \ defined(CONFIG_EFM32_TIMER1_PWM) || \ defined(CONFIG_EFM32_TIMER2_PWM) || \ - defined(CONFIG_EFM32_TIMER3_PWM) + defined(CONFIG_EFM32_TIMER3_PWM) /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/efm32/efm32_pwm.h b/arch/arm/src/efm32/efm32_pwm.h index 61e4f5f116d..909137c9c07 100644 --- a/arch/arm/src/efm32/efm32_pwm.h +++ b/arch/arm/src/efm32/efm32_pwm.h @@ -36,9 +36,9 @@ #ifndef __ARCH_ARM_SRC_EFM32_EFM32_PWM_H #define __ARCH_ARM_SRC_EFM32_EFM32_PWM_H -/* The EFM32 does not have dedicated PWM hardware. Rather, pulsed output - * control is a capability of the EFM32 timers. The logic in this file - * implements the lower half of the standard, NuttX PWM interface using the +/* The EFM32 does not have dedicated PWM hardware. Rather, pulsed output + * control is a capability of the EFM32 timers. The logic in this file + * implements the lower half of the standard, NuttX PWM interface using the * EFM32 timers. That interface is described in include/nuttx/drivers/pwm.h. */ @@ -55,9 +55,9 @@ ****************************************************************************/ /* Configuration **************************************************************/ /* Timer devices may be used for different purposes. One special purpose is - * to generate modulated outputs for such things as motor control. - * If CONFIG_EFM32_TIMERn is defined then the CONFIG_EFM32_TIMERn_PWM must also - * be defined to indicate that timer "n" is intended to be used for pulsed + * to generate modulated outputs for such things as motor control. + * If CONFIG_EFM32_TIMERn is defined then the CONFIG_EFM32_TIMERn_PWM must also + * be defined to indicate that timer "n" is intended to be used for pulsed * output signal generation. */ diff --git a/arch/arm/src/efm32/efm32_serial.c b/arch/arm/src/efm32/efm32_serial.c index a13bfe4d588..133974d6f65 100644 --- a/arch/arm/src/efm32/efm32_serial.c +++ b/arch/arm/src/efm32/efm32_serial.c @@ -243,7 +243,7 @@ struct efm32_usart_s ****************************************************************************/ static inline uint32_t efm32_serialin(struct efm32_usart_s *priv, int offset); -static inline void efm32_serialout(struct efm32_usart_s *priv, int offset, +static inline void efm32_serialout(struct efm32_usart_s *priv, int offset, uint32_t value); static inline void efm32_setuartint(struct efm32_usart_s *priv); @@ -897,7 +897,7 @@ static int efm32_ioctl(struct file *filep, int cmd, unsigned long arg) #ifdef CONFIG_SERIAL_IFLOWCONTROL priv->iflow = (termiosp->c_cflag & CRTS_IFLOW) != 0; #endif -#endif +#endif /* Note that only cfgetispeed is used because we have knowledge * that only one speed is supported. diff --git a/arch/arm/src/imx6/imx_ecspi.c b/arch/arm/src/imx6/imx_ecspi.c index 2018c410bba..9b6b34ceffd 100644 --- a/arch/arm/src/imx6/imx_ecspi.c +++ b/arch/arm/src/imx6/imx_ecspi.c @@ -136,7 +136,7 @@ ****************************************************************************/ /* Per SPI callouts to board-specific logic */ - + typedef CODE void (*imx_select_t)(FAR struct spi_dev_s *dev, uint32_t devid, bool selected); typedef CODE uint8_t (*imx_status_t)(FAR struct spi_dev_s *dev, diff --git a/arch/arm/src/imx6/imx_iomuxc.h b/arch/arm/src/imx6/imx_iomuxc.h index 2a28fdf1cfb..dc7a7082d1f 100644 --- a/arch/arm/src/imx6/imx_iomuxc.h +++ b/arch/arm/src/imx6/imx_iomuxc.h @@ -143,7 +143,7 @@ typedef uint16_t iomux_pinset_t; /**************************************************************************** * Public Function Prototypes ****************************************************************************/ - + /**************************************************************************** * Name: imx_padmux_map * diff --git a/arch/arm/src/imx6/imx_timerisr.c b/arch/arm/src/imx6/imx_timerisr.c index 36cd8cced00..7d2cfba7e1a 100644 --- a/arch/arm/src/imx6/imx_timerisr.c +++ b/arch/arm/src/imx6/imx_timerisr.c @@ -230,7 +230,7 @@ void arm_timer_initialize(void) putreg32(GPT_OCR3_VALUE, IMX_GPT_OCR3); putreg32(GPT_PR_VALUE - 1, IMX_GPT_PR); - + /* Configure restart mode. Interrupts will be received on OC3, then OC2, * then OC1 when the counter will be reset to zero and the whole sequence * starts again. diff --git a/arch/arm/src/kinetis/chip/kinetis_usbotg.h b/arch/arm/src/kinetis/chip/kinetis_usbotg.h index 16cecc22610..490eae1ff73 100644 --- a/arch/arm/src/kinetis/chip/kinetis_usbotg.h +++ b/arch/arm/src/kinetis/chip/kinetis_usbotg.h @@ -153,11 +153,11 @@ #ifdef KINETIS_K64 # define KINETIS_USB_USBFRMADJUST \ - (KINETIS_USB0_BASE+KINETIS_USB_USBFRMADJUST_OFFSET) + (KINETIS_USB0_BASE+KINETIS_USB_USBFRMADJUST_OFFSET) # define KINETIS_USB_USB0_CLK_RECOVER_CTRL \ - (KINETIS_USB0_BASE+KINETIS_USB_USB0_CLK_RECOVER_CTRL_OFFSET) + (KINETIS_USB0_BASE+KINETIS_USB_USB0_CLK_RECOVER_CTRL_OFFSET) # define KINETIS_USB_USB0_CLK_RECOVER_IRC_EN \ - (KINETIS_USB0_BASE+KINETIS_USB_USB0_CLK_RECOVER_IRC_EN_OFFSET) + (KINETIS_USB0_BASE+KINETIS_USB_USB0_CLK_RECOVER_IRC_EN_OFFSET) # define KINETIS_USB_USB0_CLK_RECOVER_INT_STATUS \ (KINETIS_USB0_BASE+KINETIS_USB_USB0_CLK_RECOVER_INT_STATUS_OFFSET) #endif diff --git a/arch/arm/src/kinetis/kinetis_enet.c b/arch/arm/src/kinetis/kinetis_enet.c index 1a13ab856a1..76e12a9b058 100644 --- a/arch/arm/src/kinetis/kinetis_enet.c +++ b/arch/arm/src/kinetis/kinetis_enet.c @@ -170,7 +170,7 @@ #define BOARD_PHY_100BASET(s) (((s) & (2 << MII_PHYCTRL2_MODE_SHIFT)) != 0) #define BOARD_PHY_ISDUPLEX(s) (((s) & (4 << MII_PHYCTRL2_MODE_SHIFT)) != 0) -/* Estimate the MII_SPEED in order to get an MDC close to 2.5MHz, +/* Estimate the MII_SPEED in order to get an MDC close to 2.5MHz, based on the internal module (ENET) clock: * * MII_SPEED = ENET_FREQ/5000000 -1 @@ -1761,7 +1761,7 @@ static inline int kinetis_initphy(struct kinetis_driver_s *priv) usleep(LINK_WAITUS); } - if (phydata & MII_MSR_ANEGCOMPLETE) + if (phydata & MII_MSR_ANEGCOMPLETE) { ninfo("%s: Autonegotiation complete\n", BOARD_PHY_NAME); ninfo("%s: MII_MSR: %04x\n", BOARD_PHY_NAME, phydata); @@ -1769,14 +1769,14 @@ static inline int kinetis_initphy(struct kinetis_driver_s *priv) else { /* TODO: Autonegotitation has right now failed. Maybe the Eth cable is not connected. - PHY chip have mechanisms to configure link OK. We should leave autconf on, + PHY chip have mechanisms to configure link OK. We should leave autconf on, and find a way to re-configure MCU whenever the link is ready. */ ninfo("%s: Autonegotiation failed [%d] (is cable plugged-in ?), default to 10Mbs mode\n", \ BOARD_PHY_NAME, retries); /* Stop auto negotiation */ - + kinetis_writemii(priv, phyaddr, MII_MCR, 0); } diff --git a/arch/arm/src/kinetis/kinetis_usbdev.c b/arch/arm/src/kinetis/kinetis_usbdev.c index ace2400ae19..4d10d422fd7 100644 --- a/arch/arm/src/kinetis/kinetis_usbdev.c +++ b/arch/arm/src/kinetis/kinetis_usbdev.c @@ -1651,7 +1651,7 @@ static int khci_rdsetup(struct khci_ep_s *privep, uint8_t *dest, int readlen) /* Then give the BDT to the USB */ - bdtinfo("EP%d BDT OUT [%p] {%08x, %08x}\n", + bdtinfo("EP%d BDT OUT [%p] {%08x, %08x}\n", epno, bdtout, status, bdtout->addr); bdtout->status = status; diff --git a/arch/arm/src/lpc2378/chip.h b/arch/arm/src/lpc2378/chip.h index 1f213eaeabd..0902ae2cad9 100644 --- a/arch/arm/src/lpc2378/chip.h +++ b/arch/arm/src/lpc2378/chip.h @@ -101,7 +101,7 @@ #define LPC23XX_EMAC_BASE 0xFFE00000 /* Ethernet MAC base address */ #define LPC23XX_USB_BASE 0xFFE0C200 /* USB base address */ #define LPC23XX_SCB_BASE 0xE01FC000 /* System Control Block (SBC) base address */ -#define LPC23XX_EXT_BASE 0xe01fc140 /* External Interrupt base address */ +#define LPC23XX_EXT_BASE 0xe01fc140 /* External Interrupt base address */ /* AHB Register block base addresses */ @@ -367,7 +367,7 @@ #define CAN1RID_OFFSET 0x24 #define CAN1RDA_OFFSET 0x28 #define CAN1RDB_OFFSET 0x2C - + #define CAN1TFI1_OFFSET 0x30 #define CAN1TID1_OFFSET 0x34 #define CAN1TDA1_OFFSET 0x38 @@ -394,7 +394,7 @@ #define CAN2RID_OFFSET 0x24 #define CAN2RDA_OFFSET 0x28 #define CAN2RDB_OFFSET 0x2C - + #define CAN2TFI1_OFFSET 0x30 #define CAN2TID1_OFFSET 0x34 #define CAN2TDA1_OFFSET 0x38 diff --git a/arch/arm/src/lpc43xx/spifi/changelog.txt b/arch/arm/src/lpc43xx/spifi/changelog.txt index f96920a1f51..34e149edc13 100644 --- a/arch/arm/src/lpc43xx/spifi/changelog.txt +++ b/arch/arm/src/lpc43xx/spifi/changelog.txt @@ -24,7 +24,7 @@ renamed from lib_llpcspifi_Mx.a to lib_lpcspifi_Mx.a] LPCSpifilib version <1.01> ========================== Release date <12/11/2014> -1. Changed reported device string on S25FL512S from "S25FL512S 256kSec" to "S25FL512S". +1. Changed reported device string on S25FL512S from "S25FL512S 256kSec" to "S25FL512S". 2. Changelog update: Added support for MX25L1635E, MX25L6435E, MX25L8035E, S25FL016K, S25FL064P, S25FL128S, S25FL256S, S25FL512S, W25Q16DV, and W25Q64FV devices. 3. Changelog update: Changed maxRead to 16128 (was 32768). @@ -66,9 +66,9 @@ Change Log: 2. Added support for Winbond W25Q80BV. 3. Added API's to return max speed for specific functions: Read, QuadRead, Program, Quad Program. -4. Added prvGetStatus, prvSetStatus and prvSetQuadMode Functions to device definition structure. +4. Added prvGetStatus, prvSetStatus and prvSetQuadMode Functions to device definition structure. 5. Added spifiDevGetCount function. -6. Consolidated MX25L3235E and S25FL164K support into spifilib_fam_standard_cmd module +6. Consolidated MX25L3235E and S25FL164K support into spifilib_fam_standard_cmd module (removed SPIFI_REG_FAMILY_xxx registration functions and replaced with spifi_REG_FAMILY_StandardCommandSet function). 7. Fixed bug in spifiRegisterFamily where NULL was being returned instead of the diff --git a/arch/arm/src/sam34/sam4cm_cpustart.c b/arch/arm/src/sam34/sam4cm_cpustart.c index 3f6a4c6a194..591760b8c7d 100644 --- a/arch/arm/src/sam34/sam4cm_cpustart.c +++ b/arch/arm/src/sam34/sam4cm_cpustart.c @@ -231,7 +231,7 @@ int up_cpu_start(int cpu) putreg32(0x1, SAM_IPC0_IECR); /* enable : write-only */ irq_attach(SAM_IRQ_IPC0, arm_pause_handler, NULL); up_enable_irq(SAM_IRQ_IPC0); - + spin_lock(&g_cpu1_boot); /* CPU1 boot done */ diff --git a/arch/arm/src/sama5/chip/sam_emaca.h b/arch/arm/src/sama5/chip/sam_emaca.h index 2681b0567cb..3e4bb7409cb 100644 --- a/arch/arm/src/sama5/chip/sam_emaca.h +++ b/arch/arm/src/sama5/chip/sam_emaca.h @@ -1,6 +1,6 @@ /************************************************************************************ * arch/arm/src/sama5/chip/sam_emaca.h - * This is the form of the EMAC interface used the SAMA5D3 + * This is the form of the EMAC interface used the SAMA5D3 * * Copyright (C) 2013-2014 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/arch/arm/src/sama5/chip/sam_flexcom.h b/arch/arm/src/sama5/chip/sam_flexcom.h index 1e690d1ba55..990a73b1c7d 100644 --- a/arch/arm/src/sama5/chip/sam_flexcom.h +++ b/arch/arm/src/sama5/chip/sam_flexcom.h @@ -123,5 +123,5 @@ /* Flexcom TWI Register Definitions *************************************************/ #include "chip/sam_flexcom_twi.h" - + #endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_FLEXCOM_H */ diff --git a/arch/arm/src/sama5/chip/sam_matrix.h b/arch/arm/src/sama5/chip/sam_matrix.h index e68e85fddf9..f1da2826851 100644 --- a/arch/arm/src/sama5/chip/sam_matrix.h +++ b/arch/arm/src/sama5/chip/sam_matrix.h @@ -814,7 +814,7 @@ #if defined(ATSAMA5D2) || defined(ATSAMA5D4) /* Master Error Interrupt Enable Register, Master Error Interrupt Disable Register, - * Master Error Interrupt Mask Register, and Master Error Status Register + * Master Error Interrupt Mask Register, and Master Error Status Register */ # define MATRIX_MEINT_MERR(n) (1 << (n)) /* Master x Access Error, n=0..9 */ diff --git a/arch/arm/src/sama5/chip/sam_xdmac.h b/arch/arm/src/sama5/chip/sam_xdmac.h index 06b055ccbc9..41ed95453e7 100644 --- a/arch/arm/src/sama5/chip/sam_xdmac.h +++ b/arch/arm/src/sama5/chip/sam_xdmac.h @@ -283,7 +283,7 @@ #define XDMAC_CHINT_DI (1 << 2) /* Bit 2: End of Disable Interrupt */ #define XDMAC_CHINT_FI (1 << 3) /* Bit 3: End of Flush Interrupt */ #define XDMAC_CHINT_RBI (1 << 4) /* Bit 4: Read Bus Error Interrupt */ -#define XDMAC_CHINT_WBI (1 << 5) /* Bit 5: Write Bus Error Interrupt */ +#define XDMAC_CHINT_WBI (1 << 5) /* Bit 5: Write Bus Error Interrupt */ #define XDMAC_CHINT_ROI (1 << 6) /* Bit 6: Request Overflow Error Interrupt Disable Bit */ #define XDMAC_CHINT_ERRORS (0x00000070) diff --git a/arch/arm/src/sama5/sam_emacb.c b/arch/arm/src/sama5/sam_emacb.c index c08725216c4..c9fb251acac 100644 --- a/arch/arm/src/sama5/sam_emacb.c +++ b/arch/arm/src/sama5/sam_emacb.c @@ -3,7 +3,7 @@ * 10/100 Base-T Ethernet driver for the SAMA5D4. * * The SAMA5D3 and SAMA5D4 EMAC implementations differ in register naming - * and in register layout but are functionally equivalent. Here they are + * and in register layout but are functionally equivalent. Here they are * distinguished as 'A' and 'B'. For now, the 'A' and 'B' drivers are kept * separate (mostly because the 'B' driver needs to support two EMAC blocks. * But the 'B' driver should replace the 'A' driver someday. diff --git a/arch/arm/src/samdl/chip/saml_dmac.h b/arch/arm/src/samdl/chip/saml_dmac.h index 191e888a7d4..a8df353074d 100644 --- a/arch/arm/src/samdl/chip/saml_dmac.h +++ b/arch/arm/src/samdl/chip/saml_dmac.h @@ -173,9 +173,9 @@ # define DMAC_QOSCTRL_DQOS_LOW (1 << DMAC_QOSCTRL_DQOS_SHIFT) /* Sensitive bandwidth */ # define DMAC_QOSCTRL_DQOS_MEDIUM (2 << DMAC_QOSCTRL_DQOS_SHIFT) /* Sensitive latency */ # define DMAC_QOSCTRL_DQOS_HIGH (3 << DMAC_QOSCTRL_DQOS_SHIFT) /* Critical latency */ - + /* Common bit definitions for: Software Trigger Control Register, Interrupt Status Register, - * Busy Channels Register, and Pending Channels Register + * Busy Channels Register, and Pending Channels Register */ #define DMAC_CHAN(n) (1 << (n)) /* DMAC Channel n, n=0-15 */ diff --git a/arch/arm/src/samv7/chip/sam_usbhs.h b/arch/arm/src/samv7/chip/sam_usbhs.h index 04c9c4db511..3661ca91e7e 100644 --- a/arch/arm/src/samv7/chip/sam_usbhs.h +++ b/arch/arm/src/samv7/chip/sam_usbhs.h @@ -335,7 +335,7 @@ * Device Endpoint Mask Register * Device Endpoint Enable Register * - * (1) Control, Bulk, Interrupt endpoints + * (1) Control, Bulk, Interrupt endpoints * (2) Isochronous endpoints only */ @@ -464,7 +464,7 @@ * (1) Not clear or set registers * (2) Not clear register */ - + #define USBHS_HSTINT_DCONNI (1 << 0) /* Bit 0: Device Connection Interrupt */ #define USBHS_HSTINT_DDISCI (1 << 1) /* Bit 1: Device Disconnection Interrupt */ #define USBHS_HSTINT_RSTI (1 << 2) /* Bit 2: USB Reset Sent Interrupt */ @@ -644,7 +644,7 @@ */ /* All registers */ - + #define USBHS_HSTPIPINT_RXINI (1 << 0) /* Bit 0: Received IN Data Interrupt */ #define USBHS_HSTPIPINT_TXOUTI (1 << 1) /* Bit 1: Transmitted OUT Data Interrupt */ #define USBHS_HSTPIPINT_TXSTPI (1 << 2) /* Bit 2: Transmitted SETUP Interrupt (1) */ diff --git a/arch/arm/src/samv7/chip/sam_xdmac.h b/arch/arm/src/samv7/chip/sam_xdmac.h index cac9a5857a6..1cf968fbd85 100644 --- a/arch/arm/src/samv7/chip/sam_xdmac.h +++ b/arch/arm/src/samv7/chip/sam_xdmac.h @@ -244,7 +244,7 @@ #define XDMAC_CHINT_DI (1 << 2) /* Bit 2: End of Disable Interrupt */ #define XDMAC_CHINT_FI (1 << 3) /* Bit 3: End of Flush Interrupt */ #define XDMAC_CHINT_RBI (1 << 4) /* Bit 4: Read Bus Error Interrupt */ -#define XDMAC_CHINT_WBI (1 << 5) /* Bit 5: Write Bus Error Interrupt */ +#define XDMAC_CHINT_WBI (1 << 5) /* Bit 5: Write Bus Error Interrupt */ #define XDMAC_CHINT_ROI (1 << 6) /* Bit 6: Request Overflow Error Interrupt Disable Bit */ #define XDMAC_CHINT_ERRORS (0x00000070) diff --git a/arch/arm/src/samv7/sam_progmem.c b/arch/arm/src/samv7/sam_progmem.c index 41126bff7a7..535817bdff5 100644 --- a/arch/arm/src/samv7/sam_progmem.c +++ b/arch/arm/src/samv7/sam_progmem.c @@ -709,7 +709,7 @@ ssize_t up_progmem_write(size_t address, const void *buffer, size_t buflen) for (i = 0; i < (SAMV7_PAGE_SIZE / sizeof(uint32_t)); i++) { - *dest++ = *src++; + *dest++ = *src++; ARM_DMB(); } diff --git a/arch/arm/src/samv7/sam_usbdevhs.c b/arch/arm/src/samv7/sam_usbdevhs.c index d2904fc96ca..d27dafd5cc8 100644 --- a/arch/arm/src/samv7/sam_usbdevhs.c +++ b/arch/arm/src/samv7/sam_usbdevhs.c @@ -2545,7 +2545,7 @@ static void sam_dma_interrupt(struct sam_usbdev_s *priv, int epno) if (byct > 0 || nbusybk > 0) { - /* Not all of the data has been sent to the host. A NBUSYBKE + /* Not all of the data has been sent to the host. A NBUSYBKE * interrupt will be generated later. It has already been enabled. * Now wait for the transfer to complete. */ diff --git a/arch/arm/src/stm32/chip/stm32_otghs.h b/arch/arm/src/stm32/chip/stm32_otghs.h index 95b4772a37a..2e8f124f5cf 100644 --- a/arch/arm/src/stm32/chip/stm32_otghs.h +++ b/arch/arm/src/stm32/chip/stm32_otghs.h @@ -169,7 +169,7 @@ #define STM32_OTGHS_DVBUSPULSE_OFFSET 0x082c /* Device VBUS pulsing time register */ #define STM32_OTGHS_DIEPEMPMSK_OFFSET 0x0834 /* Device IN endpoint FIFO empty interrupt mask register */ -#define STM32_OTGHS_DIEP_OFFSET(n) (0x0900 + ((n) << 5)) +#define STM32_OTGHS_DIEP_OFFSET(n) (0x0900 + ((n) << 5)) #define STM32_OTGHS_DIEPCTL_EPOFFSET 0x0000 /* Device endpoint control register */ #define STM32_OTGHS_DIEPINT_EPOFFSET 0x0008 /* Device endpoint interrupt register */ #define STM32_OTGHS_DIEPTSIZ_EPOFFSET 0x0010 /* Device IN endpoint transfer size register */ diff --git a/arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h b/arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h index d44c664edbf..c5a4c4d5d30 100644 --- a/arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h +++ b/arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h @@ -426,7 +426,7 @@ #define GPIO_I2C3_SDA_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTH|GPIO_PIN8) #if defined(CONFIG_STM32_STM32F411) # define GPIO_I2C3_SDA_3 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN4) -# define GPIO_I2C3_SDA_4 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN8) +# define GPIO_I2C3_SDA_4 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN8) #endif #define GPIO_I2C3_SMBA_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN9) #define GPIO_I2C3_SMBA_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN9) diff --git a/arch/arm/src/stm32/stm32_capture.h b/arch/arm/src/stm32/stm32_capture.h index 5c81e77d9c2..004f953fe73 100644 --- a/arch/arm/src/stm32/stm32_capture.h +++ b/arch/arm/src/stm32/stm32_capture.h @@ -91,7 +91,7 @@ typedef enum STM32_CAP_MAPPED_TI1 = (1< 0)); for (i = 0; i < cchannels - 1; i ++) { diff --git a/arch/arm/src/stm32/stm32_sdadc.h b/arch/arm/src/stm32/stm32_sdadc.h index b2f7ffedd9a..24b89dbf9e8 100644 --- a/arch/arm/src/stm32/stm32_sdadc.h +++ b/arch/arm/src/stm32/stm32_sdadc.h @@ -114,8 +114,8 @@ /* SDADC Channels/DMA ****************************************************** * The maximum number of channels that can be sampled at each scan. - * If DMA support is not enabled, then only a single channel - * ought to be sampled. + * If DMA support is not enabled, then only a single channel + * ought to be sampled. * Otherwise, unless sampling frequency is reduced, * data overruns would occur. */ diff --git a/arch/arm/src/stm32/stm32_tickless.c b/arch/arm/src/stm32/stm32_tickless.c index 6d7a004693b..9696ac81a85 100644 --- a/arch/arm/src/stm32/stm32_tickless.c +++ b/arch/arm/src/stm32/stm32_tickless.c @@ -248,7 +248,7 @@ static int stm32_tickless_setchannel(uint8_t channel) */ ccmr_val = (ATIM_CCMR_MODE_FRZN << ATIM_CCMR1_OC1M_SHIFT); - + /* Set polarity */ ccer_val |= ATIM_CCER_CC1P << (channel << 2); @@ -913,7 +913,7 @@ int up_timer_start(FAR const struct timespec *ts) */ g_tickless.period = (uint16_t)(period + count); - + STM32_TIM_SETCOMPARE(g_tickless.tch, g_tickless.channel, g_tickless.period); diff --git a/arch/arm/src/stm32/stm32f37xxx_rcc.c b/arch/arm/src/stm32/stm32f37xxx_rcc.c index 6b83ee316c9..7cb9300e0f6 100644 --- a/arch/arm/src/stm32/stm32f37xxx_rcc.c +++ b/arch/arm/src/stm32/stm32f37xxx_rcc.c @@ -598,7 +598,7 @@ static void stm32_stdclockconfig(void) #endif #if defined(CONFIG_RTC_LSECLOCK) - /* Low speed external clock source LSE + /* Low speed external clock source LSE * * TODO: There is another case where the LSE needs to * be enabled: if the MCO pin selects LSE as source. diff --git a/arch/arm/src/stm32f0/stm32f0_hsi48.c b/arch/arm/src/stm32f0/stm32f0_hsi48.c index 2a33b9cf857..74230b25aa1 100644 --- a/arch/arm/src/stm32f0/stm32f0_hsi48.c +++ b/arch/arm/src/stm32f0/stm32f0_hsi48.c @@ -176,7 +176,7 @@ void stm32f0_disable_hsi48(void) regval = getreg32(STM32F0_CRS_CFGR); regval &= ~CRS_CFGR_SYNCSRC_MASK; putreg32(regval, STM32F0_CRS_CFGR); - + regval = getreg32(STM32F0_CRS_CR); regval &= ~CRS_CR_AUTOTRIMEN; putreg32(regval, STM32F0_CRS_CR); diff --git a/arch/arm/src/stm32f0/stm32f0_hsi48.h b/arch/arm/src/stm32f0/stm32f0_hsi48.h index d299db13e19..6c9eb38b107 100644 --- a/arch/arm/src/stm32f0/stm32f0_hsi48.h +++ b/arch/arm/src/stm32f0/stm32f0_hsi48.h @@ -53,7 +53,7 @@ enum syncsrc_e { SYNCSRC_GPIO = 0, /* GPIO selected as SYNC signal source */ SYNCSRC_LSE, /* LSE selected as SYNC signal source */ - SYNCSRC_USB, /* USB SOF selected as SYNC signal source */ + SYNCSRC_USB, /* USB SOF selected as SYNC signal source */ }; /************************************************************************************ diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_memorymap.h b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_memorymap.h index 889cf23192e..41675c60b37 100644 --- a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_memorymap.h +++ b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_memorymap.h @@ -210,6 +210,6 @@ */ #define STM32_DEBUGMCU_BASE 0xe0042000 - + #endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */ #endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XXX75XXX_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_tim.h b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_tim.h index eca76e95aae..5fad1f5a781 100644 --- a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_tim.h +++ b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_tim.h @@ -678,7 +678,7 @@ #define ATIM_CCMR3_OC6CE (1 << 15) /* Bit 15: Output Compare 7 Clear Enable */ #define ATIM_CCMR3_OC5M (1 << 16) /* Bit 16: Output Compare 5 mode - bit 3 */ #define ATIM_CCMR3_OC6M (1 << 24) /* Bit 24: Output Compare 6 mode - bit 3 */ - + /* Capture/compare enable register */ diff --git a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_memorymap.h b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_memorymap.h index 81f3512fe6a..db2ca6d3a95 100644 --- a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_memorymap.h +++ b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_memorymap.h @@ -216,6 +216,6 @@ */ #define STM32_DEBUGMCU_BASE 0xe0042000 - + #endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */ #endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XXX75XXX_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32f7/stm32_sdmmc.c b/arch/arm/src/stm32f7/stm32_sdmmc.c index 9225312bd1b..6be8f5f496e 100644 --- a/arch/arm/src/stm32f7/stm32_sdmmc.c +++ b/arch/arm/src/stm32f7/stm32_sdmmc.c @@ -2886,7 +2886,7 @@ static int stm32_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer, /* Configure the RX DMA */ stm32_configxfrints(priv, STM32_SDMMC_DMARECV_MASK); - + sdmmc_modifyreg32(priv, STM32_SDMMC_DCTRL_OFFSET, 0, STM32_SDMMC_DCTRL_DMAEN); stm32_dmasetup(priv->dma, priv->base + STM32_SDMMC_FIFO_OFFSET, (uint32_t)buffer, (buflen + 3) >> 2, @@ -3312,7 +3312,7 @@ void sdio_wrprotect(FAR struct sdio_dev_s *dev, bool wrprotect) { priv->cdstatus &= ~SDIO_STATUS_WRPROTECTED; } - + mcinfo("cdstatus: %02x\n", priv->cdstatus); leave_critical_section(flags); } diff --git a/arch/arm/src/stm32l4/chip/stm32l4_tim.h b/arch/arm/src/stm32l4/chip/stm32l4_tim.h index 23ff67ad4fe..83f6902aae7 100644 --- a/arch/arm/src/stm32l4/chip/stm32l4_tim.h +++ b/arch/arm/src/stm32l4/chip/stm32l4_tim.h @@ -651,7 +651,7 @@ #define ATIM_CCMR3_OC6M_MASK (7 << ATIM_CCMR3_OC6M_SHIFT) /* (See common (unshifted) bit field definitions below) */ #define ATIM_CCMR3_OC6CE (1 << 15) /* Bit 15: Output Compare 7 Clear Enable */ - + #define ATIM_CCMR3_OC5M (1 << 16) /* Bit 16: Output Compare 5 mode - bit 3 */ #define ATIM_CCMR3_OC6M (1 << 24) /* Bit 24: Output Compare 6 mode - bit 3 */ diff --git a/arch/arm/src/stm32l4/stm32l4_can.h b/arch/arm/src/stm32l4/stm32l4_can.h index b5db2c42865..ded35c173ba 100644 --- a/arch/arm/src/stm32l4/stm32l4_can.h +++ b/arch/arm/src/stm32l4/stm32l4_can.h @@ -62,7 +62,7 @@ # undef CONFIG_STM32L4_CAN1 #endif -#if defined(CONFIG_CAN) && defined(CONFIG_STM32L4_CAN1) +#if defined(CONFIG_CAN) && defined(CONFIG_STM32L4_CAN1) /* CAN BAUD */ diff --git a/arch/arm/src/stm32l4/stm32l4_oneshot.c b/arch/arm/src/stm32l4/stm32l4_oneshot.c index 9a7eb87b611..2c5191404d9 100644 --- a/arch/arm/src/stm32l4/stm32l4_oneshot.c +++ b/arch/arm/src/stm32l4/stm32l4_oneshot.c @@ -238,7 +238,7 @@ int stm32l4_oneshot_initialize(FAR struct stm32l4_oneshot_s *oneshot, * ****************************************************************************/ -int stm32l4_oneshot_max_delay(FAR struct stm32l4_oneshot_s *oneshot, +int stm32l4_oneshot_max_delay(FAR struct stm32l4_oneshot_s *oneshot, FAR uint64_t *usec) { DEBUGASSERT(oneshot != NULL && usec != NULL); diff --git a/arch/arm/src/stm32l4/stm32l4_pwm.c b/arch/arm/src/stm32l4/stm32l4_pwm.c index 71c4f1dad2c..c0879f676ca 100644 --- a/arch/arm/src/stm32l4/stm32l4_pwm.c +++ b/arch/arm/src/stm32l4/stm32l4_pwm.c @@ -643,7 +643,7 @@ static uint16_t stm32l4pwm_getreg(struct stm32l4_pwmtimer_s *priv, int offset) * ****************************************************************************/ -static void stm32l4pwm_putreg(struct stm32l4_pwmtimer_s *priv, int offset, +static void stm32l4pwm_putreg(struct stm32l4_pwmtimer_s *priv, int offset, uint16_t value) { if (priv->timtype == TIMTYPE_GENERAL32 && @@ -2027,7 +2027,7 @@ static int stm32l4pwm_stop(FAR struct pwm_lowerhalf_s *dev) * ****************************************************************************/ -static int stm32l4pwm_ioctl(FAR struct pwm_lowerhalf_s *dev, int cmd, +static int stm32l4pwm_ioctl(FAR struct pwm_lowerhalf_s *dev, int cmd, unsigned long arg) { #ifdef CONFIG_DEBUG_PWM_INFO diff --git a/arch/arm/src/stm32l4/stm32l4_pwr.c b/arch/arm/src/stm32l4/stm32l4_pwr.c index bc9a022fa09..816392895c8 100644 --- a/arch/arm/src/stm32l4/stm32l4_pwr.c +++ b/arch/arm/src/stm32l4/stm32l4_pwr.c @@ -81,7 +81,7 @@ static inline void stm32l4_pwr_modifyreg(uint8_t offset, uint16_t clearbits, uin * Enable/disable the clock to the power control peripheral. Enabling must be done * after the APB1 clock is validly configured, and prior to using any functionality * controlled by the PWR block (i.e. much of anything else provided by this module). - * + * * Input Parameters: * enable - True: enable the clock to the Power control (PWR) block. * @@ -94,7 +94,7 @@ bool stm32l4_pwr_enableclk(bool enable) { uint32_t regval; bool wasenabled; - + regval = getreg32(STM32L4_RCC_APB1ENR1); wasenabled = ((regval & RCC_APB1ENR1_PWREN) != 0); @@ -114,7 +114,7 @@ bool stm32l4_pwr_enableclk(bool enable) regval |= RCC_APB1ENR1_PWREN; putreg32(regval, STM32L4_RCC_APB1ENR1); } - + return wasenabled; } diff --git a/arch/arm/src/stm32l4/stm32l4_pwr.h b/arch/arm/src/stm32l4/stm32l4_pwr.h index 14891fe00a4..77d87b3dfe2 100644 --- a/arch/arm/src/stm32l4/stm32l4_pwr.h +++ b/arch/arm/src/stm32l4/stm32l4_pwr.h @@ -73,7 +73,7 @@ extern "C" * Enable/disable the clock to the power control peripheral. Enabling must be done * after the APB1 clock is validly configured, and prior to using any functionality * controlled by the PWR block (i.e. much of anything else provided by this module). - * + * * Input Parameters: * enable - True: enable the clock to the Power control (PWR) block. * diff --git a/arch/arm/src/stm32l4/stm32l4_qspi.c b/arch/arm/src/stm32l4/stm32l4_qspi.c index 0f55e764a0d..07bff36906c 100644 --- a/arch/arm/src/stm32l4/stm32l4_qspi.c +++ b/arch/arm/src/stm32l4/stm32l4_qspi.c @@ -240,7 +240,7 @@ struct qspi_xctnspec_s uint8_t isddr; /* true if 'double data rate' */ uint8_t issioo; /* true if 'send instruction only once' mode */ - + #ifdef STM32L4_QSPI_INTERRUPTS uint8_t function; /* functional mode; to distinguish a read or write */ int8_t disposition; /* how it all turned out */ @@ -1059,8 +1059,8 @@ static void qspi_ccrconfig(struct stm32l4_qspidev_s *priv, * automatic status polling, etc. * * Input Parameters: - * irq - - * context - + * irq - + * context - * * Returned Value: * OK means we handled it @@ -1072,21 +1072,21 @@ static int qspi0_interrupt(int irq, void *context, FAR void *arg) uint32_t status; uint32_t cr; uint32_t regval; - + /* Let's find out what is going on */ - + status = qspi_getreg(&g_qspi0dev, STM32L4_QUADSPI_SR_OFFSET); cr = qspi_getreg(&g_qspi0dev, STM32L4_QUADSPI_CR_OFFSET); - + /* Is it 'FIFO Threshold'? */ - + if ((status & QSPI_SR_FTF) && (cr & QSPI_CR_FTIE)) { volatile uint32_t *datareg = (volatile uint32_t*)(g_qspi0dev.base + STM32L4_QUADSPI_DR_OFFSET); if (g_qspi0dev.xctn->function == CCR_FMODE_INDWR) { /* Write data until we have no more or have no place to put it */ - + while((regval = qspi_getreg(&g_qspi0dev, STM32L4_QUADSPI_SR_OFFSET)) & QSPI_SR_FTF) { if (g_qspi0dev.xctn->idxnow < g_qspi0dev.xctn->datasize) @@ -1097,7 +1097,7 @@ static int qspi0_interrupt(int irq, void *context, FAR void *arg) else { /* Fresh out of data to write */ - + break; } } @@ -1105,7 +1105,7 @@ static int qspi0_interrupt(int irq, void *context, FAR void *arg) else if (g_qspi0dev.xctn->function == CCR_FMODE_INDRD) { /* Read data until we have no more or have no place to put it */ - + while((regval = qspi_getreg(&g_qspi0dev, STM32L4_QUADSPI_SR_OFFSET)) & QSPI_SR_FTF) { if (g_qspi0dev.xctn->idxnow < g_qspi0dev.xctn->datasize) @@ -1116,7 +1116,7 @@ static int qspi0_interrupt(int irq, void *context, FAR void *arg) else { /* no room at the inn */ - + break; } } @@ -1124,27 +1124,27 @@ static int qspi0_interrupt(int irq, void *context, FAR void *arg) } /* Is it 'Transfer Complete'? */ - + if ((status & QSPI_SR_TCF) && (cr & QSPI_CR_TCIE)) { /* Acknowledge interrupt */ - + qspi_putreg(&g_qspi0dev, QSPI_FCR_CTCF, STM32L4_QUADSPI_FCR); /* Disable the QSPI FIFO Threshold, Transfer Error and Transfer complete Interrupts */ - + regval = qspi_getreg(&g_qspi0dev, STM32L4_QUADSPI_CR_OFFSET); regval &= ~(QSPI_CR_TEIE | QSPI_CR_TCIE | QSPI_CR_FTIE); qspi_putreg(&g_qspi0dev, regval, STM32L4_QUADSPI_CR_OFFSET); - + /* Do the last bit of read if needed */ - + if (g_qspi0dev.xctn->function == CCR_FMODE_INDRD) { volatile uint32_t *datareg = (volatile uint32_t*)(g_qspi0dev.base + STM32L4_QUADSPI_DR_OFFSET); /* Read any remaining data */ - + while(((regval = qspi_getreg(&g_qspi0dev, STM32L4_QUADSPI_SR_OFFSET)) & QSPI_SR_FLEVEL_MASK) != 0) { if (g_qspi0dev.xctn->idxnow < g_qspi0dev.xctn->datasize) @@ -1162,42 +1162,42 @@ static int qspi0_interrupt(int irq, void *context, FAR void *arg) } /* Use 'abort' to ditch any stray fifo contents and clear BUSY flag */ - + qspi_abort(&g_qspi0dev); /* Set success status */ - + g_qspi0dev.xctn->disposition = OK; - + /* Signal complete */ - + sem_post(&g_qspi0dev.op_sem); } /* Is it 'Status Match'? */ - + if ((status & QSPI_SR_SMF) && (cr & QSPI_CR_SMIE)) { /* Acknowledge interrupt */ - + qspi_putreg(&g_qspi0dev, QSPI_FCR_CSMF, STM32L4_QUADSPI_FCR); - + /* If 'automatic poll mode stop' is activated, we're done */ - + if (cr & QSPI_CR_APMS) { /* Disable the QSPI Transfer Error and Status Match Interrupts */ - + regval = qspi_getreg(&g_qspi0dev, STM32L4_QUADSPI_CR_OFFSET); regval &= ~(QSPI_CR_TEIE | QSPI_CR_SMIE); qspi_putreg(&g_qspi0dev, regval, STM32L4_QUADSPI_CR_OFFSET); /* Set success status */ - + g_qspi0dev.xctn->disposition = OK; - + /* Signal complete */ - + sem_post(&g_qspi0dev.op_sem); } else @@ -1207,15 +1207,15 @@ static int qspi0_interrupt(int irq, void *context, FAR void *arg) } /* Is it' Transfer Error'? :( */ - + if ((status & QSPI_SR_TEF) && (cr & QSPI_CR_TEIE)) { /* Acknowledge interrupt */ - + qspi_putreg(&g_qspi0dev, QSPI_FCR_CTEF, STM32L4_QUADSPI_FCR); - + /* Disable all the QSPI Interrupts */ - + regval = qspi_getreg(&g_qspi0dev, STM32L4_QUADSPI_CR_OFFSET); regval &= ~(QSPI_CR_TEIE | QSPI_CR_TCIE | QSPI_CR_FTIE | QSPI_CR_SMIE | QSPI_CR_TOIE); qspi_putreg(&g_qspi0dev, regval, STM32L4_QUADSPI_CR_OFFSET); @@ -1225,22 +1225,22 @@ static int qspi0_interrupt(int irq, void *context, FAR void *arg) * presumably relative to the FSIZE field in CCR; the manual is not * explicit, but what else could it be? */ - + g_qspi0dev.xctn->disposition = - EIO; /* Signal complete */ - + sem_post(&g_qspi0dev.op_sem); } /* Is it 'Timeout'? */ - + if ((status & QSPI_SR_TOF) && (cr & QSPI_CR_TOIE)) { /* Acknowledge interrupt */ - + qspi_putreg(&g_qspi0dev, QSPI_FCR_CTOF, STM32L4_QUADSPI_FCR); - + /* XXX this interrupt simply means that, in 'memory mapped mode', * the QSPI memory has not been accessed for a while, and the * IP block was configured to automatically de-assert CS after @@ -1400,7 +1400,7 @@ static int qspi_memory_dma(struct stm32l4_qspidev_s *priv, if (QSPIMEM_ISWRITE(meminfo->flags)) { /* Setup the DMA (memory-to-peripheral) */ - + dmaflags = (QSPI_DMA_PRIO | DMA_CCR_MSIZE_8BITS | DMA_CCR_PSIZE_8BITS | DMA_CCR_MINC | DMA_CCR_DIR); } else @@ -1409,7 +1409,7 @@ static int qspi_memory_dma(struct stm32l4_qspidev_s *priv, dmaflags = (QSPI_DMA_PRIO | DMA_CCR_MSIZE_8BITS | DMA_CCR_PSIZE_8BITS | DMA_CCR_MINC ); } - + stm32l4_dmasetup(priv->dmach, qspi_regaddr(priv, STM32L4_QUADSPI_DR_OFFSET), (uint32_t)meminfo->buffer, meminfo->buflen, dmaflags); @@ -1825,7 +1825,7 @@ static void qspi_setmode(struct qspi_dev_s *dev, enum qspi_mode_e mode) */ return; } - + spiinfo("mode=%d\n", mode); /* Has the mode changed? */ @@ -1924,12 +1924,12 @@ static int qspi_command(struct qspi_dev_s *dev, * automatically cancel the memory mapping. You must exit the * memory mapped mode first. */ - + if (priv->memmap) { return -EBUSY; } - + /* Set up the transaction descriptor as per command info */ ret = qspi_setupxctnfromcmd(&xctn, cmdinfo); @@ -1953,7 +1953,7 @@ static int qspi_command(struct qspi_dev_s *dev, #ifdef STM32L4_QSPI_INTERRUPTS /* interrupt mode will need access to the transaction context */ - + priv->xctn = &xctn; if (QSPICMD_ISDATA(cmdinfo->flags)) @@ -1964,7 +1964,7 @@ static int qspi_command(struct qspi_dev_s *dev, if (QSPICMD_ISWRITE(cmdinfo->flags)) { uint32_t regval; - + /* Set up the Communications Configuration Register as per command * info */ @@ -1974,7 +1974,7 @@ static int qspi_command(struct qspi_dev_s *dev, /* Enable 'Transfer Error' 'FIFO Threshhold' and 'Transfer Complete' * interrupts. */ - + regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); regval |= (QSPI_CR_TEIE | QSPI_CR_FTIE | QSPI_CR_TCIE); qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); @@ -1983,9 +1983,9 @@ static int qspi_command(struct qspi_dev_s *dev, { uint32_t regval; uint32_t addrval; - + addrval = qspi_getreg(priv, STM32L4_QUADSPI_AR_OFFSET); - + /* Set up the Communications Configuration Register as per command * info */ @@ -1993,13 +1993,13 @@ static int qspi_command(struct qspi_dev_s *dev, qspi_ccrconfig(priv, &xctn, CCR_FMODE_INDRD); /* Start the transfer by re-writing the address in AR register */ - + qspi_putreg(priv, addrval, STM32L4_QUADSPI_AR_OFFSET); /* Enable 'Transfer Error' 'FIFO Threshhold' and 'Transfer Complete' * interrupts */ - + regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); regval |= (QSPI_CR_TEIE | QSPI_CR_FTIE | QSPI_CR_TCIE); qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); @@ -2008,13 +2008,13 @@ static int qspi_command(struct qspi_dev_s *dev, else { uint32_t regval; - + /* We have no data phase, the command will execute as soon as we emit * the CCR */ /* Enable 'Transfer Error' and 'Transfer Complete' interrupts */ - + regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); regval |= (QSPI_CR_TEIE | QSPI_CR_TCIE); qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); @@ -2025,14 +2025,14 @@ static int qspi_command(struct qspi_dev_s *dev, qspi_ccrconfig(priv, &xctn, CCR_FMODE_INDRD); } - + /* Wait for the interrupt routine to finish it's magic */ - + sem_wait(&priv->op_sem); MEMORY_SYNC(); - + /* Convey the result */ - + ret = xctn.disposition; /* because command transfers are so small, we're not going to use @@ -2073,7 +2073,7 @@ static int qspi_command(struct qspi_dev_s *dev, qspi_waitstatusflags(priv, QSPI_SR_TCF,1); qspi_waitstatusflags(priv, QSPI_SR_BUSY,0); - + #endif return ret; @@ -2105,12 +2105,12 @@ static int qspi_memory(struct qspi_dev_s *dev, * automatically cancel the memory mapping. You must exit the * memory mapped mode first. */ - + if (priv->memmap) { return -EBUSY; } - + /* Set up the transaction descriptor as per command info */ ret = qspi_setupxctnfrommem(&xctn, meminfo); @@ -2134,7 +2134,7 @@ static int qspi_memory(struct qspi_dev_s *dev, #ifdef STM32L4_QSPI_INTERRUPTS /* interrupt mode will need access to the transaction context */ - + priv->xctn = &xctn; DEBUGASSERT(meminfo->buffer != NULL && meminfo->buflen > 0); @@ -2143,7 +2143,7 @@ static int qspi_memory(struct qspi_dev_s *dev, if (QSPIMEM_ISWRITE(meminfo->flags)) { uint32_t regval; - + /* Set up the Communications Configuration Register as per command * info */ @@ -2153,7 +2153,7 @@ static int qspi_memory(struct qspi_dev_s *dev, /* Enable 'Transfer Error' 'FIFO Threshhold' and 'Transfer Complete' * interrupts */ - + regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); regval |= (QSPI_CR_TEIE | QSPI_CR_FTIE | QSPI_CR_TCIE); qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); @@ -2162,9 +2162,9 @@ static int qspi_memory(struct qspi_dev_s *dev, { uint32_t regval; uint32_t addrval; - + addrval = qspi_getreg(priv, STM32L4_QUADSPI_AR_OFFSET); - + /* Set up the Communications Configuration Register as per command * info */ @@ -2172,25 +2172,25 @@ static int qspi_memory(struct qspi_dev_s *dev, qspi_ccrconfig(priv, &xctn, CCR_FMODE_INDRD); /* Start the transfer by re-writing the address in AR register */ - + qspi_putreg(priv, addrval, STM32L4_QUADSPI_AR_OFFSET); /* Enable 'Transfer Error' 'FIFO Threshhold' and 'Transfer Complete' * interrupts */ - + regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); regval |= (QSPI_CR_TEIE | QSPI_CR_FTIE | QSPI_CR_TCIE); qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); } /* Wait for the interrupt routine to finish it's magic */ - + sem_wait(&priv->op_sem); MEMORY_SYNC(); /* convey the result */ - + ret = xctn.disposition; #elif defined(CONFIG_STM32L4_QSPI_DMA) @@ -2230,7 +2230,7 @@ static int qspi_memory(struct qspi_dev_s *dev, qspi_waitstatusflags(priv, QSPI_SR_TCF,1); qspi_waitstatusflags(priv, QSPI_SR_BUSY,0); - + MEMORY_SYNC(); } @@ -2260,7 +2260,7 @@ static int qspi_memory(struct qspi_dev_s *dev, qspi_waitstatusflags(priv, QSPI_SR_TCF,1); qspi_waitstatusflags(priv, QSPI_SR_BUSY,0); - + MEMORY_SYNC(); #endif @@ -2607,17 +2607,17 @@ void stm32l4_qspi_enter_memorymapped(struct qspi_dev_s* dev, struct qspi_xctnspec_s xctn; /* lock during this mode change */ - + qspi_lock(dev, true); - + if (priv->memmap) { qspi_lock(dev, false); return; } - + /* Abort anything in-progress */ - + qspi_abort(priv); /* Wait till BUSY flag reset */ @@ -2625,22 +2625,22 @@ void stm32l4_qspi_enter_memorymapped(struct qspi_dev_s* dev, qspi_waitstatusflags(priv, QSPI_SR_BUSY, 0); /* if we want the 'low-power timeout counter' */ - + if (lpto > 0) { /* Set the Low Power Timeout value (automatically de-assert * CS if memory is not accessed for a while) */ - + qspi_putreg(priv, lpto, STM32L4_QUADSPI_LPTR_OFFSET); - + /* Clear Timeout interrupt */ - + qspi_putreg(&g_qspi0dev, QSPI_FCR_CTOF, STM32L4_QUADSPI_FCR); - + #ifdef STM32L4_QSPI_INTERRUPTS /* Enable Timeout interrupt */ - + regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); regval |= (QSPI_CR_TCEN | QSPI_CR_TOIE); qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); @@ -2654,24 +2654,24 @@ void stm32l4_qspi_enter_memorymapped(struct qspi_dev_s* dev, } /* create a transaction object */ - + qspi_setupxctnfrommem(&xctn, meminfo); - + #ifdef STM32L4_QSPI_INTERRUPTS priv->xctn = NULL; #endif /* set it into the ccr */ - + qspi_ccrconfig(priv, &xctn, CCR_FMODE_MEMMAP); priv->memmap = true; - + /* we should be in memory mapped mode now */ - + qspi_dumpregs(priv, "After memory mapped:"); /* finished this mode change */ - + qspi_lock(dev, false); } @@ -2692,14 +2692,14 @@ void stm32l4_qspi_enter_memorymapped(struct qspi_dev_s* dev, void stm32l4_qspi_exit_memorymapped(struct qspi_dev_s* dev) { struct stm32l4_qspidev_s *priv = (struct stm32l4_qspidev_s *)dev; - + qspi_lock(dev, true); - + /* A simple abort is sufficient */ - + qspi_abort(priv); priv->memmap = false; - + qspi_lock(dev, false); } diff --git a/arch/arm/src/stm32l4/stm32l4_rcc.h b/arch/arm/src/stm32l4/stm32l4_rcc.h index 8a8d2d7f2a1..741b5620d5e 100644 --- a/arch/arm/src/stm32l4/stm32l4_rcc.h +++ b/arch/arm/src/stm32l4/stm32l4_rcc.h @@ -9,7 +9,7 @@ * are met: * * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. + * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the diff --git a/arch/arm/src/stm32l4/stm32l4_start.c b/arch/arm/src/stm32l4/stm32l4_start.c index 916985cccfc..b2053f25ed0 100644 --- a/arch/arm/src/stm32l4/stm32l4_start.c +++ b/arch/arm/src/stm32l4/stm32l4_start.c @@ -299,7 +299,7 @@ void __start(void) * under application-specific circumstances. On the other hand, if we're * using this memory for, say, additional heap space, then this is handy. */ - + for (dest = (uint32_t *)SRAM2_START; dest < (uint32_t *)SRAM2_END; ) { *dest++ = 0; diff --git a/arch/arm/src/stm32l4/stm32l4_tim.c b/arch/arm/src/stm32l4/stm32l4_tim.c index 938be218ae0..2180884d7e4 100644 --- a/arch/arm/src/stm32l4/stm32l4_tim.c +++ b/arch/arm/src/stm32l4/stm32l4_tim.c @@ -230,7 +230,7 @@ struct stm32l4_tim_priv_s static inline uint16_t stm32l4_getreg16(FAR struct stm32l4_tim_dev_s *dev, uint8_t offset); -static inline void stm32l4_putreg16(FAR struct stm32l4_tim_dev_s *dev, +static inline void stm32l4_putreg16(FAR struct stm32l4_tim_dev_s *dev, uint8_t offset, uint16_t value); static inline void stm32l4_modifyreg16(FAR struct stm32l4_tim_dev_s *dev, uint8_t offset, uint16_t clearbits, @@ -261,9 +261,9 @@ static int stm32l4_tim_setclock(FAR struct stm32l4_tim_dev_s *dev, static void stm32l4_tim_setperiod(FAR struct stm32l4_tim_dev_s *dev, uint32_t period); static uint32_t stm32l4_tim_getcounter(FAR struct stm32l4_tim_dev_s *dev); -static int stm32l4_tim_setchannel(FAR struct stm32l4_tim_dev_s *dev, +static int stm32l4_tim_setchannel(FAR struct stm32l4_tim_dev_s *dev, uint8_t channel, stm32l4_tim_channel_t mode); -static int stm32l4_tim_setcompare(FAR struct stm32l4_tim_dev_s *dev, +static int stm32l4_tim_setcompare(FAR struct stm32l4_tim_dev_s *dev, uint8_t channel, uint32_t compare); static int stm32l4_tim_getcapture(FAR struct stm32l4_tim_dev_s *dev, uint8_t channel); diff --git a/arch/arm/src/stm32l4/stm32l4x6xx_dma.c b/arch/arm/src/stm32l4/stm32l4x6xx_dma.c index 335e008b182..e63c73be4f9 100644 --- a/arch/arm/src/stm32l4/stm32l4x6xx_dma.c +++ b/arch/arm/src/stm32l4/stm32l4x6xx_dma.c @@ -476,7 +476,7 @@ void stm32l4_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, DEBUGASSERT(handle != NULL); DEBUGASSERT(ntransfers<65536); - + /* Then DMA_CNDTRx register can only be modified if the DMA channel is * disabled. */ diff --git a/arch/arm/src/tiva/chip/tiva_i2c.h b/arch/arm/src/tiva/chip/tiva_i2c.h index 61c0fec5bed..4ca70eaf265 100644 --- a/arch/arm/src/tiva/chip/tiva_i2c.h +++ b/arch/arm/src/tiva/chip/tiva_i2c.h @@ -1040,13 +1040,13 @@ /* I2C Peripheral Properties */ #if defined(CONFIG_ARCH_CHIP_TM4C) -# define I2CSC_PP_HS (1 << 0) /* Bit 0: High-Speed Capable */ +# define I2CSC_PP_HS (1 << 0) /* Bit 0: High-Speed Capable */ #endif /* I2C Peripheral Configuration */ #if defined(CONFIG_ARCH_CHIP_TM4C) -# define I2CSC_PC_HS (1 << 0) /* Bit 0: High-Speed Capable */ +# define I2CSC_PC_HS (1 << 0) /* Bit 0: High-Speed Capable */ #endif /************************************************************************************ diff --git a/arch/arm/src/tiva/chip/tiva_timer.h b/arch/arm/src/tiva/chip/tiva_timer.h index 9a7a3f1808c..8415ffe789c 100644 --- a/arch/arm/src/tiva/chip/tiva_timer.h +++ b/arch/arm/src/tiva/chip/tiva_timer.h @@ -6,7 +6,7 @@ * Copyright (C) 2012, 2014 Max Nekludov. All rights reserved. * Author: Max Nekludov * - * Ongoing support and major revision to support the TM4C129 family + * Ongoing support and major revision to support the TM4C129 family * (essentially a full file replacement): * * Copyright (C) 2015 Gregory Nutt. All rights reserved. diff --git a/arch/arm/src/tiva/tm4c_ethernet.c b/arch/arm/src/tiva/tm4c_ethernet.c index b41461eb848..3458db363cd 100644 --- a/arch/arm/src/tiva/tm4c_ethernet.c +++ b/arch/arm/src/tiva/tm4c_ethernet.c @@ -3587,7 +3587,7 @@ static inline void tiva_phy_initialize(FAR struct tiva_ethmac_s *priv) /* Enable pulse-per-second (PPS) output signal */ tiva_configgpio(GPIO_EN0_PPS); -#endif +#endif } /**************************************************************************** diff --git a/arch/arm/src/tms570/tms570_clockconfig.c b/arch/arm/src/tms570/tms570_clockconfig.c index 2e8b76a480f..40938bbc7a8 100644 --- a/arch/arm/src/tms570/tms570_clockconfig.c +++ b/arch/arm/src/tms570/tms570_clockconfig.c @@ -432,7 +432,7 @@ static void tms570_clocksrc_configure(void) /* Work Around for Errata SYS#46: Errata Description: Clock Source * Switching Not Qualified with Clock Source Enable And Clock Source Valid * Workaround: Always check the CSDIS register to make sure the clock source - * is turned on and check the CSVSTAT register to make sure the clock source + * is turned on and check the CSVSTAT register to make sure the clock source * is valid. Then write to GHVSRC to switch the clock. */ diff --git a/arch/arm/src/tms570/tms570_esm.c b/arch/arm/src/tms570/tms570_esm.c index dfecf47e8a7..f267f1a8fde 100644 --- a/arch/arm/src/tms570/tms570_esm.c +++ b/arch/arm/src/tms570/tms570_esm.c @@ -121,7 +121,7 @@ int tms570_esm_initialize(void) putreg32(0xffffffff, TMS570_ESM_ILCR4); /* Set interrupt level (Writing zero does nothing) */ - + putreg32(0, TMS570_ESM_ILSR1); putreg32(0, TMS570_ESM_ILSR4); diff --git a/arch/arm/src/xmc4/xmc4_lowputc.c b/arch/arm/src/xmc4/xmc4_lowputc.c index c1416194fc3..3e374106d04 100644 --- a/arch/arm/src/xmc4/xmc4_lowputc.c +++ b/arch/arm/src/xmc4/xmc4_lowputc.c @@ -364,7 +364,7 @@ int xmc4_uart_configure(enum usic_channel_e channel, * - DPTR = 16 * - LIMIT = 1 * - STBTEN = 0, the trigger of the standard transmit buffer event is - * based on the transition of the fill level from equal to below the + * based on the transition of the fill level from equal to below the * limit, not the fact being below * - SIZE = 16 * - LOF = 0, A standard transmit buffer event occurs when the filling diff --git a/arch/avr/include/avr/irq.h b/arch/avr/include/avr/irq.h index e2592875101..aa409fe450b 100644 --- a/arch/avr/include/avr/irq.h +++ b/arch/avr/include/avr/irq.h @@ -119,7 +119,7 @@ struct xcptcontext uint8_t saved_pc0; # if defined(REG_PC2) uint8_t saved_pc2; -# endif +# endif uint8_t saved_sreg; #endif diff --git a/arch/avr/src/avr/up_switchcontext.S b/arch/avr/src/avr/up_switchcontext.S index 913cbfb39a8..3fc1b6ae42e 100644 --- a/arch/avr/src/avr/up_switchcontext.S +++ b/arch/avr/src/avr/up_switchcontext.S @@ -40,7 +40,7 @@ #include #include - + #include "excptmacros.h" /************************************************************************************ diff --git a/arch/mips/include/pic32mz/chip.h b/arch/mips/include/pic32mz/chip.h index a96fb6ca707..d36c4515252 100644 --- a/arch/mips/include/pic32mz/chip.h +++ b/arch/mips/include/pic32mz/chip.h @@ -134,7 +134,7 @@ #ifdef __cplusplus #define EXTERN extern "C" -extern "C" +extern "C" { #else #define EXTERN extern diff --git a/arch/mips/src/pic32mz/chip/pic32mzec-pps.h b/arch/mips/src/pic32mz/chip/pic32mzec-pps.h index 04a88967729..8ee9f4d7e74 100644 --- a/arch/mips/src/pic32mz/chip/pic32mzec-pps.h +++ b/arch/mips/src/pic32mz/chip/pic32mzec-pps.h @@ -373,7 +373,7 @@ #define IC3R_RPC14 7 #define IC3R_RPD2 0 #define IC3R_RPD6 14 -#define IC3R_RPD10 3 +#define IC3R_RPD10 3 #define IC3R_RPD14 11 #define IC3R_RPF1 4 #define IC3R_RPF4 2 @@ -430,7 +430,7 @@ #define IC7R_RPC14 7 #define IC7R_RPD2 0 #define IC7R_RPD6 14 -#define IC7R_RPD10 3 +#define IC7R_RPD10 3 #define IC7R_RPD14 11 #define IC7R_RPF1 4 #define IC7R_RPF4 2 @@ -501,7 +501,7 @@ #define INT3R_RPC14 7 #define INT3R_RPD2 0 #define INT3R_RPD6 14 -#define INT3R_RPD10 3 +#define INT3R_RPD10 3 #define INT3R_RPD14 11 #define INT3R_RPF1 4 #define INT3R_RPF4 2 @@ -544,7 +544,7 @@ #define REFCLKI1R_RPC14 7 #define REFCLKI1R_RPD2 0 #define REFCLKI1R_RPD6 14 -#define REFCLKI1R_RPD10 3 +#define REFCLKI1R_RPD10 3 #define REFCLKI1R_RPD14 11 #define REFCLKI1R_RPF1 4 #define REFCLKI1R_RPF4 2 @@ -587,7 +587,7 @@ #define SDI1R_RPC14 7 #define SDI1R_RPD2 0 #define SDI1R_RPD6 14 -#define SDI1R_RPD10 3 +#define SDI1R_RPD10 3 #define SDI1R_RPD14 11 #define SDI1R_RPF1 4 #define SDI1R_RPF4 2 @@ -616,7 +616,7 @@ #define SDI3R_RPC1 10 #define SDI3R_RPC14 7 #define SDI3R_RPD2 0 -#define SDI3R_RPD10 3 +#define SDI3R_RPD10 3 #define SDI3R_RPD14 11 #define SDI3R_RPD6 14 #define SDI3R_RPF1 4 @@ -647,7 +647,7 @@ #define SDI5R_RPC14 7 #define SDI5R_RPD2 0 #define SDI5R_RPD6 14 -#define SDI5R_RPD10 3 +#define SDI5R_RPD10 3 #define SDI5R_RPD14 11 #define SDI5R_RPF1 4 #define SDI5R_RPF4 2 @@ -744,7 +744,7 @@ #define SS6R_RPC14 7 #define SS6R_RPD2 0 #define SS6R_RPD6 14 -#define SS6R_RPD10 3 +#define SS6R_RPD10 3 #define SS6R_RPD14 11 #define SS6R_RPF1 4 #define SS6R_RPF4 2 @@ -759,7 +759,7 @@ #define T2CKR_RPC14 7 #define T2CKR_RPD2 0 #define T2CKR_RPD6 14 -#define T2CKR_RPD10 3 +#define T2CKR_RPD10 3 #define T2CKR_RPD14 11 #define T2CKR_RPF1 4 #define T2CKR_RPF4 2 @@ -816,7 +816,7 @@ #define T6CKR_RPC14 7 #define T6CKR_RPD2 0 #define T6CKR_RPD6 14 -#define T6CKR_RPD10 3 +#define T6CKR_RPD10 3 #define T6CKR_RPD14 11 #define T6CKR_RPF1 4 #define T6CKR_RPF4 2 @@ -887,7 +887,7 @@ #define U1RXR_RPC14 7 #define U1RXR_RPD2 0 #define U1RXR_RPD6 14 -#define U1RXR_RPD10 3 +#define U1RXR_RPD10 3 #define U1RXR_RPD14 11 #define U1RXR_RPF1 4 #define U1RXR_RPF4 2 @@ -902,7 +902,7 @@ #define U2CTSR_RPC14 7 #define U2CTSR_RPD2 0 #define U2CTSR_RPD6 14 -#define U2CTSR_RPD10 3 +#define U2CTSR_RPD10 3 #define U2CTSR_RPD14 11 #define U2CTSR_RPF1 4 #define U2CTSR_RPF4 2 @@ -1001,7 +1001,7 @@ #define U5RXR_RPC14 7 #define U5RXR_RPD2 0 #define U5RXR_RPD6 14 -#define U5RXR_RPD10 3 +#define U5RXR_RPD10 3 #define U5RXR_RPD14 11 #define U5RXR_RPF1 4 #define U5RXR_RPF4 2 @@ -1016,7 +1016,7 @@ #define U6CTSR_RPC14 7 #define U6CTSR_RPD2 0 #define U6CTSR_RPD6 14 -#define U6CTSR_RPD10 3 +#define U6CTSR_RPD10 3 #define U6CTSR_RPD14 11 #define U6CTSR_RPF1 4 #define U6CTSR_RPF4 2 diff --git a/arch/misoc/src/lm32/chip.h b/arch/misoc/src/lm32/chip.h index 78d671f7f94..46061985159 100644 --- a/arch/misoc/src/lm32/chip.h +++ b/arch/misoc/src/lm32/chip.h @@ -78,7 +78,7 @@ static inline void irq_setmask(unsigned int mask) static inline unsigned int irq_pending(void) { - + unsigned int pending; __asm__ __volatile__("rcsr %0, IP" : "=r" (pending)); return pending; diff --git a/arch/misoc/src/lm32/lm32_dumpstate.c b/arch/misoc/src/lm32/lm32_dumpstate.c index 229aee8bfd2..1a26791cb11 100644 --- a/arch/misoc/src/lm32/lm32_dumpstate.c +++ b/arch/misoc/src/lm32/lm32_dumpstate.c @@ -65,9 +65,9 @@ static inline uint32_t up_getsp(void) { register uint32_t sp; - + __asm__ __volatile__("addi %0, sp, 0" : "=r" (sp)); - + return sp; } diff --git a/arch/misoc/src/lm32/lm32_swint.c b/arch/misoc/src/lm32/lm32_swint.c index 7a49cdbb337..17bbc487525 100644 --- a/arch/misoc/src/lm32/lm32_swint.c +++ b/arch/misoc/src/lm32/lm32_swint.c @@ -136,7 +136,7 @@ int lm32_swint(int irq, FAR void *context, FAR void *arg) DEBUGASSERT(g_current_regs == NULL); g_current_regs = regs; - + /* Software interrupt 0 is invoked with REG_A0 (REG_X10) = system call * command and REG_A1-6 = variable number of * arguments depending on the system call. diff --git a/arch/risc-v/include/arch.h b/arch/risc-v/include/arch.h index e0e60b4e1b2..8e0abb258ee 100644 --- a/arch/risc-v/include/arch.h +++ b/arch/risc-v/include/arch.h @@ -57,7 +57,7 @@ /* Macros to get the core and vendor ID, HART, arch and ISA codes, etc. */ -#ifdef CONFIG_RV32IM_SYSTEM_CSRRS_SUPPORT +#ifdef CONFIG_RV32IM_SYSTEM_CSRRS_SUPPORT uint32_t up_getmisa(void); uint32_t up_getarchid(void); @@ -91,7 +91,7 @@ uint32_t up_gethartid(void); * Public Function Prototypes ****************************************************************************/ -#ifdef CONFIG_RV32IM_HW_MULDIV +#ifdef CONFIG_RV32IM_HW_MULDIV uint32_t up_hard_mul(uint32_t a, uint32_t b); uint32_t up_hard_mulh(uint32_t a, uint32_t b); uint32_t up_hard_mulhsu(uint32_t a, uint32_t b); diff --git a/arch/risc-v/src/Makefile b/arch/risc-v/src/Makefile index e5916c35342..4ebba1c476f 100644 --- a/arch/risc-v/src/Makefile +++ b/arch/risc-v/src/Makefile @@ -42,7 +42,7 @@ ifeq ($(CONFIG_ARCH_RV32I),y) # Base Integer support ARCH_SUBDIR = rv32i else ifeq ($(CONFIG_ARCH_RV32IM),y) # Integer + math support ARCH_SUBDIR = rv32im -else +else ARCH_SUBDIR = rv32i # Default to base RV32I core endif @@ -152,7 +152,7 @@ VPATH += $(CHIP_DIR) all: $(HEAD_OBJ) $(BIN) -.PHONY: board/libboard$(LIBEXT) +.PHONY: board/libboard$(LIBEXT) $(AOBJS) $(UAOBJS) $(HEAD_OBJ): %$(OBJEXT): %.S $(call ASSEMBLE, $<, $@) @@ -162,7 +162,7 @@ $(COBJS) $(UCOBJS): %$(OBJEXT): %.c $(BIN) $(KBIN): $(OBJS) $(call ARCHIVE, $@, $(OBJS)) - @$(MAKE) depend + @$(MAKE) depend $(UBIN): $(UOBJS) $(call ARCHIVE, $@, $(UOBJS)) diff --git a/arch/risc-v/src/nr5m100/Make.defs b/arch/risc-v/src/nr5m100/Make.defs index 8d7b9ee85b4..02187de74a7 100644 --- a/arch/risc-v/src/nr5m100/Make.defs +++ b/arch/risc-v/src/nr5m100/Make.defs @@ -45,7 +45,7 @@ endif # Override the arch to enable hardware MUL during assembly. # This is to support our hardware mul test. For that test, -# we have to disable hardware mul for C code so the soft +# we have to disable hardware mul for C code so the soft # math libs will be used to compare software mul vs hw mul. # But hw mul must be enabled to compile the .S file, or we # will get an illegal instruction error. diff --git a/arch/risc-v/src/nr5m100/chip/nr5m1xx_timer.h b/arch/risc-v/src/nr5m100/chip/nr5m1xx_timer.h index 4739965cf43..98ea8aa8035 100644 --- a/arch/risc-v/src/nr5m100/chip/nr5m1xx_timer.h +++ b/arch/risc-v/src/nr5m100/chip/nr5m1xx_timer.h @@ -54,7 +54,7 @@ /* Timer 1 address definitions */ -#ifdef CONFIG_NR5_TIMER1 +#ifdef CONFIG_NR5_TIMER1 #define NR5_TIMER1_TACTL_OFFSET (NR5_TIMER1_BASE+NR5_TIMERA_TACTL_OFFSET) #define NR5_TIMER1_TAR_OFFSET (NR5_TIMER1_BASE+NR5_TIMERA_TAR_OFFSET) #define NR5_TIMER1_TACCTL0_OFFSET (NR5_TIMER1_BASE+NR5_TIMERA_TACCTL0_OFFSET) @@ -68,7 +68,7 @@ /* Timer 2 address definitions */ -#ifdef CONFIG_NR5_TIMER2 +#ifdef CONFIG_NR5_TIMER2 #define NR5_TIMER2_TACTL_OFFSET (NR5_TIMER2_BASE+NR5_TIMERA_TACTL_OFFSET) #define NR5_TIMER2_TAR_OFFSET (NR5_TIMER2_BASE+NR5_TIMERA_TAR_OFFSET) #define NR5_TIMER2_TACCTL0_OFFSET (NR5_TIMER2_BASE+NR5_TIMERA_TACCTL0_OFFSET) @@ -82,7 +82,7 @@ /* Timer 3 address definitions */ -#ifdef CONFIG_NR5_TIMER3 +#ifdef CONFIG_NR5_TIMER3 #define NR5_TIMER3_TACTL_OFFSET (NR5_TIMER3_BASE+NR5_TIMERA_TACTL_OFFSET) #define NR5_TIMER3_TAR_OFFSET (NR5_TIMER3_BASE+NR5_TIMERA_TAR_OFFSET) #define NR5_TIMER3_TACCTL0_OFFSET (NR5_TIMER3_BASE+NR5_TIMERA_TACCTL0_OFFSET) @@ -96,7 +96,7 @@ /* Timer 4 address definitions */ -#ifdef CONFIG_NR5_TIMER4 +#ifdef CONFIG_NR5_TIMER4 #define NR5_TIMER4_TACTL_OFFSET (NR5_TIMER4_BASE+NR5_TIMERA_TACTL_OFFSET) #define NR5_TIMER4_TAR_OFFSET (NR5_TIMER4_BASE+NR5_TIMERA_TAR_OFFSET) #define NR5_TIMER4_TACCTL0_OFFSET (NR5_TIMER4_BASE+NR5_TIMERA_TACCTL0_OFFSET) @@ -110,7 +110,7 @@ /* Timer 5 address definitions */ -#ifdef CONFIG_NR5_TIMER5 +#ifdef CONFIG_NR5_TIMER5 #define NR5_TIMER5_TACTL_OFFSET (NR5_TIMER5_BASE+NR5_TIMERA_TACTL_OFFSET) #define NR5_TIMER5_TAR_OFFSET (NR5_TIMER5_BASE+NR5_TIMERA_TAR_OFFSET) #define NR5_TIMER5_TACCTL0_OFFSET (NR5_TIMER5_BASE+NR5_TIMERA_TACCTL0_OFFSET) @@ -126,7 +126,7 @@ /* Control register TACTL Bit definitions */ -#define TIMERA_TACTL_TAIFG (1 << 0) /* Bit 0: Interrupt Pending Flag */ +#define TIMERA_TACTL_TAIFG (1 << 0) /* Bit 0: Interrupt Pending Flag */ #define TIMERA_TACTL_TAIE (1 << 1) /* Bit 1: Interrupt Enable */ #define TIMERA_TACTL_TACLR (1 << 2) /* Bit 2: TAR counter clear */ #define TIMERA_TACTL_MC_SHIFT 4 /* Bits 4-5: Mode Control */ @@ -146,14 +146,14 @@ # define TIMERA_TACTL_SYS_CLOCK (2 << TIMERA_TACTL_TASSEL_SHIFT) # define TIMERA_TACTL_EXT_CLOCK (3 << TIMERA_TACTL_TASSEL_SHIFT) #define TIMERA_TACTL_TAPRE_SHIFT 10 /* Bits 10-15: Clock Prescaler */ -#define TIMERA_TACTL_TAPRE_MASK 0x3F +#define TIMERA_TACTL_TAPRE_MASK 0x3F # define TIMERA_TACTL_TAPRE(x) (((x) & TIMERA_TACTL_TAPRE_MASK) << TIMERA_TACTL_TAPRE_SHIFT) /* Capture / Compare register bit definitions */ -#define TIMERA_TACCTL_CCIFG (1 << 0) /* Bit 0: Capture/compare interrupt Flag */ -#define TIMERA_TACCTL_COV (1 << 1) /* Bit 1: Capture overflow */ -#define TIMERA_TACCTL_OUTVAL (1 << 2) /* Bit 2: Output value */ +#define TIMERA_TACCTL_CCIFG (1 << 0) /* Bit 0: Capture/compare interrupt Flag */ +#define TIMERA_TACCTL_COV (1 << 1) /* Bit 1: Capture overflow */ +#define TIMERA_TACCTL_OUTVAL (1 << 2) /* Bit 2: Output value */ #define TIMERA_TACCTL_CCI (1 << 3) /* Bit 3: Capture/compare input value */ #define TIMERA_TACCTL_CCIE (1 << 4) /* Bit 4: Capture/Compare interrupt Enable */ #define TIMERA_TACCTL_OUTMOD_SHIFT 5 /* Bits 5-7: Output Mode */ @@ -165,9 +165,9 @@ # define TIMERA_TACCTL_RESET (5 << TIMERA_TACCTL_OUTMOD_SHIFT) # define TIMERA_TACCTL_TOGGLE_SET (6 << TIMERA_TACCTL_OUTMOD_SHIFT) # define TIMERA_TACCTL_RESET_SET (7 << TIMERA_TACCTL_OUTMOD_SHIFT) -#define TIMERA_TACCTL_CAP (1 << 8) /* Bit 8: Capture mode select */ -#define TIMERA_TACCTL_SCCI (1 << 10) /* Bit 10: Synchronized capture input */ -#define TIMERA_TACCTL_SCS (1 << 11) /* Bit 11: Syncronize capture source */ +#define TIMERA_TACCTL_CAP (1 << 8) /* Bit 8: Capture mode select */ +#define TIMERA_TACCTL_SCCI (1 << 10) /* Bit 10: Synchronized capture input */ +#define TIMERA_TACCTL_SCS (1 << 11) /* Bit 11: Syncronize capture source */ #define TIMERA_TACCTL_CCIS_SHIFT 12 /* Bits 12-13: Capture Input Select */ # define TIMERA_TACCTL_CCIS_CCIA (0 << TIMERA_TACCTL_CCIS_SHIFT) # define TIMERA_TACCTL_CCIS_CCIB (1 << TIMERA_TACCTL_CCIS_SHIFT) diff --git a/arch/risc-v/src/nr5m100/chip/nr5m1xx_uart.h b/arch/risc-v/src/nr5m100/chip/nr5m1xx_uart.h index 5a790782e98..215f8916fee 100644 --- a/arch/risc-v/src/nr5m100/chip/nr5m1xx_uart.h +++ b/arch/risc-v/src/nr5m100/chip/nr5m1xx_uart.h @@ -41,7 +41,7 @@ * No parity. * * It has a programmable baud rate and RX / TX interrupt capability - * and that's about it. The primary goal for the UART is to provide a + * and that's about it. The primary goal for the UART is to provide a * debug console to the part. */ diff --git a/arch/risc-v/src/nr5m100/nr5_csr.S b/arch/risc-v/src/nr5m100/nr5_csr.S index 13133005a02..faf5c048574 100644 --- a/arch/risc-v/src/nr5m100/nr5_csr.S +++ b/arch/risc-v/src/nr5m100/nr5_csr.S @@ -269,7 +269,7 @@ up_setq2: ret /**************************************************************************** - * Calls the NR5M100 specific LSBENC opcode. This opcode will find the + * Calls the NR5M100 specific LSBENC opcode. This opcode will find the * first least significant non-zero bit in a0 and return it's ordinal value. ****************************************************************************/ diff --git a/arch/risc-v/src/nr5m100/nr5_head.S b/arch/risc-v/src/nr5m100/nr5_head.S index cc0d2156321..e41ddc39d57 100644 --- a/arch/risc-v/src/nr5m100/nr5_head.S +++ b/arch/risc-v/src/nr5m100/nr5_head.S @@ -64,7 +64,7 @@ .global irq_handler -#ifdef CONFIG_RV32IM_HW_MULDIV +#ifdef CONFIG_RV32IM_HW_MULDIV .global time_hard_mul .global hard_mul .global hard_mulh @@ -183,7 +183,7 @@ __start: la t0, __nr5_init jr t0 - + /* We shouldn't return from __nr5_init */ .global _init @@ -403,7 +403,7 @@ irq_handler: lw x31, 31*4(x1) /* Restore return PC to q0. This will cause the - * processor to enter a critical state where + * processor to enter a critical state where * higher priority IRQs won't happen until after * the mret, thus protecting our shared QREGS. */ @@ -515,7 +515,7 @@ irq_regs: irq_stack: irq_regs_addr: - .fill 4,4 + .fill 4,4 irq_stack_addr: .fill 4,4 @@ -525,7 +525,7 @@ irq_stack_addr: * the MUL / DIV opcodes for performing HARD vs SOFT testing. ****************************************************************************/ -#ifdef CONFIG_RV32IM_HW_MULDIV +#ifdef CONFIG_RV32IM_HW_MULDIV /* Multiply, return lower 32 bits */ diff --git a/arch/risc-v/src/nr5m100/nr5_irq.c b/arch/risc-v/src/nr5m100/nr5_irq.c index fd973e74541..a47b1397814 100644 --- a/arch/risc-v/src/nr5m100/nr5_irq.c +++ b/arch/risc-v/src/nr5m100/nr5_irq.c @@ -167,7 +167,7 @@ void up_irqinitialize(void) csrw %0, 0(zero) \ csrw %1, 0(zero) \ csrw %2, 0(zero) " :: - "i"(NR5_EPIC_PRI1_REG), "i"(NR5_EPIC_PRI2_REG), + "i"(NR5_EPIC_PRI1_REG), "i"(NR5_EPIC_PRI2_REG), "i"(NR5_EPIC_PRI3_REG) ); #endif @@ -300,7 +300,7 @@ irqstate_t up_irq_save(void) * continue to fire, but no general purpose ints. */ - __asm__ volatile("csrrw %0, %1, %2" : "=r"(oldIrqPri) : + __asm__ volatile("csrrw %0, %1, %2" : "=r"(oldIrqPri) : "i"(NR5_EPIC_PRIMASK), "r"(newIrqPri)); return oldIrqPri; diff --git a/arch/risc-v/src/nr5m100/nr5_irq_dispatch.c b/arch/risc-v/src/nr5m100/nr5_irq_dispatch.c index 5271d51abf3..2178cfdb66d 100644 --- a/arch/risc-v/src/nr5m100/nr5_irq_dispatch.c +++ b/arch/risc-v/src/nr5m100/nr5_irq_dispatch.c @@ -4,7 +4,7 @@ * Copyright (C) 2016 Ken Pettit. All rights reserved. * Author: Ken Pettit * - * Modified for RISC-V: + * Modified for RISC-V: * * Copyright (C) 2016 Ken Pettit. All rights reserved. * Author: Ken Pettit diff --git a/arch/risc-v/src/nr5m100/nr5_serial.c b/arch/risc-v/src/nr5m100/nr5_serial.c index 32572a5ebc4..4f39dddaaa4 100644 --- a/arch/risc-v/src/nr5m100/nr5_serial.c +++ b/arch/risc-v/src/nr5m100/nr5_serial.c @@ -432,7 +432,7 @@ static int up_interrupt(int irq, void *context, FAR void *arg) for (passes = 0; passes < 256 && handled; passes++) { handled = false; - + status = up_serialin(priv, NR5_UART_STATUS_REG_OFFSET); /* Handle incoming, received bytes. The RX FIFO is configured to diff --git a/arch/risc-v/src/nr5m100/nr5_uart.c b/arch/risc-v/src/nr5m100/nr5_uart.c index 312c6743d17..a97abd21eb8 100644 --- a/arch/risc-v/src/nr5m100/nr5_uart.c +++ b/arch/risc-v/src/nr5m100/nr5_uart.c @@ -101,7 +101,7 @@ static volatile struct nr5_uart_regs_s g_nr5_uart1_regs = .tx_irq = NR5_IRQ_UART1_TX, }; -static struct nr5_uart_s g_nr5_uart1 = +static struct nr5_uart_s g_nr5_uart1 = { .regs = &g_nr5_uart1_regs, .rx_buf = &g_nr5_uart1_rx_buf, @@ -172,7 +172,7 @@ void nr5_uart_init(int uart) //up_enable_irq(dev->regs->rx_irq); // Set the baud rate - + if (up_getimpid() == cmpval) { *dev->regs->pBaud = 0x0d; @@ -200,7 +200,7 @@ uint8_t nr5_uart_get_rx() rxdata = pBuf->buffer[pBuf->tail++]; if (pBuf->tail == pBuf->size) - pBuf->tail = 0; + pBuf->tail = 0; } up_enableints(); return rxdata; diff --git a/arch/risc-v/src/nr5m100/nr5_vectors.S b/arch/risc-v/src/nr5m100/nr5_vectors.S index ea239d91ce7..32ce4f0b747 100644 --- a/arch/risc-v/src/nr5m100/nr5_vectors.S +++ b/arch/risc-v/src/nr5m100/nr5_vectors.S @@ -46,7 +46,7 @@ ************************************************************************************/ __reset_vec: - csrw NR5_EPIC_PRIMASK, 7 + csrw NR5_EPIC_PRIMASK, 7 j __start /************************************************************************************ diff --git a/arch/risc-v/src/rv32im/Toolchain.defs b/arch/risc-v/src/rv32im/Toolchain.defs index a89cf6cb266..3229dd2be58 100644 --- a/arch/risc-v/src/rv32im/Toolchain.defs +++ b/arch/risc-v/src/rv32im/Toolchain.defs @@ -3,7 +3,7 @@ # # Copyright (C) 2012-2013, 2015 Gregory Nutt. All rights reserved. # Author: Gregory Nutt -# +# # modified for RISC-V: # # Copyright (C) 2016 Ken Pettit. All rights reserved. @@ -89,9 +89,9 @@ ifeq ($(CONFIG_RISCV_TOOLCHAIN),GNU_RVGW) WINTOOL = y endif ifeq ($(CONFIG_RV32IM_HW_MULDIV),y) - ARCHCPUFLAGS = -march=RV32IMXcustom -m32 + ARCHCPUFLAGS = -march=RV32IMXcustom -m32 else - ARCHCPUFLAGS = -march=RV32IXcustom -m32 + ARCHCPUFLAGS = -march=RV32IXcustom -m32 endif endif diff --git a/arch/risc-v/src/rv32im/up_dumpstate.c b/arch/risc-v/src/rv32im/up_dumpstate.c index 97f74c64110..6a27ef29150 100644 --- a/arch/risc-v/src/rv32im/up_dumpstate.c +++ b/arch/risc-v/src/rv32im/up_dumpstate.c @@ -124,7 +124,7 @@ static inline void up_registerdump(void) g_current_regs[REG_S11]); #ifdef RISCV_SAVE_GP _alert("GP:%08x SP:%08x FP:%08x TP:%08x RA:%08x\n", - g_current_regs[REG_GP], g_current_regs[REG_SP], g_current_regs[REG_FP], + g_current_regs[REG_GP], g_current_regs[REG_SP], g_current_regs[REG_FP], g_current_regs[REG_TP], g_current_regs[REG_RA]); #else _alert("SP:%08x FP:%08x TP:%08x RA:%08x\n", diff --git a/arch/risc-v/src/rv32im/up_initialstate.c b/arch/risc-v/src/rv32im/up_initialstate.c index 492f9f10860..74b5a00bc9f 100644 --- a/arch/risc-v/src/rv32im/up_initialstate.c +++ b/arch/risc-v/src/rv32im/up_initialstate.c @@ -119,7 +119,7 @@ void up_initial_state(struct tcb_s *tcb) # warning "Missing logic" #endif - /* Set the initial value of the interrupt context register. + /* Set the initial value of the interrupt context register. * * Since various RISC-V platforms use different interrupt * methodologies, the value of the interrupt context is diff --git a/arch/sim/Kconfig b/arch/sim/Kconfig index 5bf46951542..df46ddab302 100644 --- a/arch/sim/Kconfig +++ b/arch/sim/Kconfig @@ -119,7 +119,7 @@ config SIM_NET_HOST_ROUTE ---help--- Add a host route for the simulation that points to the created tap device. The simulation will not be able to access the public network unless iptables is - configured to masquerade for it. See configs/sim/NETWORK-LINUX.txt for more + configured to masquerade for it. See configs/sim/NETWORK-LINUX.txt for more information. config SIM_NET_BRIDGE diff --git a/arch/sim/src/up_oneshot.c b/arch/sim/src/up_oneshot.c index 7481e40017b..e41f10fa89a 100644 --- a/arch/sim/src/up_oneshot.c +++ b/arch/sim/src/up_oneshot.c @@ -213,7 +213,7 @@ static int sim_start(FAR struct oneshot_lowerhalf_s *lower, nsec = (int64_t)ts->tv_sec * NSEC_PER_SEC + (int64_t)ts->tv_nsec; ticks = (systime_t)((nsec + NSEC_PER_TICK - 1) / NSEC_PER_TICK); - + /* Save the callback information and start the timer */ priv->callback = callback; diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index 948f0edd533..e073ff6aca6 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -51,7 +51,7 @@ config XTENSA_CP_LAZY processor was never used, and (2) tasks must explicitly enable and disable co-processors. - An alternative, "lazy" co-processor state restore is enabled with + An alternative, "lazy" co-processor state restore is enabled with this option. That logic works like as follows: a. CPENABLE is set to zero on each context switch, disabling all co- diff --git a/arch/xtensa/include/xtensa/core.h b/arch/xtensa/include/xtensa/core.h index b138aa558a4..f254fd36373 100644 --- a/arch/xtensa/include/xtensa/core.h +++ b/arch/xtensa/include/xtensa/core.h @@ -485,7 +485,7 @@ #define XCHAL_HAVE_OLD_EXC_ARCH XCHAL_HAVE_XEA1 /* (DEPRECATED) 1 if * old exception - * architecture (XEA1), + * architecture (XEA1), * 0 otherwise (eg. * XEA2) */ #define XCHAL_HAVE_EXCM XCHAL_HAVE_XEA2 /* (DEPRECATED) 1 if @@ -876,7 +876,7 @@ # define XCHAL_KSEG_CACHED_PADDR 0x00000000 /* phys.addr of * kseg_cached */ # define XCHAL_KSEG_CACHED_SIZE 0x08000000 /* size in bytes of - * kseg_cached (assumed + * kseg_cached (assumed * power of 2!!!) */ # define XCHAL_KSEG_BYPASS_VADDR 0xD8000000 /* virt.addr of kernel * RAM bypass @@ -885,7 +885,7 @@ # define XCHAL_KSEG_BYPASS_PADDR 0x00000000 /* phys.addr of * kseg_bypass */ # define XCHAL_KSEG_BYPASS_SIZE 0x08000000 /* size in bytes of - * kseg_bypass (assumed + * kseg_bypass (assumed * power of 2!!!) */ # define XCHAL_KIO_CACHED_VADDR 0xE0000000 /* virt.addr of kernel * I/O cached static @@ -956,7 +956,7 @@ .endif .endm -/* Align portion of save area and bring ptr in range if necessary. Used by +/* Align portion of save area and bring ptr in range if necessary. Used by * save area load/store sequences. Not usually invoked directly. Allows * combining multiple (sub-)sequences arbitrarily. ptr pointer to save * area (may be off, see .Lxchal_pofs_) minofs,maxofs range of offset from diff --git a/arch/xtensa/include/xtensa/xtensa_coproc.h b/arch/xtensa/include/xtensa/xtensa_coproc.h index 26829a7a3a4..0eb24a3d13b 100644 --- a/arch/xtensa/include/xtensa/xtensa_coproc.h +++ b/arch/xtensa/include/xtensa/xtensa_coproc.h @@ -74,7 +74,7 @@ * This restriction is introduced to reduce the overhead of saving and * restoring co-processor state (which can be quite large) and in particular * remove that overhead from interrupt handlers. - * + * * The co-processor state save area may be in any convenient per-thread * location such as in the thread control block or above the thread stack * area. It need not be in the interrupt stack frame since interrupts don't diff --git a/arch/xtensa/src/esp32/esp32_gpio.c b/arch/xtensa/src/esp32/esp32_gpio.c index 892b87d51c5..b351765126a 100644 --- a/arch/xtensa/src/esp32/esp32_gpio.c +++ b/arch/xtensa/src/esp32/esp32_gpio.c @@ -287,7 +287,7 @@ void esp32_gpiowrite(int pin, bool value) bool esp32_gpioread(int pin) { uint32_t regval; - + DEBUGASSERT(pin >=0 && pin <= ESP32_NIRQ_GPIO); if (pin < 32) diff --git a/arch/xtensa/src/esp32/rom/esp32_gpio.h b/arch/xtensa/src/esp32/rom/esp32_gpio.h index 00680ff995c..c29d21ee462 100644 --- a/arch/xtensa/src/esp32/rom/esp32_gpio.h +++ b/arch/xtensa/src/esp32/rom/esp32_gpio.h @@ -329,7 +329,7 @@ void gpio_matrix_out(uint32_t gpio, uint32_t signal_idx, bool out_inv, bool oen_inv); /**************************************************************************** - * Name: + * Name: * * Description: * Select pad as a gpio function from IOMUX.