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arch/: Remove dangling space at the end of lines.

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This commit is contained in:
Gregory Nutt
2017-06-28 13:16:48 -06:00
parent 56e8f480f5
commit 1c5ec07414
99 changed files with 299 additions and 299 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/include/stm32l4/chip.h
+1 -1
View File
@@ -55,7 +55,7 @@
* - L486 has AES
* - L496, L4A6 has 320 Kib SRAM, 2xCAN and CameraIF. Most (all?) of these have I2C4.
* - L4A6 has AES and HASH
*
*
* ----------- ---------------- ----- ------ ------ ---- ---- -----
* PART PACKAGE GPIOs LCD Tamper FSMC CapS AdcCh
* ----------- ---------------- ----- ------ ------ ---- ---- -----
arch/arm/src/armv7-a/gtm.h
+1 -1
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@@ -112,7 +112,7 @@ extern "C"
#endif
/****************************************************************************
* Name:
* Name:
*
* Description:
*
arch/arm/src/armv7-m/arch_clean_dcache.c
+1 -1
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@@ -119,7 +119,7 @@ void arch_clean_dcache(uintptr_t start, uintptr_t end)
int32_t tmpways = ways;
/* Isolate the cache line associated with this address. For example
* if the cache line size is 32 bytes and the cache size is 16KB, then
* if the cache line size is 32 bytes and the cache size is 16KB, then
*
* sshift = 5 : Offset to the beginning of the set field
* smask = 0x007f : Mask of the set field
arch/arm/src/armv7-m/arch_flush_dcache.c
+1 -1
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@@ -119,7 +119,7 @@ void arch_flush_dcache(uintptr_t start, uintptr_t end)
int32_t tmpways = ways;
/* Isolate the cache line associated with this address. For example
* if the cache line size is 32 bytes and the cache size is 16KB, then
* if the cache line size is 32 bytes and the cache size is 16KB, then
*
* sshift = 5 : Offset to the beginning of the set field
* smask = 0x007f : Mask of the set field
arch/arm/src/armv7-m/arch_invalidate_dcache.c
+1 -1
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@@ -120,7 +120,7 @@ void arch_invalidate_dcache(uintptr_t start, uintptr_t end)
int32_t tmpways = ways;
/* Isolate the cache line associated with this address. For example
* if the cache line size is 32 bytes and the cache size is 16KB, then
* if the cache line size is 32 bytes and the cache size is 16KB, then
*
* sshift = 5 : Offset to the beginning of the set field
* smask = 0x007f : Mask of the set field
arch/arm/src/armv7-m/dwt.h
+1 -1
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@@ -26,7 +26,7 @@
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*
* Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
* Author: Pierre-noel Bouteville <pnb990@gmail.com>
*
arch/arm/src/armv7-m/iar/up_fullcontextrestore.S
+2 -2
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@@ -78,7 +78,7 @@
************************************************************************************/
THUMB
up_fullcontextrestore:
/* Perform the System call with R0=1 and R1=regs */
@@ -90,5 +90,5 @@ up_fullcontextrestore:
/* This call should not return */
bx lr /* Unnecessary ... will not return */
END
arch/arm/src/armv7-m/up_itm.c
+3 -3
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@@ -111,7 +111,7 @@ uint32_t itm_sendchar(uint32_t ch)
/****************************************************************************
* Name: itm_receivechar
*
*
* Description:
*
* Input Parameters:
@@ -122,7 +122,7 @@ uint32_t itm_sendchar(uint32_t ch)
*
****************************************************************************/
int32_t itm_receivechar(void)
int32_t itm_receivechar(void)
{
int32_t ch = -1; /* Assume no character available */
@@ -150,7 +150,7 @@ int32_t itm_receivechar(void)
*
****************************************************************************/
int32_t itm_checkchar (void)
int32_t itm_checkchar (void)
{
return (g_itm_rxbuffer != ITM_RXBUFFER_EMPTY);
}
arch/arm/src/common/up_createstack.c
+1 -1
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@@ -223,7 +223,7 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype)
top_of_stack = (uint32_t)tcb->stack_alloc_ptr + stack_size - 4;
/* The ARM stack must be aligned to 8-byte alignment for EABI.
* If necessary top_of_stack must be rounded down to the next
* If necessary top_of_stack must be rounded down to the next
* boundary
*/
arch/arm/src/common/up_usestack.c
+1 -1
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@@ -133,7 +133,7 @@ int up_use_stack(struct tcb_s *tcb, void *stack, size_t stack_size)
top_of_stack = (uint32_t)tcb->stack_alloc_ptr + stack_size - 4;
/* The ARM stack must be aligned to 8-byte alignment for EABI.
* If necessary top_of_stack must be rounded down to the next
* If necessary top_of_stack must be rounded down to the next
* boundary
*/
arch/arm/src/efm32/Make.defs
+1 -1
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@@ -98,7 +98,7 @@ CHIP_CSRCS = efm32_start.c efm32_clockconfig.c efm32_irq.c efm32_timerisr.c
CHIP_CSRCS += efm32_gpio.c efm32_lowputc.c efm32_timer.c efm32_i2c.c
ifeq ($(CONFIG_EFM32_FLASHPROG),y)
CHIP_CSRCS += efm32_flash.c
CHIP_CSRCS += efm32_flash.c
endif
ifeq ($(CONFIG_EFM32_BITBAND),y)
arch/arm/src/efm32/chip/efm32_calibrate.h
+1 -1
View File
@@ -88,6 +88,6 @@ struct efm32_calibrate_s
{
const uint32_t address; /* Address of calibration register */
const uint32_t value; /* Default value for calibration register */
};
};
#endif /* __ARCH_ARM_SRC_EFM32_CHIP_EFM32_CALIBRATE_H */
arch/arm/src/efm32/chip/efm32_devinfo.h
+25 -25
View File
@@ -79,16 +79,16 @@
/* MSC Register Offsets ********************************************************************************************************/
#define EFM32_DEVINFO_CAL_OFFSET 0x0000
#define EFM32_DEVINFO_ADC0CALn_OFFSET(n) (0x0004+(n)*4)
#define EFM32_DEVINFO_DAC0CALn_OFFSET(n) (0x0018+(n)*4)
#define EFM32_DEVINFO_AUXHFRCOCALn_OFFSET(n) (0x0024+(n)*4)
#define EFM32_DEVINFO_HFRCOCALn_OFFSET(n) (0x002c+(n)*4)
#define EFM32_DEVINFO_MEMINFO_PAGE_SIZE_OFFSET 0x0034
#define EFM32_DEVINFO_UNIQUEL_OFFSET 0x0040
#define EFM32_DEVINFO_UNIQUEH_OFFSET 0x0044
#define EFM32_DEVINFO_MEMINFO_SIZE_OFFSET 0x0048
#define EFM32_DEVINFO_PART_OFFSET 0x004c
#define EFM32_DEVINFO_CAL_OFFSET 0x0000
#define EFM32_DEVINFO_ADC0CALn_OFFSET(n) (0x0004+(n)*4)
#define EFM32_DEVINFO_DAC0CALn_OFFSET(n) (0x0018+(n)*4)
#define EFM32_DEVINFO_AUXHFRCOCALn_OFFSET(n) (0x0024+(n)*4)
#define EFM32_DEVINFO_HFRCOCALn_OFFSET(n) (0x002c+(n)*4)
#define EFM32_DEVINFO_MEMINFO_PAGE_SIZE_OFFSET 0x0034
#define EFM32_DEVINFO_UNIQUEL_OFFSET 0x0040
#define EFM32_DEVINFO_UNIQUEH_OFFSET 0x0044
#define EFM32_DEVINFO_MEMINFO_SIZE_OFFSET 0x0048
#define EFM32_DEVINFO_PART_OFFSET 0x004c
/* MSC Register Addresses ******************************************************************************************************/
@@ -121,7 +121,7 @@
#define _DEVINFO_CAL_CRC_SHIFT 0 /* Integrity CRC checksum shift */
#define _DEVINFO_CAL_TEMP_MASK 0x00FF0000UL /* Calibration temperature, DegC, mask */
#define _DEVINFO_CAL_TEMP_SHIFT 16 /* Calibration temperature shift */
#define _DEVINFO_ADC0CAL0_1V25_GAIN_MASK 0x00007F00UL /* Gain for 1V25 reference, mask */
#define _DEVINFO_ADC0CAL0_1V25_GAIN_SHIFT 8 /* Gain for 1V25 reference, shift */
#define _DEVINFO_ADC0CAL0_1V25_OFFSET_MASK 0x0000007FUL /* Offset for 1V25 reference, mask */
@@ -130,7 +130,7 @@
#define _DEVINFO_ADC0CAL0_2V5_GAIN_SHIFT 24 /* Gain for 2V5 reference, shift */
#define _DEVINFO_ADC0CAL0_2V5_OFFSET_MASK 0x007F0000UL /* Offset for 2V5 reference, mask */
#define _DEVINFO_ADC0CAL0_2V5_OFFSET_SHIFT 16 /* Offset for 2V5 reference, shift */
#define _DEVINFO_ADC0CAL1_VDD_GAIN_MASK 0x00007F00UL /* Gain for VDD reference, mask */
#define _DEVINFO_ADC0CAL1_VDD_GAIN_SHIFT 8 /* Gain for VDD reference, shift */
#define _DEVINFO_ADC0CAL1_VDD_OFFSET_MASK 0x0000007FUL /* Offset for VDD reference, mask */
@@ -139,33 +139,33 @@
#define _DEVINFO_ADC0CAL1_5VDIFF_GAIN_SHIFT 24 /* Gain for 5VDIFF reference, mask */
#define _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_MASK 0x007F0000UL /* Offset for 5VDIFF reference, mask */
#define _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_SHIFT 16 /* Offset for 5VDIFF reference, shift */
#define _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_MASK 0x0000007FUL /* Offset for 2XVDDVSS reference, mask */
#define _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_SHIFT 0 /* Offset for 2XVDDVSS reference, shift */
#define _DEVINFO_ADC0CAL2_TEMP1V25_MASK 0xFFF00000UL /* Temperature reading at 1V25 reference, mask */
#define _DEVINFO_ADC0CAL2_TEMP1V25_SHIFT 20 /* Temperature reading at 1V25 reference, DegC */
#define _DEVINFO_DAC0CAL0_1V25_GAIN_MASK 0x007F0000UL /* Gain for 1V25 reference, mask */
#define _DEVINFO_DAC0CAL0_1V25_GAIN_SHIFT 16 /* Gain for 1V25 reference, shift */
#define _DEVINFO_DAC0CAL0_1V25_CH1_OFFSET_MASK 0x00003F00UL /* Channel 1 offset for 1V25 reference, mask */
#define _DEVINFO_DAC0CAL0_1V25_CH1_OFFSET_SHIFT 8 /* Channel 1 offset for 1V25 reference, shift */
#define _DEVINFO_DAC0CAL0_1V25_CH0_OFFSET_MASK 0x0000003FUL /* Channel 0 offset for 1V25 reference, mask */
#define _DEVINFO_DAC0CAL0_1V25_CH0_OFFSET_SHIFT 0 /* Channel 0 offset for 1V25 reference, shift */
#define _DEVINFO_DAC0CAL1_2V5_GAIN_MASK 0x007F0000UL /* Gain for 2V5 reference, mask */
#define _DEVINFO_DAC0CAL1_2V5_GAIN_SHIFT 16 /* Gain for 2V5 reference, shift */
#define _DEVINFO_DAC0CAL1_2V5_CH1_OFFSET_MASK 0x00003F00UL /* Channel 1 offset for 2V5 reference, mask */
#define _DEVINFO_DAC0CAL1_2V5_CH1_OFFSET_SHIFT 8 /* Channel 1 offset for 2V5 reference, shift */
#define _DEVINFO_DAC0CAL1_2V5_CH0_OFFSET_MASK 0x0000003FUL /* Channel 0 offset for 2V5 reference, mask */
#define _DEVINFO_DAC0CAL1_2V5_CH0_OFFSET_SHIFT 0 /* Channel 0 offset for 2V5 reference, shift */
#define _DEVINFO_DAC0CAL2_VDD_GAIN_MASK 0x007F0000UL /* Gain for VDD reference, mask */
#define _DEVINFO_DAC0CAL2_VDD_GAIN_SHIFT 16 /* Gain for VDD reference, shift */
#define _DEVINFO_DAC0CAL2_VDD_CH1_OFFSET_MASK 0x00003F00UL /* Channel 1 offset for VDD reference, mask */
#define _DEVINFO_DAC0CAL2_VDD_CH1_OFFSET_SHIFT 8 /* Channel 1 offset for VDD reference, shift */
#define _DEVINFO_DAC0CAL2_VDD_CH0_OFFSET_MASK 0x0000003FUL /* Channel 0 offset for VDD reference, mask */
#define _DEVINFO_DAC0CAL2_VDD_CH0_OFFSET_SHIFT 0 /* Channel 0 offset for VDD reference, shift*/
#define _DEVINFO_AUXHFRCOCAL0_BAND1_MASK 0x000000FFUL /* 1MHz tuning value for AUXHFRCO, mask */
#define _DEVINFO_AUXHFRCOCAL0_BAND1_SHIFT 0 /* 1MHz tuning value for AUXHFRCO, shift */
#define _DEVINFO_AUXHFRCOCAL0_BAND7_MASK 0x0000FF00UL /* 7MHz tuning value for AUXHFRCO, mask */
@@ -174,12 +174,12 @@
#define _DEVINFO_AUXHFRCOCAL0_BAND11_SHIFT 16 /* 11MHz tuning value for AUXHFRCO, shift */
#define _DEVINFO_AUXHFRCOCAL0_BAND14_MASK 0xFF000000UL /* 14MHz tuning value for AUXHFRCO, mask */
#define _DEVINFO_AUXHFRCOCAL0_BAND14_SHIFT 24 /* 14MHz tuning value for AUXHFRCO, shift */
#define _DEVINFO_AUXHFRCOCAL1_BAND21_MASK 0x000000FFUL /* 21MHz tuning value for AUXHFRCO, mask */
#define _DEVINFO_AUXHFRCOCAL1_BAND21_SHIFT 0 /* 21MHz tuning value for AUXHFRCO, shift */
#define _DEVINFO_AUXHFRCOCAL1_BAND28_MASK 0x0000FF00UL /* 28MHz tuning value for AUXHFRCO, shift */
#define _DEVINFO_AUXHFRCOCAL1_BAND28_SHIFT 8 /* 28MHz tuning value for AUXHFRCO, mask */
#define _DEVINFO_HFRCOCAL0_BAND1_MASK 0x000000FFUL /* 1MHz tuning value for HFRCO, mask */
#define _DEVINFO_HFRCOCAL0_BAND1_SHIFT 0 /* 1MHz tuning value for HFRCO, shift */
#define _DEVINFO_HFRCOCAL0_BAND7_MASK 0x0000FF00UL /* 7MHz tuning value for HFRCO, mask */
@@ -188,26 +188,26 @@
#define _DEVINFO_HFRCOCAL0_BAND11_SHIFT 16 /* 11MHz tuning value for HFRCO, shift */
#define _DEVINFO_HFRCOCAL0_BAND14_MASK 0xFF000000UL /* 14MHz tuning value for HFRCO, mask */
#define _DEVINFO_HFRCOCAL0_BAND14_SHIFT 24 /* 14MHz tuning value for HFRCO, shift */
#define _DEVINFO_HFRCOCAL1_BAND21_MASK 0x000000FFUL /* 21MHz tuning value for HFRCO, mask */
#define _DEVINFO_HFRCOCAL1_BAND21_SHIFT 0 /* 21MHz tuning value for HFRCO, shift */
#define _DEVINFO_HFRCOCAL1_BAND28_MASK 0x0000FF00UL /* 28MHz tuning value for HFRCO, shift */
#define _DEVINFO_HFRCOCAL1_BAND28_SHIFT 8 /* 28MHz tuning value for HFRCO, mask */
#define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK 0xFF000000UL /* Flash page size (refer to ref.man for encoding) mask */
#define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_SHIFT 24 /* Flash page size shift */
#define _DEVINFO_UNIQUEL_MASK 0xFFFFFFFFUL /* Lower part of 64-bit device unique number */
#define _DEVINFO_UNIQUEL_SHIFT 0 /* Unique Low 32-bit shift */
#define _DEVINFO_UNIQUEH_MASK 0xFFFFFFFFUL /* High part of 64-bit device unique number */
#define _DEVINFO_UNIQUEH_SHIFT 0 /* Unique High 32-bit shift */
#define _DEVINFO_MEMINFO_SIZE_SRAM_MASK 0xFFFF0000UL /* Flash size in kilobytes */
#define _DEVINFO_MEMINFO_SIZE_SRAM_SHIFT 16 /* Bit position for flash size */
#define _DEVINFO_MEMINFO_SIZE_FLASH_MASK 0x0000FFFFUL /* SRAM size in kilobytes */
#define _DEVINFO_MEMINFO_SIZE_FLASH_SHIFT 0 /* Bit position for SRAM size */
#define _DEVINFO_PART_PROD_REV_MASK 0xFF000000UL /* Production revision */
#define _DEVINFO_PART_PROD_REV_SHIFT 24 /* Bit position for production revision */
#define _DEVINFO_PART_DEVICE_FAMILY_MASK 0x00FF0000UL /* Device Family, 0x47 for Gecko */
arch/arm/src/efm32/chip/efm32_flash.h
+1 -1
View File
@@ -52,6 +52,6 @@
# define EFM32_FLASH_PAGESIZE 512
#elif defined(CONFIG_EFM32_EFM32TG)
# define EFM32_FLASH_PAGESIZE 512
#endif
#endif
#endif /* __ARCH_ARM_SRC_EFM32_CHIP_EFM32_FLASH_H */
arch/arm/src/efm32/chip/efm32_gpio.h
+1 -1
View File
@@ -284,7 +284,7 @@
#endif
/* GPIO Register Bit Field Definitions *****************************************************************************************/
/* Bit fields for GPIO P_CTRL */
#define _GPIO_P_CTRL_RESETVALUE 0x00000000UL /* Default value for GPIO_P_CTRL */
arch/arm/src/efm32/chip/efm32_romtable.h
+1 -1
View File
@@ -109,6 +109,6 @@ struct efm32_romtable_s
const uint32_t pid2; /* Chip minor rev MSB, JEP_106_PRESENT, JEP_106_NO */
const uint32_t pid3; /* Chip minor rev LSB */
const uint32_t cid0; /* Unused */
};
};
#endif /* __ARCH_ARM_SRC_EFM32_CHIP_EFM32_ROMTABLE_H */
arch/arm/src/efm32/efm32_leserial.c
+1 -1
View File
@@ -152,7 +152,7 @@ struct efm32_leuart_s
****************************************************************************/
static inline uint32_t efm32_serialin(struct efm32_leuart_s *priv, int offset);
static inline void efm32_serialout(struct efm32_leuart_s *priv, int offset,
static inline void efm32_serialout(struct efm32_leuart_s *priv, int offset,
uint32_t value);
static inline void efm32_setuartint(struct efm32_leuart_s *priv);
arch/arm/src/efm32/efm32_pwm.c
+1 -1
View File
@@ -66,7 +66,7 @@
#if defined(CONFIG_EFM32_TIMER0_PWM) || \
defined(CONFIG_EFM32_TIMER1_PWM) || \
defined(CONFIG_EFM32_TIMER2_PWM) || \
defined(CONFIG_EFM32_TIMER3_PWM)
defined(CONFIG_EFM32_TIMER3_PWM)
/****************************************************************************
* Pre-processor Definitions
arch/arm/src/efm32/efm32_pwm.h
+6 -6
View File
@@ -36,9 +36,9 @@
#ifndef __ARCH_ARM_SRC_EFM32_EFM32_PWM_H
#define __ARCH_ARM_SRC_EFM32_EFM32_PWM_H
/* The EFM32 does not have dedicated PWM hardware. Rather, pulsed output
* control is a capability of the EFM32 timers. The logic in this file
* implements the lower half of the standard, NuttX PWM interface using the
/* The EFM32 does not have dedicated PWM hardware. Rather, pulsed output
* control is a capability of the EFM32 timers. The logic in this file
* implements the lower half of the standard, NuttX PWM interface using the
* EFM32 timers. That interface is described in include/nuttx/drivers/pwm.h.
*/
@@ -55,9 +55,9 @@
****************************************************************************/
/* Configuration **************************************************************/
/* Timer devices may be used for different purposes. One special purpose is
* to generate modulated outputs for such things as motor control.
* If CONFIG_EFM32_TIMERn is defined then the CONFIG_EFM32_TIMERn_PWM must also
* be defined to indicate that timer "n" is intended to be used for pulsed
* to generate modulated outputs for such things as motor control.
* If CONFIG_EFM32_TIMERn is defined then the CONFIG_EFM32_TIMERn_PWM must also
* be defined to indicate that timer "n" is intended to be used for pulsed
* output signal generation.
*/
arch/arm/src/efm32/efm32_serial.c
+2 -2
View File
@@ -243,7 +243,7 @@ struct efm32_usart_s
****************************************************************************/
static inline uint32_t efm32_serialin(struct efm32_usart_s *priv, int offset);
static inline void efm32_serialout(struct efm32_usart_s *priv, int offset,
static inline void efm32_serialout(struct efm32_usart_s *priv, int offset,
uint32_t value);
static inline void efm32_setuartint(struct efm32_usart_s *priv);
@@ -897,7 +897,7 @@ static int efm32_ioctl(struct file *filep, int cmd, unsigned long arg)
#ifdef CONFIG_SERIAL_IFLOWCONTROL
priv->iflow = (termiosp->c_cflag & CRTS_IFLOW) != 0;
#endif
#endif
#endif
/* Note that only cfgetispeed is used because we have knowledge
* that only one speed is supported.
arch/arm/src/imx6/imx_ecspi.c
+1 -1
View File
@@ -136,7 +136,7 @@
****************************************************************************/
/* Per SPI callouts to board-specific logic */
typedef CODE void (*imx_select_t)(FAR struct spi_dev_s *dev,
uint32_t devid, bool selected);
typedef CODE uint8_t (*imx_status_t)(FAR struct spi_dev_s *dev,
arch/arm/src/imx6/imx_iomuxc.h
+1 -1
View File
@@ -143,7 +143,7 @@ typedef uint16_t iomux_pinset_t;
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: imx_padmux_map
*
arch/arm/src/imx6/imx_timerisr.c
+1 -1
View File
@@ -230,7 +230,7 @@ void arm_timer_initialize(void)
putreg32(GPT_OCR3_VALUE, IMX_GPT_OCR3);
putreg32(GPT_PR_VALUE - 1, IMX_GPT_PR);
/* Configure restart mode. Interrupts will be received on OC3, then OC2,
* then OC1 when the counter will be reset to zero and the whole sequence
* starts again.
arch/arm/src/kinetis/chip/kinetis_usbotg.h
+3 -3
View File
@@ -153,11 +153,11 @@
#ifdef KINETIS_K64
# define KINETIS_USB_USBFRMADJUST \
(KINETIS_USB0_BASE+KINETIS_USB_USBFRMADJUST_OFFSET)
(KINETIS_USB0_BASE+KINETIS_USB_USBFRMADJUST_OFFSET)
# define KINETIS_USB_USB0_CLK_RECOVER_CTRL \
(KINETIS_USB0_BASE+KINETIS_USB_USB0_CLK_RECOVER_CTRL_OFFSET)
(KINETIS_USB0_BASE+KINETIS_USB_USB0_CLK_RECOVER_CTRL_OFFSET)
# define KINETIS_USB_USB0_CLK_RECOVER_IRC_EN \
(KINETIS_USB0_BASE+KINETIS_USB_USB0_CLK_RECOVER_IRC_EN_OFFSET)
(KINETIS_USB0_BASE+KINETIS_USB_USB0_CLK_RECOVER_IRC_EN_OFFSET)
# define KINETIS_USB_USB0_CLK_RECOVER_INT_STATUS \
(KINETIS_USB0_BASE+KINETIS_USB_USB0_CLK_RECOVER_INT_STATUS_OFFSET)
#endif
arch/arm/src/kinetis/kinetis_enet.c
+4 -4
View File
@@ -170,7 +170,7 @@
#define BOARD_PHY_100BASET(s) (((s) & (2 << MII_PHYCTRL2_MODE_SHIFT)) != 0)
#define BOARD_PHY_ISDUPLEX(s) (((s) & (4 << MII_PHYCTRL2_MODE_SHIFT)) != 0)
/* Estimate the MII_SPEED in order to get an MDC close to 2.5MHz,
/* Estimate the MII_SPEED in order to get an MDC close to 2.5MHz,
based on the internal module (ENET) clock:
*
* MII_SPEED = ENET_FREQ/5000000 -1
@@ -1761,7 +1761,7 @@ static inline int kinetis_initphy(struct kinetis_driver_s *priv)
usleep(LINK_WAITUS);
}
if (phydata & MII_MSR_ANEGCOMPLETE)
if (phydata & MII_MSR_ANEGCOMPLETE)
{
ninfo("%s: Autonegotiation complete\n", BOARD_PHY_NAME);
ninfo("%s: MII_MSR: %04x\n", BOARD_PHY_NAME, phydata);
@@ -1769,14 +1769,14 @@ static inline int kinetis_initphy(struct kinetis_driver_s *priv)
else
{
/* TODO: Autonegotitation has right now failed. Maybe the Eth cable is not connected.
PHY chip have mechanisms to configure link OK. We should leave autconf on,
PHY chip have mechanisms to configure link OK. We should leave autconf on,
and find a way to re-configure MCU whenever the link is ready. */
ninfo("%s: Autonegotiation failed [%d] (is cable plugged-in ?), default to 10Mbs mode\n", \
BOARD_PHY_NAME, retries);
/* Stop auto negotiation */
kinetis_writemii(priv, phyaddr, MII_MCR, 0);
}
arch/arm/src/kinetis/kinetis_usbdev.c
+1 -1
View File
@@ -1651,7 +1651,7 @@ static int khci_rdsetup(struct khci_ep_s *privep, uint8_t *dest, int readlen)
/* Then give the BDT to the USB */
bdtinfo("EP%d BDT OUT [%p] {%08x, %08x}\n",
bdtinfo("EP%d BDT OUT [%p] {%08x, %08x}\n",
epno, bdtout, status, bdtout->addr);
bdtout->status = status;
arch/arm/src/lpc2378/chip.h
+3 -3
View File
@@ -101,7 +101,7 @@
#define LPC23XX_EMAC_BASE 0xFFE00000 /* Ethernet MAC base address */
#define LPC23XX_USB_BASE 0xFFE0C200 /* USB base address */
#define LPC23XX_SCB_BASE 0xE01FC000 /* System Control Block (SBC) base address */
#define LPC23XX_EXT_BASE 0xe01fc140 /* External Interrupt base address */
#define LPC23XX_EXT_BASE 0xe01fc140 /* External Interrupt base address */
/* AHB Register block base addresses */
@@ -367,7 +367,7 @@
#define CAN1RID_OFFSET 0x24
#define CAN1RDA_OFFSET 0x28
#define CAN1RDB_OFFSET 0x2C
#define CAN1TFI1_OFFSET 0x30
#define CAN1TID1_OFFSET 0x34
#define CAN1TDA1_OFFSET 0x38
@@ -394,7 +394,7 @@
#define CAN2RID_OFFSET 0x24
#define CAN2RDA_OFFSET 0x28
#define CAN2RDB_OFFSET 0x2C
#define CAN2TFI1_OFFSET 0x30
#define CAN2TID1_OFFSET 0x34
#define CAN2TDA1_OFFSET 0x38
arch/arm/src/lpc43xx/spifi/changelog.txt
+3 -3
View File
@@ -24,7 +24,7 @@ renamed from lib_llpcspifi_Mx.a to lib_lpcspifi_Mx.a]
LPCSpifilib version <1.01>
==========================
Release date <12/11/2014>
1. Changed reported device string on S25FL512S from "S25FL512S 256kSec" to "S25FL512S".
1. Changed reported device string on S25FL512S from "S25FL512S 256kSec" to "S25FL512S".
2. Changelog update: Added support for MX25L1635E, MX25L6435E, MX25L8035E, S25FL016K, S25FL064P, S25FL128S, S25FL256S,
S25FL512S, W25Q16DV, and W25Q64FV devices.
3. Changelog update: Changed maxRead to 16128 (was 32768).
@@ -66,9 +66,9 @@ Change Log:
2. Added support for Winbond W25Q80BV.
3. Added API's to return max speed for specific functions:
Read, QuadRead, Program, Quad Program.
4. Added prvGetStatus, prvSetStatus and prvSetQuadMode Functions to device definition structure.
4. Added prvGetStatus, prvSetStatus and prvSetQuadMode Functions to device definition structure.
5. Added spifiDevGetCount function.
6. Consolidated MX25L3235E and S25FL164K support into spifilib_fam_standard_cmd module
6. Consolidated MX25L3235E and S25FL164K support into spifilib_fam_standard_cmd module
(removed SPIFI_REG_FAMILY_xxx registration functions and replaced with
spifi_REG_FAMILY_StandardCommandSet function).
7. Fixed bug in spifiRegisterFamily where NULL was being returned instead of the
arch/arm/src/sam34/sam4cm_cpustart.c
+1 -1
View File
@@ -231,7 +231,7 @@ int up_cpu_start(int cpu)
putreg32(0x1, SAM_IPC0_IECR); /* enable : write-only */
irq_attach(SAM_IRQ_IPC0, arm_pause_handler, NULL);
up_enable_irq(SAM_IRQ_IPC0);
spin_lock(&g_cpu1_boot);
/* CPU1 boot done */
arch/arm/src/sama5/chip/sam_emaca.h
+1 -1
View File
@@ -1,6 +1,6 @@
/************************************************************************************
* arch/arm/src/sama5/chip/sam_emaca.h
* This is the form of the EMAC interface used the SAMA5D3
* This is the form of the EMAC interface used the SAMA5D3
*
* Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
arch/arm/src/sama5/chip/sam_flexcom.h
+1 -1
View File
@@ -123,5 +123,5 @@
/* Flexcom TWI Register Definitions *************************************************/
#include "chip/sam_flexcom_twi.h"
#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_FLEXCOM_H */
arch/arm/src/sama5/chip/sam_matrix.h
+1 -1
View File
@@ -814,7 +814,7 @@
#if defined(ATSAMA5D2) || defined(ATSAMA5D4)
/* Master Error Interrupt Enable Register, Master Error Interrupt Disable Register,
* Master Error Interrupt Mask Register, and Master Error Status Register
* Master Error Interrupt Mask Register, and Master Error Status Register
*/
# define MATRIX_MEINT_MERR(n) (1 << (n)) /* Master x Access Error, n=0..9 */
arch/arm/src/sama5/chip/sam_xdmac.h
+1 -1
View File
@@ -283,7 +283,7 @@
#define XDMAC_CHINT_DI (1 << 2) /* Bit 2: End of Disable Interrupt */
#define XDMAC_CHINT_FI (1 << 3) /* Bit 3: End of Flush Interrupt */
#define XDMAC_CHINT_RBI (1 << 4) /* Bit 4: Read Bus Error Interrupt */
#define XDMAC_CHINT_WBI (1 << 5) /* Bit 5: Write Bus Error Interrupt */
#define XDMAC_CHINT_WBI (1 << 5) /* Bit 5: Write Bus Error Interrupt */
#define XDMAC_CHINT_ROI (1 << 6) /* Bit 6: Request Overflow Error Interrupt Disable Bit */
#define XDMAC_CHINT_ERRORS (0x00000070)
arch/arm/src/sama5/sam_emacb.c
+1 -1
View File
@@ -3,7 +3,7 @@
* 10/100 Base-T Ethernet driver for the SAMA5D4.
*
* The SAMA5D3 and SAMA5D4 EMAC implementations differ in register naming
* and in register layout but are functionally equivalent. Here they are
* and in register layout but are functionally equivalent. Here they are
* distinguished as 'A' and 'B'. For now, the 'A' and 'B' drivers are kept
* separate (mostly because the 'B' driver needs to support two EMAC blocks.
* But the 'B' driver should replace the 'A' driver someday.
arch/arm/src/samdl/chip/saml_dmac.h
+2 -2
View File
@@ -173,9 +173,9 @@
# define DMAC_QOSCTRL_DQOS_LOW (1 << DMAC_QOSCTRL_DQOS_SHIFT) /* Sensitive bandwidth */
# define DMAC_QOSCTRL_DQOS_MEDIUM (2 << DMAC_QOSCTRL_DQOS_SHIFT) /* Sensitive latency */
# define DMAC_QOSCTRL_DQOS_HIGH (3 << DMAC_QOSCTRL_DQOS_SHIFT) /* Critical latency */
/* Common bit definitions for: Software Trigger Control Register, Interrupt Status Register,
* Busy Channels Register, and Pending Channels Register
* Busy Channels Register, and Pending Channels Register
*/
#define DMAC_CHAN(n) (1 << (n)) /* DMAC Channel n, n=0-15 */
arch/arm/src/samv7/chip/sam_usbhs.h
+3 -3
View File
@@ -335,7 +335,7 @@
* Device Endpoint Mask Register
* Device Endpoint Enable Register
*
* (1) Control, Bulk, Interrupt endpoints
* (1) Control, Bulk, Interrupt endpoints
* (2) Isochronous endpoints only
*/
@@ -464,7 +464,7 @@
* (1) Not clear or set registers
* (2) Not clear register
*/
#define USBHS_HSTINT_DCONNI (1 << 0) /* Bit 0: Device Connection Interrupt */
#define USBHS_HSTINT_DDISCI (1 << 1) /* Bit 1: Device Disconnection Interrupt */
#define USBHS_HSTINT_RSTI (1 << 2) /* Bit 2: USB Reset Sent Interrupt */
@@ -644,7 +644,7 @@
*/
/* All registers */
#define USBHS_HSTPIPINT_RXINI (1 << 0) /* Bit 0: Received IN Data Interrupt */
#define USBHS_HSTPIPINT_TXOUTI (1 << 1) /* Bit 1: Transmitted OUT Data Interrupt */
#define USBHS_HSTPIPINT_TXSTPI (1 << 2) /* Bit 2: Transmitted SETUP Interrupt (1) */
arch/arm/src/samv7/chip/sam_xdmac.h
+1 -1
View File
@@ -244,7 +244,7 @@
#define XDMAC_CHINT_DI (1 << 2) /* Bit 2: End of Disable Interrupt */
#define XDMAC_CHINT_FI (1 << 3) /* Bit 3: End of Flush Interrupt */
#define XDMAC_CHINT_RBI (1 << 4) /* Bit 4: Read Bus Error Interrupt */
#define XDMAC_CHINT_WBI (1 << 5) /* Bit 5: Write Bus Error Interrupt */
#define XDMAC_CHINT_WBI (1 << 5) /* Bit 5: Write Bus Error Interrupt */
#define XDMAC_CHINT_ROI (1 << 6) /* Bit 6: Request Overflow Error Interrupt Disable Bit */
#define XDMAC_CHINT_ERRORS (0x00000070)
arch/arm/src/samv7/sam_progmem.c
+1 -1
View File
@@ -709,7 +709,7 @@ ssize_t up_progmem_write(size_t address, const void *buffer, size_t buflen)
for (i = 0; i < (SAMV7_PAGE_SIZE / sizeof(uint32_t)); i++)
{
*dest++ = *src++;
*dest++ = *src++;
ARM_DMB();
}
arch/arm/src/samv7/sam_usbdevhs.c
+1 -1
View File
@@ -2545,7 +2545,7 @@ static void sam_dma_interrupt(struct sam_usbdev_s *priv, int epno)
if (byct > 0 || nbusybk > 0)
{
/* Not all of the data has been sent to the host. A NBUSYBKE
/* Not all of the data has been sent to the host. A NBUSYBKE
* interrupt will be generated later. It has already been enabled.
* Now wait for the transfer to complete.
*/
arch/arm/src/stm32/chip/stm32_otghs.h
+1 -1
View File
@@ -169,7 +169,7 @@
#define STM32_OTGHS_DVBUSPULSE_OFFSET 0x082c /* Device VBUS pulsing time register */
#define STM32_OTGHS_DIEPEMPMSK_OFFSET 0x0834 /* Device IN endpoint FIFO empty interrupt mask register */
#define STM32_OTGHS_DIEP_OFFSET(n) (0x0900 + ((n) << 5))
#define STM32_OTGHS_DIEP_OFFSET(n) (0x0900 + ((n) << 5))
#define STM32_OTGHS_DIEPCTL_EPOFFSET 0x0000 /* Device endpoint control register */
#define STM32_OTGHS_DIEPINT_EPOFFSET 0x0008 /* Device endpoint interrupt register */
#define STM32_OTGHS_DIEPTSIZ_EPOFFSET 0x0010 /* Device IN endpoint transfer size register */
arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h
+1 -1
View File
@@ -426,7 +426,7 @@
#define GPIO_I2C3_SDA_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTH|GPIO_PIN8)
#if defined(CONFIG_STM32_STM32F411)
# define GPIO_I2C3_SDA_3 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN4)
# define GPIO_I2C3_SDA_4 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN8)
# define GPIO_I2C3_SDA_4 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN8)
#endif
#define GPIO_I2C3_SMBA_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN9)
#define GPIO_I2C3_SMBA_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN9)
arch/arm/src/stm32/stm32_capture.h
+3 -3
View File
@@ -91,7 +91,7 @@ typedef enum
STM32_CAP_MAPPED_TI1 = (1<<GTIM_CCMR1_CC1S_SHIFT),
STM32_CAP_MAPPED_TI2 = (2<<GTIM_CCMR1_CC1S_SHIFT),
/*TODO STM32_CAP_MAPPED_TRC = (3<<GTIM_CCMR1_CC1S_SHIFT),*/
/* Event prescaler */
STM32_CAP_INPSC_MASK = (GTIM_CCMR1_IC1PSC_MASK),
@@ -144,7 +144,7 @@ typedef enum
STM32_CAP_CLK_EXT,
/* TODO: Add other clock */
} stm32_cap_clk_t;
/* Capture flags */
@@ -170,7 +170,7 @@ typedef enum
#define STM32_CAP_FLAG_IRQ_CH(ch) (GTIM_SR_CC1IF<<((ch)-1))
#define STM32_CAP_FLAG_OF_CH(ch) (GTIM_SR_CC1OF<<((ch)-1))
#define STM32_CAP_CHANNEL_COUNTER 0
/* Capture Operations */
struct stm32_cap_ops_s
arch/arm/src/stm32/stm32_rtcounter.c
+2 -2
View File
@@ -392,11 +392,11 @@ int up_rtc_initialize(void)
modifyreg32(STM32_RCC_BDCR, RCC_BDCR_BDRST, 0);
putreg16(RTC_MAGIC, RTC_MAGIC_REG);
}
/* Select the lower power external 32,768Hz (Low-Speed External, LSE) oscillator
* as RTC Clock Source and enable the Clock.
*/
modifyreg16(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSE);
/* Enable RTC and wait for RSF */
arch/arm/src/stm32/stm32_sdadc.c
+14 -14
View File
@@ -83,7 +83,7 @@
# error "This chip is not yet supported"
#endif
/* TODO: At the moment there is no implementation
/* TODO: At the moment there is no implementation
for timer and external triggers */
#if defined(SDADC_HAVE_TIMER)
@@ -641,7 +641,7 @@ static void sdadc_rccreset(FAR struct stm32_dev_s *priv, bool reset)
*
****************************************************************************/
#if 0
#if 0
static void sdadc_power_down_idle(FAR struct stm32_dev_s *priv, bool pdi_high)
{
uint32_t regval;
@@ -785,7 +785,7 @@ static int sdadc_bind(FAR struct adc_dev_s *dev,
* sdadc_register()
* Does mostly the SDAC register setting.
* Leave the device in power down mode.
* Note that SDACx clock is already enable (for all SDADC) by the
* Note that SDACx clock is already enable (for all SDADC) by the
* rcc_enableapb2()
*
* Input Parameters:
@@ -867,7 +867,7 @@ static void sdadc_reset(FAR struct adc_dev_s *dev)
/* TODO: JEXTEN / JEXTSEL */
/* Number of calibrations is for 3 configurations */
setbits |= (2 << SDADC_CR2_CALIBCNT_SHIFT);
/* Set CR2 configuration */
@@ -929,10 +929,10 @@ static void sdadc_reset(FAR struct adc_dev_s *dev)
*
* Description:
* Configure the ADC. This method is called the first time that the SDADC
* device is opened.
* device is opened.
* This is called by the upper half driver sdadc_open().
* This will occur when the port is first
* opened in the application code (/dev/sdadcN).
* opened in the application code (/dev/sdadcN).
* It would be called again after closing all references to this file and
* reopening it.
* This function wakes up the device and setup the DMA / IRQ
@@ -1008,7 +1008,7 @@ static int sdadc_setup(FAR struct adc_dev_s *dev)
* Name: sdadc_shutdown
*
* Description:
* Disable the ADC. This method is called when the last instance
* Disable the ADC. This method is called when the last instance
* of the SDADC device is closed by the user application.
* This method reverses the operation the setup method.
*
@@ -1085,12 +1085,12 @@ static void sdadc_rxint(FAR struct adc_dev_s *dev, bool enable)
}
else
{
/* Interrupt enable for injected channel group overrun
/* Interrupt enable for injected channel group overrun
and end of conversion */
setbits = SDADC_CR1_JOVRIE | SDADC_CR1_JEOCIE;
setbits = SDADC_CR1_JOVRIE | SDADC_CR1_JEOCIE;
}
#else
setbits = SDADC_CR1_JOVRIE | SDADC_CR1_JEOCIE;
setbits = SDADC_CR1_JOVRIE | SDADC_CR1_JEOCIE;
#endif
if (enable)
@@ -1273,7 +1273,7 @@ static int sdadc_interrupt(int irq, FAR void *context, FAR void *arg)
}
/* do no clear this interrupt (cleared by reading data) */
pending &= ~SDADC_ISR_JEOCF;
}
@@ -1300,14 +1300,14 @@ static int sdadc_interrupt(int irq, FAR void *context, FAR void *arg)
* The logic is, save and initialize the channel list in the private driver
* structure and return the corresponding adc device structure.
*
* Each SDADC will convert the channels indicated each
* Each SDADC will convert the channels indicated each
* time a conversion is triggered either by sofware, timer or external event.
* Channels are numbered from 0 - 8 and must be given in order (contrarily
* to what says ST RM0313 doc !!!).
*
* Input Parameters:
* intf - Could be {1,2,3} for SDADC1, SDADC2, or SDADC3
* chanlist - The list of channels eg. { 0, 3, 7, 8 }
* chanlist - The list of channels eg. { 0, 3, 7, 8 }
* cchannels - Number of channels
*
* Returned Value:
@@ -1350,7 +1350,7 @@ struct adc_dev_s *stm32_sdadcinitialize(int intf, FAR const uint8_t *chanlist,
}
/* Check channel list in order */
DEBUGASSERT((cchannels <= SDADC_MAX_SAMPLES) && (cchannels > 0));
for (i = 0; i < cchannels - 1; i ++)
{
arch/arm/src/stm32/stm32_sdadc.h
+2 -2
View File
@@ -114,8 +114,8 @@
/* SDADC Channels/DMA ******************************************************
* The maximum number of channels that can be sampled at each scan.
* If DMA support is not enabled, then only a single channel
* ought to be sampled.
* If DMA support is not enabled, then only a single channel
* ought to be sampled.
* Otherwise, unless sampling frequency is reduced,
* data overruns would occur.
*/
arch/arm/src/stm32/stm32_tickless.c
+2 -2
View File
@@ -248,7 +248,7 @@ static int stm32_tickless_setchannel(uint8_t channel)
*/
ccmr_val = (ATIM_CCMR_MODE_FRZN << ATIM_CCMR1_OC1M_SHIFT);
/* Set polarity */
ccer_val |= ATIM_CCER_CC1P << (channel << 2);
@@ -913,7 +913,7 @@ int up_timer_start(FAR const struct timespec *ts)
*/
g_tickless.period = (uint16_t)(period + count);
STM32_TIM_SETCOMPARE(g_tickless.tch, g_tickless.channel,
g_tickless.period);
arch/arm/src/stm32/stm32f37xxx_rcc.c
+1 -1
View File
@@ -598,7 +598,7 @@ static void stm32_stdclockconfig(void)
#endif
#if defined(CONFIG_RTC_LSECLOCK)
/* Low speed external clock source LSE
/* Low speed external clock source LSE
*
* TODO: There is another case where the LSE needs to
* be enabled: if the MCO pin selects LSE as source.
arch/arm/src/stm32f0/stm32f0_hsi48.c
+1 -1
View File
@@ -176,7 +176,7 @@ void stm32f0_disable_hsi48(void)
regval = getreg32(STM32F0_CRS_CFGR);
regval &= ~CRS_CFGR_SYNCSRC_MASK;
putreg32(regval, STM32F0_CRS_CFGR);
regval = getreg32(STM32F0_CRS_CR);
regval &= ~CRS_CR_AUTOTRIMEN;
putreg32(regval, STM32F0_CRS_CR);
arch/arm/src/stm32f0/stm32f0_hsi48.h
+1 -1
View File
@@ -53,7 +53,7 @@ enum syncsrc_e
{
SYNCSRC_GPIO = 0, /* GPIO selected as SYNC signal source */
SYNCSRC_LSE, /* LSE selected as SYNC signal source */
SYNCSRC_USB, /* USB SOF selected as SYNC signal source */
SYNCSRC_USB, /* USB SOF selected as SYNC signal source */
};
/************************************************************************************
arch/arm/src/stm32f7/chip/stm32f74xx75xx_memorymap.h
+1 -1
View File
@@ -210,6 +210,6 @@
*/
#define STM32_DEBUGMCU_BASE 0xe0042000
#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */
#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XXX75XXX_MEMORYMAP_H */

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