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SAM4E: Update SAM3/4 GPBR, HSMCI, PWM, RSTC, RTC, RTT, SMC, and WDT register definition header files
This commit is contained in:
Gregory Nutt
@@ -1,7 +1,7 @@
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/****************************************************************************************
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* arch/arm/src/sam34/chip/sam_gpbr.h
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*
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* Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
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* Copyright (C) 2009, 2013-2014 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@@ -61,6 +61,21 @@
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#define SAM_GPBR6_OFFSET 0x18
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#define SAM_GPBR7_OFFSET 0x1c
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#if defined(CONFIG_ARCH_CHIP_SAM4E)
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# define SAM_GPBR8_OFFSET 0x20
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# define SAM_GPBR9_OFFSET 0x24
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# define SAM_GPBR10_OFFSET 0x28
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# define SAM_GPBR11_OFFSET 0x2c
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# define SAM_GPBR12_OFFSET 0x30
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# define SAM_GPBR13_OFFSET 0x34
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# define SAM_GPBR14_OFFSET 0x38
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# define SAM_GPBR15_OFFSET 0x3c
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# define SAM_GPBR16_OFFSET 0x40
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# define SAM_GPBR17_OFFSET 0x44
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# define SAM_GPBR18_OFFSET 0x48
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# define SAM_GPBR19_OFFSET 0x4c
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#endif
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/* GPBR register adresses ***************************************************************/
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#define SAM_GPBR(n)) (SAM_GPBR_BASE+SAM_GPBR_OFFSET(n))
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@@ -73,8 +88,25 @@
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#define SAM_GPBR6 (SAM_GPBR_BASE+SAM_GPBR6_OFFSET)
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#define SAM_GPBR7 (SAM_GPBR_BASE+SAM_GPBR7_OFFSET)
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#if defined(CONFIG_ARCH_CHIP_SAM4E)
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# define SAM_GPBR8 (SAM_GPBR_BASE+SAM_GPBR8_OFFSET)
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# define SAM_GPBR9 (SAM_GPBR_BASE+SAM_GPBR9_OFFSET)
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# define SAM_GPBR10 (SAM_GPBR_BASE+SAM_GPBR10_OFFSET)
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# define SAM_GPBR11 (SAM_GPBR_BASE+SAM_GPBR11_OFFSET)
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# define SAM_GPBR12 (SAM_GPBR_BASE+SAM_GPBR12_OFFSET)
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# define SAM_GPBR13 (SAM_GPBR_BASE+SAM_GPBR13_OFFSET)
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# define SAM_GPBR14 (SAM_GPBR_BASE+SAM_GPBR14_OFFSET)
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# define SAM_GPBR15 (SAM_GPBR_BASE+SAM_GPBR15_OFFSET)
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# define SAM_GPBR16 (SAM_GPBR_BASE+SAM_GPBR16_OFFSET)
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# define SAM_GPBR17 (SAM_GPBR_BASE+SAM_GPBR17_OFFSET)
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# define SAM_GPBR18 (SAM_GPBR_BASE+SAM_GPBR18_OFFSET)
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# define SAM_GPBR19 (SAM_GPBR_BASE+SAM_GPBR19_OFFSET)
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#endif
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/* GPBR register bit definitions ********************************************************/
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/* All 32-bit values */
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/****************************************************************************************
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* Public Types
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****************************************************************************************/
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@@ -1,7 +1,7 @@
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/****************************************************************************************
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* arch/arm/src/sam34/chip/sam_hsmci.h
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*
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* Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
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* Copyright (C) 2009, 2013-2014 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@@ -127,15 +127,17 @@
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#define HSMCI_MR_CLKDIV_SHIFT (0) /* Bits 0-7: Clock Divider */
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#define HSMCI_MR_CLKDIV_MASK (0xff << HSMCI_MR_CLKDIV_SHIFT)
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# define HSMCI_MR_CLKDIV(n) ((uint32_t)(n) << HSMCI_MR_CLKDIV_SHIFT)
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#define HSMCI_MR_PWSDIV_SHIFT (8) /* Bits 8-10: Power Saving Divider */
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#define HSMCI_MR_PWSDIV_MASK (7 << HSMCI_MR_PWSDIV_SHIFT)
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# define HSMCI_MR_PWSDIV(n) ((uint32_t)(n) << HSMCI_MR_PWSDIV_SHIFT)
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# define HSMCI_MR_PWSDIV_MAX (7 << HSMCI_MR_PWSDIV_SHIFT)
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#define HSMCI_MR_RDPROOF (1 << 11) /* Bit 11: Read Proof Enable */
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#define HSMCI_MR_WRPROOF (1 << 12) /* Bit 12: Write Proof Enable */
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#define HSMCI_MR_FBYTE (1 << 13) /* Bit 13: Force Byte Transfer */
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#define HSMCI_MR_PADV (1 << 14) /* Bit 14: Padding Value */
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#if defined(CONFIG_ARCH_CHIP_SAM4S)
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#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
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# define HSMCI_MR_PDCMODE (1 << 15) /* Bit 15: PDC-oriented Mode */
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#endif
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@@ -144,10 +146,15 @@
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# define HSMCI_MR_BLKLEN_MASK (0xffff << HSMCI_MR_BLKLEN_SHIFT)
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#endif
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#if defined(CONFIG_ARCH_CHIP_SAM4E)
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# define HSMCI_MR_CLKODD (1 << 16) /* Bit 16: Clock divider is odd */
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#endif
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/* HSMCI Data Timeout Register */
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#define HSMCI_DTOR_DTOCYC_SHIFT (0) /* Bits 0-3: Data Timeout Cycle Number */
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#define HSMCI_DTOR_DTOCYC_MASK (15 << HSMCI_DTOR_DTOCYC_SHIFT)
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# define HSMCI_DTOR_DTOCYC(n) ((uint32_t)(n) << HSMCI_DTOR_DTOCYC_SHIFT)
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# define HSMCI_DTOR_DTOCYC_MAX (15 << HSMCI_DTOR_DTOCYC_SHIFT)
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#define HSMCI_DTOR_DTOMUL_SHIFT (4) /* Bits 4-6: Data Timeout Multiplier */
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#define HSMCI_DTOR_DTOMUL_MASK (7 << HSMCI_DTOR_DTOMUL_SHIFT)
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@@ -178,6 +185,7 @@
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#define HSMCI_CMDR_CMDNB_SHIFT (0) /* Bits 0-5: Command Number */
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#define HSMCI_CMDR_CMDNB_MASK (63 << HSMCI_CMDR_CMDNB_SHIFT)
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# define HSMCI_CMDR_CMDNB(n) ((uint32_t)(n) << HSMCI_CMDR_CMDNB_SHIFT)
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#define HSMCI_CMDR_RSPTYP_SHIFT (6) /* Bits 6-7: Response Type */
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#define HSMCI_CMDR_RSPTYP_MASK (3 << HSMCI_CMDR_RSPTYP_SHIFT)
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# define HSMCI_CMDR_RSPTYP_NONE (0 << HSMCI_CMDR_RSPTYP_SHIFT) /* No response */
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@@ -223,13 +231,16 @@
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#define HSMCI_BLKR_BCNT_SHIFT (0) /* Bits 0-15: MMC/SDIO Block Count - SDIO Byte Count */
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#define HSMCI_BLKR_BCNT_MASK (0xffff << HSMCI_BLKR_BCNT_SHIFT)
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# define HSMCI_BLKR_BCNT(n) ((uint32_t)(n) << HSMCI_BLKR_BCNT_SHIFT)
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#define HSMCI_BLKR_BLKLEN_SHIFT (16) /* Bits 16-31: Data Block Length */
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#define HSMCI_BLKR_BLKLEN_MASK (0xffff << HSMCI_BLKR_BLKLEN_SHIFT)
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# define HSMCI_BLKR_BLKLEN(n) ((uint32_t)(n) << HSMCI_BLKR_BLKLEN_SHIFT)
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/* HSMCI Completion Signal Timeout Register */
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#define HSMCI_CSTOR_CSTOCYC_SHIFT (0) /* Bits 0-3: Completion Signal Timeout Cycle Number */
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#define HSMCI_CSTOR_CSTOCYC_MASK (15 << HSMCI_CSTOR_CSTOCYC_SHIFT)
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# define HSMCI_CSTOR_CSTOCYC(n) ((uint32_t)(n) << HSMCI_CSTOR_CSTOCYC_SHIFT)
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#define HSMCI_CSTOR_CSTOMUL_SHIFT (4) /* Bits 4-6: Completion Signal Timeout Multiplier */
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#define HSMCI_CSTOR_CSTOMUL_MASK (7 << HSMCI_CSTOR_CSTOMUL_SHIFT)
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# define HSMCI_CSTOR_CSTOMUL_1 (0 << HSMCI_CSTOR_CSTOMUL_SHIFT)
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@@ -256,7 +267,7 @@
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#define HSMCI_INT_DTIP (1 << 4) /* Bit 4: Data Transfer in Progress */
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#define HSMCI_INT_NOTBUSY (1 << 5) /* Bit 6: HSMCI Not Busy */
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#if defined(CONFIG_ARCH_CHIP_SAM4S)
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#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
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# define HSMCI_INT_ENDRX (1 << 6) /* Bit 6: End of RX Buffer */
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# define HSMCI_INT_ENDTX (1 << 7) /* Bit 7: End of TX Buffer */
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#endif
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@@ -265,7 +276,7 @@
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#define HSMCI_INT_SDIOWAIT (1 << 12) /* Bit 12: SDIO Read Wait Operation Status */
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#define HSMCI_INT_CSRCV (1 << 13) /* Bit 13: CE-ATA Completion Signal Received */
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#if defined(CONFIG_ARCH_CHIP_SAM4S)
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#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
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# define HSMCI_INT_RXBUFF (1 << 14) /* Bit 14: RXBUFF: RX Buffer Full */
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# define HSMCI_INT_TXBUFE (1 << 15) /* Bit 15: TXBUFE: TX Buffer Empty */
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#endif
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+321
-119
File diff suppressed because it is too large
Load Diff
@@ -1,8 +1,8 @@
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/****************************************************************************************
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* arch/arm/src/sam34/chip/sam_rstc.h
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* Reset Controller (RSTC) definitions for the SAM3U and SAM4S
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* Reset Controller (RSTC) definitions for the SAM3U, SAM4E, and SAM4S
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*
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* Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
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* Copyright (C) 2009, 2013-2014 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@@ -64,6 +64,8 @@
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/* RSTC register bit definitions ********************************************************/
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/* Reset Controller Control Register */
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#define RSTC_CR_PROCRST (1 << 0) /* Bit 0: Processor Reset */
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#define RSTC_CR_PERRST (1 << 2) /* Bit 2: Peripheral Reset */
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#define RSTC_CR_EXTRST (1 << 3) /* Bit 3: External Reset */
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@@ -71,6 +73,8 @@
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#define RSTC_CR_KEY_MASK (0xff << RSTC_CR_KEY_SHIFT)
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# define RSTC_CR_KEY (0xa5 << RSTC_CR_KEY_SHIFT)
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/* Reset Controller Status Register */
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#define RSTC_SR_URSTS (1 << 0) /* Bit 0: User Reset Status */
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#define RSTC_SR_RSTTYP_SHIFT (8) /* Bits 8-10: Reset Type */
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#define RSTC_SR_RSTTYP_MASK (7 << RSTC_SR_RSTTYP_SHIFT)
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@@ -82,10 +86,13 @@
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#define RSTC_SR_NRSTL (1 << 16) /* Bit 16: NRST Pin Level */
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#define RSTC_SR_SRCMP (1 << 17) /* Bit 17: Software Reset Command in Progress */
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/* Reset Controller Mode Register */
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#define RSTC_MR_URSTEN (1 << 0) /* Bit 0: User Reset Enable */
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#define RSTC_MR_URSTIEN (1 << 4) /* Bit 4: User Reset Interrupt Enable */
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#define RSTC_MR_ERSTL_SHIFT (8) /* Bits 8-11: External Reset Length */
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#define RSTC_MR_ERSTL_MASK (15 << RSTC_MR_ERSTL_SHIFT)
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# define RSTC_MR_ERSTL(n) ((uint32_t)(n) << RSTC_MR_ERSTL_SHIFT)
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#define RSTC_MR_KEY_SHIFT (24) /* Bits 24-31: Password */
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#define RSTC_MR_KEY_MASK (0xff << RSTC_CR_KEY_SHIFT)
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# define RSTC_MR_KEY (0xa5 << RSTC_CR_KEY_SHIFT)
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@@ -1,8 +1,8 @@
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/****************************************************************************************
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* arch/arm/src/sam34/chip/sam_rtc.h
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* Real-time Clock (RTC) definitions for the SAM3U and SAM4S
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* Real-time Clock (RTC) definitions for the SAM3U, SAM4E, and SAM4S
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*
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* Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
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* Copyright (C) 2009, 2013-2014 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@@ -102,11 +102,12 @@
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#define RTC_MR_HRMOD (1 << 0) /* Bit 0: 12-/24-hour Mode */
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#if defined(CONFIG_ARCH_CHIP_SAM4S)
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#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
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# define RTC_MR_PERSIAN (1 << 1) /* Bit 1: PERSIAN Calendar */
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# define RTC_MR_NEGPPM (1 << 4) /* Bit 4: Negative PPM Correction */
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# define RTC_MR_CORRECTION_SHIFT (8) /* Bits 8-14: Slow Clock Correction */
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# define RTC_MR_CORRECTION_
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# define RTC_MR_CORRECTION_MASK (0x7f << RTC_MR_CORRECTION_SHIFT)
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# define RTC_MR_CORRECTION(n) ((uint32_t)(n) << RTC_MR_CORRECTION_SHIFT)
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# define RTC_MR_HIGHPPM (1 << 15) /* Bit 15: HIGH PPM Correction */
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# define RTC_MR_OUT0_SHIFT (16) /* Bits 16-18: RTCOUT0 Output Source Selection */
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# define RTC_MR_OUT0_MASK (7 << RTC_MR_OUT0_SHIFT)
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@@ -130,55 +131,66 @@
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# define RTC_MR_OUT1_PROG_PULSE (7 << RTC_MR_OUT1_SHIFT) /* Duty cycle programmable pulse */
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# define RTC_MR_THIGH_SHIFT (24) /* Bits 24-26: High Duration of the Output Pulse */
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# define RTC_MR_THIGH_MASK (7 << RTC_MR_THIGH_SHIFT)
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# define RTC_MR_THIGH_ 31MS (0 << RTC_MR_THIGH_SHIFT) /* 31.2 ms */
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# define RTC_MR_THIGH_ 16MS (1 << RTC_MR_THIGH_SHIFT) /* 15.6 ms */
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# define RTC_MR_THIGH_ 4MS (2 << RTC_MR_THIGH_SHIFT) /* 3.91 ms */
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# define RTC_MR_THIGH_ 976US (3 << RTC_MR_THIGH_SHIFT) /* 976 µs */
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# define RTC_MR_THIGH_ 488US (4 << RTC_MR_THIGH_SHIFT) /* 488 µs */
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# define RTC_MR_THIGH_ 22US (5 << RTC_MR_THIGH_SHIFT) /* 122 µs */
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# define RTC_MR_THIGH_ 0US (6 << RTC_MR_THIGH_SHIFT) /* 30.5 µs */
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# define RTC_MR_THIGH_ 15US (7 << RTC_MR_THIGH_SHIFT) /* 15.2 µs */
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# define RTC_MR_THIGH_31MS (0 << RTC_MR_THIGH_SHIFT) /* 31.2 ms */
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# define RTC_MR_THIGH_16MS (1 << RTC_MR_THIGH_SHIFT) /* 15.6 ms */
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# define RTC_MR_THIGH_4MS (2 << RTC_MR_THIGH_SHIFT) /* 3.91 ms */
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# define RTC_MR_THIGH_976US (3 << RTC_MR_THIGH_SHIFT) /* 976 µs */
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# define RTC_MR_THIGH_488US (4 << RTC_MR_THIGH_SHIFT) /* 488 µs */
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# define RTC_MR_THIGH_22US (5 << RTC_MR_THIGH_SHIFT) /* 122 µs */
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# define RTC_MR_THIGH_0US (6 << RTC_MR_THIGH_SHIFT) /* 30.5 µs */
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# define RTC_MR_THIGH_15US (7 << RTC_MR_THIGH_SHIFT) /* 15.2 µs */
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# define RTC_MR_TPERIOD_SHIFT (28) /* Bits 28-29: Period of the Output Pulse */
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# define RTC_MR_TPERIOD_MASK (3 << RTC_MR_TPERIOD_SHIFT)
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# define RTC_MR_TPERIOD_ 1S (0 << RTC_MR_TPERIOD_SHIFT) /* 1 second */
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# define RTC_MR_TPERIOD_ 500MS (1 << RTC_MR_TPERIOD_SHIFT) /* 500 ms */
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# define RTC_MR_TPERIOD_ 250MS (2 << RTC_MR_TPERIOD_SHIFT) /* 250 ms */
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# define RTC_MR_TPERIOD_ 125MS (3 << RTC_MR_TPERIOD_SHIFT) /* 125 ms */
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# define RTC_MR_TPERIOD_1S (0 << RTC_MR_TPERIOD_SHIFT) /* 1 second */
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# define RTC_MR_TPERIOD_500MS (1 << RTC_MR_TPERIOD_SHIFT) /* 500 ms */
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# define RTC_MR_TPERIOD_250MS (2 << RTC_MR_TPERIOD_SHIFT) /* 250 ms */
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# define RTC_MR_TPERIOD_125MS (3 << RTC_MR_TPERIOD_SHIFT) /* 125 ms */
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#endif
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/* RTC Time Register */
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#define RTC_TIMR_SEC_SHIFT (0) /* Bits 0-6: Current Second */
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#define RTC_TIMR_SEC_MASK (0x7f << RTC_TIMR_SEC_SHIFT)
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# define RTC_TIMR_SEC(n) ((uint32_t)(n) << RTC_TIMR_SEC_SHIFT)
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#define RTC_TIMR_MIN_SHIFT (8) /* Bits 8-14: Current Minute */
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#define RTC_TIMR_MIN_MASK (0x7f << RTC_TIMR_MIN_SHIFT)
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# define RTC_TIMR_MIN(n) ((uint32_t)(n) << RTC_TIMR_MIN_SHIFT)
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#define RTC_TIMR_HOUR_SHIFT (16) /* Bits 16-21: Current Hour */
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#define RTC_TIMR_HOUR_MASK (0x3f << RTC_TIMR_HOUR_SHIFT)
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# define RTC_TIMR_HOUR(n) ((uint32_t)(n) << RTC_TIMR_HOUR_SHIFT)
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#define RTC_TIMR_AMPM (1 << 22) /* Bit 22: Ante Meridiem Post Meridiem Indicator */
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/* RTC Calendar Register */
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#define RTC_CALR_CENT_SHIFT (0) /* Bits 0-6: Current Century */
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#define RTC_CALR_CENT_MASK (0x7f << RTC_CALR_CENT_SHIFT)
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# define RTC_CALR_CENT(n) ((uint32_t)(n) << RTC_CALR_CENT_SHIFT)
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#define RTC_CALR_YEAR_SHIFT (8) /* Bits 8-15: Current Year */
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#define RTC_CALR_YEAR_MASK (0xff << RTC_CALR_YEAR_SHIFT)
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# define RTC_CALR_YEAR(n) ((uint32_t)(n) << RTC_CALR_YEAR_SHIFT)
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#define RTC_CALR_MONTH_SHIFT (16) /* Bits 16-20: Current Month */
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#define RTC_CALR_MONTH_MASK (0x1f << RTC_CALR_MONTH_SHIFT)
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# define RTC_CALR_MONTH(n) ((uint32_t)(n) << RTC_CALR_MONTH_SHIFT)
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#define RTC_CALR_DAY_SHIFT (21) /* Bits 21-23: Current Day in Current Week */
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#define RTC_CALR_DAY_MASK (7 << RTC_CALR_DAY_SHIFT)
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# define RTC_CALR_DAY(n) ((uint32_t)(n)7 << RTC_CALR_DAY_SHIFT)
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#define RTC_CALR_DATE_SHIFT (24) /* Bits 24-29: Current Day in Current Month */
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#define RTC_CALR_DATE_MASK (0x3f << RTC_CALR_DATE_SHIFT)
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# define RTC_CALR_DATE(n) ((uint32_t)(n) << RTC_CALR_DATE_SHIFT)
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/* RTC Time Alarm Register */
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#define RTC_TIMALR_SEC_SHIFT (0) /* Bits 0-6: Second Alarm */
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#define RTC_TIMALR_SEC_MASK (0x7f << RTC_TIMALR_SEC_SHIFT)
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# define RTC_TIMALR_SEC(n) ((uint32_t)(n) << RTC_TIMALR_SEC_SHIFT)
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#define RTC_TIMALR_SECEN (1 << 7) /* Bit 7: Second Alarm Enable */
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#define RTC_TIMALR_MIN_SHIFT (8) /* Bits 8-14: Minute Alarm */
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#define RTC_TIMALR_MIN_MASK (0x7f << RTC_TIMALR_MIN_SHIFT)
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# define RTC_TIMALR_MIN(n) ((uint32_t)(n) << RTC_TIMALR_MIN_SHIFT)
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#define RTC_TIMALR_MINEN (1 << 15) /* Bit 15: Minute Alarm Enable */
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#define RTC_TIMALR_HOUR_SHIFT (16) /* Bits 16-21: Hour Alarm */
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#define RTC_TIMALR_HOUR_MASK (0x3f << RTC_TIMALR_HOUR_SHIFT)
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# define RTC_TIMALR_HOUR(n) ((uint32_t)(n) << RTC_TIMALR_HOUR_SHIFT)
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#define RTC_TIMALR_AMPM (1 << 22) /* Bit 22: AM/PM Indicator */
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#define RTC_TIMALR_HOUREN (1 << 23) /* Bit 23: Hour Alarm Enable */
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@@ -186,9 +198,11 @@
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#define RTC_CALALR_MONTH_SHIFT (16) /* Bits 16-20: Month Alarm */
|
||||
#define RTC_CALALR_MONTH_MASK (0x1f << RTC_CALALR_MONTH_SHIFT)
|
||||
# define RTC_CALALR_MONTH(n) ((uint32_t)(n) << RTC_CALALR_MONTH_SHIFT)
|
||||
#define RTC_CALALR_MTHEN (1 << 23) /* Bit 23: Month Alarm Enable */
|
||||
#define RTC_CALALR_DATE_SHIFT (24) /* Bits 24-29: Date Alarm */
|
||||
#define RTC_CALALR_DATE_MASK (0x3f << RTC_CALALR_DATE_SHIFT)
|
||||
# define RTC_CALALR_DATE(n) ((uint32_t)(n) << RTC_CALALR_DATE_SHIFT)
|
||||
#define RTC_CALALR_DATEEN (1 << 31) /* Bit 31: Date Alarm Enable */
|
||||
|
||||
/* RTC Status Register */
|
||||
@@ -199,7 +213,7 @@
|
||||
#define RTC_SR_TIMEV (1 << 3) /* Bit 3: Time Event */
|
||||
#define RTC_SR_CALEV (1 << 4) /* Bit 4: Calendar Event */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM4S)
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
# define RTC_SR_TDERR (1 << 5) /* Bit 5: Time and/or Date Free Running Error */
|
||||
#endif
|
||||
|
||||
@@ -211,7 +225,7 @@
|
||||
#define RTC_SCCR_TIMCLR (1 << 3) /* Bit 3: Time Clear */
|
||||
#define RTC_SCCR_CALCLR (1 << 4) /* Bit 4: Calendar Clear */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM4S)
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
# define RTC_SR_TDERRCLR (1 << 5) /* Bit 5: Time and/or Date Free Running Error Clear */
|
||||
#endif
|
||||
|
||||
@@ -223,7 +237,7 @@
|
||||
#define RTC_IER_TIMEN (1 << 3) /* Bit 3: Time Event Interrupt Enable */
|
||||
#define RTC_IER_CALEN (1 << 4) /* Bit 4: Calendar Event Interrupt Enable */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM4S)
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
# define RTC_SR_TDERREN (1 << 5) /* Bit 5: Time and/or Date Error Interrupt Enable */
|
||||
#endif
|
||||
|
||||
@@ -235,7 +249,7 @@
|
||||
#define RTC_IDR_TIMDIS (1 << 3) /* Bit 3: Time Event Interrupt Disable */
|
||||
#define RTC_IDR_CALDIS (1 << 4) /* Bit 4: Calendar Event Interrupt Disable */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM4S)
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
# define RTC_SR_TDERRDIS (1 << 5) /* Bit 5: Time and/or Date Error Interrupt Disable */
|
||||
#endif
|
||||
|
||||
|
||||
@@ -1,8 +1,8 @@
|
||||
/****************************************************************************************
|
||||
* arch/arm/src/sam34/chip/sam_rtt.h
|
||||
* Real-time Timer (RTT) definitions for the SAM3U and SAM4S
|
||||
* Real-time Timer (RTT) definitions for the SAM3U, SAM4E, and SAM4S
|
||||
*
|
||||
* Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2009, 2013-2014 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@@ -69,12 +69,13 @@
|
||||
/* Real-time Timer Mode Register */
|
||||
|
||||
#define RTT_MR_RTPRES_SHIFT (0) /* Bits 0-15: Real-time Timer Prescaler Value */
|
||||
#define RTT_MR_RTPRES__MASK (0xffff << RTT_MR_RTPRES_SHIFT)
|
||||
#define RTT_MR_RTPRES_MASK (0xffff << RTT_MR_RTPRES_SHIFT)
|
||||
# define RTT_MR_RTPRES(n) ((uint32_t)(n) << RTT_MR_RTPRES_SHIFT)
|
||||
#define RTT_MR_ALMIEN (1 << 16) /* Bit 16: Alarm Interrupt Enable */
|
||||
#define RTT_MR_RTTINCIEN (1 << 17) /* Bit 17: Real-time Timer Increment Int Enable */
|
||||
#define RTT_MR_RTTRST (1 << 18) /* Bit 18: Real-time Timer Restart */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM4S)
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
# define RTT_MR_RTTDIS (1 << 20) /* Bit 20: Real-time Timer Disable */
|
||||
# define RTT_MR_RTC1HZ (1 << 24) /* Bit 24: Real-Time Clock 1Hz Clock Selection */
|
||||
#endif
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
/****************************************************************************************
|
||||
* arch/arm/src/sam34/chip/sam_smc.h
|
||||
* Static Memory Controller (SMC) definitions for the SAM3U and SAM4S
|
||||
* Static Memory Controller (SMC) definitions for the SAM3U, SAM4E, and SAM4S
|
||||
*
|
||||
* Copyright (C) 2009, 2013-2014 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
|
||||
@@ -1,8 +1,8 @@
|
||||
/****************************************************************************************
|
||||
* arch/arm/src/sam34/chip/sam3u_wdt.h
|
||||
* Watchdog Timer (WDT) definitions for the SAM3U, SAM3X, SAM3A, and SAM4S
|
||||
* arch/arm/src/sam34/chip/sam_wdt.h
|
||||
* Watchdog Timer (WDT) definitions for the SAM3U, SAM3X, SAM3A, SAM4E, and SAM4S
|
||||
*
|
||||
* Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2009, 2013-2014 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@@ -74,12 +74,14 @@
|
||||
|
||||
#define WDT_MR_WDV_SHIFT (0) /* Bits 0-11: Watchdog Counter Value */
|
||||
#define WDT_MR_WDV_MASK (0xfff << WDT_MR_WDV_SHIFT)
|
||||
# define WDT_MR_WDV(n) ((uint32_t)(n) << WDT_MR_WDV_SHIFT)
|
||||
#define WDT_MR_WDFIEN (1 << 12) /* Bit 12: Watchdog Fault Interrupt Enable */
|
||||
#define WDT_MR_WDRSTEN (1 << 13) /* Bit 13: Watchdog Reset Enable */
|
||||
#define WDT_MR_WDRPROC (1 << 14) /* Bit 14: Watchdog Reset Processor */
|
||||
#define WDT_MR_WDDIS (1 << 15) /* Bit 15: Watchdog Disable */
|
||||
#define WDT_MR_WDD_SHIFT (16) /* Bits 16-27: Watchdog Delta Value */
|
||||
#define WDT_MR_WDD_MASK (0xfff << WDT_MR_WDD_SHIFT)
|
||||
# define WDT_MR_WDD(n) ((uint32_t)(n) << WDT_MR_WDD_SHIFT)
|
||||
#define WDT_MR_WDDBGHLT (1 << 28) /* Bit 28: Watchdog Debug Halt */
|
||||
#define WDT_MR_WDIDLEHLT (1 << 29) /* Bit 29: Watchdog Idle Halt */
|
||||
|
||||
@@ -51,7 +51,7 @@
|
||||
#include "sam_clockconfig.h"
|
||||
#include "chip/sam_pmc.h"
|
||||
#include "chip/sam_eefc.h"
|
||||
#include "chip/sam3u_wdt.h"
|
||||
#include "chip/sam_wdt.h"
|
||||
#include "chip/sam_supc.h"
|
||||
#include "chip/sam_matrix.h"
|
||||
|
||||
|
||||
Reference in New Issue
Block a user