mirror of
https://github.com/apache/nuttx.git
synced 2026-05-31 14:27:37 +08:00
Fix nuttx coding style
Remove TABs Fix indentation Fix Multi-line comments Fix Comments to the Right of Statements. Fix nuttx coding style Fix Comments to the Right of Statements.
This commit is contained in:
simbit18
Xiang Xiao
@@ -100,6 +100,7 @@
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#define XCPTCONTEXT_REGS (68)
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#define XCPTCONTEXT_SIZE (4 * XCPTCONTEXT_REGS)
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/* Alternate register names *************************************************/
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/* %psr: processor status register */
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@@ -211,69 +212,67 @@
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#define SPARC_SWTRAP_SYSCALL 0
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#define SPARC_SWTRAP_IRQDIS 9
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#define SPARC_SWTRAP_IRQEN 10
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/**
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* PSR masks and starting bit positions
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*
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/* PSR masks and starting bit positions
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* NOTE: Reserved bits are ignored.
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*/
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#define SPARC_PSR_CWP_MASK 0x00000007 /* bits 0 - 4 */
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/** This constant is a mask for the ET bits in the PSR. */
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/* This constant is a mask for the ET bits in the PSR. */
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#define SPARC_PSR_ET_MASK 0x00000020 /* bit 5 */
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/** This constant is a mask for the PS bits in the PSR. */
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/* This constant is a mask for the PS bits in the PSR. */
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#define SPARC_PSR_PS_MASK 0x00000040 /* bit 6 */
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/** This constant is a mask for the S bits in the PSR. */
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/* This constant is a mask for the S bits in the PSR. */
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#define SPARC_PSR_S_MASK 0x00000080 /* bit 7 */
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/** This constant is a mask for the PIL bits in the PSR. */
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/* This constant is a mask for the PIL bits in the PSR. */
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#define SPARC_PSR_PIL_MASK 0x00000F00 /* bits 8 - 11 */
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/** This constant is a mask for the EF bits in the PSR. */
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/* This constant is a mask for the EF bits in the PSR. */
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#define SPARC_PSR_EF_MASK 0x00001000 /* bit 12 */
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/** This constant is a mask for the EC bits in the PSR. */
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/* This constant is a mask for the EC bits in the PSR. */
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#define SPARC_PSR_EC_MASK 0x00002000 /* bit 13 */
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/** This constant is a mask for the ICC bits in the PSR. */
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/* This constant is a mask for the ICC bits in the PSR. */
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#define SPARC_PSR_ICC_MASK 0x00F00000 /* bits 20 - 23 */
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/** This constant is a mask for the VER bits in the PSR. */
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/* This constant is a mask for the VER bits in the PSR. */
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#define SPARC_PSR_VER_MASK 0x0F000000 /* bits 24 - 27 */
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/** This constant is a mask for the IMPL bits in the PSR. */
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/* This constant is a mask for the IMPL bits in the PSR. */
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#define SPARC_PSR_IMPL_MASK 0xF0000000 /* bits 28 - 31 */
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/** This constant is the starting bit position of the CWP in the PSR. */
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/* This constant is the starting bit position of the CWP in the PSR. */
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#define SPARC_PSR_CWP_BIT_POSITION 0 /* bits 0 - 4 */
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/** This constant is the starting bit position of the ET in the PSR. */
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/* This constant is the starting bit position of the ET in the PSR. */
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#define SPARC_PSR_ET_BIT_POSITION 5 /* bit 5 */
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/** This constant is the starting bit position of the PS in the PSR. */
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/* This constant is the starting bit position of the PS in the PSR. */
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#define SPARC_PSR_PS_BIT_POSITION 6 /* bit 6 */
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/** This constant is the starting bit position of the S in the PSR. */
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/* This constant is the starting bit position of the S in the PSR. */
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#define SPARC_PSR_S_BIT_POSITION 7 /* bit 7 */
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/** This constant is the starting bit position of the PIL in the PSR. */
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/* This constant is the starting bit position of the PIL in the PSR. */
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#define SPARC_PSR_PIL_BIT_POSITION 8 /* bits 8 - 11 */
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/** This constant is the starting bit position of the EF in the PSR. */
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/* This constant is the starting bit position of the EF in the PSR. */
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#define SPARC_PSR_EF_BIT_POSITION 12 /* bit 12 */
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/** This constant is the starting bit position of the EC in the PSR. */
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/* This constant is the starting bit position of the EC in the PSR. */
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#define SPARC_PSR_EC_BIT_POSITION 13 /* bit 13 */
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/** This constant is the starting bit position of the ICC in the PSR. */
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/* This constant is the starting bit position of the ICC in the PSR. */
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#define SPARC_PSR_ICC_BIT_POSITION 20 /* bits 20 - 23 */
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/** This constant is the starting bit position of the VER in the PSR. */
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/* This constant is the starting bit position of the VER in the PSR. */
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#define SPARC_PSR_VER_BIT_POSITION 24 /* bits 24 - 27 */
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/** This constant is the starting bit position of the IMPL in the PSR. */
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/* This constant is the starting bit position of the IMPL in the PSR. */
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#define SPARC_PSR_IMPL_BIT_POSITION 28 /* bits 28 - 31 */
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#define SPARC_NUMBER_OF_REGISTER_WINDOWS 8
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@@ -296,20 +295,20 @@
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#define CPU_STACK_FRAME_PAD0_OFFSET 0x5c
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#define CPU_MINIMUM_STACK_FRAME_SIZE 0x60
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#define ISF_STACK_FRAME_OFFSET 0x00
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#define ISF_STACK_FRAME_OFFSET 0x00
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#define ISF_PSR_OFFSET (CPU_MINIMUM_STACK_FRAME_SIZE + 0x00)
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#define ISF_PC_OFFSET (CPU_MINIMUM_STACK_FRAME_SIZE + 0x04)
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#define ISF_NPC_OFFSET (CPU_MINIMUM_STACK_FRAME_SIZE + 0x08)
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#define ISF_G1_OFFSET (CPU_MINIMUM_STACK_FRAME_SIZE + 0x0c)
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#define ISF_G2_OFFSET (CPU_MINIMUM_STACK_FRAME_SIZE + 0x10)
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#define ISF_G4_OFFSET (CPU_MINIMUM_STACK_FRAME_SIZE + 0x18)
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#define ISF_G6_OFFSET (CPU_MINIMUM_STACK_FRAME_SIZE + 0x20)
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#define ISF_I0_OFFSET (CPU_MINIMUM_STACK_FRAME_SIZE + 0x28)
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#define ISF_I2_OFFSET (CPU_MINIMUM_STACK_FRAME_SIZE + 0x30)
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#define ISF_I4_OFFSET (CPU_MINIMUM_STACK_FRAME_SIZE + 0x38)
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#define ISF_I6_FP_OFFSET (CPU_MINIMUM_STACK_FRAME_SIZE + 0x40)
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#define ISF_Y_OFFSET (CPU_MINIMUM_STACK_FRAME_SIZE + 0x48)
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#define ISF_PSR_OFFSET (CPU_MINIMUM_STACK_FRAME_SIZE + 0x00)
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#define ISF_PC_OFFSET (CPU_MINIMUM_STACK_FRAME_SIZE + 0x04)
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#define ISF_NPC_OFFSET (CPU_MINIMUM_STACK_FRAME_SIZE + 0x08)
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#define ISF_G1_OFFSET (CPU_MINIMUM_STACK_FRAME_SIZE + 0x0c)
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#define ISF_G2_OFFSET (CPU_MINIMUM_STACK_FRAME_SIZE + 0x10)
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#define ISF_G4_OFFSET (CPU_MINIMUM_STACK_FRAME_SIZE + 0x18)
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#define ISF_G6_OFFSET (CPU_MINIMUM_STACK_FRAME_SIZE + 0x20)
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#define ISF_I0_OFFSET (CPU_MINIMUM_STACK_FRAME_SIZE + 0x28)
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#define ISF_I2_OFFSET (CPU_MINIMUM_STACK_FRAME_SIZE + 0x30)
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#define ISF_I4_OFFSET (CPU_MINIMUM_STACK_FRAME_SIZE + 0x38)
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#define ISF_I6_FP_OFFSET (CPU_MINIMUM_STACK_FRAME_SIZE + 0x40)
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#define ISF_Y_OFFSET (CPU_MINIMUM_STACK_FRAME_SIZE + 0x48)
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#define ISF_FSR_OFFSET (CPU_MINIMUM_STACK_FRAME_SIZE + 0x4c)
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@@ -335,46 +334,46 @@
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#define CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE (CPU_MINIMUM_STACK_FRAME_SIZE + 0x50 + 32*4)
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/* Offsets of fields with Context_Control for assembly routines. */
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/* Offsets of fields with Context_Control for assembly routines. */
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/** This macro defines an offset into the context for use in assembly. */
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/* This macro defines an offset into the context for use in assembly. */
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#define PSR_OFFSET 0x00
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/** This macro defines an offset into the context for use in assembly. */
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/* This macro defines an offset into the context for use in assembly. */
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#define PC_OFFSET 0x04
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/** This macro defines an offset into the context for use in assembly. */
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/* This macro defines an offset into the context for use in assembly. */
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#define NPC_OFFSET 0x08
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/** This macro defines an offset into the context for use in assembly. */
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/* This macro defines an offset into the context for use in assembly. */
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#define G1_OFFSET 0x0C
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/** This macro defines an offset into the context for use in assembly. */
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/* This macro defines an offset into the context for use in assembly. */
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#define G2_OFFSET 0x10
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/** This macro defines an offset into the context for use in assembly. */
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/* This macro defines an offset into the context for use in assembly. */
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#define G3_OFFSET 0x14
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/** This macro defines an offset into the context for use in assembly. */
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/* This macro defines an offset into the context for use in assembly. */
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#define G4_OFFSET 0x18
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/** This macro defines an offset into the context for use in assembly. */
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/* This macro defines an offset into the context for use in assembly. */
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#define G5_OFFSET 0x1C
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/** This macro defines an offset into the context for use in assembly. */
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/* This macro defines an offset into the context for use in assembly. */
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#define G6_OFFSET 0x20
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/** This macro defines an offset into the context for use in assembly. */
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/* This macro defines an offset into the context for use in assembly. */
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#define G7_OFFSET 0x24
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/** This macro defines an offset into the context for use in assembly. */
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/* This macro defines an offset into the context for use in assembly. */
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#define O0_OFFSET 0x28
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/** This macro defines an offset into the context for use in assembly. */
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/* This macro defines an offset into the context for use in assembly. */
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#define O1_OFFSET 0x2C
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/** This macro defines an offset into the context for use in assembly. */
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/* This macro defines an offset into the context for use in assembly. */
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#define O2_OFFSET 0x30
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/** This macro defines an offset into the context for use in assembly. */
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/* This macro defines an offset into the context for use in assembly. */
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#define O3_OFFSET 0x34
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/** This macro defines an offset into the context for use in assembly. */
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/* This macro defines an offset into the context for use in assembly. */
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#define O4_OFFSET 0x38
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/** This macro defines an offset into the context for use in assembly. */
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/* This macro defines an offset into the context for use in assembly. */
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#define O5_OFFSET 0x3C
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/** This macro defines an offset into the context for use in assembly. */
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/* This macro defines an offset into the context for use in assembly. */
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#define O6_SP_OFFSET 0x40
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/** This macro defines an offset into the context for use in assembly. */
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/* This macro defines an offset into the context for use in assembly. */
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#define O7_OFFSET 0x44
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#define Y_OFFSET 0x48
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@@ -401,8 +400,7 @@
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#define F30_OFFSET 0xc8
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#if ( SPARC_HAS_FPU == 1 )
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/**
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* @brief Offset of the CPU_Per_CPU_control::fsr field relative to the
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/* Offset of the CPU_Per_CPU_control::fsr field relative to the
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* Per_CPU_Control begin.
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*/
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#define SPARC_PER_CPU_FSR_OFFSET 4
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@@ -477,9 +475,7 @@ struct xcptcontext
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* Inline functions
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****************************************************************************/
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/**
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* @brief Macro to set the PSR.
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*
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/* Macro to set the PSR.
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* This macro sets the PSR register to the value in @a _psr.
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*/
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#define sparc_set_psr( _psr ) \
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@@ -490,9 +486,7 @@ struct xcptcontext
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nop(); \
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} while ( 0 )
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/**
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* @brief Macro to obtain the PSR.
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*
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/* Macro to obtain the PSR.
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* This macro returns the current contents of the PSR register in @a _psr.
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*/
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#define sparc_get_psr( _psr ) \
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@@ -501,17 +495,14 @@ struct xcptcontext
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__asm__ volatile( "rd %%psr, %0" : "=r" (_psr) : "0" (_psr) ); \
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} while ( 0 )
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/**
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* This macro is a standard nop instruction.
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/* This macro is a standard nop instruction.
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*/
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#define nop() \
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do { \
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__asm__ volatile ( "nop" ); \
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} while ( 0 )
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/**
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* @brief Macro to obtain the TBR.
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*
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/* Macro to obtain the TBR.
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* This macro returns the current contents of the TBR register in @a _tbr.
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*/
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#define sparc_get_tbr( _tbr ) \
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@@ -520,9 +511,7 @@ struct xcptcontext
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__asm__ volatile( "rd %%tbr, %0" : "=r" (_tbr) : "0" (_tbr) ); \
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} while ( 0 )
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/**
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* @brief Macro to set the TBR.
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*
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/* Macro to set the TBR.
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* This macro sets the TBR register to the value in @a _tbr.
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*/
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#define sparc_set_tbr( _tbr ) \
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@@ -530,9 +519,7 @@ struct xcptcontext
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__asm__ volatile( "wr %0, 0, %%tbr" : "=r" (_tbr) : "0" (_tbr) ); \
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} while ( 0 )
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/**
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* @brief Macro to obtain the WIM.
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*
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/* Macro to obtain the WIM.
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* This macro returns the current contents of the WIM field in @a _wim.
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*/
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#define sparc_get_wim( _wim ) \
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@@ -540,9 +527,7 @@ struct xcptcontext
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__asm__ volatile( "rd %%wim, %0" : "=r" (_wim) : "0" (_wim) ); \
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} while ( 0 )
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/**
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* @brief Macro to set the WIM.
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*
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/* Macro to set the WIM.
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* This macro sets the WIM field to the value in @a _wim.
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*/
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#define sparc_set_wim( _wim ) \
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@@ -553,9 +538,7 @@ struct xcptcontext
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nop(); \
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} while ( 0 )
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/**
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* @brief Macro to obtain the Y register.
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*
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/* Macro to obtain the Y register.
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* This macro returns the current contents of the Y register in @a _y.
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*/
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#define sparc_get_y( _y ) \
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@@ -563,9 +546,7 @@ struct xcptcontext
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__asm__ volatile( "rd %%y, %0" : "=r" (_y) : "0" (_y) ); \
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} while ( 0 )
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/**
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* @brief Macro to set the Y register.
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*
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/* Macro to set the Y register.
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* This macro sets the Y register to the value in @a _y.
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*/
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#define sparc_set_y( _y ) \
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@@ -573,9 +554,7 @@ struct xcptcontext
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__asm__ volatile( "wr %0, %%y" : "=r" (_y) : "0" (_y) ); \
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} while ( 0 )
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/**
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* @brief Macro to obtain the asr17.
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*
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/* Macro to obtain the asr17.
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* This macro returns the current contents of the asr17 register in _asr17.
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*/
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#define sparc_get_asr17( _asr17 ) \
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@@ -584,11 +563,8 @@ struct xcptcontext
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__asm__ volatile( "rd %%asr17, %0" : "=r" (_asr17) : "0" (_asr17) ); \
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} while ( 0 )
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/**
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* @brief SPARC disable processor interrupts.
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*
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/* SPARC disable processor interrupts.
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* This method is invoked to disable all maskable interrupts.
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*
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* @return This method returns the entire PSR contents.
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*/
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@@ -599,11 +575,8 @@ static inline uint32_t sparc_disable_interrupts(void)
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return psr;
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}
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/**
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* @brief SPARC enable processor interrupts.
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*
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/* SPARC enable processor interrupts.
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* This method is invoked to enable all maskable interrupts.
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*
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* @param[in] psr is the PSR returned by @ref sparc_disable_interrupts.
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*/
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@@ -620,11 +593,8 @@ static inline void sparc_enable_interrupts(uint32_t psr)
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__asm__ volatile ("ta %0\nnop\n" :: "i" (SPARC_SWTRAP_IRQEN), "r" (_psr));
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}
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/**
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* @brief SPARC flash processor interrupts.
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*
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/* SPARC flash processor interrupts.
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* This method is invoked to temporarily enable all maskable interrupts.
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*
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* @param[in] _psr is the PSR returned by @ref sparc_disable_interrupts.
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*/
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@@ -634,11 +604,8 @@ static inline void sparc_enable_interrupts(uint32_t psr)
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_psr = sparc_disable_interrupts(); \
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} while ( 0 )
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/**
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* @brief SPARC obtain interrupt level.
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*
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/* SPARC obtain interrupt level.
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* This method is invoked to obtain the current interrupt disable level.
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*
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* @param[in] _level is the PSR returned by @ref sparc_disable_interrupts.
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*/
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@@ -67,16 +67,16 @@
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/* Register Bit-Field Definitions *******************************************/
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#define ODD 1
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#define ODD 1
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#define EVEN 0
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#define ON 1
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#define ON 1
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#define OFF 0
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#define NONE 2
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#define RX 0
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#define TX 1
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#define RXTX 3
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/** Uart control list - Mask */
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/* Uart control list - Mask */
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#define MSK_UART_ENABLE_RX 0x01
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#define MSK_UART_ENABLE_TX 0x02
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@@ -109,9 +109,9 @@
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#define UART_BRG_MASK 0xfff
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#define uart1_set_baudrate(baudrate) (BM3803_REG.uart_scaler1 = (uint32_t)((((BOARD_CPU_CLOCK*10)/(baudrate * 8))-5)/10))
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#define uart1_set_baudrate(baudrate) (BM3803_REG.uart_scaler1 = (uint32_t)((((BOARD_CPU_CLOCK*10)/(baudrate * 8))-5)/10))
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#define uart1_parity_config(uart_parity) ( uart_parity == ODD \
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#define uart1_parity_config(uart_parity) ( uart_parity == ODD \
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? (BM3803_REG.uart_ctrl1 = ((BM3803_REG.uart_ctrl1 | MSK_UART_PAR) | MSK_UART_ENABLE_PAR)) \
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: ( uart_parity == EVEN \
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? (BM3803_REG.uart_ctrl1 = ((BM3803_REG.uart_ctrl1 & ~MSK_UART_PAR) | MSK_UART_ENABLE_PAR)) \
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@@ -130,12 +130,12 @@
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) \
|
||||
)
|
||||
|
||||
#define uart1_flow_ctrl_config(uart_flow) ( uart_flow == ON \
|
||||
#define uart1_flow_ctrl_config(uart_flow) ( uart_flow == ON \
|
||||
? (BM3803_REG.uart_ctrl1 |= MSK_UART_ENABLE_FLOW) \
|
||||
: (BM3803_REG.uart_ctrl1 &= ~MSK_UART_ENABLE_FLOW) \
|
||||
)
|
||||
|
||||
#define uart1_loopback_config(uart_loopb) ( uart_loopb == ON \
|
||||
#define uart1_loopback_config(uart_loopb) ( uart_loopb == ON \
|
||||
? (BM3803_REG.uart_ctrl1 |= MSK_UART_LOOPBACK) \
|
||||
: (BM3803_REG.uart_ctrl1 &= ~MSK_UART_LOOPBACK) \
|
||||
)
|
||||
@@ -146,11 +146,11 @@
|
||||
#define uart1_tx_ready() ((BM3803_REG.uart_status1 & MSK_UART_TXH_READY) == MSK_UART_TXH_READY )
|
||||
#define uart1_rx_ready() ((BM3803_REG.uart_status1 & MSK_UART_DATA_READY) == MSK_UART_DATA_READY)
|
||||
|
||||
#define uart1_send_byte(ch) (BM3803_REG.uart_data1 = ch)
|
||||
#define uart1_send_byte(ch) (BM3803_REG.uart_data1 = ch)
|
||||
|
||||
#define uart2_set_baudrate(baudrate) (BM3803_REG.uart_scaler2 = (((BOARD_CPU_CLOCK*10)/(baudrate*8))-5)/10)
|
||||
#define uart2_set_baudrate(baudrate) (BM3803_REG.uart_scaler2 = (((BOARD_CPU_CLOCK*10)/(baudrate*8))-5)/10)
|
||||
|
||||
#define uart2_parity_config(uart_parity) ( uart_parity == ODD \
|
||||
#define uart2_parity_config(uart_parity) ( uart_parity == ODD \
|
||||
? (BM3803_REG.uart_ctrl2 = ((BM3803_REG.uart_ctrl2 | MSK_UART_PAR) | MSK_UART_ENABLE_PAR)) \
|
||||
: ( uart_parity == EVEN \
|
||||
? (BM3803_REG.uart_ctrl2 = ((BM3803_REG.uart_ctrl2 & ~MSK_UART_PAR) | MSK_UART_ENABLE_PAR)) \
|
||||
@@ -158,12 +158,12 @@
|
||||
) \
|
||||
)
|
||||
|
||||
#define uart2_flow_ctrl_config(uart_flow) ( uart_flow == ON \
|
||||
#define uart2_flow_ctrl_config(uart_flow) ( uart_flow == ON \
|
||||
? (BM3803_REG.uart_ctrl2 |= MSK_UART_ENABLE_FLOW) \
|
||||
: (BM3803_REG.uart_ctrl2 &= ~MSK_UART_ENABLE_FLOW) \
|
||||
)
|
||||
|
||||
#define uart2_loopback_config(uart_loopb) ( uart_loopb == ON \
|
||||
#define uart2_loopback_config(uart_loopb) ( uart_loopb == ON \
|
||||
? (BM3803_REG.uart_ctrl2 |= MSK_UART_LOOPBACK) \
|
||||
: (BM3803_REG.uart_ctrl2 &= ~MSK_UART_LOOPBACK) \
|
||||
)
|
||||
@@ -174,11 +174,11 @@
|
||||
#define uart2_tx_ready() ((BM3803_REG.uart_status2 & MSK_UART_TXH_READY) == MSK_UART_TXH_READY )
|
||||
#define uart2_rx_ready() ((BM3803_REG.uart_status2 & MSK_UART_DATA_READY) == MSK_UART_DATA_READY)
|
||||
|
||||
#define uart2_send_byte(ch) (BM3803_REG.uart_data2 = ch)
|
||||
#define uart2_send_byte(ch) (BM3803_REG.uart_data2 = ch)
|
||||
|
||||
#define uart3_set_baudrate(baudrate) (BM3803_REG.uart_scaler3 = (((BOARD_CPU_CLOCK*10)/(baudrate*8))-5)/10)
|
||||
#define uart3_set_baudrate(baudrate) (BM3803_REG.uart_scaler3 = (((BOARD_CPU_CLOCK*10)/(baudrate*8))-5)/10)
|
||||
|
||||
#define uart3_parity_config(uart_parity) ( uart_parity == ODD \
|
||||
#define uart3_parity_config(uart_parity) ( uart_parity == ODD \
|
||||
? (BM3803_REG.uart_ctrl3 = ((BM3803_REG.uart_ctrl3 | MSK_UART_PAR) | MSK_UART_ENABLE_PAR)) \
|
||||
: ( uart_parity == EVEN \
|
||||
? (BM3803_REG.uart_ctrl3 = ((BM3803_REG.uart_ctrl3 & ~MSK_UART_PAR) | MSK_UART_ENABLE_PAR)) \
|
||||
@@ -186,7 +186,7 @@
|
||||
) \
|
||||
)
|
||||
|
||||
#define uart3_flow_ctrl_config(uart_flow) ( uart_flow == ON \
|
||||
#define uart3_flow_ctrl_config(uart_flow) ( uart_flow == ON \
|
||||
? (BM3803_REG.uart_ctrl3 |= MSK_UART_ENABLE_FLOW) \
|
||||
: (BM3803_REG.uart_ctrl3 &= ~MSK_UART_ENABLE_FLOW) \
|
||||
)
|
||||
@@ -202,7 +202,7 @@
|
||||
#define uart3_tx_ready() ((BM3803_REG.uart_status3 & MSK_UART_TXH_READY) == MSK_UART_TXH_READY )
|
||||
#define uart3_rx_ready() ((BM3803_REG.uart_status3 & MSK_UART_DATA_READY) == MSK_UART_DATA_READY)
|
||||
|
||||
#define uart3_send_byte(ch) (BM3803_REG.uart_data3 = ch)
|
||||
#define uart3_send_byte(ch) (BM3803_REG.uart_data3 = ch)
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
|
||||
@@ -84,7 +84,7 @@
|
||||
#define TX 1
|
||||
#define RXTX 3
|
||||
|
||||
/** Uart control list - Mask */
|
||||
/* Uart control list - Mask */
|
||||
|
||||
#define MSK_UART_ENABLE_RX 0x01
|
||||
#define MSK_UART_ENABLE_TX 0x02
|
||||
@@ -162,7 +162,7 @@
|
||||
#define uart_tx_ready() ((S698PM_REG.uart_status1 & UART_STA_TF) != UART_STA_TF)
|
||||
#define uart_rx_ready() ((S698PM_REG.uart_status1 & UART_STA_DR) == UART_STA_DR)
|
||||
|
||||
#define uart_send_byte(ch) (S698PM_REG.uart_data1 = ch)
|
||||
#define uart_send_byte(ch) (S698PM_REG.uart_data1 = ch)
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
|
||||
Reference in New Issue
Block a user