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z20x: Changes to reduce serial Rx data overrun
boards/z80/ez80/z20x: Increase RX buffer size to 4Kb, reduce BAUD to 2400 in w25boot configuration arch/z80/src/ez80/ez80_serial.c: Reduce Rx FIFO trigger level for eZ80F92 to 1 so that will respond more quickly to incoming data.
This commit is contained in:
Gregory Nutt
committed by
Abdelatif Guettouche
Abdelatif Guettouche
parent
9f3648d329
commit
199b4d6852
@@ -5,6 +5,8 @@
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if ARCH_CHIP_EZ80
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# Chip capabilities
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config ARCH_EZ80_HAVE_PLL
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bool
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default n
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@@ -21,6 +23,8 @@ config ARCH_EZ80_HAVE_TIMER_INTREGS
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bool
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default n
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# Chip selection
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choice
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prompt "eZ80 Chip Selection"
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default ARCH_CHIP_EZ80F91
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@@ -72,6 +76,8 @@ config EZ80_ZDSII_V533
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endchoice # ZDS-II Toolchain version
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# Build type selection
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config EZ80_BOOTLOADER
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bool
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default n
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@@ -89,20 +95,29 @@ config EZ80_PROGRAM
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may require special properties such as re-direction of interrupts
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(eZ80F92)
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# Peripheral selection
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config EZ80_UART
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bool
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default n
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menu "ez80 Peripheral Support"
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config EZ80_UART0
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bool "UART0"
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select EZ80_UART
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select UART0_SERIALDRIVER
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default n
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config EZ80_UART1
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bool "UART1"
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select EZ80_UART
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select UART1_SERIALDRIVER
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default n
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config EZ80_UART2
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bool "UART2"
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select EZ80_UART
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select UART2_SERIALDRIVER
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default n
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depends on ARCH_EZ80_HAVE_UART2
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@@ -132,6 +147,30 @@ config EZ80_EMAC
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endmenu # ez80 Peripheral Support
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# UART Configuration
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choice
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prompt "UART Rx FIFO depth"
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default EZ80_UART_RXFIFO_1 if ARCH_CHIP_EZ80F92 || ARCH_CHIP_EZ80F93
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default EZ80_UART_RXFIFO_4 if ARCH_CHIP_EZ80F91
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depends on EZ80_UART
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config EZ80_UART_RXFIFO_1
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bool "1"
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config EZ80_UART_RXFIFO_4
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bool "4"
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config EZ80_UART_RXFIFO_8
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bool "8"
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config EZ80_UART_RXFIFO_14
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bool "14"
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endchoice
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# RTC/Crystal Configuration
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config EZ80_RTC_32KHZ
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bool "32KHz crystal present"
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default y
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@@ -148,10 +187,12 @@ config EZ80_RTC_LINEFREQ50
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If there is no 32Hz crystal, the RTC will fall back to use the line
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frequency, either 50 or 60Hz.
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# EMAC Configuration
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if EZ80_EMAC
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config EZ80_FIAD
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hex "PHY Address"
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hex "PHY Address"
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range 0x00 0x1f
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default 0x1f
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---help---
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@@ -208,6 +249,8 @@ config ARCH_MCFILTER
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endif # EZ80_EMAC
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# System integration
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config ARCH_TIMERHOOK
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bool "Timer Hook"
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default n
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@@ -1,36 +1,20 @@
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/****************************************************************************
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* arch/z80/src/ez08/ez80_serial.c
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*
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* Copyright (C) 2008-2009, 2012, 2017 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License. *
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****************************************************************************/
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/****************************************************************************
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@@ -67,12 +51,12 @@
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struct ez80_dev_s
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{
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uint16_t uartbase; /* Base address of UART registers */
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unsigned int baud; /* Configured baud */
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uint8_t irq; /* IRQ associated with this UART */
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uint8_t parity; /* 0=none, 1=odd, 2=even */
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uint8_t bits; /* Number of bits (7 or 8) */
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bool stopbits2; /* true: Configure with 2 (vs 1) */
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uint16_t uartbase; /* Base address of UART registers */
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unsigned int baud; /* Configured baud */
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uint8_t irq; /* IRQ associated with this UART */
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uint8_t parity; /* 0=none, 1=odd, 2=even */
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uint8_t bits; /* Number of bits (7 or 8) */
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bool stopbits2; /* true: Configure with 2 (vs 1) */
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};
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/****************************************************************************
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@@ -285,7 +269,7 @@ static void ez80_disableuartint(FAR struct ez80_dev_s *priv)
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static void ez80_restoreuartint(FAR struct ez80_dev_s *priv, uint8_t bits)
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{
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uint8_t ier = ez80_serialin(priv, EZ80_UART_IER);
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ier |= bits & (EZ80_UARTEIR_TIE|EZ80_UARTEIR_RIE);
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ier |= bits & (EZ80_UARTEIR_TIE | EZ80_UARTEIR_RIE);
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ez80_serialout(priv, EZ80_UART_IER, ier);
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}
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@@ -325,19 +309,19 @@ static void ez80_setbaud(FAR struct ez80_dev_s *priv, uint24_t baud)
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* BRG_Divisor = SYSTEM_CLOCK_FREQUENCY / 16 / BAUD
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*/
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brg_divisor = (ez80_systemclock + (baud << 3)) / (baud << 4);
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brg_divisor = (ez80_systemclock + (baud << 3)) / (baud << 4);
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/* Set the DLAB bit to enable access to the BRG registers */
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/* Set the DLAB bit to enable access to the BRG registers */
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lctl = ez80_serialin(priv, EZ80_UART_LCTL);
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lctl |= EZ80_UARTLCTL_DLAB;
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ez80_serialout(priv, EZ80_UART_LCTL, lctl);
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lctl = ez80_serialin(priv, EZ80_UART_LCTL);
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lctl |= EZ80_UARTLCTL_DLAB;
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ez80_serialout(priv, EZ80_UART_LCTL, lctl);
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ez80_serialout(priv, EZ80_UART_BRGL, (uint8_t)(brg_divisor & 0xff));
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ez80_serialout(priv, EZ80_UART_BRGH, (uint8_t)(brg_divisor >> 8));
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ez80_serialout(priv, EZ80_UART_BRGL, (uint8_t)(brg_divisor & 0xff));
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ez80_serialout(priv, EZ80_UART_BRGH, (uint8_t)(brg_divisor >> 8));
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lctl &= ~EZ80_UARTLCTL_DLAB;
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ez80_serialout(priv, EZ80_UART_LCTL, lctl);
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lctl &= ~EZ80_UARTLCTL_DLAB;
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ez80_serialout(priv, EZ80_UART_LCTL, lctl);
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}
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/****************************************************************************
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@@ -376,7 +360,7 @@ static int ez80_setup(FAR struct uart_dev_s *dev)
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}
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else if (priv->parity == 2) /* Even parity */
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{
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cval |= (EZ80_UARTLCTL_PEN|EZ80_UARTLCTL_EPS);
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cval |= (EZ80_UARTLCTL_PEN | EZ80_UARTLCTL_EPS);
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}
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/* Set the baud rate */
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@@ -392,16 +376,32 @@ static int ez80_setup(FAR struct uart_dev_s *dev)
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/* Enable and flush the receive FIFO */
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reg = EZ80_UARTFCTL_FIFOEN;
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reg = EZ80_UARTFCTL_FIFOEN;
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ez80_serialout(priv, EZ80_UART_FCTL, reg);
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reg |= (EZ80_UARTFCTL_CLRTxF|EZ80_UARTFCTL_CLRRxF);
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reg |= (EZ80_UARTFCTL_CLRTXF | EZ80_UARTFCTL_CLRRXF);
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ez80_serialout(priv, EZ80_UART_FCTL, reg);
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/* Set the receive trigger level to 4 */
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/* Set the Rx FIFO trigger level. Small values assure the quickest
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* response to get data from the Rx FIFO. This minimizes the
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* likelihood of Rx overruns with a penalty of more time spent
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* handling Rx interrupts.
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*/
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#if defined(CONFIG_EZ80_UART_RXFIFO_1)
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reg |= EZ80_UARTTRIG_1;
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#elif defined(CONFIG_EZ80_UART_RXFIFO_4)
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reg |= EZ80_UARTTRIG_4;
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#elif defined(CONFIG_EZ80_UART_RXFIFO_8)
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reg |= EZ80_UARTTRIG_8;
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#elif defined(CONFIG_EZ80_UART_RXFIFO_14)
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reg |= EZ80_UARTTRIG_14;
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#else
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# error No Rx FIFO trigger level
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#endif
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ez80_serialout(priv, EZ80_UART_FCTL, reg);
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#endif
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return OK;
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}
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@@ -415,7 +415,7 @@ static int ez80_setup(FAR struct uart_dev_s *dev)
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static void ez80_shutdown(FAR struct uart_dev_s *dev)
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{
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FAR struct ez80_dev_s *priv = (FAR struct ez80_dev_s*)dev->priv;
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FAR struct ez80_dev_s *priv = (FAR struct ez80_dev_s *)dev->priv;
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ez80_disableuartint(priv);
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}
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@@ -423,20 +423,21 @@ static void ez80_shutdown(FAR struct uart_dev_s *dev)
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* Name: ez80_attach
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*
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* Description:
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* Configure the UART to operation in interrupt driven mode. This method is
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* called when the serial port is opened. Normally, this is just after the
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* the setup() method is called, however, the serial console may operate in
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* a non-interrupt driven mode during the boot phase.
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* Configure the UART to operation in interrupt driven mode. This method
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* is called when the serial port is opened. Normally, this is just after
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* the the setup() method is called, however, the serial console may
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* operate in a non-interrupt driven mode during the boot phase.
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*
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* RX and TX interrupts are not enabled when by the attach method (unless the
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* hardware supports multiple levels of interrupt enabling). The RX and TX
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* interrupts are not enabled until the txint() and rxint() methods are called.
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* RX and TX interrupts are not enabled when by the attach method (unless
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* the hardware supports multiple levels of interrupt enabling). The RX
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* and TX interrupts are not enabled until the txint() and rxint() methods
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* are called.
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*
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****************************************************************************/
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static int ez80_attach(FAR struct uart_dev_s *dev)
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{
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FAR struct ez80_dev_s *priv = (FAR struct ez80_dev_s*)dev->priv;
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FAR struct ez80_dev_s *priv = (FAR struct ez80_dev_s *)dev->priv;
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/* Attach the IRQ */
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@@ -448,14 +449,14 @@ static int ez80_attach(FAR struct uart_dev_s *dev)
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*
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* Description:
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* Detach UART interrupts. This method is called when the serial port is
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* closed normally just before the shutdown method is called. The exception
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* is the serial console which is never shutdown.
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* closed normally just before the shutdown method is called. The
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* exception is the serial console which is never shutdown.
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*
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****************************************************************************/
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static void ez80_detach(FAR struct uart_dev_s *dev)
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{
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FAR struct ez80_dev_s *priv = (FAR struct ez80_dev_s*)dev->priv;
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FAR struct ez80_dev_s *priv = (FAR struct ez80_dev_s *)dev->priv;
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ez80_disableuartint(priv);
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irq_detach(priv->irq);
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}
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@@ -480,7 +481,7 @@ static int ez80_interrupt(int irq, FAR void *context, FAR void *arg)
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volatile uint32_t cause;
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DEBUGASSERT(dev != NULL && dev->priv != NULL);
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priv = (struct ez80_dev_s*)dev->priv;
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priv = (struct ez80_dev_s *)dev->priv;
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cause = ez80_serialin(priv, EZ80_UART_IIR) & EZ80_UARTIIR_CAUSEMASK;
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@@ -528,7 +529,7 @@ static int ez80_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
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static int ez80_receive(FAR struct uart_dev_s *dev, FAR unsigned int *status)
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{
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FAR struct ez80_dev_s *priv = (FAR struct ez80_dev_s*)dev->priv;
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FAR struct ez80_dev_s *priv = (FAR struct ez80_dev_s *)dev->priv;
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uint8_t rbr = ez80_serialin(priv, EZ80_UART_RBR);
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uint8_t lsr = ez80_serialin(priv, EZ80_UART_LSR);
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@@ -546,7 +547,7 @@ static int ez80_receive(FAR struct uart_dev_s *dev, FAR unsigned int *status)
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static void ez80_rxint(FAR struct uart_dev_s *dev, bool enable)
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{
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FAR struct ez80_dev_s *priv = (FAR struct ez80_dev_s*)dev->priv;
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FAR struct ez80_dev_s *priv = (FAR struct ez80_dev_s *)dev->priv;
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uint8_t ier = ez80_serialin(priv, EZ80_UART_IER);
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if (enable)
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@@ -573,7 +574,7 @@ static void ez80_rxint(FAR struct uart_dev_s *dev, bool enable)
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static bool ez80_rxavailable(FAR struct uart_dev_s *dev)
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{
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FAR struct ez80_dev_s *priv = (FAR struct ez80_dev_s*)dev->priv;
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FAR struct ez80_dev_s *priv = (FAR struct ez80_dev_s *)dev->priv;
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return (ez80_serialin(priv, EZ80_UART_LSR) & EZ80_UARTLSR_DR) != 0;
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}
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@@ -587,7 +588,7 @@ static bool ez80_rxavailable(FAR struct uart_dev_s *dev)
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static void ez80_send(FAR struct uart_dev_s *dev, int ch)
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{
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FAR struct ez80_dev_s *priv = (FAR struct ez80_dev_s*)dev->priv;
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FAR struct ez80_dev_s *priv = (FAR struct ez80_dev_s *)dev->priv;
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ez80_serialout(priv, EZ80_UART_THR, (uint8_t)ch);
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}
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@@ -601,7 +602,7 @@ static void ez80_send(FAR struct uart_dev_s *dev, int ch)
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static void ez80_txint(FAR struct uart_dev_s *dev, bool enable)
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{
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FAR struct ez80_dev_s *priv = (FAR struct ez80_dev_s*)dev->priv;
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FAR struct ez80_dev_s *priv = (FAR struct ez80_dev_s *)dev->priv;
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uint8_t ier = ez80_serialin(priv, EZ80_UART_IER);
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if (enable)
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@@ -628,7 +629,7 @@ static void ez80_txint(FAR struct uart_dev_s *dev, bool enable)
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static bool ez80_txready(FAR struct uart_dev_s *dev)
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{
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FAR struct ez80_dev_s *priv = (FAR struct ez80_dev_s*)dev->priv;
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FAR struct ez80_dev_s *priv = (FAR struct ez80_dev_s *)dev->priv;
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return (ez80_serialin(priv, EZ80_UART_LSR) & EZ80_UARTLSR_THRE) != 0;
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}
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@@ -642,7 +643,7 @@ static bool ez80_txready(FAR struct uart_dev_s *dev)
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static bool ez80_txempty(FAR struct uart_dev_s *dev)
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{
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FAR struct ez80_dev_s *priv = (FAR struct ez80_dev_s*)dev->priv;
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FAR struct ez80_dev_s *priv = (FAR struct ez80_dev_s *)dev->priv;
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return (ez80_serialin(priv, EZ80_UART_LSR) & EZ80_UARTLSR_TEMT) != 0;
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}
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@@ -733,7 +734,7 @@ void z80_serial_initialize(void)
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int up_putc(int ch)
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{
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#ifdef CONSOLE_DEV
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FAR struct ez80_dev_s *priv = (FAR struct ez80_dev_s*)CONSOLE_DEV.priv;
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FAR struct ez80_dev_s *priv = (FAR struct ez80_dev_s *)CONSOLE_DEV.priv;
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uint8_t ier = ez80_serialin(priv, EZ80_UART_IER);
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ez80_disableuartint(priv);
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+29
-41
@@ -1,36 +1,20 @@
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/************************************************************************************
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* arch/z80/src/ez80/ez80f91.h
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*
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||||
* Copyright (C) 2008, 2009 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License. *
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_Z80_SRC_EZ80_EZ80F91_H
|
||||
@@ -195,7 +179,7 @@
|
||||
#define EZ80_TMR3_OC3L 0x88 /* RW: Timer 3 output compare value 3 (low) */
|
||||
#define EZ80_TMR3_OC3H 0x89 /* RW: Timer 3 output compare value 3 (high) */
|
||||
|
||||
/* TMR0/1/2/3 CTL Register Bit Definitions *******************************************/
|
||||
/* TMR0/1/2/3 CTL Register Bit Definitions ******************************************/
|
||||
|
||||
#define EZ80_TMRCTL_BRKSTOP 0x80 /* Bit 7: Stop timer for debug operation */
|
||||
#define EZ80_TMRCTL_CLKSEL 0x60 /* Bits 6-5: Timer source */
|
||||
@@ -212,7 +196,8 @@
|
||||
#define EZ80_TMRCTL_RLD 0x02 /* Bit 1: Force reload */
|
||||
#define EZ80_TMRCTL_TIMEN 0x01 /* Bit 0: Programmable reload timer enabled */
|
||||
|
||||
/* TMR0/1/2/3 IER Register Bit Definitions *******************************************/
|
||||
/* TMR0/1/2/3 IER Register Bit Definitions ******************************************/
|
||||
|
||||
/* Bit 7: Reserved */
|
||||
#define EZ80_TMRIER_OC3EN 0x40 /* Bit 6: TMR3 OC3 enabled */
|
||||
#define EZ80_TMRIER_OC2EN 0x20 /* Bit 5: TMR3 OC2 enabled */
|
||||
@@ -222,7 +207,8 @@
|
||||
#define EZ80_TMRIER_ICAEN 0x02 /* Bit 1: TMR1/3 capture pin enabled */
|
||||
#define EZ80_TMRIER_EOCEN 0x01 /* Bit 0: End of count interrupt enabled */
|
||||
|
||||
/* TMR0/1/2/3 IER Register Bit Definitions *******************************************/
|
||||
/* TMR0/1/2/3 IER Register Bit Definitions ******************************************/
|
||||
|
||||
/* Bit 7: Reserved */
|
||||
#define EZ80_TMRIIR_OC3 0x40 /* Bit 6: TMR3 OC3 */
|
||||
#define EZ80_TMRIIR_OC2 0x20 /* Bit 5: TMR3 OC2 */
|
||||
@@ -232,7 +218,7 @@
|
||||
#define EZ80_TMRIIR_ICA 0x02 /* Bit 1: TMR1/3 capture pin */
|
||||
#define EZ80_TMRIIR_EOC 0x01 /* Bit 0: End of count interrupt */
|
||||
|
||||
/* PWM Registers *********************************************************************/
|
||||
/* PWM Registers ********************************************************************/
|
||||
|
||||
#define EZ80_PWM_CTL1 0x79
|
||||
#define EZ80_PWM_CTL2 0x7a
|
||||
@@ -254,12 +240,12 @@
|
||||
#define EZ80_PWM3F_L 0x8a
|
||||
#define EZ80_PWM3F_H 0x8b
|
||||
|
||||
/* WDT Registers *********************************************************************/
|
||||
/* WDT Registers ********************************************************************/
|
||||
|
||||
#define EZ80_WDT_CTL 0x93
|
||||
#define EZ80_WDT_RR 0x94
|
||||
|
||||
/* GPIO Registers ********************************************************************/
|
||||
/* GPIO Registers *******************************************************************/
|
||||
|
||||
#define EZ80_PA_DR 0x96
|
||||
#define EZ80_PA_DDR 0x97
|
||||
@@ -282,7 +268,7 @@
|
||||
#define EZ80_PD_ALT1 0xa4
|
||||
#define EZ80_PD_ALT2 0xa5
|
||||
|
||||
/* CS Registers **********************************************************************/
|
||||
/* CS Registers *********************************************************************/
|
||||
|
||||
#define EZ80_CS0_LBR 0xa8
|
||||
#define EZ80_CS0_UBR 0xa9
|
||||
@@ -297,7 +283,7 @@
|
||||
#define EZ80_CS3_UBR 0xb2
|
||||
#define EZ80_CS3_CTL 0xb3
|
||||
|
||||
/* RAMCTL reggisters *****************************************************************/
|
||||
/* RAMCTL reggisters ****************************************************************/
|
||||
|
||||
#define EZ80_RAM_CTL 0xb4
|
||||
#define EZ80_RAM_CTL0 0xb4
|
||||
@@ -305,12 +291,12 @@
|
||||
#define EZ80_MBIST_GPR 0xb6
|
||||
#define EZ80_MBIST_EMR 0xb7
|
||||
|
||||
/* RAMCTL bit definitions ************************************************************/
|
||||
/* RAMCTL bit definitions ***********************************************************/
|
||||
|
||||
#define RAMCTL_ERAMEN (1 << 6) /* Bit 7: 1=On chip EMAC SRAM is enabled */
|
||||
#define RAMCTL_GPRAMEN (1 << 7) /* Bit 7: 1=On chip GP SRAM is enabled */
|
||||
|
||||
/* SPI Registers *********************************************************************/
|
||||
/* SPI Registers ********************************************************************/
|
||||
|
||||
#define EZ80_SPI_BRG_L 0xb8
|
||||
#define EZ80_SPI_BRG_H 0xb9
|
||||
@@ -319,7 +305,8 @@
|
||||
#define EZ80_SPI_RBR 0xbc
|
||||
#define EZ80_SPI_TSR 0xbc
|
||||
|
||||
/* UART Register Offsets *************************************************************/
|
||||
/* UART Register Offsets ************************************************************/
|
||||
|
||||
/* DLAB=0: */
|
||||
#define EZ80_UART_THR 0x00 /* W: UART Transmit holding register */
|
||||
#define EZ80_UART_RBR 0x00 /* R : UART Receive buffer register */
|
||||
@@ -373,8 +360,8 @@
|
||||
# define EZ80_UARTTRIG_8 0x80 /* 10: Receive FIFO trigger level=8 */
|
||||
# define EZ80_UARTTRIG_14 0xc0 /* 11: Receive FIFO trigger level=14 */
|
||||
/* Bit 3-5: Reserved */
|
||||
#define EZ80_UARTFCTL_CLRTxF 0x04 /* Bit 2: Transmit enable */
|
||||
#define EZ80_UARTFCTL_CLRRxF 0x02 /* Bit 1: Receive enable */
|
||||
#define EZ80_UARTFCTL_CLRTXF 0x04 /* Bit 2: Transmit enable */
|
||||
#define EZ80_UARTFCTL_CLRRXF 0x02 /* Bit 1: Receive enable */
|
||||
#define EZ80_UARTFCTL_FIFOEN 0x01 /* Bit 0: Enable receive/transmit FIFOs */
|
||||
|
||||
/* UART0/1 LCTL register bits *******************************************************/
|
||||
@@ -394,6 +381,7 @@
|
||||
#define EZ80_UARTLCTL_MASK 0x3f
|
||||
|
||||
/* UART0/1 MCTL register bits *******************************************************/
|
||||
|
||||
/* Bit 7: Reserved */
|
||||
#define EZ80_UARTMCTL_POLARITY 0x40 /* Bit 6: Invert polarity of RxD and TxD */
|
||||
#define EZ80_UARTMCTL_MDM 0x20 /* Bit 5: Multi-drop mode enable */
|
||||
|
||||
@@ -166,6 +166,7 @@
|
||||
#define EZ80_IR_CTL 0xbf /* Infrared Encoder/Decoder Control */
|
||||
|
||||
/* UART Register Offsets ************************************************************/
|
||||
|
||||
/* DLAB=0: */
|
||||
#define EZ80_UART_THR 0x00 /* W: UART Transmit holding register */
|
||||
#define EZ80_UART_RBR 0x00 /* R : UART Receive buffer register */
|
||||
@@ -222,8 +223,8 @@
|
||||
# define EZ80_UARTTRIG_8 0x80 /* 10: Receive FIFO trigger level=8 */
|
||||
# define EZ80_UARTTRIG_14 0xc0 /* 11: Receive FIFO trigger level=14 */
|
||||
/* Bit 3-5: Reserved */
|
||||
#define EZ80_UARTFCTL_CLRTxF 0x04 /* Bit 2: Transmit enable */
|
||||
#define EZ80_UARTFCTL_CLRRxF 0x02 /* Bit 1: Receive enable */
|
||||
#define EZ80_UARTFCTL_CLRTXF 0x04 /* Bit 2: Transmit enable */
|
||||
#define EZ80_UARTFCTL_CLRRXF 0x02 /* Bit 1: Receive enable */
|
||||
#define EZ80_UARTFCTL_FIFOEN 0x01 /* Bit 0: Enable receive/transmit FIFOs */
|
||||
|
||||
/* UART0/1 LCTL register bits *******************************************************/
|
||||
|
||||
Reference in New Issue
Block a user