mirror of
https://github.com/apache/nuttx.git
synced 2026-06-07 09:18:00 +08:00
pcie: add framework
Squashed commits: 1. x86_64: qemu: implement pci-e functions and enumerate pci-e devices on boot 2. virt: add qemu pci-testdev driver 3. pcie: types array should be null terminated 4. pcie: enable don't take flags, hardcoded enabling flags 5. pcie: checking bar > 4 for 64bit bars are sufficient 6. pcie: qemu: remove not used header 7. pcie: qemu: return -EINVAL if buffer argument is NULL 8. pcie: make pcie enumerate routine as common instead of architecture dependent 9. pcie: cosmetic changes to fit check tools 10. pcie: create MSI/MSIX related marcos and simplify the msi/msix routines
This commit is contained in:
Yang Chung-Fan
committed by
Xiang Xiao
Xiang Xiao
parent
204f4a18a0
commit
18f97bf2f8
@@ -2,3 +2,11 @@
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# For a description of the syntax of this configuration file,
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# see the file kconfig-language.txt in the NuttX tools repository.
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#
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#
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config QEMU_PCIE
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bool "Initialize and enumerate PCI-E Bus"
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default n
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select PCIE
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---help---
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Enables initialization and scaning of standard x86-64 pcie bus.
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@@ -66,6 +66,8 @@ extern "C"
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* Public Function Prototypes
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****************************************************************************/
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void qemu_pcie_init(void);
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#undef EXTERN
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#if defined(__cplusplus)
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}
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@@ -26,4 +26,8 @@ ifeq ($(CONFIG_BOARDCTL),y)
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CSRCS += qemu_appinit.c
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endif
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ifeq ($(CONFIG_QEMU_PCIE),y)
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CSRCS += qemu_pcie.c
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endif
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include $(TOPDIR)/boards/Board.mk
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@@ -66,6 +66,12 @@ void x86_64_boardinitialize(void)
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uart_putreg(CONFIG_16550_UART1_BASE, UART_MCR_OFFSET, UART_MCR_OUT2);
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#endif
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#ifdef CONFIG_QEMU_PCIE
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/* Initialization of system */
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qemu_pcie_init();
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#endif
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/* Configure on-board LEDs if LED support has been selected. */
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#ifdef CONFIG_ARCH_LEDS
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@@ -0,0 +1,398 @@
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/****************************************************************************
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* boards/x86_64/intel64/qemu-intel64/src/qemu_pcie.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/* The MSI and MSI-X vector setup function are taken from Jailhouse inmate
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* library
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*
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* Jailhouse, a Linux-based partitioning hypervisor
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*
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* Copyright (c) Siemens AG, 2014
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*
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* Authors:
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* Jan Kiszka <jan.kiszka@siemens.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2. See
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* the COPYING file in the top-level directory.
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*
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* Alternatively, you can use or redistribute this file under the following
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* BSD license:
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <assert.h>
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#include <nuttx/pcie/pcie.h>
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#include "qemu_pcie_readwrite.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/****************************************************************************
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* Private Functions Definitions
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****************************************************************************/
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static int qemu_pci_cfg_write(FAR struct pcie_dev_s *dev, uintptr_t addr,
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FAR const void *buffer, unsigned int size);
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static int qemu_pci_cfg_read(FAR struct pcie_dev_s *dev, uintptr_t addr,
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FAR void *buffer, unsigned int size);
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static int qemu_pci_map_bar(FAR struct pcie_dev_s *dev, uint32_t addr,
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unsigned long length);
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static int qemu_pci_map_bar64(FAR struct pcie_dev_s *dev, uint64_t addr,
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unsigned long length);
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static int qemu_pci_msix_register(FAR struct pcie_dev_s *dev,
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uint32_t vector, uint32_t index);
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static int qemu_pci_msi_register(FAR struct pcie_dev_s *dev,
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uint16_t vector);
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/****************************************************************************
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* Public Data
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****************************************************************************/
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struct pcie_bus_ops_s qemu_pcie_bus_ops =
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{
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.pci_cfg_write = qemu_pci_cfg_write,
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.pci_cfg_read = qemu_pci_cfg_read,
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.pci_map_bar = qemu_pci_map_bar,
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.pci_map_bar64 = qemu_pci_map_bar64,
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.pci_msix_register = qemu_pci_msix_register,
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.pci_msi_register = qemu_pci_msi_register,
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};
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struct pcie_bus_s qemu_pcie_bus =
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{
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.ops = &qemu_pcie_bus_ops,
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};
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: qemu_pci_cfg_write
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*
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* Description:
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* Write 8, 16, 32, 64 bits data to PCI-E configuration space of device
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* specified by dev
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*
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* Input Parameters:
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* bdf - Device private data
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* buffer - A pointer to the read-only buffer of data to be written
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* size - The number of bytes to send from the buffer
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*
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* Returned Value:
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* 0: success, <0: A negated errno
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*
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****************************************************************************/
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static int qemu_pci_cfg_write(FAR struct pcie_dev_s *dev, uintptr_t addr,
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FAR const void *buffer, unsigned int size)
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{
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if (!buffer)
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return -EINVAL;
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switch (size)
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{
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case 1:
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case 2:
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case 4:
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return __qemu_pci_cfg_write(dev->bdf, addr, buffer, size);
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case 8:
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return __qemu_pci_cfg_write(dev->bdf, addr, buffer, size);
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default:
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return -EINVAL;
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}
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}
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/****************************************************************************
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* Name: qemu_pci_cfg_read
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*
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* Description:
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* Read 8, 16, 32, 64 bits data from PCI-E configuration space of device
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* specified by dev
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*
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* Input Parameters:
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* dev - Device private data
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* buffer - A pointer to a buffer to receive the data from the device
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* size - The requested number of bytes to be read
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*
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* Returned Value:
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* 0: success, <0: A negated errno
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*
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****************************************************************************/
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static int qemu_pci_cfg_read(FAR struct pcie_dev_s *dev, uintptr_t addr,
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FAR void *buffer, unsigned int size)
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{
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if (!buffer)
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return -EINVAL;
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switch (size)
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{
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case 1:
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case 2:
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case 4:
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return __qemu_pci_cfg_read(dev->bdf, addr, buffer, size);
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case 8:
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return __qemu_pci_cfg_read64(dev->bdf, addr, buffer, size);
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default:
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return -EINVAL;
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}
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}
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/****************************************************************************
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* Name: qemu_pci_map_bar
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*
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* Description:
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* Map address in a 32 bits bar in the memory address space
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*
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* Input Parameters:
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* dev - Device private data
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* bar - Bar number
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* length - Map length, multiple of PAGE_SIZE
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* ret - Bar Content
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*
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* Returned Value:
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* 0: success, <0: A negated errno
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*
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****************************************************************************/
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static int qemu_pci_map_bar(FAR struct pcie_dev_s *dev, uint32_t addr,
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unsigned long length)
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{
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up_map_region((void *)((uintptr_t)addr), length,
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X86_PAGE_WR | X86_PAGE_PRESENT | X86_PAGE_NOCACHE | X86_PAGE_GLOBAL);
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return OK;
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}
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/****************************************************************************
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* Name: qemu_pci_map_bar64
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*
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* Description:
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* Map address in a 64 bits bar in the memory address space
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*
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* Input Parameters:
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* dev - Device private data
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* bar - Bar number
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* length - Map length, multiple of PAGE_SIZE
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* ret - Bar Content
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*
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* Returned Value:
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* 0: success, <0: A negated errno
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*
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****************************************************************************/
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static int qemu_pci_map_bar64(FAR struct pcie_dev_s *dev, uint64_t addr,
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unsigned long length)
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{
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up_map_region((void *)((uintptr_t)addr), length,
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X86_PAGE_WR | X86_PAGE_PRESENT | X86_PAGE_NOCACHE | X86_PAGE_GLOBAL);
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return OK;
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}
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/****************************************************************************
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* Name: qemu_pci_msix_register
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*
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* Description:
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* Map a device MSI-X vector to a platform IRQ vector
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*
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* Input Parameters:
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* dev - Device
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* vector - IRQ number of the platform
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* index - Device MSI-X vector number
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*
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* Returned Value:
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* <0: Mapping failed
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* 0: Mapping succeed
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*
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****************************************************************************/
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static int qemu_pci_msix_register(FAR struct pcie_dev_s *dev,
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uint32_t vector, uint32_t index)
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{
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unsigned int bar;
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uint16_t message_control;
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uint32_t table_bar_ind;
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uint32_t table_addr_32;
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uint64_t msix_table_addr = 0;
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int cap = pci_find_cap(dev, PCI_CAP_MSIX);
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if (cap < 0)
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return -EINVAL;
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__qemu_pci_cfg_read(dev->bdf, cap + PCI_MSIX_MCR,
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&message_control, PCI_MSIX_MCR_SIZE);
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/* bounds check */
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if (index > (message_control & PCI_MSIX_MCR_TBL_MASK))
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return -EINVAL;
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__qemu_pci_cfg_read(dev->bdf, cap + PCI_MSIX_TBL,
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&table_bar_ind, PCI_MSIX_TBL_SIZE);
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bar = (table_bar_ind & PCI_MSIX_BIR_MASK);
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if (!pci_get_bar(dev, bar, &table_addr_32))
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{
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/* 32 bit bar */
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msix_table_addr = table_addr_32;
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}
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else
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{
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pci_get_bar64(dev, bar, &msix_table_addr);
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}
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msix_table_addr &= ~0xf;
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msix_table_addr += table_bar_ind & ~PCI_MSIX_BIR_MASK;
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/* enable and mask */
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message_control |= (PCI_MSIX_MCR_EN | PCI_MSIX_MCR_FMASK);
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__qemu_pci_cfg_write(dev->bdf, cap + PCI_MSIX_MCR,
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&message_control, PCI_MSIX_MCR_SIZE);
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msix_table_addr += PCI_MSIX_TBL_ENTRY_SIZE * index;
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mmio_write32((uint32_t *)(msix_table_addr + PCI_MSIX_TBL_LO_ADDR),
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0xfee00000 | up_apic_cpu_id() << PCI_MSIX_APIC_ID_OFFSET);
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mmio_write32((uint32_t *)(msix_table_addr + PCI_MSIX_TBL_HI_ADDR),
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0);
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mmio_write32((uint32_t *)(msix_table_addr + PCI_MSIX_TBL_MSG_DATA),
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vector);
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mmio_write32((uint32_t *)(msix_table_addr + PCI_MSIX_TBL_VEC_CTL),
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0);
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/* enable and unmask */
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message_control &= ~PCI_MSIX_MCR_FMASK;
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__qemu_pci_cfg_write(dev->bdf, cap + PCI_MSIX_MCR,
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&message_control, PCI_MSIX_MCR_SIZE);
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return 0;
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}
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/****************************************************************************
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* Name: qemu_pci_msi_register
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*
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* Description:
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* Map device MSI vectors to a platform IRQ vector
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*
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* Input Parameters:
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* dev - Device
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* vector - IRQ number of the platform
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*
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* Returned Value:
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* <0: Mapping failed
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* 0: Mapping succeed
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*
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****************************************************************************/
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static int qemu_pci_msi_register(FAR struct pcie_dev_s *dev, uint16_t vector)
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{
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uint16_t ctl;
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uint16_t data;
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int cap = pci_find_cap(dev, PCI_CAP_MSI);
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if (cap < 0)
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return -1;
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uint32_t dest = 0xfee00000 | (up_apic_cpu_id() << PCI_MSI_APIC_ID_OFFSET);
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__qemu_pci_cfg_write(dev->bdf, cap + PCI_MSI_MAR, &dest, PCI_MSI_MAR_SIZE);
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__qemu_pci_cfg_read(dev->bdf, cap + PCI_MSI_MCR, &ctl, PCI_MSI_MCR_SIZE);
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if ((ctl & PCI_MSI_MCR_64) == PCI_MSI_MCR_64)
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{
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uint32_t tmp = 0;
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__qemu_pci_cfg_write(dev->bdf,
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cap + PCI_MSI_MAR64_HI, &tmp,
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PCI_MSI_MAR64_HI_SIZE);
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data = cap + PCI_MSI_MDR64;
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}
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else
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{
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data = cap + PCI_MSI_MDR;
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}
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__qemu_pci_cfg_write(dev->bdf, data, &vector, PCI_MSI_MDR_SIZE);
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__qemu_pci_cfg_write(dev->bdf, cap + PCI_MSI_MCR, &vector,
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PCI_MSI_MCR_SIZE);
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uint16_t tmp = PCI_MSI_MCR_EN;
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__qemu_pci_cfg_write(dev->bdf, cap + PCI_MSI_MCR, &tmp, PCI_MSI_MCR_SIZE);
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return OK;
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}
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|
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/****************************************************************************
|
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* Public Functions
|
||||
****************************************************************************/
|
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|
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/****************************************************************************
|
||||
* Name: qemu_pcie_init
|
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*
|
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* Description:
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* Initialize the PCI-E bus *
|
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*
|
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****************************************************************************/
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void qemu_pcie_init(void)
|
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{
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pcie_initialize(&qemu_pcie_bus);
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}
|
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@@ -0,0 +1,240 @@
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/****************************************************************************
|
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* boards/x86_64/intel64/qemu-intel64/src/qemu_pcie_readwrite.h
|
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*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/* The PCI-E Definitions and part of the access routines are taken from
|
||||
* Jailhouse inmate library
|
||||
*
|
||||
* Jailhouse, a Linux-based partitioning hypervisor
|
||||
*
|
||||
* Copyright (c) Siemens AG, 2014
|
||||
*
|
||||
* Authors:
|
||||
* Jan Kiszka <jan.kiszka@siemens.com>
|
||||
*
|
||||
* This work is licensed under the terms of the GNU GPL, version 2. See
|
||||
* the COPYING file in the top-level directory.
|
||||
*
|
||||
* Alternatively, you can use or redistribute this file under the following
|
||||
* BSD license:
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef __INCLUDE_NUTTX_PCIE_PCIE_READWRITE_H
|
||||
#define __INCLUDE_NUTTX_PCIE_PCIE_READWRITE_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <assert.h>
|
||||
|
||||
#include <nuttx/pcie/pcie.h>
|
||||
|
||||
#include <nuttx/board.h>
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "up_arch.h"
|
||||
#include "up_internal.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#define PCI_REG_ADDR_PORT 0xcf8
|
||||
#define PCI_REG_DATA_PORT 0xcfc
|
||||
|
||||
#define PCI_CONE (1 << 31)
|
||||
|
||||
/****************************************************************************
|
||||
* Name: __qemu_pci_cfg_write
|
||||
*
|
||||
* Description:
|
||||
* Write 8, 16, 32 bits data to PCI-E configuration space of device
|
||||
* specified by dev
|
||||
*
|
||||
* Input Parameters:
|
||||
* bfd - Device private data
|
||||
* buffer - A pointer to the read-only buffer of data to be written
|
||||
* size - The number of bytes to send from the buffer
|
||||
*
|
||||
* Returned Value:
|
||||
* 0: success, <0: A negated errno
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline int __qemu_pci_cfg_write(uint16_t bfd, uintptr_t addr,
|
||||
FAR const void *buffer,
|
||||
unsigned int size)
|
||||
{
|
||||
if (!buffer)
|
||||
return -EINVAL;
|
||||
|
||||
outl(PCI_CONE | ((uint32_t)bfd << 8) | (addr & 0xfc), PCI_REG_ADDR_PORT);
|
||||
|
||||
switch (size)
|
||||
{
|
||||
case 1:
|
||||
outb(*(uint8_t *)(buffer), PCI_REG_DATA_PORT + (addr & 0x3));
|
||||
break;
|
||||
case 2:
|
||||
outw(*(uint16_t *)(buffer), PCI_REG_DATA_PORT + (addr & 0x3));
|
||||
break;
|
||||
case 4:
|
||||
outl(*(uint32_t *)(buffer), PCI_REG_DATA_PORT);
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: __qemu_pci_cfg_write64
|
||||
*
|
||||
* Description:
|
||||
* Write 64 bits data to PCI-E configuration space of device
|
||||
* specified by dev
|
||||
*
|
||||
* Input Parameters:
|
||||
* bfd - Device private data
|
||||
* buffer - A pointer to the read-only buffer of data to be written
|
||||
* size - The number of bytes to send from the buffer
|
||||
*
|
||||
* Returned Value:
|
||||
* 0: success, <0: A negated errno
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline int __qemu_pci_cfg_write64(uint16_t bfd, uintptr_t addr,
|
||||
FAR const void *buffer,
|
||||
unsigned int size)
|
||||
{
|
||||
int ret;
|
||||
|
||||
if (!buffer)
|
||||
return -EINVAL;
|
||||
|
||||
ret = __qemu_pci_cfg_write(bfd, addr + 4, buffer + 4, 4);
|
||||
ret |= __qemu_pci_cfg_write(bfd, addr, buffer, 4);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: __qemu_pci_cfg_read
|
||||
*
|
||||
* Description:
|
||||
* Read 8, 16, 32 bits data from PCI-E configuration space of device
|
||||
* specified by dev
|
||||
*
|
||||
* Input Parameters:
|
||||
* dev - Device private data
|
||||
* buffer - A pointer to a buffer to receive the data from the device
|
||||
* size - The requested number of bytes to be read
|
||||
*
|
||||
* Returned Value:
|
||||
* 0: success, <0: A negated errno
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline int __qemu_pci_cfg_read(uint16_t bfd, uintptr_t addr,
|
||||
FAR void *buffer, unsigned int size)
|
||||
{
|
||||
if (!buffer)
|
||||
return -EINVAL;
|
||||
|
||||
outl(PCI_CONE | ((uint32_t)bfd << 8) | (addr & 0xfc), PCI_REG_ADDR_PORT);
|
||||
|
||||
switch (size)
|
||||
{
|
||||
case 1:
|
||||
*(uint8_t *)(buffer) = inb(PCI_REG_DATA_PORT + (addr & 0x3));
|
||||
break;
|
||||
case 2:
|
||||
*(uint16_t *)(buffer) = inw(PCI_REG_DATA_PORT + (addr & 0x3));
|
||||
break;
|
||||
case 4:
|
||||
*(uint32_t *)(buffer) = inl(PCI_REG_DATA_PORT);
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: __qemu_pci_cfg_read
|
||||
*
|
||||
* Description:
|
||||
* Read 64 bits data from PCI-E configuration space of device
|
||||
* specified by dev
|
||||
*
|
||||
* Input Parameters:
|
||||
* dev - Device private data
|
||||
* buffer - A pointer to a buffer to receive the data from the device
|
||||
* size - The requested number of bytes to be read
|
||||
*
|
||||
* Returned Value:
|
||||
* 0: success, <0: A negated errno
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline int __qemu_pci_cfg_read64(uint16_t bfd,
|
||||
uintptr_t addr,
|
||||
FAR void *buffer,
|
||||
unsigned int size)
|
||||
{
|
||||
int ret;
|
||||
|
||||
if (!buffer)
|
||||
return -EINVAL;
|
||||
|
||||
ret = __qemu_pci_cfg_read(bfd, addr + 4, buffer + 4, 4);
|
||||
ret |= __qemu_pci_cfg_read(bfd, addr, buffer, 4);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
#endif /* __INCLUDE_NUTTX_PCIE_PCIE_READWRITE_H */
|
||||
Reference in New Issue
Block a user