More changes from Uros

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3431 42af7a65-404d-4744-a932-0658087f49c3

configs/stm3210e-eval/include/board.h

@@ -57,39 +57,47 @@
 
 /* On-board crystal frequency is 8MHz (HSE) */
 
-#define STM32_BOARD_XTAL       8000000ul
+#define STM32_BOARD_XTAL        8000000ul
 
 /* PLL source is HSE/1, PLL multipler is 9: PLL frequency is 8MHz (XTAL) x 9 = 72MHz */
 
-#define STM32_CFGR_PLLSRC      RCC_CFGR_PLLSRC
+#define STM32_CFGR_PLLSRC       RCC_CFGR_PLLSRC
-#define STM32_CFGR_PLLXTPRE    0
+#define STM32_CFGR_PLLXTPRE     0
-#define STM32_CFGR_PLLMUL      RCC_CFGR_PLLMUL_CLKx9
+#define STM32_CFGR_PLLMUL       RCC_CFGR_PLLMUL_CLKx9
-#define STM32_PLL_FREQUENCY    (9*STM32_BOARD_XTAL)
+#define STM32_PLL_FREQUENCY     (9*STM32_BOARD_XTAL)
 
 /* Use the PLL and set the SYSCLK source to be the PLL */
 
-#define STM32_SYSCLK_SW        RCC_CFGR_SW_PLL
+#define STM32_SYSCLK_SW         RCC_CFGR_SW_PLL
-#define STM32_SYSCLK_SWS       RCC_CFGR_SWS_PLL
+#define STM32_SYSCLK_SWS        RCC_CFGR_SWS_PLL
-#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY
+#define STM32_SYSCLK_FREQUENCY  STM32_PLL_FREQUENCY
 
 /* AHB clock (HCLK) is SYSCLK (72MHz) */
 
-#define STM32_RCC_CFGR_HPRE    RCC_CFGR_HPRE_SYSCLK
+#define STM32_RCC_CFGR_HPRE     RCC_CFGR_HPRE_SYSCLK
-#define STM32_HCLK_FREQUENCY   STM32_PLL_FREQUENCY
+#define STM32_HCLK_FREQUENCY    STM32_PLL_FREQUENCY
+#define STM32_BOARD_HCLK        STM32_HCLK_FREQUENCY    /* same as above, to satisfy compiler */
 
 /* APB2 clock (PCLK2) is HCLK (72MHz) */
 
-#define STM32_RCC_CFGR_PPRE2   RCC_CFGR_PPRE2_HCLK
+#define STM32_RCC_CFGR_PPRE2    RCC_CFGR_PPRE2_HCLK
-#define STM32_PCLK2_FREQUENCY  STM32_HCLK_FREQUENCY
+#define STM32_PCLK2_FREQUENCY   STM32_HCLK_FREQUENCY
 
 /* APB1 clock (PCLK1) is HCLK/2 (36MHz) */
 
-#define STM32_RCC_CFGR_PPRE1   RCC_CFGR_PPRE1_HCLKd2
+#define STM32_RCC_CFGR_PPRE1    RCC_CFGR_PPRE1_HCLKd2
-#define STM32_PCLK1_FREQUENCY  (STM32_HCLK_FREQUENCY/2)
+#define STM32_PCLK1_FREQUENCY   (STM32_HCLK_FREQUENCY/2)
 
 /* USB divider -- Divide PLL clock by 1.5 */
 
-#define STM32_CFGR_USBPRE      0
+#define STM32_CFGR_USBPRE       0
+
+/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
+ * otherwise frequency is 2xAPBx. 
+ * Note: TIM1,8 are on APB2, others on APB1 */
+
+#define STM32_TIM18_FREQUENCY   STM32_HCLK_FREQUENCY
+#define STM32_TIM27_FREQUENCY   STM32_HCLK_FREQUENCY
 
 /* SDIO dividers.  Note that slower clocking is required when DMA is disabled 
  * in order to avoid RX overrun/TX underrun errors due to delayed responses
@@ -99,16 +107,16 @@
  * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz
  */
   
-#define SDIO_INIT_CLKDIV       (178 << SDIO_CLKCR_CLKDIV_SHIFT)
+#define SDIO_INIT_CLKDIV        (178 << SDIO_CLKCR_CLKDIV_SHIFT)
 
 /* DMA ON:  HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz
  * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz
  */
 
 #ifdef CONFIG_SDIO_DMA
-#  define SDIO_MMCXFR_CLKDIV   (2 << SDIO_CLKCR_CLKDIV_SHIFT) 
+#  define SDIO_MMCXFR_CLKDIV    (2 << SDIO_CLKCR_CLKDIV_SHIFT) 
 #else
-#  define SDIO_MMCXFR_CLKDIV   (3 << SDIO_CLKCR_CLKDIV_SHIFT) 
+#  define SDIO_MMCXFR_CLKDIV    (3 << SDIO_CLKCR_CLKDIV_SHIFT) 
 #endif
 
 /* DMA ON:  HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz
@@ -116,9 +124,9 @@
  */
 
 #ifdef CONFIG_SDIO_DMA
-#  define SDIO_SDXFR_CLKDIV    (1 << SDIO_CLKCR_CLKDIV_SHIFT)
+#  define SDIO_SDXFR_CLKDIV     (1 << SDIO_CLKCR_CLKDIV_SHIFT)
 #else
-#  define SDIO_SDXFR_CLKDIV    (3 << SDIO_CLKCR_CLKDIV_SHIFT)
+#  define SDIO_SDXFR_CLKDIV     (3 << SDIO_CLKCR_CLKDIV_SHIFT)
 #endif
 
 /* LED definitions ******************************************************************/

configs/vsn/nsh/defconfig

@@ -503,6 +503,13 @@ CONFIG_PREALLOC_TIMERS=4
 CONFIG_FS_FAT=y
 CONFIG_FS_ROMFS=y
 
+#
+# I2C Settings
+#
+CONFIG_I2C_WRITEREAD=y
+CONFIG_I2C_TRANSFER=y
+CONFIG_I2C_SLAVE=n
+
 #
 # SPI-based MMC/SD driver
 #
@@ -858,3 +865,6 @@ CONFIG_HEAP_SIZE=
 # Application configuration
 
 CONFIG_APPS_DIR="../apps"
+
+# Provide /dev/ramX and then: mount -t binfs /dev/ram0 /bin
+CONFIG_APPS_BINDIR=y

configs/vsn/src/rtac.c

@@ -80,3 +80,27 @@ int rtac_waitg(int group, int time)
 {
     // blocking variant of rtac_exec with timeout if specified
 }
+
+
+/** Power optimization of base systick timer
+ * 
+ * 1. Simple method to skip wake-ups:
+ *  - ask timers about the min. period, which is Ns * systick
+ *  - set the preload register with floor(Ns) * DEFAULT_PRELOAD
+ *  - on wake-up call routines Ns times.
+ * 
+ * 2. If intermediate ISR occuried then:
+ *  - check how many periods have passed by reading the counter: Np
+ *  - set the new counter value as (counter % DEFAULT_PRELOAD)
+ *  - call timer routines Np times; the next call is as usual, starting
+ *    at 1. point above
+ * 
+ * This is okay if ISR's do not read timers, if they read timers then:
+ *  - on ISR wake-up the code described under 2. must be called first
+ *    (on wake-up from IDLE)
+ * 
+ * BUT: the problem is that SYSTICK does not run in Stop mode but RTC
+ *   only, so it might be better to replace SYSTICK with RTAC (this
+ *   module) and do the job above, permitting ultra low power modes of
+ *   25 uA or further down to 5 uA.
+ */

configs/vsn/src/sif.c

@@ -272,6 +272,25 @@ int sif_gpios_unlock(vsn_sif_state_t peripheral)
 }
 
 
+/****************************************************************************
+ * ST LIS331DL
+ ****************************************************************************/ 
+
+void st_lis331dl_open(void)
+{
+}
+
+
+void st_lis331dl_config(void)
+{
+}
+
+
+void st_lis331dl_getreadings(void)
+{
+}
+
+
 /****************************************************************************
  * Analog Outputs
  ****************************************************************************/