boards/arm/s32k1xx/s32k118evb: More build fixes.

This commit is contained in:
Gregory Nutt
2019-08-14 13:31:21 -06:00
parent 963031f42c
commit 17a4efe031
6 changed files with 79 additions and 70 deletions
+3 -2
View File
@@ -36,8 +36,9 @@
# Common ARM source files # Common ARM source files
HEAD_ASRC = HEAD_ASRC =
CMN_ASRCS = up_allocateheap.c up_exit.c up_initialize.c up_interruptcontext.c CMN_ASRCS =
CMN_ASRCS += up_lowputs.c up_mdelay.c up_modifyreg8.c up_modifyreg16.c CMN_CSRCS = up_allocateheap.c up_exit.c up_initialize.c up_interruptcontext.c
CMN_CSRCS += up_lowputs.c up_mdelay.c up_modifyreg8.c up_modifyreg16.c
CMN_CSRCS += up_modifyreg32.c up_puts.c up_releasestack.c up_stackframe.c CMN_CSRCS += up_modifyreg32.c up_puts.c up_releasestack.c up_stackframe.c
CMN_CSRCS += up_task_start.c up_udelay.c up_usestack.c up_vfork.c CMN_CSRCS += up_task_start.c up_udelay.c up_usestack.c up_vfork.c
-1
View File
@@ -192,7 +192,6 @@ void __start(void)
{ {
const uint32_t *src; const uint32_t *src;
uint32_t *dest; uint32_t *dest;
uint32_t regval;
/* Make sure that interrupts are disabled */ /* Make sure that interrupts are disabled */
@@ -48,8 +48,8 @@ CONFIG_NUNGET_CHARS=0
CONFIG_PREALLOC_TIMERS=0 CONFIG_PREALLOC_TIMERS=0
CONFIG_PREALLOC_WDOGS=4 CONFIG_PREALLOC_WDOGS=4
CONFIG_PTHREAD_STACK_DEFAULT=1536 CONFIG_PTHREAD_STACK_DEFAULT=1536
CONFIG_RAM_SIZE=16384 CONFIG_RAM_SIZE=23552
CONFIG_RAM_START=0x20000000 CONFIG_RAM_START=0x1ffffc00
CONFIG_RAW_BINARY=y CONFIG_RAW_BINARY=y
CONFIG_RR_INTERVAL=200 CONFIG_RR_INTERVAL=200
CONFIG_S32K1XX_LPUART0=y CONFIG_S32K1XX_LPUART0=y
+72 -64
View File
@@ -34,7 +34,7 @@
****************************************************************************/ ****************************************************************************/
/* The S32K118 has 256KB of FLASH beginning at address 0x0000:0000 and /* The S32K118 has 256KB of FLASH beginning at address 0x0000:0000 and
* 25KB of SRAM beginning at address 0x1fff:fc00 (incl. 2Kb of FlexRAM) * 23KB of SRAM beginning at address 0x1fff:fc00 (plus 2Kb of FlexRAM)
* *
* The on-chip RAM is split in two regions: SRAM_L and SRAM_U. The RAM is * The on-chip RAM is split in two regions: SRAM_L and SRAM_U. The RAM is
* implemented such that the SRAM_L and SRAM_U ranges form a contiguous * implemented such that the SRAM_L and SRAM_U ranges form a contiguous
@@ -46,7 +46,7 @@
MEMORY MEMORY
{ {
flash (rx) : ORIGIN = 0x00000000, LENGTH = 256K flash (rx) : ORIGIN = 0x00000000, LENGTH = 256K
sram (rwx) : ORIGIN = 0x20000000, LENGTH = 23K sram (rwx) : ORIGIN = 0x1ffffc00, LENGTH = 23K
} }
OUTPUT_ARCH(arm) OUTPUT_ARCH(arm)
@@ -55,75 +55,83 @@ ENTRY(_stext)
SECTIONS SECTIONS
{ {
.text : { .text :
_stext = ABSOLUTE(.); {
*(.vectors) _stext = ABSOLUTE(.);
*(.text .text.*) *(.vectors)
*(.fixup) *(.text .text.*)
*(.gnu.warning) *(.fixup)
*(.rodata .rodata.*) *(.gnu.warning)
*(.gnu.linkonce.t.*) *(.rodata .rodata.*)
*(.glue_7) *(.gnu.linkonce.t.*)
*(.glue_7t) *(.glue_7)
*(.got) *(.glue_7t)
*(.gcc_except_table) *(.got)
*(.gnu.linkonce.r.*) *(.gcc_except_table)
_etext = ABSOLUTE(.); *(.gnu.linkonce.r.*)
} > flash _etext = ABSOLUTE(.);
} > flash
.init_section : { .init_section :
_sinit = ABSOLUTE(.); {
*(.init_array .init_array.*) _sinit = ABSOLUTE(.);
_einit = ABSOLUTE(.); *(.init_array .init_array.*)
} > flash _einit = ABSOLUTE(.);
} > flash
.ARM.extab : { .ARM.extab :
*(.ARM.extab*) {
} >flash *(.ARM.extab*)
} >flash
__exidx_start = ABSOLUTE(.); __exidx_start = ABSOLUTE(.);
.ARM.exidx : { .ARM.exidx :
*(.ARM.exidx*) {
} >flash *(.ARM.exidx*)
__exidx_end = ABSOLUTE(.); } >flash
__exidx_end = ABSOLUTE(.);
.data : { .data :
_sdata = ABSOLUTE(.); {
*(.data .data.*) _sdata = ABSOLUTE(.);
*(.gnu.linkonce.d.*) *(.data .data.*)
CONSTRUCTORS *(.gnu.linkonce.d.*)
_edata = ABSOLUTE(.); CONSTRUCTORS
} > sram AT > flash _edata = ABSOLUTE(.);
} > sram AT > flash
_eronly = LOADADDR(.data); _eronly = LOADADDR(.data);
.ramfunc ALIGN(4): { .ramfunc ALIGN(4):
_sramfuncs = ABSOLUTE(.); {
*(.ramfunc .ramfunc.*) _sramfuncs = ABSOLUTE(.);
_eramfuncs = ABSOLUTE(.); *(.ramfunc .ramfunc.*)
} > sram AT > flash _eramfuncs = ABSOLUTE(.);
} > sram AT > flash
_framfuncs = LOADADDR(.ramfunc); _framfuncs = LOADADDR(.ramfunc);
.bss : { .bss :
_sbss = ABSOLUTE(.); {
*(.bss .bss.*) _sbss = ABSOLUTE(.);
*(.gnu.linkonce.b.*) *(.bss .bss.*)
*(COMMON) *(.gnu.linkonce.b.*)
_ebss = ABSOLUTE(.); *(COMMON)
} > sram _ebss = ABSOLUTE(.);
} > sram
/* Stabs debugging sections. */ /* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) } .stab 0 : { *(.stab) }
.stab.excl 0 : { *(.stab.excl) } .stabstr 0 : { *(.stabstr) }
.stab.exclstr 0 : { *(.stab.exclstr) } .stab.excl 0 : { *(.stab.excl) }
.stab.index 0 : { *(.stab.index) } .stab.exclstr 0 : { *(.stab.exclstr) }
.stab.indexstr 0 : { *(.stab.indexstr) } .stab.index 0 : { *(.stab.index) }
.comment 0 : { *(.comment) } .stab.indexstr 0 : { *(.stab.indexstr) }
.debug_abbrev 0 : { *(.debug_abbrev) } .comment 0 : { *(.comment) }
.debug_info 0 : { *(.debug_info) } .debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) } .debug_info 0 : { *(.debug_info) }
.debug_pubnames 0 : { *(.debug_pubnames) } .debug_line 0 : { *(.debug_line) }
.debug_aranges 0 : { *(.debug_aranges) } .debug_pubnames 0 : { *(.debug_pubnames) }
.debug_aranges 0 : { *(.debug_aranges) }
} }
@@ -49,7 +49,7 @@
#include "chip.h" #include "chip.h"
#include "up_arch.h" #include "up_arch.h"
#include "up_internal.h" #include "up_internal.h"
#include "stm32.h"
#include "s32k118evb.h" #include "s32k118evb.h"
#ifdef CONFIG_ARCH_LEDS #ifdef CONFIG_ARCH_LEDS
@@ -39,6 +39,7 @@
#include <nuttx/config.h> #include <nuttx/config.h>
#include <sys/types.h>
#include <sys/mount.h> #include <sys/mount.h>
#include <syslog.h> #include <syslog.h>