SAMA5: Fix out of range USB PLL divisor

This commit is contained in:
Gregory Nutt
2013-08-14 14:20:01 -06:00
parent 79d5239023
commit 152a5e6da6
+5 -3
View File
@@ -120,12 +120,14 @@
* *
* USB Clock = PLLACK / (USBDIV + 1) = 48MHz * USB Clock = PLLACK / (USBDIV + 1) = 48MHz
* USBDIV = PLLACK / 48MHz - 1 * USBDIV = PLLACK / 48MHz - 1
* = 16.5 * = 15.5
* REVISIT: USBDIV = 16 gives a clock of 46.59MHz which is an error of 3% *
* The maximum value of USBDIV is 15 corresponding to a divisor of 16.
* REVISIT: USBDIV = 15 gives a clock of 49.5MHz which is an error of 3%
*/ */
# define BOARD_OHCI_INPUT PMC_USB_USBS_PLLA # define BOARD_OHCI_INPUT PMC_USB_USBS_PLLA
# define BOARD_OHCI_DIVIDER (16) # define BOARD_OHCI_DIVIDER (15)
#endif #endif
#if 0 #if 0