mirror of
https://github.com/apache/nuttx.git
synced 2026-05-24 07:46:16 +08:00
arch: cxd32xx: Add cxd32xx SoC support
Supported drivers - Serial(PL011), Timer, NVIC
This commit is contained in:
Takuya Miyashita
committed by
Xiang Xiao
Xiang Xiao
parent
95c4463618
commit
146975d069
@@ -686,6 +686,13 @@ config ARCH_CHIP_AT32
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---help---
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Artery AT32 architectures (ARM Cortex-M4)
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config ARCH_CHIP_CXD32XX
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bool "Sony CXD32xx"
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select ARCH_CORTEXM4
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select ARCH_HAVE_FPU
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---help---
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Sony CXD32XX (ARM Cortex-M4) architectures
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config ARCH_CHIP_ARM_CUSTOM
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bool "Custom ARM chip"
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select ARCH_CHIP_CUSTOM
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@@ -1104,6 +1111,7 @@ config ARCH_CHIP
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default "mps" if ARCH_CHIP_MPS
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default "goldfish" if ARCH_CHIP_GOLDFISH_ARM
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default "at32" if ARCH_CHIP_AT32
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default "cxd32xx" if ARCH_CHIP_CXD32XX
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config ARM_THUMB
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bool "Thumb Mode"
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@@ -1588,4 +1596,7 @@ endif
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if ARCH_CHIP_AT32
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source "arch/arm/src/at32/Kconfig"
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endif
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if ARCH_CHIP_CXD32XX
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source "arch/arm/src/cxd32xx/Kconfig"
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endif
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endif # ARCH_ARM
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@@ -0,0 +1,38 @@
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/****************************************************************************
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* arch/arm/include/cxd32xx/chip.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_CXD32XX_CHIP_H
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#define __ARCH_ARM_INCLUDE_CXD32XX_CHIP_H
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/****************************************************************************
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* Pre-processor Prototypes
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****************************************************************************/
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#define CXD32M4_SYSH_PRIORITY_MIN 0xe0 /* All bits[7:5] set is minimum priority */
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#define CXD32M4_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
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#define CXD32M4_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
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#define CXD32M4_SYSH_PRIORITY_STEP 0x20 /* Steps between priorities */
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#define NVIC_SYSH_PRIORITY_MIN CXD32M4_SYSH_PRIORITY_MIN
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#define NVIC_SYSH_PRIORITY_DEFAULT CXD32M4_SYSH_PRIORITY_DEFAULT
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#define NVIC_SYSH_PRIORITY_MAX CXD32M4_SYSH_PRIORITY_MAX
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#define NVIC_SYSH_PRIORITY_STEP CXD32M4_SYSH_PRIORITY_STEP
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#endif /* __ARCH_ARM_INCLUDE_CXD32XX_CHIP_H */
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@@ -0,0 +1,126 @@
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/****************************************************************************
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* arch/arm/include/cxd32xx/irq.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/* This file should never be included directly but, rather,
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* only indirectly through nuttx/irq.h
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*/
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#ifndef __ARCH_ARM_INCLUDE_CXD32XX_IRQ_H
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#define __ARCH_ARM_INCLUDE_CXD32XX_IRQ_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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#endif
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/****************************************************************************
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* Pre-processor Prototypes
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****************************************************************************/
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/* IRQ numbers. The IRQ number corresponds vector number and hence map
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* directly to bits in the NVIC. This does, however, waste several words of
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* memory in the IRQ to handle mapping tables.
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*/
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/* Processor Exceptions (vectors 0-15) */
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#define CXD32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
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/* Vector 0: Reset stack pointer value */
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/* Vector 1: Reset (not handler as an IRQ) */
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#define CXD32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
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#define CXD32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
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#define CXD32_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
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#define CXD32_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
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#define CXD32_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
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#define CXD32_IRQ_SIGNVALUE (7) /* Vector 7: Sign value */
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#define CXD32_IRQ_SVCALL (11)/* Vector 11: SVC call */
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#define CXD32_IRQ_DBGMONITOR (12)/* Vector 12: Debug Monitor */
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/* Vector 13: Reserved */
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#define CXD32_IRQ_PENDSV (14)/* Vector 14: Pendable system service request */
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#define CXD32_IRQ_SYSTICK (15)/* Vector 15: System tick */
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#define CXD32_IRQ_EXTINT (16)/* Vector 16: Vector number of the first external interrupt */
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/* Cortex-M4 External interrupts (vectors >= 16) */
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#define CXD32_IRQ_XXX (CXD32_IRQ_EXTINT+0) /* XXX IRQ number */
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/* XXX The details of interrupt number will be described later. */
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#define CXD32_IRQ_UART0 (CXD32_IRQ_EXTINT+73) /* 16+73: UART0 interrupt */
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#define CXD32_IRQ_TIM01 (CXD32_IRQ_EXTINT+77) /* 16+77: TIMER0_1 interrupt */
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#define CXD32_IRQ_TIM02 (CXD32_IRQ_EXTINT+78) /* 16+78: TIMER0_2 interrupt */
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#define CXD32_IRQ_TIM11 (CXD32_IRQ_EXTINT+79) /* 16+79: TIMER1_1 interrupt */
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#define CXD32_IRQ_TIM12 (CXD32_IRQ_EXTINT+80) /* 16+80: TIMER1_2 interrupt */
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#define CXD32_IRQ_TIM21 (CXD32_IRQ_EXTINT+81) /* 16+81: TIMER2_1 interrupt */
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#define CXD32_IRQ_TIM22 (CXD32_IRQ_EXTINT+82) /* 16+82: TIMER2_2 interrupt */
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#define CXD32_IRQ_TIM31 (CXD32_IRQ_EXTINT+83) /* 16+83: TIMER3_1 interrupt */
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#define CXD32_IRQ_TIM32 (CXD32_IRQ_EXTINT+84) /* 16+84: TIMER3_2 interrupt */
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#define CXD32_IRQ_TIM41 (CXD32_IRQ_EXTINT+85) /* 16+85: TIMER4_1 interrupt */
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#define CXD32_IRQ_TIM42 (CXD32_IRQ_EXTINT+86) /* 16+86: TIMER4_2 interrupt */
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#define CXD32_IRQ_NEXTINT (128)
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#define CXD32_IRQ_NIRQS (CXD32_IRQ_EXTINT+CXD32_IRQ_NEXTINT)
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/* Total number of IRQ numbers (This will need to be revisited if/when the
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* Cortex-M0 is supported)
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*/
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#define NR_VECTORS CXD32_IRQ_NIRQS
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#define NR_IRQS CXD32_IRQ_NIRQS
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/****************************************************************************
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* Public Types
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****************************************************************************/
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#ifndef __ASSEMBLY__
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typedef void (*vic_vector_t)(uint32_t *regs);
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#endif
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/****************************************************************************
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* Inline functions
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****************************************************************************/
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#ifndef __ASSEMBLY__
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif
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#endif /* __ARCH_ARM_INCLUDE_CXD32XX_IRQ_H */
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@@ -0,0 +1,16 @@
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#
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# For a description of the syntax of this configuration file,
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# see the file kconfig-language.txt in the NuttX tools repository.
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#
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menu "Peripheral Support"
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config CXD32_UART0
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bool "UART0"
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default y
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select UART0_SERIALDRIVER
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select ARCH_HAVE_SERIAL_TERMIOS
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---help---
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UART0 must be used as console device at CXD32xx.
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endmenu # "Peripheral Support"
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@@ -0,0 +1,32 @@
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############################################################################
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# arch/arm/src/cxd32xx/Make.defs
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#
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# Licensed to the Apache Software Foundation (ASF) under one or more
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# contributor license agreements. See the NOTICE file distributed with
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# this work for additional information regarding copyright ownership. The
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# ASF licenses this file to you under the Apache License, Version 2.0 (the
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# "License"); you may not use this file except in compliance with the
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# License. You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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# License for the specific language governing permissions and limitations
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# under the License.
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#
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############################################################################
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include armv7-m/Make.defs
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CHIP_ASRCS +=
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CHIP_CSRCS += cxd32_start.c cxd32_uart.c cxd32_irq.c cxd32_timerisr.c
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ifeq ($(CONFIG_UART_PL011),y)
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CHIP_CSRCS += cxd32_serial_pl011.c
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else
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CHIP_CSRCS += cxd32_serial.c
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endif
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@@ -0,0 +1,47 @@
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/****************************************************************************
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* arch/arm/src/cxd32xx/chip.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_CXD32XX_CHIP_H
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#define __ARCH_ARM_SRC_CXD32XX_CHIP_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <nuttx/arch.h>
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#endif
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/* Include the chip capabilities file */
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#include <arch/cxd32xx/chip.h>
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#define ARMV7M_PERIPHERAL_INTERRUPTS 128
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#include "hardware/cxd3277_clockfreq.h"
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#include "hardware/cxd3277_memorymap.h"
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/****************************************************************************
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* Macro Definitions
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****************************************************************************/
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#endif /* __ARCH_ARM_SRC_CXD32XX_CHIP_H */
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@@ -0,0 +1,60 @@
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/****************************************************************************
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* arch/arm/src/cxd32xx/cxd32_config.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
|
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
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* "License"); you may not use this file except in compliance with the
|
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
|
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_CXD32XX_CXD32_CONFIG_H
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#define __ARCH_ARM_SRC_CXD32XX_CXD32_CONFIG_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Required configuration settings */
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/* Are any UARTs enabled? */
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#undef HAVE_UART
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#if defined(CONFIG_CXD32_UART0)
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# define HAVE_UART 1
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#endif
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/* Is there a serial console? There should be at most one defined. It could
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* be on any UARTn, n=0,1,2,3 - OR - there might not be any serial console at
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* all.
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*/
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#if defined(CONFIG_UART0_SERIAL_CONSOLE)
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# define HAVE_CONSOLE 1
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#endif
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/****************************************************************************
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* Public Types
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****************************************************************************/
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/****************************************************************************
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* Public Data
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****************************************************************************/
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#endif /* __ARCH_ARM_SRC_CXD32XX_CXD32_CONFIG_H */
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@@ -0,0 +1,483 @@
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/****************************************************************************
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* arch/arm/src/cxd32xx/cxd32_irq.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
|
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* contributor license agreements. See the NOTICE file distributed with
|
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* this work for additional information regarding copyright ownership. The
|
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
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* "License"); you may not use this file except in compliance with the
|
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* License. You may obtain a copy of the License at
|
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*
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* http://www.apache.org/licenses/LICENSE-2.0
|
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*
|
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* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
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****************************************************************************/
|
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <assert.h>
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#include <debug.h>
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#include <nuttx/board.h>
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#include <nuttx/irq.h>
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#include <nuttx/arch.h>
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#include <nuttx/spinlock.h>
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#include <arch/board/board.h>
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#include "chip.h"
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#include "nvic.h"
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#include "ram_vectors.h"
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#include "arm_internal.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Get a 32-bit version of the default priority */
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#define DEFPRIORITY32 \
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(CXD32M4_SYSH_PRIORITY_DEFAULT << 24 | CXD32M4_SYSH_PRIORITY_DEFAULT << 16 | \
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CXD32M4_SYSH_PRIORITY_DEFAULT << 8 | CXD32M4_SYSH_PRIORITY_DEFAULT)
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#define INTC_EN(n) (CXD32_INTC_BASE + 0x10 + (((n) >> 5) << 2))
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/****************************************************************************
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* Public Data
|
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****************************************************************************/
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: cxd32_dumpnvic
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*
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* Description:
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* Dump some interesting NVIC registers
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*
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****************************************************************************/
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#if defined(CONFIG_DEBUG_IRQ_INFO)
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static void cxd32_dumpnvic(const char *msg, int irq)
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{
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irqstate_t flags;
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flags = enter_critical_section();
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irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
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irqinfo(" INTCTRL: %08x VECTAB: %08x\n", getreg32(NVIC_INTCTRL),
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getreg32(NVIC_VECTAB));
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irqinfo(" IRQ ENABLE: %08x %08x\n", getreg32(NVIC_IRQ0_31_ENABLE),
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getreg32(NVIC_IRQ32_63_ENABLE));
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irqinfo(" SYSH_PRIO: %08x %08x %08x\n",
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getreg32(NVIC_SYSH4_7_PRIORITY),
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getreg32(NVIC_SYSH8_11_PRIORITY),
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getreg32(NVIC_SYSH12_15_PRIORITY));
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irqinfo(" IRQ PRIO: %08x %08x %08x %08x\n",
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getreg32(NVIC_IRQ0_3_PRIORITY),
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getreg32(NVIC_IRQ4_7_PRIORITY),
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getreg32(NVIC_IRQ8_11_PRIORITY),
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getreg32(NVIC_IRQ12_15_PRIORITY));
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irqinfo(" %08x %08x %08x %08x\n",
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getreg32(NVIC_IRQ16_19_PRIORITY),
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getreg32(NVIC_IRQ20_23_PRIORITY),
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getreg32(NVIC_IRQ24_27_PRIORITY),
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getreg32(NVIC_IRQ28_31_PRIORITY));
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irqinfo(" %08x %08x %08x %08x\n",
|
||||
getreg32(NVIC_IRQ32_35_PRIORITY),
|
||||
getreg32(NVIC_IRQ36_39_PRIORITY),
|
||||
getreg32(NVIC_IRQ40_43_PRIORITY),
|
||||
getreg32(NVIC_IRQ44_47_PRIORITY));
|
||||
irqinfo(" %08x %08x %08x\n",
|
||||
getreg32(NVIC_IRQ48_51_PRIORITY),
|
||||
getreg32(NVIC_IRQ52_55_PRIORITY),
|
||||
getreg32(NVIC_IRQ56_59_PRIORITY));
|
||||
leave_critical_section(flags);
|
||||
}
|
||||
#else
|
||||
# define cxd32_dumpnvic(msg, irq)
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: cxd32_nmi, cxd32_pendsv, cxd32_pendsv, cxd32_reserved
|
||||
*
|
||||
* Description:
|
||||
* Handlers for various exceptions. None are handled and all are fatal
|
||||
* error conditions. The only advantage these provided over the default
|
||||
* unexpected interrupt handler is that they provide a diagnostic output.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_DEBUG_FEATURES
|
||||
static int cxd32_nmi(int irq, void *context, void *arg)
|
||||
{
|
||||
up_irq_save();
|
||||
_err("PANIC!!! NMI received\n");
|
||||
PANIC();
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int cxd32_pendsv(int irq, void *context, void *arg)
|
||||
{
|
||||
up_irq_save();
|
||||
_err("PANIC!!! PendSV received\n");
|
||||
PANIC();
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int cxd32_reserved(int irq, void *context, void *arg)
|
||||
{
|
||||
up_irq_save();
|
||||
_err("PANIC!!! Reserved interrupt\n");
|
||||
PANIC();
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: cxd32_prioritize_syscall
|
||||
*
|
||||
* Description:
|
||||
* Set the priority of an exception. This function may be needed
|
||||
* internally even if support for prioritized interrupts is not enabled.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_ARMV7M_USEBASEPRI
|
||||
static inline void cxd32_prioritize_syscall(int priority)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
/* SVCALL is system handler 11 */
|
||||
|
||||
regval = getreg32(NVIC_SYSH8_11_PRIORITY);
|
||||
regval &= ~NVIC_SYSH_PRIORITY_PR11_MASK;
|
||||
regval |= (priority << NVIC_SYSH_PRIORITY_PR11_SHIFT);
|
||||
putreg32(regval, NVIC_SYSH8_11_PRIORITY);
|
||||
}
|
||||
#endif
|
||||
|
||||
static int excinfo(int irq, uintptr_t *regaddr, uint32_t *bit)
|
||||
{
|
||||
*regaddr = NVIC_SYSHCON;
|
||||
switch (irq)
|
||||
{
|
||||
case CXD32_IRQ_MEMFAULT:
|
||||
*bit = NVIC_SYSHCON_MEMFAULTENA;
|
||||
break;
|
||||
|
||||
case CXD32_IRQ_BUSFAULT:
|
||||
*bit = NVIC_SYSHCON_BUSFAULTENA;
|
||||
break;
|
||||
|
||||
case CXD32_IRQ_USAGEFAULT:
|
||||
*bit = NVIC_SYSHCON_USGFAULTENA;
|
||||
break;
|
||||
|
||||
case CXD32_IRQ_SYSTICK:
|
||||
*regaddr = NVIC_SYSTICK_CTRL;
|
||||
*bit = NVIC_SYSTICK_CTRL_ENABLE;
|
||||
break;
|
||||
|
||||
default:
|
||||
return ERROR; /* Invalid or unsupported exception */
|
||||
}
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_irqinitialize
|
||||
*
|
||||
* Description:
|
||||
* Complete initialization of the interrupt system and enable normal,
|
||||
* interrupt processing.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_irqinitialize(void)
|
||||
{
|
||||
uint32_t regaddr;
|
||||
int num_priority_registers;
|
||||
|
||||
/* Disable all interrupts */
|
||||
|
||||
putreg32(0, NVIC_IRQ0_31_ENABLE);
|
||||
putreg32(0, NVIC_IRQ32_63_ENABLE);
|
||||
putreg32(0, NVIC_IRQ64_95_ENABLE);
|
||||
putreg32(0, NVIC_IRQ96_127_ENABLE);
|
||||
|
||||
/* Make sure that we are using the correct vector table. The default
|
||||
* vector address is 0x0000:0000 but if we are executing code that is
|
||||
* positioned in SRAM or in external FLASH, then we may need to reset
|
||||
* the interrupt vector so that it refers to the table in SRAM or in
|
||||
* external FLASH.
|
||||
*/
|
||||
|
||||
putreg32((uint32_t)_vectors, NVIC_VECTAB);
|
||||
|
||||
#ifdef CONFIG_ARCH_RAMVECTORS
|
||||
/* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based
|
||||
* vector table that requires special initialization.
|
||||
*/
|
||||
|
||||
arm_ramvec_initialize();
|
||||
#endif
|
||||
|
||||
/* Set all interrupts (and exceptions) to the default priority */
|
||||
|
||||
putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY);
|
||||
putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY);
|
||||
putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY);
|
||||
|
||||
/* The NVIC ICTR register (bits 0-4) holds the number of interrupt
|
||||
* lines that the NVIC supports:
|
||||
*
|
||||
* 0 -> 32 interrupt lines, 8 priority registers
|
||||
* 1 -> 64 " " " ", 16 priority registers
|
||||
* 2 -> 96 " " " ", 32 priority registers
|
||||
* ...
|
||||
*/
|
||||
|
||||
num_priority_registers = (getreg32(NVIC_ICTR) + 1) * 8;
|
||||
|
||||
/* Now set all of the interrupt lines to the default priority */
|
||||
|
||||
regaddr = NVIC_IRQ0_3_PRIORITY;
|
||||
while (num_priority_registers--)
|
||||
{
|
||||
putreg32(DEFPRIORITY32, regaddr);
|
||||
regaddr += 4;
|
||||
}
|
||||
|
||||
/* Attach the SVCall and Hard Fault exception handlers. The SVCall
|
||||
* exception is used for performing context switches; The Hard Fault
|
||||
* must also be caught because a SVCall may show up as a Hard Fault
|
||||
* under certain conditions.
|
||||
*/
|
||||
|
||||
irq_attach(CXD32_IRQ_SVCALL, arm_svcall, NULL);
|
||||
irq_attach(CXD32_IRQ_HARDFAULT, arm_hardfault, NULL);
|
||||
|
||||
/* Set the priority of the SVCall interrupt */
|
||||
|
||||
#ifdef CONFIG_ARCH_IRQPRIO
|
||||
/* up_prioritize_irq(CXD32_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN);
|
||||
*/
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARMV7M_USEBASEPRI
|
||||
cxd32_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY);
|
||||
#endif
|
||||
|
||||
/* If the MPU is enabled, then attach and enable the Memory Management
|
||||
* Fault handler.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_ARM_MPU
|
||||
irq_attach(CXD32_IRQ_MEMFAULT, arm_memfault, NULL);
|
||||
up_enable_irq(CXD32_IRQ_MEMFAULT);
|
||||
#endif
|
||||
|
||||
/* Attach all other processor exceptions (except reset and sys tick) */
|
||||
|
||||
#ifdef CONFIG_DEBUG_FEATURES
|
||||
irq_attach(CXD32_IRQ_NMI, cxd32_nmi, NULL);
|
||||
# ifndef CONFIG_ARM_MPU
|
||||
irq_attach(CXD32_IRQ_MEMFAULT, arm_memfault, NULL);
|
||||
# endif
|
||||
irq_attach(CXD32_IRQ_BUSFAULT, arm_busfault, NULL);
|
||||
irq_attach(CXD32_IRQ_USAGEFAULT, arm_usagefault, NULL);
|
||||
irq_attach(CXD32_IRQ_PENDSV, cxd32_pendsv, NULL);
|
||||
arm_enable_dbgmonitor();
|
||||
irq_attach(CXD32_IRQ_DBGMONITOR, arm_dbgmonitor, NULL);
|
||||
irq_attach(CXD32_IRQ_RESERVED, cxd32_reserved, NULL);
|
||||
#endif
|
||||
|
||||
cxd32_dumpnvic("initial", CXD32_IRQ_NIRQS);
|
||||
|
||||
/* If a debugger is connected, try to prevent it from catching hardfaults.
|
||||
* If CONFIG_ARMV7M_USEBASEPRI, no hardfaults are expected in normal
|
||||
* operation.
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_DEBUG_FEATURES) && !defined(CONFIG_ARMV7M_USEBASEPRI)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
regval = getreg32(NVIC_DEMCR);
|
||||
regval &= ~NVIC_DEMCR_VCHARDERR;
|
||||
putreg32(regval, NVIC_DEMCR);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* And finally, enable interrupts */
|
||||
|
||||
#ifndef CONFIG_SUPPRESS_INTERRUPTS
|
||||
up_irq_enable();
|
||||
#endif
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_disable_irq
|
||||
*
|
||||
* Description:
|
||||
* Disable the IRQ specified by 'irq'
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_disable_irq(int irq)
|
||||
{
|
||||
uintptr_t regaddr;
|
||||
uint32_t regval;
|
||||
uint32_t bit;
|
||||
|
||||
if (irq >= CXD32_IRQ_EXTINT)
|
||||
{
|
||||
irqstate_t flags = spin_lock_irqsave(NULL);
|
||||
irq -= CXD32_IRQ_EXTINT;
|
||||
bit = 1 << (irq & 0x1f);
|
||||
|
||||
regval = getreg32(INTC_EN(irq));
|
||||
regval &= ~bit;
|
||||
putreg32(regval, INTC_EN(irq));
|
||||
spin_unlock_irqrestore(NULL, flags);
|
||||
putreg32(bit, NVIC_IRQ_CLEAR(irq));
|
||||
}
|
||||
else
|
||||
{
|
||||
if (excinfo(irq, ®addr, &bit) == OK)
|
||||
{
|
||||
regval = getreg32(regaddr);
|
||||
regval &= ~bit;
|
||||
putreg32(regval, regaddr);
|
||||
}
|
||||
}
|
||||
|
||||
cxd32_dumpnvic("disable", irq);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_enable_irq
|
||||
*
|
||||
* Description:
|
||||
* Enable the IRQ specified by 'irq'
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_enable_irq(int irq)
|
||||
{
|
||||
uintptr_t regaddr;
|
||||
uint32_t regval;
|
||||
uint32_t bit;
|
||||
|
||||
if (irq >= CXD32_IRQ_EXTINT)
|
||||
{
|
||||
irqstate_t flags = spin_lock_irqsave(NULL);
|
||||
irq -= CXD32_IRQ_EXTINT;
|
||||
bit = 1 << (irq & 0x1f);
|
||||
|
||||
regval = getreg32(INTC_EN(irq));
|
||||
regval |= bit;
|
||||
putreg32(regval, INTC_EN(irq));
|
||||
spin_unlock_irqrestore(NULL, flags);
|
||||
putreg32(bit, NVIC_IRQ_ENABLE(irq));
|
||||
}
|
||||
else
|
||||
{
|
||||
if (excinfo(irq, ®addr, &bit) == OK)
|
||||
{
|
||||
regval = getreg32(regaddr);
|
||||
regval |= bit;
|
||||
putreg32(regval, regaddr);
|
||||
}
|
||||
}
|
||||
|
||||
cxd32_dumpnvic("enable", irq);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: arm_ack_irq
|
||||
*
|
||||
* Description:
|
||||
* Acknowledge the IRQ
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void arm_ack_irq(int irq)
|
||||
{
|
||||
#ifdef CONFIG_ARCH_LEDS_CPU_ACTIVITY
|
||||
board_autoled_on(LED_CPU);
|
||||
#endif
|
||||
|
||||
/* Check for external interrupt */
|
||||
|
||||
if (irq >= CXD32_IRQ_EXTINT)
|
||||
{
|
||||
irq -= CXD32_IRQ_EXTINT;
|
||||
putreg32(1 << (irq & 0x1f), NVIC_IRQ_CLRPEND(irq));
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_prioritize_irq
|
||||
*
|
||||
* Description:
|
||||
* Set the priority of an IRQ.
|
||||
*
|
||||
* Since this API is not supported on all architectures, it should be
|
||||
* avoided in common implementations where possible.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_ARCH_IRQPRIO
|
||||
int up_prioritize_irq(int irq, int priority)
|
||||
{
|
||||
uint32_t regaddr;
|
||||
uint32_t regval;
|
||||
int shift;
|
||||
|
||||
DEBUGASSERT(irq >= CXD32_IRQ_MEMFAULT && irq < NR_IRQS &&
|
||||
(unsigned)priority <= NVIC_SYSH_PRIORITY_MIN);
|
||||
|
||||
if (irq < CXD32_IRQ_EXTINT)
|
||||
{
|
||||
/* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority
|
||||
* registers (0-3 are invalid)
|
||||
*/
|
||||
|
||||
regaddr = NVIC_SYSH_PRIORITY(irq);
|
||||
irq -= 4;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */
|
||||
|
||||
irq -= CXD32_IRQ_EXTINT;
|
||||
regaddr = NVIC_IRQ_PRIORITY(irq);
|
||||
}
|
||||
|
||||
regval = getreg32(regaddr);
|
||||
shift = ((irq & 3) << 3);
|
||||
regval &= ~(0xff << shift);
|
||||
regval |= (priority << shift);
|
||||
putreg32(regval, regaddr);
|
||||
|
||||
cxd32_dumpnvic("prioritize", irq);
|
||||
return OK;
|
||||
}
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,50 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/cxd32xx/cxd32_serial.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_CXD32XX_CXD32_SERIAL_H
|
||||
#define __ARCH_ARM_SRC_CXD32XX_CXD32_SERIAL_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Inline Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_CXD32XX_CXD32_SERIAL_H */
|
||||
@@ -0,0 +1,106 @@
|
||||
/***************************************************************************
|
||||
* arch/arm/src/cxd32xx/cxd32_serial_pl011.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
***************************************************************************/
|
||||
|
||||
/***************************************************************************
|
||||
* Included Files
|
||||
***************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <sys/types.h>
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include <unistd.h>
|
||||
#include <string.h>
|
||||
#include <assert.h>
|
||||
#include <errno.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/serial/uart_pl011.h>
|
||||
|
||||
#include "arm_internal.h"
|
||||
|
||||
#ifdef USE_SERIALDRIVER
|
||||
|
||||
/***************************************************************************
|
||||
* Public Functions
|
||||
***************************************************************************/
|
||||
|
||||
/***************************************************************************
|
||||
* Name: arm_earlyserialinit
|
||||
*
|
||||
* Description:
|
||||
* see arm_internal.h
|
||||
*
|
||||
***************************************************************************/
|
||||
|
||||
#ifdef USE_EARLYSERIALINIT
|
||||
void arm_earlyserialinit(void)
|
||||
{
|
||||
/* Enable the console UART. The other UARTs will be initialized if and
|
||||
* when they are first opened.
|
||||
*/
|
||||
|
||||
pl011_earlyserialinit();
|
||||
}
|
||||
#endif
|
||||
|
||||
/***************************************************************************
|
||||
* Name: arm_serialinit
|
||||
*
|
||||
* Description:
|
||||
* see arm_internal.h
|
||||
*
|
||||
***************************************************************************/
|
||||
|
||||
void arm_serialinit(void)
|
||||
{
|
||||
pl011_serialinit();
|
||||
}
|
||||
|
||||
#ifdef CONFIG_UART_PL011_PLATFORMIF
|
||||
/***************************************************************************
|
||||
* Name: pl011_platform interface
|
||||
*
|
||||
* Description:
|
||||
* see drivers/serial/serial_pl011.c
|
||||
* pl011_setup
|
||||
* pl011_shutdown
|
||||
*
|
||||
***************************************************************************/
|
||||
|
||||
int pl011_platform_setup(uint32_t base)
|
||||
{
|
||||
/* If needed, implement platform specific process such as enabling pl011
|
||||
* to reduce power consumption.
|
||||
*/
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int pl011_platform_shutdown(uint32_t base)
|
||||
{
|
||||
/* If needed, implement platform specific process such as disabling pl011
|
||||
* to reduce power consumption.
|
||||
*/
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_UART_PL011_PLATFORMIF */
|
||||
#endif /* USE_SERIALDRIVER */
|
||||
@@ -0,0 +1,177 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/cxd32xx/cxd32_start.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <assert.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/arch.h>
|
||||
#include <nuttx/init.h>
|
||||
#include <arch/board/board.h>
|
||||
#include <arch/irq.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "arm_internal.h"
|
||||
#include "init/init.h"
|
||||
|
||||
#include "cxd32_uart.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: showprogress
|
||||
*
|
||||
* Description:
|
||||
* Print a character on the UART to show boot status.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_DEBUG_FEATURES
|
||||
# define showprogress(c) arm_lowputc(c)
|
||||
#else
|
||||
# define showprogress(c)
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
/* _sbss is the start of the BSS region (see the linker script) _ebss is the
|
||||
* end of the BSS region (see the linker script). The idle task stack starts
|
||||
* at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE. The IDLE
|
||||
* thread is the thread that the system boots on and, eventually, becomes the
|
||||
* idle, do nothing task that runs only when there is nothing else to run.
|
||||
* The heap continues from there until the configured end of memory.
|
||||
* g_idle_topstack is the beginning of this heap region (not necessarily
|
||||
* aligned).
|
||||
*/
|
||||
|
||||
const uintptr_t g_idle_topstack = (uintptr_t)_ebss +
|
||||
CONFIG_IDLETHREAD_STACKSIZE;
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: __start
|
||||
*
|
||||
* Description:
|
||||
* This is the reset entry point.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void __start(void) __attribute__((section(".entry")));
|
||||
void __start(void)
|
||||
{
|
||||
const uint32_t *src;
|
||||
uint32_t *dest;
|
||||
|
||||
/* Set MSP/PSP to IDLE stack */
|
||||
|
||||
__asm__ __volatile__("\tmsr msp, %0\n" :
|
||||
: "r" (_ebss + CONFIG_IDLETHREAD_STACKSIZE));
|
||||
__asm__ __volatile__("\tmsr psp, %0\n" :
|
||||
: "r" (_ebss + CONFIG_IDLETHREAD_STACKSIZE));
|
||||
|
||||
up_irq_disable();
|
||||
|
||||
cxd32_lowsetup();
|
||||
showprogress('A');
|
||||
|
||||
/* Clear .bss. We'll do this inline (vs. calling memset) just to be
|
||||
* certain that there are no issues with the state of global variables.
|
||||
*/
|
||||
|
||||
for (dest = (uint32_t *)_sbss; dest < (uint32_t *)_ebss; )
|
||||
{
|
||||
*dest++ = 0;
|
||||
}
|
||||
|
||||
showprogress('B');
|
||||
|
||||
/* Move the initialized data section from his temporary holding spot in
|
||||
* FLASH into the correct place in SRAM. The correct place in SRAM is
|
||||
* give by _sdata and _edata. The temporary location is in FLASH at the
|
||||
* end of all of the other read-only data (.text, .rodata) at _eronly.
|
||||
*/
|
||||
|
||||
for (src = (const uint32_t *)_eronly,
|
||||
dest = (uint32_t *)_sdata; dest < (uint32_t *)_edata;
|
||||
)
|
||||
{
|
||||
*dest++ = *src++;
|
||||
}
|
||||
|
||||
showprogress('C');
|
||||
|
||||
/* Initialize the FPU (if configured) */
|
||||
|
||||
arm_fpuconfig();
|
||||
|
||||
showprogress('D');
|
||||
|
||||
#ifdef CONFIG_ARMV7M_ITMSYSLOG
|
||||
/* Perform ARMv7-M ITM SYSLOG initialization */
|
||||
|
||||
itm_syslog_initialize();
|
||||
#endif
|
||||
|
||||
/* Perform early serial initialization */
|
||||
|
||||
#ifdef USE_EARLYSERIALINIT
|
||||
arm_earlyserialinit();
|
||||
#endif
|
||||
showprogress('E');
|
||||
|
||||
/* For the case of the separate user-/kernel-space build, perform whatever
|
||||
* platform specific initialization of the user memory is required.
|
||||
* Normally this just means initializing the user space .data and .bss
|
||||
* segments.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_BUILD_PROTECTED
|
||||
showprogress('F');
|
||||
#endif
|
||||
|
||||
/* Initialize onboard resources */
|
||||
|
||||
cxd32_boardinitialize();
|
||||
showprogress('G');
|
||||
|
||||
/* Then start NuttX */
|
||||
|
||||
showprogress('\r');
|
||||
showprogress('\n');
|
||||
|
||||
nx_start();
|
||||
|
||||
/* Shouldn't get here */
|
||||
|
||||
for (; ; );
|
||||
}
|
||||
@@ -0,0 +1,171 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/cxd32xx/cxd32_timerisr.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <time.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/arch.h>
|
||||
|
||||
#include "clock/clock.h"
|
||||
#include "arm_internal.h"
|
||||
#include "hardware/cxd32_timer.h"
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* The desired timer interrupt frequency is provided by the definition
|
||||
* CLK_TCK (see include/time.h). CLK_TCK defines the desired number of
|
||||
* system clock ticks per second. That value is a user configurable setting
|
||||
* that defaults to 100 (100 ticks per second = 10 MS interval).
|
||||
*
|
||||
* The Clock Source: Either the internal CCLK or external STCLK (P3.26) clock
|
||||
* as the source in the STCTRL register. This file alwyays configures the
|
||||
* timer to use CCLK as its source.
|
||||
*/
|
||||
|
||||
#define TICK_RELOAD ((CXD32_TIMER_BASEFREQ / CLK_TCK) - 1)
|
||||
|
||||
/* The size of the reload field is 24 bits. Verify taht the reload value
|
||||
* will fit in the reload register.
|
||||
*/
|
||||
|
||||
#if TICK_RELOAD > 0x00ffffff
|
||||
# error TICK_RELOAD exceeds the range of the RELOAD register
|
||||
#endif
|
||||
|
||||
#define TIMER4_CH0 (CXD32_TIMER4_BASE+CXD32_TIMER_CH0_OFFSET)
|
||||
#define TIMER4_CH1 (CXD32_TIMER4_BASE+CXD32_TIMER_CH1_OFFSET)
|
||||
#define TIMER4_CH1_INITVALUE 0xFFFFFFFF
|
||||
|
||||
/****************************************************************************
|
||||
* Private Types
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Function: cxd32_timerisr
|
||||
*
|
||||
* Description:
|
||||
* The timer ISR will perform a variety of services for various portions
|
||||
* of the systems.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static int cxd32_timerisr(int irq, uint32_t *regs, void *arg)
|
||||
{
|
||||
/* Process timer interrupt */
|
||||
|
||||
putreg32(TIMER_INTERRUPT, TIMER4_CH0 + CXD32_TIMER_INTCLR);
|
||||
|
||||
nxsched_process_timer();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Function: up_timer_initialize
|
||||
*
|
||||
* Description:
|
||||
* This function is called during start-up to initialize
|
||||
* the timer interrupt.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static void cxd32_timer0_initialize(void)
|
||||
{
|
||||
uint32_t ctrl;
|
||||
|
||||
/* Configure Tick to interrupt at the requested rate */
|
||||
|
||||
putreg32(TICK_RELOAD, TIMER4_CH0 + CXD32_TIMER_LOAD);
|
||||
|
||||
/* Attach the timer interrupt vector */
|
||||
|
||||
(void)irq_attach(CXD32_IRQ_TIM41, (xcpt_t)cxd32_timerisr, NULL);
|
||||
|
||||
/* Enable Timer */
|
||||
|
||||
ctrl = (TIMERCTRL_ENABLE | TIMERCTRL_DIV_1 |
|
||||
TIMERCTRL_SIZE_32BIT | TIMERCTRL_MODE_WRAP);
|
||||
ctrl |= (TIMERCTRL_PERIODIC | TIMERCTRL_INTENABLE);
|
||||
|
||||
putreg32(ctrl, TIMER4_CH0 + CXD32_TIMER_CONTROL);
|
||||
|
||||
/* And enable the timer interrupt */
|
||||
|
||||
up_enable_irq(CXD32_IRQ_TIM41);
|
||||
}
|
||||
|
||||
static void cxd32_timer1_initialize(void)
|
||||
{
|
||||
uint32_t ctrl;
|
||||
|
||||
/* Configure the coutner */
|
||||
|
||||
putreg32(TIMER4_CH1_INITVALUE, TIMER4_CH1 + CXD32_TIMER_LOAD);
|
||||
|
||||
/* Enable Timer */
|
||||
|
||||
ctrl = (TIMERCTRL_ENABLE | TIMERCTRL_DIV_1 |
|
||||
TIMERCTRL_SIZE_32BIT | TIMERCTRL_MODE_WRAP);
|
||||
ctrl |= (TIMERCTRL_PERIODIC);
|
||||
|
||||
putreg32(ctrl, TIMER4_CH1 + CXD32_TIMER_CONTROL);
|
||||
}
|
||||
|
||||
void up_timer_initialize(void)
|
||||
{
|
||||
cxd32_timer0_initialize();
|
||||
cxd32_timer1_initialize();
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Function: cxd32_timerget
|
||||
*
|
||||
* Description:
|
||||
* This function returns the count of timer.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
uint32_t cxd32_timerget(void)
|
||||
{
|
||||
return getreg32(TIMER4_CH1 + CXD32_TIMER_VALUE);
|
||||
}
|
||||
@@ -0,0 +1,289 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/cxd32xx/cxd32_uart.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include <nuttx/spinlock.h>
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include <errno.h>
|
||||
|
||||
#include "arm_internal.h"
|
||||
#include "chip.h"
|
||||
#include "cxd32_config.h"
|
||||
#include "cxd32_uart.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Select UART parameters for the selected console */
|
||||
|
||||
#if defined(CONFIG_UART0_SERIAL_CONSOLE)
|
||||
#define CONSOLE_BASE CXD32_UART0_BASE
|
||||
#define CONSOLE_BASEFREQ CXD32_UART_BASEFREQ
|
||||
#define CONSOLE_BAUD CONFIG_UART0_BAUD
|
||||
#define CONSOLE_BITS CONFIG_UART0_BITS
|
||||
#define CONSOLE_PARITY CONFIG_UART0_PARITY
|
||||
#define CONSOLE_2STOP CONFIG_UART0_2STOP
|
||||
#elif defined(HAVE_CONSOLE)
|
||||
#error "No CONFIG_UARTn_SERIAL_CONSOLE Setting"
|
||||
#endif
|
||||
|
||||
/* Get word length setting for the console */
|
||||
|
||||
#if CONSOLE_BITS >= 5 && CONSOLE_BITS <= 8
|
||||
#define CONSOLE_LCR_WLS UART_LCR_WLEN(CONSOLE_BITS)
|
||||
#elif defined(HAVE_CONSOLE)
|
||||
#error "Invalid CONFIG_UARTn_BITS setting for console "
|
||||
#endif
|
||||
|
||||
/* Get parity setting for the console */
|
||||
|
||||
#if CONSOLE_PARITY == 0
|
||||
#define CONSOLE_LCR_PAR 0
|
||||
#elif CONSOLE_PARITY == 1
|
||||
#define CONSOLE_LCR_PAR (UART_LCR_PEN)
|
||||
#elif CONSOLE_PARITY == 2
|
||||
#define CONSOLE_LCR_PAR (UART_LCR_PEN | UART_LCR_EPS)
|
||||
#elif CONSOLE_PARITY == 3
|
||||
#define CONSOLE_LCR_PAR (UART_LCR_PEN | UART_LCR_SPS)
|
||||
#elif CONSOLE_PARITY == 4
|
||||
#define CONSOLE_LCR_PAR (UART_LCR_PEN | UART_LCR_EPS | UART_LCR_SPS)
|
||||
#elif defined(HAVE_CONSOLE)
|
||||
#error "Invalid CONFIG_UARTn_PARITY setting for CONSOLE"
|
||||
#endif
|
||||
|
||||
/* Get stop-bit setting for the console and UART0/1/2 */
|
||||
|
||||
#if CONSOLE_2STOP != 0
|
||||
#define CONSOLE_LCR_STOP UART_LCR_STP2
|
||||
#else
|
||||
#define CONSOLE_LCR_STOP 0
|
||||
#endif
|
||||
|
||||
/* LCR and FCR values for the console */
|
||||
|
||||
#define CONSOLE_LCR_VALUE (CONSOLE_LCR_WLS | CONSOLE_LCR_PAR | CONSOLE_LCR_STOP)
|
||||
|
||||
/****************************************************************************
|
||||
* Private Types
|
||||
****************************************************************************/
|
||||
|
||||
struct uartdev
|
||||
{
|
||||
uintptr_t uartbase; /* Base address of UART registers */
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* Private Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
static const struct uartdev g_uartdevs[] =
|
||||
{
|
||||
{
|
||||
CXD32_UART0_BASE
|
||||
},
|
||||
{
|
||||
CXD32_UART1_BASE
|
||||
},
|
||||
{
|
||||
CXD32_UART2_BASE
|
||||
}
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: arm_lowputc
|
||||
*
|
||||
* Description:
|
||||
* Output one byte on the serial console
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void arm_lowputc(char ch)
|
||||
{
|
||||
#if defined HAVE_UART && defined HAVE_CONSOLE
|
||||
/* Wait for the transmitter to be available */
|
||||
|
||||
while ((getreg32(CONSOLE_BASE + CXD32_UART_FR) & UART_FLAG_TXFF));
|
||||
|
||||
/* Send the character */
|
||||
|
||||
putreg32((uint32_t)ch, CONSOLE_BASE + CXD32_UART_DR);
|
||||
#endif
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: cxd32_lowsetup
|
||||
*
|
||||
* Description:
|
||||
* Called at the very beginning of _start. Performs low level
|
||||
* initialization of the serial console.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void cxd32_lowsetup(void)
|
||||
{
|
||||
#ifdef HAVE_UART
|
||||
/* Enable clocking and for all console UART and disable power for
|
||||
* other UARTs
|
||||
*/
|
||||
|
||||
/* Configure the console (only) */
|
||||
|
||||
#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
|
||||
{
|
||||
uint32_t val;
|
||||
val = getreg32(CONSOLE_BASE + CXD32_UART_CR);
|
||||
if (val & UART_CR_EN)
|
||||
{
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
#if defined(CONFIG_UART0_SERIAL_CONSOLE)
|
||||
cxd32_uart_setup(0);
|
||||
cxd32_uart_initialize(0);
|
||||
|
||||
putreg32(CONSOLE_LCR_VALUE, CONSOLE_BASE + CXD32_UART_LCR_H);
|
||||
cxd32_setbaud(CONSOLE_BASE, CONSOLE_BASEFREQ, CONSOLE_BAUD);
|
||||
putreg32(0, CONSOLE_BASE + CXD32_UART_IFLS);
|
||||
putreg32(UART_INTR_ALL, CONSOLE_BASE + CXD32_UART_ICR);
|
||||
#endif
|
||||
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: cxd32_uart_reset
|
||||
*
|
||||
* Description:
|
||||
* Reset a UART. This function is used by the serial driver when a
|
||||
* UART is closed.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void cxd32_uart_reset(int ch)
|
||||
{
|
||||
/* XXX: disabling uart controller */
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: cxd32_uart_setup
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void cxd32_uart_setup(int ch)
|
||||
{
|
||||
/* XXX: enabling uart contrller */
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: cxd32_uart_initialize
|
||||
*
|
||||
* Description:
|
||||
* Various initial registration
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void cxd32_uart_initialize(int ch)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
regval = 0x00000000;
|
||||
|
||||
/* disable Control register */
|
||||
|
||||
putreg32(regval, g_uartdevs[ch].uartbase + CXD32_UART_CR);
|
||||
|
||||
/* init IrDA low-power counter register */
|
||||
|
||||
putreg32(regval, g_uartdevs[ch].uartbase + CXD32_UART_ILPR);
|
||||
|
||||
/* init Integer baud rate register */
|
||||
|
||||
putreg32(regval, g_uartdevs[ch].uartbase + CXD32_UART_IBRD);
|
||||
|
||||
/* init Fractional baud rate register */
|
||||
|
||||
putreg32(regval, g_uartdevs[ch].uartbase + CXD32_UART_FBRD);
|
||||
|
||||
/* init DMA control register */
|
||||
|
||||
putreg32(regval, g_uartdevs[ch].uartbase + CXD32_UART_DMACR);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: cxd32_setbaud
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#define DIV_MASK 0x000000FF
|
||||
#define FBRD_MASK 0x3F
|
||||
|
||||
void cxd32_setbaud(uintptr_t uartbase, uint32_t basefreq, uint32_t baud)
|
||||
{
|
||||
uint64_t div;
|
||||
uint32_t ibrd;
|
||||
uint32_t fbrd;
|
||||
uint32_t lcr_h;
|
||||
|
||||
irqstate_t flags = spin_lock_irqsave(NULL);
|
||||
|
||||
div = (uint64_t)(basefreq);
|
||||
div *= (uint64_t)(256);
|
||||
div /= (uint64_t)(16);
|
||||
div /= (uint64_t)(baud);
|
||||
ibrd = (uint32_t)(div >> 8);
|
||||
fbrd = (uint32_t)(((div & DIV_MASK) * 64 + 0x80) / 256);
|
||||
|
||||
putreg32(ibrd + (fbrd >> 6), uartbase + CXD32_UART_IBRD);
|
||||
putreg32(fbrd & FBRD_MASK, uartbase + CXD32_UART_FBRD);
|
||||
|
||||
/* Baud rate is updated by writing to LCR_H. */
|
||||
|
||||
lcr_h = getreg32(uartbase + CXD32_UART_LCR_H);
|
||||
putreg32(lcr_h, uartbase + CXD32_UART_LCR_H);
|
||||
|
||||
spin_unlock_irqrestore(NULL, flags);
|
||||
}
|
||||
@@ -0,0 +1,122 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/cxd32xx/cxd32_uart.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_CXD32XX_CXD32_UART_H
|
||||
#define __ARCH_ARM_SRC_CXD32XX_CXD32_UART_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "chip.h"
|
||||
#include "hardware/cxd32_uart.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: cxd32_lowsetup
|
||||
*
|
||||
* Description:
|
||||
* Called at the very beginning of _start. Performs low level
|
||||
* initialization of the serial console.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void cxd32_lowsetup(void);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: cxd32_uart_reset
|
||||
*
|
||||
* Description:
|
||||
* Reset a UART. This function is used by the serial driver when a
|
||||
* UART is closed.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void cxd32_uart_reset(int ch);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: cxd32_uart_setup
|
||||
*
|
||||
* Description:
|
||||
* Configure the UART. This involves:
|
||||
*
|
||||
* 1. Connecting the input clock to the UART as specified in the
|
||||
* board.h file,
|
||||
* 2. Configuring the UART pins
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void cxd32_uart_setup(int);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: cxd32_setbaud
|
||||
*
|
||||
* Description:
|
||||
* Configure the UART divisors to accomplish the desired BAUD given the
|
||||
* UART base frequency.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void cxd32_setbaud(uintptr_t uartbase, uint32_t basefreq, uint32_t baud);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: cxd32_uart_initialize
|
||||
*
|
||||
* Description:
|
||||
* Various initial registration
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void cxd32_uart_initialize(int ch);
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_CXD32XX_CXD32_UART_H */
|
||||
@@ -0,0 +1,37 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/cxd32xx/hardware/cxd3277_clockfreq.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_CXD32XX_HARDWARE_CXD3277_CLOCKFREQ_H
|
||||
#define __ARCH_ARM_SRC_CXD32XX_HARDWARE_CXD3277_CLOCKFREQ_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#define CXD32_TIMER_BASEFREQ (8*1000*1000)
|
||||
#define CXD32_UART_BASEFREQ (32*1000*1000)
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_CXD32XX_HARDWARE_CXD3277_CLOCKFREQ_H */
|
||||
@@ -0,0 +1,46 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/cxd32xx/hardware/cxd3277_memorymap.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_CXD32XX_HARDWARE_CXD3277_MEMORYMAP_H
|
||||
#define __ARCH_ARM_SRC_CXD32XX_HARDWARE_CXD3277_MEMORYMAP_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#define CXD32_UART0_BASE (0x42100000+0x4000)
|
||||
#define CXD32_UART1_BASE (0x42100000+0x5000)
|
||||
#define CXD32_UART2_BASE (0x42100000+0x6000)
|
||||
|
||||
#define CXD32_TIMER0_BASE (0x42200000+0x2000)
|
||||
#define CXD32_TIMER1_BASE (0x42200000+0x3000)
|
||||
#define CXD32_TIMER2_BASE (0x42200000+0x4000)
|
||||
#define CXD32_TIMER3_BASE (0x42200000+0x5000)
|
||||
#define CXD32_TIMER4_BASE (0x42200000+0x6000)
|
||||
|
||||
#define CXD32_INTC_BASE 0xe0045000
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_CXD32XX_HARDWARE_CXD3277_MEMORYMAP_H */
|
||||
@@ -0,0 +1,100 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/cxd32xx/hardware/cxd32_timer.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_CXD32XX_HARDWARE_CXD32_TIMER_H
|
||||
#define __ARCH_ARM_SRC_CXD32XX_HARDWARE_CXD32_TIMER_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Register addresses */
|
||||
|
||||
#define CXD32_TIMER_LOAD (0x0000) /* Load register */
|
||||
#define CXD32_TIMER_VALUE (0x0004) /* Value register [RO] */
|
||||
#define CXD32_TIMER_CONTROL (0x0008) /* Control register */
|
||||
#define CXD32_TIMER_INTCLR (0x000C) /* Clear Interrupt register [WO] */
|
||||
#define CXD32_TIMER_RIS (0x0010) /* Raw Interrupt Status register [RO] */
|
||||
#define CXD32_TIMER_MIS (0x0014) /* Interrupt Status register [RO] */
|
||||
#define CXD32_TIMER_BGLOAD (0x0018) /* Backround Load register [RO] */
|
||||
#define CXD32_TIMER_ITCR (0x0F00) /* Integration Test Control register */
|
||||
#define CXD32_TIMER_ITOP (0x0F04) /* Integration Test Output register [WO] */
|
||||
#define CXD32_TIMER_PERIPHID0 (0x0FE0) /* Peripheral ID0 register [RO] */
|
||||
#define CXD32_TIMER_PERIPHID1 (0x0FE4) /* Peripheral ID1 register [RO] */
|
||||
#define CXD32_TIMER_PERIPHID2 (0x0FE8) /* Peripheral ID2 register [RO] */
|
||||
#define CXD32_TIMER_PERIPHID3 (0x0FFC) /* Peripheral ID3 register [RO] */
|
||||
#define CXD32_TIMER_PCELLID0 (0x0FF0) /* PrimeCell ID0 register [RO] */
|
||||
#define CXD32_TIMER_PCELLID1 (0x0FF4) /* PrimeCell ID1 register [RO] */
|
||||
#define CXD32_TIMER_PCELLID2 (0x0FF8) /* PrimeCell ID2 register [RO] */
|
||||
#define CXD32_TIMER_PCELLID3 (0x0FFC) /* PrimeCell ID3 register [RO] */
|
||||
|
||||
#define CXD32_TIMER_CH0_OFFSET (0x00000000)/* CHANNEL0 offset */
|
||||
#define CXD32_TIMER_CH1_OFFSET (0x00000020)/* CHANNEL1 offset */
|
||||
|
||||
/* Register bit definitions */
|
||||
|
||||
/* Control Register */
|
||||
|
||||
#define TIMERCTRL_ENABLE (0x1u << 7)
|
||||
#define TIMERCTRL_DISABLE (0x0u << 7)
|
||||
#define TIMERCTRL_PERIODIC (0x1u << 6)
|
||||
#define TIMERCTRL_FREERUN (0x0u << 6)
|
||||
#define TIMERCTRL_INTENABLE (0x1u << 5)
|
||||
#define TIMERCTRL_INTDISABLE (0x0u << 5)
|
||||
#define TIMERCTRL_DIV_256 (0x2u << 2)
|
||||
#define TIMERCTRL_DIV_16 (0x1u << 2)
|
||||
#define TIMERCTRL_DIV_1 (0x0u << 2)
|
||||
#define TIMERCTRL_SIZE_32BIT (0x1u << 1)
|
||||
#define TIMERCTRL_SIZE_16BIT (0x0u << 1)
|
||||
#define TIMERCTRL_MODE_ONESHOT (0x1u << 0)
|
||||
#define TIMERCTRL_MODE_WRAP (0x0u << 0)
|
||||
|
||||
/* Interrupt Register */
|
||||
|
||||
#define TIMER_INTERRUPT (0x1u << 0)
|
||||
|
||||
/* Integration Test Control register */
|
||||
|
||||
#define TIMERITCR_ENABLE (0x1u << 0)
|
||||
|
||||
/* Integration Test Output register */
|
||||
|
||||
#define TIMERITOP_TIMINT1 (0x1u << 0)
|
||||
#define TIMERITOP_TIMINT2 (0x1u << 1)
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_CXD32XX_HARDWARE_CXD32_TIMER_H */
|
||||
@@ -0,0 +1,119 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/cxd32xx/hardware/cxd32_uart.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_CXD32XX_HARDWARE_CXD32_UART_H
|
||||
#define __ARCH_ARM_SRC_CXD32XX_HARDWARE_CXD32_UART_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Register offsets *********************************************************/
|
||||
|
||||
/* Common Register Offsets */
|
||||
|
||||
#define CXD32_UART_DR 0x000 /* Data register */
|
||||
#define CXD32_UART_RSR_ECR 0x004 /* Receive status/error clear register */
|
||||
#define CXD32_UART_FR 0x018 /* Flag register */
|
||||
#define CXD32_UART_ILPR 0x020 /* IrDA low-power counter register */
|
||||
#define CXD32_UART_IBRD 0x024 /* Integer baud rate register */
|
||||
#define CXD32_UART_FBRD 0x028 /* Fractional baud rate register */
|
||||
#define CXD32_UART_LCR_H 0x02c /* Line control register */
|
||||
#define CXD32_UART_CR 0x030 /* Control register */
|
||||
#define CXD32_UART_IFLS 0x034 /* Interrupt FIFO level select register */
|
||||
#define CXD32_UART_IMSC 0x038 /* Interrupt mask set/clear register */
|
||||
#define CXD32_UART_RIS 0x03c /* Raw Interrupt status register */
|
||||
#define CXD32_UART_MIS 0x040 /* Masked interrupt status register */
|
||||
#define CXD32_UART_ICR 0x044 /* Interrupt clear register */
|
||||
#define CXD32_UART_DMACR 0x048 /* DMA control register */
|
||||
|
||||
#define UART_FR_RI (0x1 << 8)
|
||||
#define UART_FR_TXFE (0x1 << 7)
|
||||
#define UART_FR_RXFF (0x1 << 6)
|
||||
#define UART_FR_TXFF (0x1 << 5)
|
||||
#define UART_FR_RXFE (0x1 << 4)
|
||||
#define UART_FR_BUSY (0x1 << 3)
|
||||
#define UART_FR_DCD (0x1 << 2)
|
||||
#define UART_FR_DSR (0x1 << 1)
|
||||
#define UART_FR_CTS (0x1 << 0)
|
||||
|
||||
#define UART_LCR_SPS (1u << 7)
|
||||
#define UART_LCR_WLEN(x) ((((x)-5)&3)<<5)
|
||||
#define UART_LCR_FEN (1u << 4)
|
||||
#define UART_LCR_STP2 (1u << 3)
|
||||
#define UART_LCR_EPS (1u << 2)
|
||||
#define UART_LCR_PEN (1u << 1)
|
||||
#define UART_LCR_BRK (1u << 0)
|
||||
|
||||
#define UART_CR_CTSEN (1u << 15)
|
||||
#define UART_CR_RTSEN (1u << 14)
|
||||
#define UART_CR_OUT2 (1u << 13)
|
||||
#define UART_CR_OUT1 (1u << 12)
|
||||
#define UART_CR_RTS (1u << 11)
|
||||
#define UART_CR_DTR (1u << 10)
|
||||
#define UART_CR_RXE (1u << 9)
|
||||
#define UART_CR_TXE (1u << 8)
|
||||
#define UART_CR_LBE (1u << 7)
|
||||
#define UART_CR_SIRLP (1u << 2)
|
||||
#define UART_CR_SIREN (1u << 1)
|
||||
#define UART_CR_EN (1u << 0)
|
||||
|
||||
#define UART_INTR_RI (1u << 0) /* nUARTRI modem interrupt */
|
||||
#define UART_INTR_CTS (1u << 1) /* nUARTCTS modem interrupt */
|
||||
#define UART_INTR_DCD (1u << 2) /* nUARTDCD modem interrupt */
|
||||
#define UART_INTR_DSR (1u << 3) /* nUARTDSR modem interrupt */
|
||||
#define UART_INTR_RX (1u << 4) /* Receive interrupt */
|
||||
#define UART_INTR_TX (1u << 5) /* Transmit interrupt */
|
||||
#define UART_INTR_RT (1u << 6) /* Receive timeout interrupt */
|
||||
#define UART_INTR_FE (1u << 7) /* Framing error interrupt */
|
||||
#define UART_INTR_PE (1u << 8) /* Parity error interrupt */
|
||||
#define UART_INTR_BE (1u << 9) /* Break error interrupt */
|
||||
#define UART_INTR_OE (1u << 10) /* Overrun error interrupt */
|
||||
#define UART_INTR_ALL (0x7ff) /* All of interrupts */
|
||||
|
||||
#define UART_FLAG_RI (1u << 8) /* Ring indicator */
|
||||
#define UART_FLAG_TXFE (1u << 7) /* Transmit FIFO empty */
|
||||
#define UART_FLAG_RXFF (1u << 6) /* Receive FIFO full */
|
||||
#define UART_FLAG_TXFF (1u << 5) /* Transmit FIFO full */
|
||||
#define UART_FLAG_RXFE (1u << 4) /* Receive FIFO empty */
|
||||
#define UART_FLAG_BUSY (1u << 3) /* UART busy */
|
||||
#define UART_FLAG_DCD (1u << 2) /* Data carrier detect */
|
||||
#define UART_FLAG_DSR (1u << 1) /* Data set ready */
|
||||
#define UART_FLAG_CTS (1u << 0) /* Cleart to send */
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_CXD32XX_HARDWARE_CXD32_UART_H */
|
||||
Reference in New Issue
Block a user