From 141dc1e3e760c3795bf445d22bc9b8d351ef5fb9 Mon Sep 17 00:00:00 2001 From: Marco Casaroli Date: Sun, 8 Oct 2023 16:04:04 +0000 Subject: [PATCH] fix(esp32s3_i2c): set regs order It looks like we need to set this bit before the UPGATE, like we do on the esp32c3 port. --- arch/xtensa/src/esp32s3/esp32s3_i2c.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/xtensa/src/esp32s3/esp32s3_i2c.c b/arch/xtensa/src/esp32s3/esp32s3_i2c.c index 935623960e0..2ee06f2c71e 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_i2c.c +++ b/arch/xtensa/src/esp32s3/esp32s3_i2c.c @@ -1125,9 +1125,9 @@ static void i2c_clear_bus(struct esp32s3_i2c_priv_s *priv) I2C_SCL_RST_SLV_EN | I2C_SCL_RST_SLV_NUM_M, VALUE_TO_FIELD(I2C_SCL_CYC_NUM_DEF, I2C_SCL_RST_SLV_NUM)); - modifyreg32(I2C_CTR_REG(priv->id), 0, I2C_CONF_UPGATE); - modifyreg32(I2C_SCL_SP_CONF_REG(priv->id), 0, I2C_SCL_RST_SLV_EN); + + modifyreg32(I2C_CTR_REG(priv->id), 0, I2C_CONF_UPGATE); } /****************************************************************************