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Add more nops after enabling MMU for Cortex-A8

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This commit is contained in:
Gregory Nutt
2014-01-07 08:38:00 -06:00
parent 9d393e167c
commit 126bec4e55
3 changed files with 10 additions and 17 deletions
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ChangeLog
+3
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@@ -6378,4 +6378,7 @@
problems for assembly language. How to prevent the integer over- problems for assembly language. How to prevent the integer over-
flow warnings? (2014-1-6). flow warnings? (2014-1-6).
* arch/arm/src/a1x/a1x_serial.c: Handle BUSY interrupt (2014-1-6). * arch/arm/src/a1x/a1x_serial.c: Handle BUSY interrupt (2014-1-6).
* arch/arm/src/armv7-a/arm_head.S and arm_pghead.S: Add more nop's
after enabling the MMU. The cortex-a8 seems to need these
(2014-1-7).
arch/arm/src/armv7-a/arm_head.S
+3 -8
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@@ -505,14 +505,9 @@ __start:
/* Then write the configured control register */ /* Then write the configured control register */
mcr CP15_SCTLR(r0) /* Write control reg */ mcr CP15_SCTLR(r0) /* Write control reg */
.rept 12 /* Cortex A8 wants lots of NOPs here */
/* Read the Main ID register. This will be available in R1 after nop
* MMU trampoline (not currently used) .endr
*/
mrc CP15_MIDR(r1) /* Read main id reg */
mov r1, r1 /* Null-avoiding nop */
mov r1, r1 /* Null-avoiding nop */
/* And "jump" to .Lvstart in the newly mapped virtual address space */ /* And "jump" to .Lvstart in the newly mapped virtual address space */
arch/arm/src/armv7-a/arm_pghead.S
+4 -9
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@@ -1,7 +1,7 @@
/**************************************************************************** /****************************************************************************
* arch/arm/src/armv7-a/arm_pghead.S * arch/arm/src/armv7-a/arm_pghead.S
* *
* Copyright (C) 2013 Gregory Nutt. All rights reserved. * Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org> * Author: Gregory Nutt <gnutt@nuttx.org>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
@@ -491,14 +491,9 @@ __start:
/* Then write the configured control register */ /* Then write the configured control register */
mcr CP15_SCTLR(r0) /* Write control reg */ mcr CP15_SCTLR(r0) /* Write control reg */
.rept 12 /* Cortex A8 wants lots of NOPs here */
/* Read the Main ID register. This will be available in R1 after nop
* MMU trampoline (not currently used) .endr
*/
mrc CP15_MIDR(r1) /* Read main id reg */
mov r1, r1 /* Null-avoiding nop */
mov r1, r1 /* Null-avoiding nop */
/* And "jump" to .Lvstart in the newly mapped virtual address space */ /* And "jump" to .Lvstart in the newly mapped virtual address space */