diff --git a/boards/xtensa/esp32s2/common/Kconfig b/boards/xtensa/esp32s2/common/Kconfig new file mode 100644 index 00000000000..d09a076ca0e --- /dev/null +++ b/boards/xtensa/esp32s2/common/Kconfig @@ -0,0 +1,10 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# +config ESP32S2_QEMU_IMAGE + bool "ESP32S2 binary image for QEMU" + default n + ---help--- + Create a binary flash image used for QEMU. + diff --git a/boards/xtensa/esp32s2/common/Makefile b/boards/xtensa/esp32s2/common/Makefile new file mode 100644 index 00000000000..fa894b6eb7e --- /dev/null +++ b/boards/xtensa/esp32s2/common/Makefile @@ -0,0 +1,33 @@ +############################################################################# +# boards/xtensa/esp32s2/common/Makefile +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################# + +include $(TOPDIR)/Make.defs + +include board/Make.defs +include src/Make.defs + +DEPPATH += --dep-path board +DEPPATH += --dep-path src + +include $(TOPDIR)/boards/Board.mk + +ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src +BOARDDIR = $(ARCHSRCDIR)$(DELIM)board +CFLAGS += $(shell $(INCDIR) "$(CC)" $(BOARDDIR)$(DELIM)include) diff --git a/boards/xtensa/esp32s2/common/src/Make.defs b/boards/xtensa/esp32s2/common/src/Make.defs new file mode 100644 index 00000000000..e0193190688 --- /dev/null +++ b/boards/xtensa/esp32s2/common/src/Make.defs @@ -0,0 +1,23 @@ +############################################################################# +# boards/xtensa/esp32s2/common/src/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################# + +DEPPATH += --dep-path src +VPATH += :src +CFLAGS += $(shell $(INCDIR) "$(CC)" $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)src) diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/Kconfig b/boards/xtensa/esp32s2/esp32s2-saola-1/Kconfig new file mode 100644 index 00000000000..58cf2191c8f --- /dev/null +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/Kconfig @@ -0,0 +1,8 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_BOARD_ESP32S2_SAOLA_1 + +endif # ARCH_BOARD_ESP32S2_SAOLA_1 diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/defconfig b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/defconfig new file mode 100644 index 00000000000..a2d412c59fd --- /dev/null +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/defconfig @@ -0,0 +1,47 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_LEDS is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_CMDPARMS is not set +CONFIG_ARCH="xtensa" +CONFIG_ARCH_BOARD="esp32s2-saola-1" +CONFIG_ARCH_BOARD_ESP32S2_SAOLA_1=y +CONFIG_ARCH_CHIP="esp32s2" +CONFIG_ARCH_CHIP_ESP32S2=y +CONFIG_ARCH_CHIP_ESP32S2WROVER=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH_XTENSA=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_ESP32S2_DATA_CACHE_0KB=y +CONFIG_ESP32S2_UART0=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=3072 +CONFIG_INTELHEX_BINARY=y +CONFIG_MAX_TASKS=16 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/nsh/defconfig b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/nsh/defconfig new file mode 100644 index 00000000000..a2d412c59fd --- /dev/null +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/nsh/defconfig @@ -0,0 +1,47 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_LEDS is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_CMDPARMS is not set +CONFIG_ARCH="xtensa" +CONFIG_ARCH_BOARD="esp32s2-saola-1" +CONFIG_ARCH_BOARD_ESP32S2_SAOLA_1=y +CONFIG_ARCH_CHIP="esp32s2" +CONFIG_ARCH_CHIP_ESP32S2=y +CONFIG_ARCH_CHIP_ESP32S2WROVER=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH_XTENSA=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_ESP32S2_DATA_CACHE_0KB=y +CONFIG_ESP32S2_UART0=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=3072 +CONFIG_INTELHEX_BINARY=y +CONFIG_MAX_TASKS=16 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/include/board.h b/boards/xtensa/esp32s2/esp32s2-saola-1/include/board.h new file mode 100644 index 00000000000..be5ecb0cdbf --- /dev/null +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/include/board.h @@ -0,0 +1,81 @@ +/**************************************************************************** + * boards/xtensa/esp32s2/esp32s2-saola-1/include/board.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_XTENSA_ESP32S2_ESP32S2_CORE_INCLUDE_BOARD_H +#define __BOARDS_XTENSA_ESP32S2_ESP32S2_CORE_INCLUDE_BOARD_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* The ESP32S2 board V2 is fitted with a 40MHz crystal */ + +#define BOARD_XTAL_FREQUENCY 40000000 + +/* Clock reconfiguration is currently disabled, so the CPU will be running + * at the XTAL frequency or at two times the XTAL frequency, depending upon + * how we load the code: + * + * - If we load the code into FLASH at address 0x1000 where it is started by + * the second level bootloader, then the frequency is the crystal + * frequency. + * - If we load the code into IRAM after the second level bootloader has run + * this frequency will be twice the crystal frequency. + * + * Don't ask me for an explanation. + */ + +/* Note: The bootloader (esp-idf bootloader.bin) configures: + * + * - CPU frequency to 80MHz + * - The XTAL frequency according to the SDK config CONFIG_ESP32S2_XTAL_FREQ, + * which is 40MHz by default. + * + * Reference: + * https://github.com/espressif/esp-idf/blob + * /6fd855ab8d00d23bad4660216bc2122c2285d5be/components + * /bootloader_support/src/bootloader_clock.c#L38-L62 + */ + +#ifdef CONFIG_ESP32S2_RUN_IRAM +# define BOARD_CLOCK_FREQUENCY (2 * BOARD_XTAL_FREQUENCY) +#else +#ifdef CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ +# define BOARD_CLOCK_FREQUENCY (CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ * 1000000) +#else +# define BOARD_CLOCK_FREQUENCY 80000000 +#endif +#endif + +/* LED definitions **********************************************************/ + +/* Define how many LEDs this board has (needed by userleds) */ + +#define BOARD_NLEDS 1 + +/* GPIO pins used by the GPIO Subsystem */ + +#define BOARD_NGPIOOUT 1 /* Amount of GPIO Output pins */ +#define BOARD_NGPIOIN 1 /* Amount of GPIO Input without Interruption */ +#define BOARD_NGPIOINT 1 /* Amount of GPIO Input w/ Interruption pins */ + +#endif /* __BOARDS_XTENSA_ESP32S2_ESP32S2_CORE_INCLUDE_BOARD_H */ diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/scripts/Make.defs b/boards/xtensa/esp32s2/esp32s2-saola-1/scripts/Make.defs new file mode 100644 index 00000000000..df80445414c --- /dev/null +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/scripts/Make.defs @@ -0,0 +1,109 @@ +############################################################################ +# boards/xtensa/esp32s2/esp32s2-devkitc/scripts/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/tools/esp32s2/Config.mk +include $(TOPDIR)/arch/xtensa/src/lx7/Toolchain.defs + +LDSCRIPT1 = $(BOARD_DIR)$(DELIM)scripts$(DELIM)esp32s2_out.ld +LDSCRIPT3 = $(BOARD_DIR)$(DELIM)scripts$(DELIM)esp32s2_rom.ld +LDSCRIPT4 = $(BOARD_DIR)$(DELIM)scripts$(DELIM)esp32s2_peripherals.ld + +ifeq ($(CONFIG_ESP32S2_RUN_IRAM),y) + LDSCRIPT2 = $(BOARD_DIR)$(DELIM)scripts$(DELIM)esp32s2_iram.ld +else + LDSCRIPT2 = $(BOARD_DIR)$(DELIM)scripts$(DELIM)esp32s2_flash.ld +endif + +ifeq ($(CONFIG_CYGWIN_WINTOOL),y) + ARCHSCRIPT = -T "${shell cygpath -w $(LDSCRIPT1)}" + ARCHSCRIPT += -T "${shell cygpath -w $(LDSCRIPT2)}" + ARCHSCRIPT += -T "${shell cygpath -w $(LDSCRIPT3)}" + ARCHSCRIPT += -T "${shell cygpath -w $(LDSCRIPT4)}" +else + ARCHSCRIPT = -T$(LDSCRIPT1) -T$(LDSCRIPT2) -T$(LDSCRIPT3) -T$(LDSCRIPT4) +endif + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin -ffunction-sections -fdata-sections -fstrict-volatile-bitfields -mlongcalls +ARCHCXXFLAGS = $(ARCHCFLAGS) -fno-exceptions -fcheck-new -fno-rtti +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHPICFLAGS = -fpic + +# if SPIRAM/PSRAM is used then we need to include a workaround + +ifeq ($(CONFIG_ESP32S2_SPIRAM),y) + ARCHCFLAGS += -mfix-esp32s2-psram-cache-issue +endif + +CFLAGS := $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +# Loadable module definitions + +CMODULEFLAGS = $(CFLAGS) -mtext-section-literals + +LDMODULEFLAGS = -r -e module_initialize +ifeq ($(CONFIG_CYGWIN_WINTOOL),y) + LDMODULEFLAGS += -T "${shell cygpath -w $(TOPDIR)/libs/libc/modlib/gnu-elf.ld}" +else + LDMODULEFLAGS += -T $(TOPDIR)/libs/libc/modlib/gnu-elf.ld +endif + +# ELF module definitions + +CELFFLAGS = $(CFLAGS) -mtext-section-literals +CXXELFFLAGS = $(CXXFLAGS) -mtext-section-literals + +LDELFFLAGS = -r -e main +ifeq ($(CONFIG_CYGWIN_WINTOOL),y) + LDELFFLAGS += -T "${shell cygpath -w $(BOARD_DIR)$(DELIM)scripts$(DELIM)gnu-elf.ld}" +else + LDELFFLAGS += -T $(BOARD_DIR)$(DELIM)scripts$(DELIM)gnu-elf.ld +endif + +LDFLAGS += -nostartfiles -nodefaultlibs + +ifeq ($(CONFIG_CYGWIN_WINTOOL),y) + LDFLAGS += -Map="${shell cygpath -w $(TOPDIR)/nuttx.map}" --cref +else + LDFLAGS += -Map=$(TOPDIR)/nuttx.map --cref +endif + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/scripts/esp32s2.template.ld b/boards/xtensa/esp32s2/esp32s2-saola-1/scripts/esp32s2.template.ld new file mode 100644 index 00000000000..e57fbe8f8d5 --- /dev/null +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/scripts/esp32s2.template.ld @@ -0,0 +1,108 @@ +/**************************************************************************** + * boards/xtensa/esp32s2/esp32s2-saola-1/scripts/esp32s2.template.ld + * ESP32S2 Linker Script Memory Layout + * + * This file describes the memory layout (memory blocks) as virtual + * memory addresses. + * + * esp32s2.common.ld contains output sections to link compiler output + * into these memory blocks. + * + * NOTE: That this is not the actual linker script but rather a "template" + * for the elf32_out.ld script. This template script is passed through + * the C preprocessor to include selected configuration options. + * + ****************************************************************************/ + +#include + +#ifdef CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB +# define CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE 0x2000 +#else +# define CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE 0x4000 +#endif + +#ifdef CONFIG_ESP32S2_DATA_CACHE_0KB +# define CONFIG_ESP32S2_DATA_CACHE_SIZE 0 +#elif defined CONFIG_ESP32S2_DATA_CACHE_8KB +# define CONFIG_ESP32S2_DATA_CACHE_SIZE 0x2000 +#else +# define CONFIG_ESP32S2_DATA_CACHE_SIZE 0x4000 +#endif + +#define RAM_IRAM_START 0x40020000 +#define RAM_DRAM_START 0x3FFB0000 + +#define DATA_RAM_END 0x3FFE0000 /* 2nd stage bootloader iram_loader_seg + * starts at SRAM block 14 (reclaimed + * after app boots) + */ + +#define IRAM_ORG (RAM_IRAM_START + CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE \ + + CONFIG_ESP32S2_DATA_CACHE_SIZE) + +#define DRAM_ORG (RAM_DRAM_START + CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE \ + + CONFIG_ESP32S2_DATA_CACHE_SIZE) + +#define I_D_RAM_SIZE DATA_RAM_END - DRAM_ORG + +#define STATIC_RAM_SIZE 0 /* FIXME: Should it be configurable? */ + +MEMORY +{ + /* All these values assume the flash cache is on, and have the blocks this + * uses subtracted from the length of the various regions. The 'data access + * port' dram/drom regions map to the same iram/irom regions but are + * connected to the data port of the CPU and eg allow bytewise access. + */ + + /* IRAM for CPU */ + + iram0_0_seg (RX) : org = IRAM_ORG, len = I_D_RAM_SIZE + + /* Even though the segment name is iram, it is actually mapped to flash */ + + iram0_2_seg (RX) : org = 0x40080020, len = 0x780000-0x20 + + /* (0x20 offset above is a convenience for the app binary image generation. + * Flash cache has 64KB pages. The .bin file which is flashed to the chip + * has a 0x18 byte file header, and each segment has a 0x08 byte segment + * header. Setting this offset makes it simple to meet the flash cache MMU's + * constraint that (paddr % 64KB == vaddr % 64KB).) + */ + + /* Shared data RAM, excluding memory reserved for bootloader and ROM + * bss/data/stack. + */ + + dram0_0_seg (RW) : org = DRAM_ORG, len = I_D_RAM_SIZE - \ + STATIC_RAM_SIZE + + /* Flash mapped constant data */ + + drom0_0_seg (R) : org = 0x3f000020, len = 0x3f0000-0x20 + + /* RTC fast memory (executable). Persists over deep sleep. */ + + rtc_iram_seg(RWX) : org = 0x40070000, len = 0x2000 + + /* RTC slow memory (data accessible). Persists over deep sleep. + * Start of RTC slow memory is reserved for ULP co-processor code + data, + * if enabled. + */ + + rtc_slow_seg(RW) : org = 0x50000000 + CONFIG_ESP32S2_ULP_COPROC_RESERVE_MEM, + len = 0x2000 - CONFIG_ESP32S2_ULP_COPROC_RESERVE_MEM + + /* External memory, including data and text */ + + extmem_seg(RWX) : org = 0x3f800000, len = 0x400000 +} + +/* Heap ends at top of dram0_0_seg */ + +_eheap = 0x40000000 - CONFIG_ESP32S2_TRACEMEM_RESERVE_DRAM; + +/* Module text area ends at top of dram0_0_seg */ + +_emodtext = 0x400a0000; diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/scripts/esp32s2_flash.ld b/boards/xtensa/esp32s2/esp32s2-saola-1/scripts/esp32s2_flash.ld new file mode 100644 index 00000000000..cdbb67b43eb --- /dev/null +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/scripts/esp32s2_flash.ld @@ -0,0 +1,223 @@ +/**************************************************************************** + * boards/xtensa/esp32s2/esp32s2-saola-1/scripts/esp32s2_flash.ld + ****************************************************************************/ + +/* Default entry point: */ + +ENTRY(__start); + +SECTIONS +{ + /* Send .iram0 code to iram */ + + .iram0.vectors : + { + _iram_start = ABSOLUTE(.); + + /* Vectors go to IRAM */ + + _init_start = ABSOLUTE(.); + + /* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */ + + . = 0x0; + KEEP (*(.window_vectors.text)); + . = 0x180; + KEEP (*(.xtensa_level2_vector.text)); + . = 0x1c0; + KEEP (*(.xtensa_level3_vector.text)); + . = 0x200; + KEEP (*(.xtensa_level4_vector.text)); + . = 0x240; + KEEP (*(.xtensa_level5_vector.text)); + . = 0x280; + KEEP (*(.debug_exception_vector.text)); + . = 0x2c0; + KEEP (*(.nmi_vector.text)); + . = 0x300; + KEEP (*(.kernel_exception_vector.text)); + . = 0x340; + KEEP (*(.user_exception_vector.text)); + . = 0x3c0; + KEEP (*(.double_exception_vector.text)); + . = 0x400; + *(.*_vector.literal) + + . = ALIGN (16); + *(.entry.text) + *(.init.literal) + *(.init) + _init_end = ABSOLUTE(.); + } > iram0_0_seg + + .iram0.text : + { + /* Code marked as running out of IRAM */ + + _iram_text_start = ABSOLUTE(.); + *(.iram1 .iram1.*) + *librtc.a:(.literal .text .literal.* .text.*) + *libarch.a:esp32s2_spiflash.*(.literal .text .literal.* .text.*) + *(.wifirxiram .wifirxiram.*) + *(.wifi0iram .wifi0iram.*) + _iram_text_end = ABSOLUTE(.); + + /* Module text area starts at the end of iram0_0_seg */ + + _smodtext = ABSOLUTE(.); + _iram_text = ABSOLUTE(.); + } > iram0_0_seg + + .dram0_reserved_for_iram (NOLOAD): + { + . = ORIGIN(dram0_0_seg) + _iram_text - _iram_start; + } > dram0_0_seg + + /* Shared RAM */ + + .dram0.bss (NOLOAD) : + { + /* .bss initialized on power-up */ + + . = ALIGN (8); + _sbss = ABSOLUTE(.); + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + *(.dynbss) + KEEP (*(.bss)) + *(.bss.*) + *(.share.mem) + *(.gnu.linkonce.b.*) + *(COMMON) + *libarch.a:esp32s2_spiflash.*(.bss .bss.* COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } >dram0_0_seg + + .noinit (NOLOAD): + { + /* This section contains data that is not initialized during load, + * or during the application's initialization sequence. + */ + + *(.noinit) + } >dram0_0_seg + + .dram0.data : + { + /* .data initialized on power-up in ROMed configurations. */ + + _sdata = ABSOLUTE(.); + KEEP (*(.data)) + KEEP (*(.data.*)) + KEEP (*(.gnu.linkonce.d.*)) + KEEP (*(.data1)) + KEEP (*(.sdata)) + KEEP (*(.sdata.*)) + KEEP (*(.gnu.linkonce.s.*)) + KEEP (*(.sdata2)) + KEEP (*(.sdata2.*)) + KEEP (*(.gnu.linkonce.s2.*)) + KEEP (*(.jcr)) + *(.dram1 .dram1.*) + *libphy.a:(.rodata .rodata.*) + *libarch.a:esp32s2_spiflash.*(.rodata .rodata.*) + . = ALIGN(4); + _edata = ABSOLUTE(.); + + /* Heap starts at the end of .data */ + + _sheap = ABSOLUTE(.); + } >dram0_0_seg + + /* External memory bss, from any global variable with EXT_RAM_ATTR attribute */ + + .extmem.bss (NOLOAD) : + { + _sbss_extmem = ABSOLUTE(.); + *(.extmem.bss .extmem.bss.*) + . = ALIGN(4); + _ebss_extmem = ABSOLUTE(.); + } > extmem_seg + + .flash.rodata : + { + _srodata = ABSOLUTE(.); + *(.rodata) + *(.rodata.*) + *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.gnu.linkonce.r.*) + *(.rodata1) + __XT_EXCEPTION_TABLE_ = ABSOLUTE(.); + *(.xt_except_table) + *(.gcc_except_table) + *(.gcc_except_table.*) + *(.gnu.linkonce.e.*) + *(.gnu.version_r) + *(.eh_frame) + + . = (. + 3) & ~ 3; + + /* C++ constructor and destructor tables, properly ordered: */ + + _sinit = ABSOLUTE(.); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + _einit = ABSOLUTE(.); + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + + /* C++ exception handlers table: */ + + __XT_EXCEPTION_DESCS_ = ABSOLUTE(.); + *(.xt_except_desc) + *(.gnu.linkonce.h.*) + __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); + *(.xt_except_desc_end) + *(.dynamic) + *(.gnu.version_d) + _erodata = ABSOLUTE(.); + /* Literals are also RO data. */ + _lit4_start = ABSOLUTE(.); + *(*.lit4) + *(.lit4.*) + *(.gnu.linkonce.lit4.*) + _lit4_end = ABSOLUTE(.); + . = ALIGN(4); + } >drom0_0_seg + + .flash.text : + { + _stext = .; + _text_start = ABSOLUTE(.); + *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) + *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.fini.literal) + *(.fini) + *(.gnu.version) + _text_end = ABSOLUTE(.); + _etext = .; + } >iram0_2_seg + + .rtc.text : + { + . = ALIGN(4); + *(.rtc.literal .rtc.text) + } >rtc_iram_seg + + .rtc.data : + { + *(.rtc.data) + *(.rtc.rodata) + } > rtc_slow_seg +} diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/scripts/esp32s2_iram.ld b/boards/xtensa/esp32s2/esp32s2-saola-1/scripts/esp32s2_iram.ld new file mode 100644 index 00000000000..024150cd69c --- /dev/null +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/scripts/esp32s2_iram.ld @@ -0,0 +1,190 @@ +/**************************************************************************** + * boards/xtensa/esp32s2/esp32s2-saola-1/scripts/esp32s2s2_iram.ld + ****************************************************************************/ + +/* Default entry point: */ + +ENTRY(__start); + +SECTIONS +{ + /* Send .iram0 code to iram */ + + .iram0.vectors : + { + /* Vectors go to IRAM */ + + _init_start = ABSOLUTE(.); + + /* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */ + + . = 0x0; + KEEP (*(.window_vectors.text)); + . = 0x180; + KEEP (*(.xtensa_level2_vector.text)); + . = 0x1c0; + KEEP (*(.xtensa_level3_vector.text)); + . = 0x200; + KEEP (*(.xtensa_level4_vector.text)); + . = 0x240; + KEEP (*(.xtensa_level5_vector.text)); + . = 0x280; + KEEP (*(.debug_exception_vector.text)); + . = 0x2c0; + KEEP (*(.nmi_vector.text)); + . = 0x300; + KEEP (*(.kernel_exception_vector.text)); + . = 0x340; + KEEP (*(.user_exception_vector.text)); + . = 0x3c0; + KEEP (*(.double_exception_vector.text)); + . = 0x400; + *(.*_vector.literal) + + . = ALIGN (16); + *(.entry.text) + *(.init.literal) + *(.init) + _init_end = ABSOLUTE(.); + } > iram0_0_seg + + .iram0.text : + { + /* Code marked as running out of IRAM */ + + _iram_text_start = ABSOLUTE(.); + *(.iram1 .iram1.*) + *libphy.a:(.literal .text .literal.* .text.*) + *librtc.a:(.literal .text .literal.* .text.*) + *libpp.a:(.literal .text .literal.* .text.*) + *libhal.a:(.literal .text .literal.* .text.*) + _iram_text_end = ABSOLUTE(.); + + _stext = .; + _text_start = ABSOLUTE(.); + *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) + *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.fini.literal) + *(.fini) + *(.gnu.version) + _text_end = ABSOLUTE(.); + _etext = .; + + /* Module text area starts at the end of iram0_0_seg */ + + _smodtext = ABSOLUTE(.); + } > iram0_0_seg + + /* Shared RAM */ + + .dram0.bss (NOLOAD) : + { + /* .bss initialized on power-up */ + + . = ALIGN (8); + _sbss = ABSOLUTE(.); + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + *(.dynbss) + KEEP (*(.bss)) + *(.bss.*) + *(.share.mem) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + + /* Uninitialized .bss */ + + *(.noinit) + } >dram0_0_seg + + .dram0.data : + { + /* .data initialized on power-up in ROMed configurations. */ + + _sdata = ABSOLUTE(.); + KEEP (*(.data)) + KEEP (*(.data.*)) + KEEP (*(.gnu.linkonce.d.*)) + KEEP (*(.data1)) + KEEP (*(.sdata)) + KEEP (*(.sdata.*)) + KEEP (*(.gnu.linkonce.s.*)) + KEEP (*(.sdata2)) + KEEP (*(.sdata2.*)) + KEEP (*(.gnu.linkonce.s2.*)) + KEEP (*(.jcr)) + *(.dram1 .dram1.*) + . = ALIGN(4); + _edata = ABSOLUTE(.); + + _srodata = ABSOLUTE(.); + *(.rodata) + *(.rodata.*) + *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.gnu.linkonce.r.*) + *(.rodata1) + __XT_EXCEPTION_TABLE_ = ABSOLUTE(.); + *(.xt_except_table) + *(.gcc_except_table) + *(.gnu.linkonce.e.*) + *(.gnu.version_r) + *(.eh_frame) + + . = (. + 3) & ~ 3; + + /* C++ constructor and destructor tables, properly ordered: */ + + _sinit = ABSOLUTE(.); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + _einit = ABSOLUTE(.); + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + + /* C++ exception handlers table: */ + + __XT_EXCEPTION_DESCS_ = ABSOLUTE(.); + *(.xt_except_desc) + *(.gnu.linkonce.h.*) + __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); + *(.xt_except_desc_end) + *(.dynamic) + *(.gnu.version_d) + _erodata = ABSOLUTE(.); + /* Literals are also RO data. */ + _lit4_start = ABSOLUTE(.); + *(*.lit4) + *(.lit4.*) + *(.gnu.linkonce.lit4.*) + _lit4_end = ABSOLUTE(.); + . = ALIGN(4); + + /* Heap starts at the end of .data */ + + _sheap = ABSOLUTE(.); + } >dram0_0_seg + + .rtc.text : + { + . = ALIGN(4); + *(.rtc.literal .rtc.text) + } >rtc_iram_seg + + .rtc.data : + { + *(.rtc.data) + *(.rtc.rodata) + } > rtc_slow_seg +} diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/scripts/esp32s2_peripherals.ld b/boards/xtensa/esp32s2/esp32s2-saola-1/scripts/esp32s2_peripherals.ld new file mode 100644 index 00000000000..62f5f970cb3 --- /dev/null +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/scripts/esp32s2_peripherals.ld @@ -0,0 +1,36 @@ +/**************************************************************************** + * boards/xtensa/esp32s2/esp32s2-saola-1/scripts/esp32s2_peripherals.ld + ****************************************************************************/ + +PROVIDE ( UART0 = 0x3f400000 ); +PROVIDE ( SPIMEM1 = 0x3f402000 ); +PROVIDE ( SPIMEM0 = 0x3f403000 ); +PROVIDE ( GPIO = 0x3f404000 ); +PROVIDE ( SIGMADELTA = 0x3f404f00 ); +PROVIDE ( RTCCNTL = 0x3f408000 ); +PROVIDE ( RTCIO = 0x3f408400 ); +PROVIDE ( SENS = 0x3f408800 ); +PROVIDE ( HINF = 0x3f40b000 ); +PROVIDE ( I2S0 = 0x3f40F000 ); +PROVIDE ( UART1 = 0x3f410000 ); +PROVIDE ( I2C0 = 0x3f413000 ); +PROVIDE ( UHCI0 = 0x3f414000 ); +PROVIDE ( HOST = 0x3f415000 ); +PROVIDE ( RMT = 0x3f416000 ); +PROVIDE ( RMTMEM = 0x3f416400 ); +PROVIDE ( PCNT = 0x3f417000 ); +PROVIDE ( SLC = 0x3f418000 ); +PROVIDE ( LEDC = 0x3f419000 ); +PROVIDE ( CP_DMA = 0x3f4c3000 ); +PROVIDE ( TIMERG0 = 0x3f41f000 ); +PROVIDE ( TIMERG1 = 0x3f420000 ); +PROVIDE ( SPI2 = 0x3f424000 ); +PROVIDE ( SPI3 = 0x3f425000 ); +PROVIDE ( SYSCON = 0x3f426000 ); +PROVIDE ( I2C1 = 0x3f427000 ); +PROVIDE ( TWAI = 0x3f42b000 ); +PROVIDE ( APB_SARADC = 0x3f440000 ); +PROVIDE ( DEDIC_GPIO = 0x3f4cf000 ); +PROVIDE ( USB0 = 0x60080000 ); +PROVIDE ( USBH = 0x60080000 ); +PROVIDE ( USB_WRAP = 0x3f439000 ); diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/scripts/esp32s2_rom.ld b/boards/xtensa/esp32s2/esp32s2-saola-1/scripts/esp32s2_rom.ld new file mode 100644 index 00000000000..d6d6e1b2410 --- /dev/null +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/scripts/esp32s2_rom.ld @@ -0,0 +1,817 @@ +/** + * ESP32-S2 ROM address table (except symbols from libgcc and libc) + * Generated for ROM with MD5sum: 0a2c7ec5109c17884606d23b47045796 + * + * These are all weak symbols that could be overwritten in ESP-IDF. + */ + +PROVIDE ( abort = 0x40019fb4 ); +PROVIDE ( acm_config_descr = 0x3ffaef0f ); +PROVIDE ( acm_usb_descriptors = 0x3ffaee68 ); +PROVIDE ( boot_prepare = 0x4000f348 ); +PROVIDE ( Cache_Address_Through_DCache = 0x400180f0 ); +PROVIDE ( Cache_Address_Through_ICache = 0x400180bc ); +PROVIDE ( Cache_Allocate_SRAM = 0x40018d6c ); +PROVIDE ( Cache_Clean_Addr = 0x40018370 ); +PROVIDE ( Cache_Clean_All = 0x40018438 ); +PROVIDE ( Cache_Clean_Items = 0x40018250 ); +PROVIDE ( Cache_Config_DCache_Autoload = 0x40018794 ); +PROVIDE ( Cache_Config_ICache_Autoload = 0x40018664 ); +PROVIDE ( Cache_Count_Flash_Pages = 0x40018f70 ); +PROVIDE ( Cache_Dbus_MMU_Set = 0x40018eb0 ); +PROVIDE ( Cache_DCache_Preload_Done = 0x40018630 ); +PROVIDE ( Cache_Disable_DCache = 0x40018c68 ); +PROVIDE ( Cache_Disable_DCache_Autoload = 0x4001888c ); +PROVIDE ( Cache_Disable_DCache_PreLock = 0x40018a5c ); +PROVIDE ( Cache_Disable_ICache = 0x40018c2c ); +PROVIDE ( Cache_Disable_ICache_Autoload = 0x4001875c ); +PROVIDE ( Cache_Disable_ICache_PreLock = 0x4001892c ); +PROVIDE ( Cache_Enable_DCache = 0x40018d58 ); +PROVIDE ( Cache_Enable_DCache_Autoload = 0x40018874 ); +PROVIDE ( Cache_Enable_DCache_PreLock = 0x400189f0 ); +PROVIDE ( Cache_Enable_Defalut_DCache_Mode = 0x40018170 ); +PROVIDE ( Cache_Enable_ICache = 0x40018cf8 ); +PROVIDE ( Cache_Enable_ICache_Autoload = 0x40018744 ); +PROVIDE ( Cache_Enable_ICache_PreLock = 0x400188c0 ); +PROVIDE ( Cache_End_DCache_Preload = 0x40018644 ); +PROVIDE ( Cache_End_ICache_Preload = 0x400185b0 ); +PROVIDE ( Cache_Flash_To_SPIRAM_Copy = 0x40018fc4 ); +PROVIDE ( Cache_Get_DCache_Line_Size = 0x40017fd8 ); +PROVIDE ( Cache_Get_ICache_Line_Size = 0x40017fbc ); +PROVIDE ( Cache_Get_Memory_Addr = 0x4001929c ); +PROVIDE ( Cache_Get_Memory_BaseAddr = 0x40019244 ); +PROVIDE ( Cache_Get_Memory_value = 0x400192d8 ); +PROVIDE ( Cache_Get_Mode = 0x40017ff0 ); +PROVIDE ( Cache_Get_Virtual_Addr = 0x40019210 ); +PROVIDE ( Cache_Ibus_MMU_Set = 0x40018df4 ); +PROVIDE ( Cache_ICache_Preload_Done = 0x4001859c ); +PROVIDE ( Cache_Invalidate_Addr = 0x400182e4 ); +PROVIDE ( Cache_Invalidate_DCache_All = 0x4001842c ); +PROVIDE ( Cache_Invalidate_DCache_Items = 0x40018208 ); +PROVIDE ( Cache_Invalidate_ICache_All = 0x40018420 ); +PROVIDE ( Cache_Invalidate_ICache_Items = 0x400181b8 ); +PROVIDE ( Cache_Lock_Addr = 0x40018b10 ); +PROVIDE ( Cache_Lock_DCache_Items = 0x40018a80 ); +PROVIDE ( Cache_Lock_ICache_Items = 0x40018950 ); +PROVIDE ( Cache_Mask_All = 0x40018458 ); +PROVIDE ( cache_memory_baseaddrs = 0x3ffaf020 ); +PROVIDE ( Cache_MMU_Init = 0x40018dd8 ); +PROVIDE ( Cache_Resume_DCache = 0x40018d3c ); +PROVIDE ( Cache_Resume_DCache_Autoload = 0x4001850c ); +PROVIDE ( Cache_Resume_ICache = 0x40018cdc ); +PROVIDE ( Cache_Resume_ICache_Autoload = 0x400184c4 ); +PROVIDE ( Cache_Set_DCache_Mode = 0x40018074 ); +PROVIDE ( Cache_Set_Default_Mode = 0x4001810c ); +PROVIDE ( Cache_Set_ICache_Mode = 0x4001803c ); +PROVIDE ( Cache_Start_DCache_Preload = 0x400185c4 ); +PROVIDE ( Cache_Start_ICache_Preload = 0x40018530 ); +PROVIDE ( Cache_Suspend_DCache = 0x40018d04 ); +PROVIDE ( Cache_Suspend_DCache_Autoload = 0x400184e0 ); +PROVIDE ( Cache_Suspend_ICache = 0x40018ca4 ); +PROVIDE ( Cache_Suspend_ICache_Autoload = 0x40018498 ); +PROVIDE ( Cache_Travel_Tag_Memory = 0x4001908c ); +PROVIDE ( Cache_Unlock_Addr = 0x40018b9c ); +PROVIDE ( Cache_Unlock_DCache_Items = 0x40018ac8 ); +PROVIDE ( Cache_Unlock_ICache_Items = 0x40018998 ); +PROVIDE ( Cache_UnMask_Drom0 = 0x40018480 ); +PROVIDE ( Cache_WriteBack_Addr = 0x400183c8 ); +PROVIDE ( Cache_WriteBack_All = 0x40018444 ); +PROVIDE ( Cache_WriteBack_Items = 0x40018298 ); +PROVIDE ( cacl_rtc_memory_crc = 0x4000ffa0 ); +PROVIDE ( cdc_acm_class_handle_req = 0x40013050 ); +PROVIDE ( cdc_acm_config = 0x3ffffa10 ); +PROVIDE ( cdc_acm_dev = 0x3ffffce8 ); +PROVIDE ( cdc_acm_fifo_fill = 0x4001318c ); +PROVIDE ( cdc_acm_fifo_read = 0x40013200 ); +PROVIDE ( cdc_acm_init = 0x40013144 ); +PROVIDE ( cdc_acm_irq_callback_set = 0x400132d4 ); +PROVIDE ( cdc_acm_irq_is_pending = 0x400132b0 ); +PROVIDE ( cdc_acm_irq_rx_disable = 0x40013290 ); +PROVIDE ( cdc_acm_irq_rx_enable = 0x40013284 ); +PROVIDE ( cdc_acm_irq_rx_ready = 0x4001329c ); +PROVIDE ( cdc_acm_irq_state_disable = 0x40013264 ); +PROVIDE ( cdc_acm_irq_state_enable = 0x40013258 ); +PROVIDE ( cdc_acm_irq_tx_disable = 0x4001324c ); +PROVIDE ( cdc_acm_irq_tx_enable = 0x40013240 ); +PROVIDE ( cdc_acm_irq_tx_ready = 0x40013270 ); +PROVIDE ( cdc_acm_line_ctrl_get = 0x40013330 ); +PROVIDE ( cdc_acm_line_ctrl_set = 0x400132dc ); +PROVIDE ( cdc_acm_poll_out = 0x40013360 ); +PROVIDE ( cdc_acm_rx_fifo_cnt = 0x400131ec ); +PROVIDE ( chip723_phyrom_version = 0x4000a8a8 ); +PROVIDE ( chip_usb_detach = 0x40013508 ); +PROVIDE ( chip_usb_dw_did_persist = 0x4001337c ); +PROVIDE ( chip_usb_dw_init = 0x400133bc ); +PROVIDE ( chip_usb_dw_prepare_persist = 0x40013588 ); +PROVIDE ( chip_usb_get_persist_flags = 0x400135d8 ); +PROVIDE ( chip_usb_set_persist_flags = 0x400135e8 ); +PROVIDE ( context = 0x3fffeb34 ); +PROVIDE ( cpio_destroy = 0x4001599c ); +PROVIDE ( cpio_done = 0x40015968 ); +PROVIDE ( cpio_feed = 0x40015668 ); +PROVIDE ( cpio_start = 0x4001561c ); +PROVIDE ( crc16_le = 0x40011a10 ); +PROVIDE ( crc32_le = 0x400119dc ); +PROVIDE ( crc8_le = 0x40011a4c ); +PROVIDE ( _cvt = 0x4000f9b8 ); +PROVIDE ( _data_end_all_pro = 0x3fffff98 ); +PROVIDE ( _data_end_c = 0x3ffffd80 ); +PROVIDE ( _data_end_ets = 0x3fffe710 ); +PROVIDE ( _data_end_ets_delay = 0x3ffffd74 ); +PROVIDE ( _data_end_ets_printf = 0x3ffffd5c ); +PROVIDE ( _data_end_newlib = 0x3ffffd74 ); +PROVIDE ( _data_end_phyrom = 0x3fffff98 ); +PROVIDE ( _data_end_sip = 0x3fffeb70 ); +PROVIDE ( _data_end_slc = 0x3fffeb70 ); +PROVIDE ( _data_end_spi_flash = 0x3ffffd54 ); +PROVIDE ( _data_end_spi_slave = 0x3fffeb30 ); +PROVIDE ( _data_end_uart = 0x3ffffcf4 ); +PROVIDE ( _data_end_usbdev = 0x3ffffa6c ); +PROVIDE ( _data_end_xtos = 0x3fffef88 ); +PROVIDE ( _data_start_all_pro = 0x3fffff98 ); +PROVIDE ( _data_start_c = 0x3ffffd7c ); +PROVIDE ( _data_start_ets = 0x3fffe710 ); +PROVIDE ( _data_start_ets_delay = 0x3ffffd70 ); +PROVIDE ( _data_start_ets_printf = 0x3ffffd5c ); +PROVIDE ( _data_start_newlib = 0x3ffffd74 ); +PROVIDE ( _data_start_phyrom = 0x3ffffd90 ); +PROVIDE ( _data_start_sip = 0x3fffeb70 ); +PROVIDE ( _data_start_slc = 0x3fffeb70 ); +PROVIDE ( _data_start_spi_flash = 0x3ffffd38 ); +PROVIDE ( _data_start_spi_slave = 0x3fffeb30 ); +PROVIDE ( _data_start_uart = 0x3ffffcf4 ); +PROVIDE ( _data_start_usbdev = 0x3ffffa10 ); +PROVIDE ( _data_start_xtos = 0x3fffeb70 ); +PROVIDE ( dbus_baseaddrs = 0x3ffaf030 ); +PROVIDE ( _DebugExceptionVector = 0x40000280 ); +PROVIDE ( _DebugExceptionVector_text_end = 0x4000028b ); +PROVIDE ( _DebugExceptionVector_text_start = 0x40000280 ); +PROVIDE ( __default_global_locale = 0x3ffac600 ); +PROVIDE ( dfu_class_handle_req = 0x400152f0 ); +PROVIDE ( dfu_config_descr = 0x3ffaeeb2 ); +PROVIDE ( dfu_cpio_callback = 0x4001360c ); +PROVIDE ( dfu_custom_handle_req = 0x40015568 ); +PROVIDE ( dfu_flash_attach = 0x40015a34 ); +PROVIDE ( dfu_flash_deinit = 0x400159b4 ); +PROVIDE ( dfu_flash_erase = 0x400159bc ); +PROVIDE ( dfu_flash_init = 0x400159a4 ); +PROVIDE ( dfu_flash_program = 0x400159d0 ); +PROVIDE ( dfu_flash_read = 0x40015a24 ); +PROVIDE ( dfu_status_cb = 0x40015514 ); +PROVIDE ( dfu_updater_begin = 0x40013858 ); +PROVIDE ( dfu_updater_clear_err = 0x40013810 ); +PROVIDE ( dfu_updater_enable = 0x40013828 ); +PROVIDE ( dfu_updater_end = 0x40013900 ); +PROVIDE ( dfu_updater_feed = 0x400138b4 ); +PROVIDE ( dfu_updater_flash_read = 0x400139e8 ); +PROVIDE ( dfu_updater_get_err = 0x400137fc ); +PROVIDE ( dfu_updater_set_raw_addr = 0x400139d4 ); +PROVIDE ( dfu_usb_descriptors = 0x3ffaee4c ); +PROVIDE ( dh_group14_generator = 0x3ffadfec ); +PROVIDE ( dh_group14_prime = 0x3ffadeec ); +PROVIDE ( dh_group15_generator = 0x3ffadeeb ); +PROVIDE ( dh_group15_prime = 0x3ffadd6b ); +PROVIDE ( dh_group16_generator = 0x3ffadd6a ); +PROVIDE ( dh_group16_prime = 0x3ffadb6a ); +PROVIDE ( dh_group17_generator = 0x3ffadb69 ); +PROVIDE ( dh_group17_prime = 0x3ffad869 ); +PROVIDE ( dh_group18_generator = 0x3ffad868 ); +PROVIDE ( dh_group18_prime = 0x3ffad468 ); +PROVIDE ( dh_group1_generator = 0x3ffae18f ); +PROVIDE ( dh_group1_prime = 0x3ffae12f ); +PROVIDE ( dh_group2_generator = 0x3ffae12e ); +PROVIDE ( dh_group2_prime = 0x3ffae0ae ); +PROVIDE ( dh_group5_generator = 0x3ffae0ad ); +PROVIDE ( dh_group5_prime = 0x3ffadfed ); +PROVIDE ( disable_default_watchdog = 0x4000f270 ); +PROVIDE ( Disable_QMode = 0x400166e0 ); +PROVIDE ( dmadesc_rx = 0x3fffeb4c ); +PROVIDE ( dmadesc_tx = 0x3fffeb40 ); +PROVIDE ( _DoubleExceptionVector = 0x400003c0 ); +PROVIDE ( _DoubleExceptionVector_text_end = 0x400003c6 ); +PROVIDE ( _DoubleExceptionVector_text_start = 0x400003c0 ); +PROVIDE ( _dram0_0_start = 0x3ffeab00 ); +PROVIDE ( _dram0_rtos_reserved_start = 0x3ffffa10 ); +PROVIDE ( dummy_len_plus = 0x3ffffd54 ); +PROVIDE ( Enable_QMode = 0x40016690 ); +PROVIDE ( esp_crc8 = 0x40011a78 ); +PROVIDE ( esp_rom_config_pad_power_select = 0x40016e58 ); +PROVIDE ( esp_rom_opiflash_cache_mode_config = 0x40016754 ); +PROVIDE ( esp_rom_opiflash_exec_cmd = 0x40017e30 ); +PROVIDE ( esp_rom_opiflash_exit_continuous_read_mode = 0x40017ee8 ); +PROVIDE ( esp_rom_opiflash_mode_reset = 0x40017f90 ); +PROVIDE ( esp_rom_opiflash_pin_config = 0x400177f8 ); +PROVIDE ( esp_rom_opiflash_soft_reset = 0x40017f24 ); +PROVIDE ( esp_rom_spi_cmd_config = 0x40017c58 ); +PROVIDE ( esp_rom_spi_cmd_start = 0x40017ba8 ); +PROVIDE ( esp_rom_spi_flash_auto_sus_res = 0x400175e0 ); +PROVIDE ( esp_rom_spi_flash_auto_wait_idle = 0x4001751c ); +PROVIDE ( esp_rom_spi_flash_send_resume = 0x40017570 ); +PROVIDE ( esp_rom_spi_flash_update_id = 0x40016e44 ); +PROVIDE ( esp_rom_spi_reset_rw_mode = 0x40017984 ); +PROVIDE ( esp_rom_spi_set_dtr_swap_mode = 0x40017b60 ); +PROVIDE ( esp_rom_spi_set_op_mode = 0x400179e8 ); +PROVIDE ( _etext = 0x4001bed0 ); +PROVIDE ( ets_aes_block = 0x4000d610 ); +PROVIDE ( ets_aes_disable = 0x4000d4f8 ); +PROVIDE ( ets_aes_enable = 0x4000d4cc ); +PROVIDE ( ets_aes_set_endian = 0x4000d528 ); +PROVIDE ( ets_aes_setkey = 0x4000d594 ); +PROVIDE ( ets_aes_setkey_dec = 0x4000d5f0 ); +PROVIDE ( ets_aes_setkey_enc = 0x4000d5e0 ); +PROVIDE ( ets_bigint_disable = 0x4000d750 ); +PROVIDE ( ets_bigint_enable = 0x4000d708 ); +PROVIDE ( ets_bigint_getz = 0x4000d858 ); +PROVIDE ( ets_bigint_modexp = 0x4000d818 ); +PROVIDE ( ets_bigint_modmult = 0x4000d7f4 ); +PROVIDE ( ets_bigint_multiply = 0x4000d790 ); +PROVIDE ( ets_bigint_wait_finish = 0x4000d840 ); +PROVIDE ( ets_config_flash_by_image_hdr = 0x40010e40 ); +PROVIDE ( ets_delay_us = 0x4000d888 ); +PROVIDE ( ets_ds_disable = 0x4000d910 ); +PROVIDE ( ets_ds_enable = 0x4000d8e4 ); +PROVIDE ( ets_ds_encrypt_params = 0x4000da90 ); +PROVIDE ( ets_ds_finish_sign = 0x4000d9f8 ); +PROVIDE ( ets_ds_is_busy = 0x4000d93c ); +PROVIDE ( ets_ds_start_sign = 0x4000d96c ); +PROVIDE ( ets_efuse_cache_encryption_enabled = 0x4000e690 ); +PROVIDE ( ets_efuse_clear_program_registers = 0x4000e100 ); +PROVIDE ( ets_efuse_count_unused_key_blocks = 0x4000e2c4 ); +PROVIDE ( ets_efuse_download_modes_disabled = 0x4000e594 ); +PROVIDE ( ets_efuse_find_purpose = 0x4000e224 ); +PROVIDE ( ets_efuse_find_unused_key_block = 0x4000e2ac ); +PROVIDE ( ets_efuse_flash_opi_5pads_power_sel_vddspi = 0x4000e640 ); +PROVIDE ( ets_efuse_flash_opi_mode = 0x4000e650 ); +PROVIDE ( ets_efuse_force_send_resume = 0x4000e660 ); +PROVIDE ( ets_efuse_get_flash_delay_us = 0x4000e6d4 ); +PROVIDE ( ets_efuse_get_key_purpose = 0x4000e1b0 ); +PROVIDE ( ets_efuse_get_opiconfig = 0x4000e4fc ); +PROVIDE ( ets_efuse_get_read_register_address = 0x4000e18c ); +PROVIDE ( ets_efuse_get_spiconfig = 0x4000e4a0 ); +PROVIDE ( ets_efuse_get_uart_print_channel = 0x4000e5b4 ); +PROVIDE ( ets_efuse_get_uart_print_control = 0x4000e5a4 ); +PROVIDE ( ets_efuse_get_wp_pad = 0x4000e444 ); +PROVIDE ( ets_efuse_key_block_unused = 0x4000e250 ); +PROVIDE ( ets_efuse_legacy_spi_boot_mode_disabled = 0x4000e6b0 ); +PROVIDE ( ets_efuse_program = 0x4000e134 ); +PROVIDE ( ets_efuse_read = 0x4000e0c0 ); +PROVIDE ( ets_efuse_rs_calculate = 0x4000e6f8 ); +PROVIDE ( ets_efuse_secure_boot_aggressive_revoke_enabled = 0x4000e680 ); +PROVIDE ( ets_efuse_secure_boot_enabled = 0x4000e670 ); +PROVIDE ( ets_efuse_security_download_modes_enabled = 0x4000e5d4 ); +PROVIDE ( ets_efuse_set_timing = 0x4000df3c ); +PROVIDE ( ets_efuse_start = 0x4000e084 ); +PROVIDE ( ets_efuse_usb_download_mode_disabled = 0x4000e5f4 ); +PROVIDE ( ets_efuse_usb_force_nopersist = 0x4000e630 ); +PROVIDE ( ets_efuse_usb_module_disabled = 0x4000e5c4 ); +PROVIDE ( ets_efuse_usb_use_ext_phy = 0x4000e620 ); +PROVIDE ( ets_efuse_write_key = 0x4000e2f4 ); +PROVIDE ( ets_emsa_pss_verify = 0x40011818 ); +PROVIDE ( ets_get_apb_freq = 0x40010c58 ); +PROVIDE ( ets_get_cpu_frequency = 0x4000d8b0 ); +PROVIDE ( ets_get_printf_channel = 0x4000ff48 ); +PROVIDE ( ets_get_xtal_div = 0x40010bfc ); +PROVIDE ( ets_get_xtal_freq = 0x40010c38 ); +PROVIDE ( ets_hmac_calculate_downstream = 0x4000f120 ); +PROVIDE ( ets_hmac_calculate_message = 0x4000f020 ); +PROVIDE ( ets_hmac_disable = 0x4000eff4 ); +PROVIDE ( ets_hmac_enable = 0x4000efd8 ); +PROVIDE ( ets_hmac_invalidate_downstream = 0x4000f140 ); +PROVIDE ( ets_install_lock = 0x4000fea0 ); +PROVIDE ( ets_install_putc1 = 0x4000feb0 ); +PROVIDE ( ets_install_putc2 = 0x4000fed0 ); +PROVIDE ( ets_install_uart_printf = 0x4000fec0 ); +PROVIDE ( ets_intr_count = 0x3fffe710 ); +PROVIDE ( ets_intr_lock = 0x4000f168 ); +PROVIDE ( ets_intr_unlock = 0x4000f17c ); +PROVIDE ( ets_is_print_boot = 0x4000f2a0 ); +PROVIDE ( ets_isr_attach = 0x4000f1a4 ); +PROVIDE ( ets_isr_mask = 0x4000f1b4 ); +PROVIDE ( ets_isr_unmask = 0x4000f1c0 ); +PROVIDE ( ets_jtag_enable_temporarily = 0x4000e548 ); +PROVIDE ( ets_loader_map_range = 0x40010d4c ); +PROVIDE ( ets_mgf1_sha256 = 0x400117b0 ); +PROVIDE ( ets_printf = 0x4000fee0 ); +PROVIDE ( ets_printf_lock = 0x3ffffd64 ); +PROVIDE ( ets_printf_uart = 0x3ffffd5c ); +PROVIDE ( ets_printf_unlock = 0x3ffffd60 ); +PROVIDE ( ets_rsa_pss_verify = 0x4001191c ); +PROVIDE ( ets_run_flash_bootloader = 0x40010f58 ); +PROVIDE ( ets_secure_boot_read_key_digests = 0x400101ac ); +PROVIDE ( ets_secure_boot_revoke_public_key_digest = 0x4001025c ); +PROVIDE ( ets_secure_boot_verify_bootloader_with_keys = 0x40010444 ); +PROVIDE ( ets_secure_boot_verify_signature = 0x400102cc ); +PROVIDE ( ets_secure_boot_verify_stage_bootloader = 0x40010720 ); +PROVIDE ( ets_set_printf_channel = 0x4000ff3c ); +PROVIDE ( ets_set_user_start = 0x4000f25c ); +PROVIDE ( ets_set_xtal_div = 0x40010c18 ); +PROVIDE ( ets_sha_clone = 0x4001095c ); +PROVIDE ( ets_sha_disable = 0x400107b4 ); +PROVIDE ( ets_sha_enable = 0x40010788 ); +PROVIDE ( ets_sha_finish = 0x40010ab8 ); +PROVIDE ( ets_sha_get_state = 0x40010934 ); +PROVIDE ( ets_sha_init = 0x400107e0 ); +PROVIDE ( ets_sha_process = 0x40010988 ); +PROVIDE ( ets_sha_starts = 0x40010828 ); +PROVIDE ( ets_sha_update = 0x400109f8 ); +PROVIDE ( ets_startup_callback = 0x3fffe718 ); +PROVIDE ( ets_unpack_flash_code_legacy = 0x40011430 ); +PROVIDE ( ets_update_cpu_frequency = 0x4000d8a4 ); +PROVIDE ( ets_vprintf = 0x4000fa3c ); +PROVIDE ( ets_waiti0 = 0x4000f190 ); +PROVIDE ( ets_wdt_reset_cpu = 0x4001a82c ); +PROVIDE ( ets_write_char = 0x4000f974 ); +PROVIDE ( ets_write_char_uart = 0x4000f998 ); +PROVIDE ( exc_cause_table = 0x3ffacbe8 ); +PROVIDE ( FilePacketSendDeflatedReqMsgProc = 0x40011ed8 ); +PROVIDE ( FilePacketSendReqMsgProc = 0x40011bd8 ); +PROVIDE ( flashchip = 0x3ffffd38 ); +PROVIDE ( FlashDwnLdDeflatedStartMsgProc = 0x40011e80 ); +PROVIDE ( FlashDwnLdParamCfgMsgProc = 0x40011cc0 ); +PROVIDE ( FlashDwnLdStartMsgProc = 0x40011b74 ); +PROVIDE ( FlashDwnLdStopDeflatedReqMsgProc = 0x40011fd8 ); +PROVIDE ( FlashDwnLdStopReqMsgProc = 0x40011c90 ); +PROVIDE ( general_device_descr = 0x3ffffa58 ); +PROVIDE ( _GeneralException = 0x400073cf ); +PROVIDE ( get_id = 0x4001610c ); +PROVIDE ( GetSecurityInfoProc = 0x40012098 ); +PROVIDE ( GetUartDevice = 0x40012f60 ); +PROVIDE ( __global_locale_ptr = 0x3ffffd7c ); +PROVIDE ( g_phyFuns = 0x3ffffd90 ); +PROVIDE ( g_phyFuns_instance = 0x3ffffd94 ); +PROVIDE ( gpio_input_get = 0x400193a0 ); +PROVIDE ( gpio_input_get_high = 0x400193b4 ); +PROVIDE ( gpio_matrix_in = 0x40019430 ); +PROVIDE ( gpio_matrix_out = 0x40019460 ); +PROVIDE ( gpio_output_disable = 0x400194dc ); +PROVIDE ( gpio_output_enable = 0x400194b0 ); +PROVIDE ( gpio_output_set = 0x4001933c ); +PROVIDE ( gpio_output_set_high = 0x40019374 ); +PROVIDE ( gpio_pad_hold = 0x40019654 ); +PROVIDE ( gpio_pad_input_disable = 0x400195f0 ); +PROVIDE ( gpio_pad_input_enable = 0x400195cc ); +PROVIDE ( gpio_pad_pulldown = 0x40019598 ); +PROVIDE ( gpio_pad_pullup = 0x40019564 ); +PROVIDE ( gpio_pad_select_gpio = 0x40019510 ); +PROVIDE ( gpio_pad_set_drv = 0x40019538 ); +PROVIDE ( gpio_pad_unhold = 0x4001961c ); +PROVIDE ( gpio_pin_wakeup_disable = 0x40019404 ); +PROVIDE ( gpio_pin_wakeup_enable = 0x400193c8 ); +PROVIDE ( g_shared_buffers = 0x3ffeab04 ); +PROVIDE ( g_ticks_per_us = 0x3ffffd70 ); +PROVIDE ( hmac_md5 = 0x40005490 ); +PROVIDE ( hmac_md5_vector = 0x400053a0 ); +PROVIDE ( ibus_baseaddrs = 0x3ffaf03c ); +PROVIDE ( intr_matrix_set = 0x4000f1d0 ); +PROVIDE ( _iram0_text_end = 0x40000540 ); +PROVIDE ( _iram0_text_start = 0x40000540 ); +PROVIDE ( _iram1_text_end = 0x60021100 ); +PROVIDE ( _iram1_text_start = 0x60021100 ); +PROVIDE ( _KernelExceptionVector = 0x40000300 ); +PROVIDE ( _KernelExceptionVector_text_end = 0x40000306 ); +PROVIDE ( _KernelExceptionVector_text_start = 0x40000300 ); +PROVIDE ( _Level2FromVector = 0x400074f8 ); +PROVIDE ( _Level2HandlerLabel = 0x00000000 ); +PROVIDE ( _Level2InterruptVector_text_end = 0x40000186 ); +PROVIDE ( _Level2InterruptVector_text_start = 0x40000180 ); +PROVIDE ( _Level2Vector = 0x40000180 ); +PROVIDE ( _Level3FromVector = 0x40007594 ); +PROVIDE ( _Level3HandlerLabel = 0x00000000 ); +PROVIDE ( _Level3InterruptVector_text_end = 0x400001c6 ); +PROVIDE ( _Level3InterruptVector_text_start = 0x400001c0 ); +PROVIDE ( _Level3Vector = 0x400001c0 ); +PROVIDE ( _Level4FromVector = 0x4000762c ); +PROVIDE ( _Level4HandlerLabel = 0x00000000 ); +PROVIDE ( _Level4InterruptVector_text_end = 0x40000206 ); +PROVIDE ( _Level4InterruptVector_text_start = 0x40000200 ); +PROVIDE ( _Level4Vector = 0x40000200 ); +PROVIDE ( _Level5FromVector = 0x4000775c ); +PROVIDE ( _Level5HandlerLabel = 0x00000000 ); +PROVIDE ( _Level5InterruptVector_text_end = 0x40000246 ); +PROVIDE ( _Level5InterruptVector_text_start = 0x40000240 ); +PROVIDE ( _Level5Vector = 0x40000240 ); +PROVIDE ( _LevelOneInterrupt = 0x4000740a ); +PROVIDE ( _lit4_end = 0x40000540 ); +PROVIDE ( _lit4_start = 0x40000540 ); +PROVIDE ( lldesc_build_chain = 0x4000907c ); +PROVIDE ( lldesc_num2link = 0x4000916c ); +PROVIDE ( lldesc_set_owner = 0x40009198 ); +PROVIDE ( lldesc_setup = 0x40019ed8 ); +PROVIDE ( main = 0x4000f6c4 ); +PROVIDE ( MD5Final = 0x4000530c ); +PROVIDE ( MD5Init = 0x4000526c ); +PROVIDE ( MD5Update = 0x4000528c ); +PROVIDE ( md5_vector = 0x40005374 ); +PROVIDE ( MemDwnLdStartMsgProc = 0x40011cec ); +PROVIDE ( MemDwnLdStopReqMsgProc = 0x40011d80 ); +PROVIDE ( _memmap_cacheattr_bp_allvalid = 0x22222222 ); +PROVIDE ( _memmap_cacheattr_bp_base = 0x00000220 ); +PROVIDE ( _memmap_cacheattr_bp_strict = 0xfffff22f ); +PROVIDE ( _memmap_cacheattr_bp_trapnull = 0x2222222f ); +PROVIDE ( _memmap_cacheattr_reset = 0x2222211f ); +PROVIDE ( _memmap_cacheattr_unused_mask = 0xfffff00f ); +PROVIDE ( _memmap_cacheattr_wb_allvalid = 0x22222112 ); +PROVIDE ( _memmap_cacheattr_wba_trapnull = 0x2222211f ); +PROVIDE ( _memmap_cacheattr_wb_base = 0x00000110 ); +PROVIDE ( _memmap_cacheattr_wbna_trapnull = 0x2222211f ); +PROVIDE ( _memmap_cacheattr_wb_strict = 0xfffff11f ); +PROVIDE ( _memmap_cacheattr_wb_trapnull = 0x2222211f ); +PROVIDE ( _memmap_cacheattr_wt_allvalid = 0x22222112 ); +PROVIDE ( _memmap_cacheattr_wt_base = 0x00000110 ); +PROVIDE ( _memmap_cacheattr_wt_strict = 0xfffff11f ); +PROVIDE ( _memmap_cacheattr_wt_trapnull = 0x2222211f ); +PROVIDE ( _memmap_vecbase_reset = 0x40000000 ); +PROVIDE ( MemPacketSendReqMsgProc = 0x40011d1c ); +PROVIDE ( multofup = 0x4001bce0 ); +PROVIDE ( must_reset = 0x3ffffcf4 ); +PROVIDE ( mz_adler32 = 0x40002e90 ); +PROVIDE ( mz_crc32 = 0x40002f58 ); +PROVIDE ( mz_free = 0x40002fa4 ); +PROVIDE ( _NMIExceptionVector = 0x400002c0 ); +PROVIDE ( _NMIExceptionVector_text_end = 0x400002c3 ); +PROVIDE ( _NMIExceptionVector_text_start = 0x400002c0 ); +PROVIDE ( __packed = 0x3ffffcec ); +PROVIDE ( phy_get_romfuncs = 0x4000a88c ); +PROVIDE ( _Pri_4_HandlerAddress = 0x3fffed78 ); +PROVIDE ( _Pri_5_HandlerAddress = 0x3fffed7c ); +PROVIDE ( pthread_setcancelstate = 0x40019fa8 ); +PROVIDE ( _putc1 = 0x3ffffd6c ); +PROVIDE ( _putc2 = 0x3ffffd68 ); +PROVIDE ( RcvMsg = 0x40012f10 ); +PROVIDE ( recv_packet = 0x40012de8 ); +PROVIDE ( _ResetHandler = 0x4000044c ); +PROVIDE ( _ResetVector = 0x40000400 ); +PROVIDE ( _ResetVector_literal_end = 0x40000540 ); +PROVIDE ( _ResetVector_literal_start = 0x40000540 ); +PROVIDE ( _ResetVector_text_end = 0x4000053d ); +PROVIDE ( _ResetVector_text_start = 0x40000400 ); +PROVIDE ( _rodata_end = 0x3ffaff2c ); +PROVIDE ( _rodata_start = 0x3ffac600 ); +PROVIDE ( rom_abs_temp = 0x4000c330 ); +PROVIDE ( rom_ant_btrx_cfg = 0x4000a0fc ); +PROVIDE ( rom_ant_bttx_cfg = 0x4000a0c0 ); +PROVIDE ( rom_ant_dft_cfg = 0x40009fc8 ); +PROVIDE ( rom_ant_wifirx_cfg = 0x4000a03c ); +PROVIDE ( rom_ant_wifitx_cfg = 0x40009ff8 ); +PROVIDE ( rom_bb_bss_cbw40_dig = 0x40009a84 ); +PROVIDE ( rom_bb_wdg_cfg = 0x40009eb8 ); +PROVIDE ( rom_bb_wdg_test_en = 0x40009a48 ); +PROVIDE ( rom_bb_wdt_get_status = 0x40009d18 ); +PROVIDE ( rom_bb_wdt_int_enable = 0x40009cd4 ); +PROVIDE ( rom_bb_wdt_rst_enable = 0x40009cb4 ); +PROVIDE ( rom_bb_wdt_timeout_clear = 0x40009cfc ); +PROVIDE ( rom_cbw2040_cfg = 0x4000a550 ); +PROVIDE ( rom_check_noise_floor = 0x40009b4c ); +PROVIDE ( rom_chip_i2c_readReg = 0x4000a8e4 ); +PROVIDE ( rom_chip_i2c_writeReg = 0x4000a960 ); +PROVIDE ( rom_correct_rf_ana_gain = 0x4000d2b4 ); +PROVIDE ( rom_dc_iq_est = 0x4000c414 ); +PROVIDE ( rom_disable_agc = 0x400091cc ); +PROVIDE ( rom_enable_agc = 0x400091e4 ); +PROVIDE ( rom_freq_get_i2c_data = 0x4000bb84 ); +PROVIDE ( rom_freq_i2c_set_wifi_data = 0x4000b948 ); +PROVIDE ( rom_freq_i2c_write_set = 0x4000b3bc ); +PROVIDE ( rom_gen_rx_gain_table = 0x4000a300 ); +PROVIDE ( rom_get_bbgain_db = 0x400094ec ); +PROVIDE ( rom_get_data_sat = 0x40009338 ); +PROVIDE ( rom_get_fm_sar_dout = 0x4000c024 ); +PROVIDE ( rom_get_i2c_read_mask = 0x4000a8c0 ); +PROVIDE ( rom_get_power_db = 0x4000ce28 ); +PROVIDE ( rom_get_pwctrl_correct = 0x4000d470 ); +PROVIDE ( rom_get_rfcal_rxiq_data = 0x4000cab0 ); +PROVIDE ( rom_get_rf_gain_qdb = 0x4000d29c ); +PROVIDE ( rom_get_sar_dout = 0x4000d400 ); +PROVIDE ( rom_i2c_clk_sel = 0x4000a788 ); +PROVIDE ( rom_i2c_readreg = 0x4000a940 ); +PROVIDE ( rom_i2c_readreg_mask = 0x4000a9c4 ); +PROVIDE ( rom_i2c_writereg = 0x4000a9a8 ); +PROVIDE ( rom_i2c_writereg_mask = 0x4000aa00 ); +PROVIDE ( rom_index_to_txbbgain = 0x4000bd10 ); +PROVIDE ( rom_iq_est_disable = 0x4000c3d8 ); +PROVIDE ( rom_iq_est_enable = 0x4000c358 ); +PROVIDE ( rom_linear_to_db = 0x4000cdbc ); +PROVIDE ( rom_loopback_mode_en = 0x40009304 ); +PROVIDE ( rom_mac_enable_bb = 0x40009e48 ); +PROVIDE ( rom_meas_tone_pwr_db = 0x4000ce64 ); +PROVIDE ( rom_mhz2ieee = 0x4000a4e8 ); +PROVIDE ( rom_noise_floor_auto_set = 0x40009ab4 ); +PROVIDE ( rom_pbus_debugmode = 0x4000ac70 ); +PROVIDE ( rom_pbus_force_mode = 0x4000aa6c ); +PROVIDE ( rom_pbus_force_test = 0x4000abd0 ); +PROVIDE ( rom_pbus_rd = 0x4000ac2c ); +PROVIDE ( rom_pbus_rd_addr = 0x4000ab34 ); +PROVIDE ( rom_pbus_rd_shift = 0x4000ab80 ); +PROVIDE ( rom_pbus_rx_dco_cal = 0x4000c49c ); +PROVIDE ( rom_pbus_set_dco = 0x4000ae2c ); +PROVIDE ( rom_pbus_set_rxgain = 0x4000ac98 ); +PROVIDE ( rom_pbus_workmode = 0x4000ac84 ); +PROVIDE ( rom_pbus_xpd_rx_off = 0x4000acfc ); +PROVIDE ( rom_pbus_xpd_rx_on = 0x4000ad30 ); +PROVIDE ( rom_pbus_xpd_tx_off = 0x4000ad84 ); +PROVIDE ( rom_pbus_xpd_tx_on = 0x4000add4 ); +PROVIDE ( rom_phy_ant_init = 0x40009f48 ); +PROVIDE ( rom_phy_byte_to_word = 0x40009d60 ); +PROVIDE ( rom_phy_chan_dump_cfg = 0x4000a180 ); +PROVIDE ( rom_phy_chan_filt_set = 0x4000a614 ); +PROVIDE ( rom_phy_close_pa = 0x4000a810 ); +PROVIDE ( rom_phy_disable_cca = 0x40009208 ); +PROVIDE ( rom_phy_disable_low_rate = 0x4000a2b8 ); +PROVIDE ( rom_phy_enable_cca = 0x40009234 ); +PROVIDE ( rom_phy_enable_low_rate = 0x4000a280 ); +PROVIDE ( rom_phy_freq_correct = 0x4000b0b4 ); +PROVIDE ( rom_phy_get_noisefloor = 0x40009b04 ); +PROVIDE ( rom_phy_get_rx_freq = 0x4000a6ac ); +PROVIDE ( rom_phy_get_tx_rate = 0x40009d50 ); +PROVIDE ( rom_phy_rx11blr_cfg = 0x40009c5c ); +PROVIDE ( rom_phy_rx_sense_set = 0x4000a704 ); +PROVIDE ( rom_phy_set_bbfreq_init = 0x4000d3d0 ); +PROVIDE ( rom_pll_correct_dcap = 0x4000bad4 ); +PROVIDE ( rom_pow_usr = 0x4000924c ); +PROVIDE ( rom_read_hw_noisefloor = 0x40009c38 ); +PROVIDE ( rom_read_sar_dout = 0x4000bfd4 ); +PROVIDE ( rom_restart_cal = 0x4000ae74 ); +PROVIDE ( rom_rfcal_pwrctrl = 0x4000d098 ); +PROVIDE ( rom_rfcal_rxiq = 0x4000ca3c ); +PROVIDE ( rom_rfcal_txcap = 0x4000ccac ); +PROVIDE ( rom_rfpll_set_freq = 0x4000afa4 ); +PROVIDE ( rom_rftx_init = 0x4000b24c ); +PROVIDE ( rom_rx_gain_force = 0x40009558 ); +PROVIDE ( rom_rxiq_cover_mg_mp = 0x4000c954 ); +PROVIDE ( rom_rxiq_get_mis = 0x4000c7d8 ); +PROVIDE ( rom_rxiq_set_reg = 0x4000c8ec ); +PROVIDE ( rom_set_cal_rxdc = 0x400092c4 ); +PROVIDE ( rom_set_cca = 0x4000a59c ); +PROVIDE ( rom_set_chan_cal_interp = 0x4000cba4 ); +PROVIDE ( rom_set_channel_freq = 0x4000b00c ); +PROVIDE ( rom_set_loopback_gain = 0x40009268 ); +PROVIDE ( rom_set_noise_floor = 0x40009bf4 ); +PROVIDE ( rom_set_pbus_mem = 0x40009380 ); +PROVIDE ( rom_set_rf_freq_offset = 0x4000b214 ); +PROVIDE ( rom_set_rxclk_en = 0x400095cc ); +PROVIDE ( rom_set_txcap_reg = 0x4000cc34 ); +PROVIDE ( rom_set_txclk_en = 0x4000959c ); +PROVIDE ( rom_set_tx_dig_gain = 0x40009514 ); +PROVIDE ( rom_set_xpd_sar = 0x40009f08 ); +PROVIDE ( rom_spur_cal = 0x4000a47c ); +PROVIDE ( rom_spur_reg_write_one_tone = 0x400097c4 ); +PROVIDE ( rom_start_tx_tone = 0x400096f0 ); +PROVIDE ( rom_start_tx_tone_step = 0x40009608 ); +PROVIDE ( rom_stop_tx_tone = 0x4000a428 ); +PROVIDE ( _rom_store = 0x4001bed0 ); +PROVIDE ( _rom_store_table = 0x4001bd64 ); +PROVIDE ( rom_target_power_add_backoff = 0x4000d278 ); +PROVIDE ( rom_txbbgain_to_index = 0x4000bce0 ); +PROVIDE ( rom_txcal_work_mode = 0x4000bf30 ); +PROVIDE ( rom_txdc_cal_init = 0x4000bd2c ); +PROVIDE ( rom_txdc_cal_v70 = 0x4000bdc0 ); +PROVIDE ( rom_txiq_cover = 0x4000c1ac ); +PROVIDE ( rom_txiq_get_mis_pwr = 0x4000c0f8 ); +PROVIDE ( rom_txiq_set_reg = 0x4000bf64 ); +PROVIDE ( rom_tx_paon_set = 0x40009db8 ); +PROVIDE ( rom_tx_pwr_backoff = 0x4000ceb8 ); +PROVIDE ( rom_txtone_linear_pwr = 0x4000c0b0 ); +PROVIDE ( rom_usb_dev = 0x3ffffb9c ); /* static "usb_dev" */ +PROVIDE ( rom_usb_dev_end = 0x3ffffc78 ); /* end of "usb_dev" */ +PROVIDE ( rom_usb_dw_ctrl = 0x3ffffa74 ); /* static "usb_dw_ctrl" */ +PROVIDE ( rom_usb_dw_ctrl_end = 0x3ffffb9c ); /* end of "usb_dw_ctrl" */ +PROVIDE ( rom_usb_curr_desc = 0x3ffffa54 ); /* static "s_curr_descr" */ +PROVIDE ( rom_wait_rfpll_cal_end = 0x4000af3c ); +PROVIDE ( rom_wifi_11g_rate_chg = 0x4000d260 ); +PROVIDE ( rom_wifi_rifs_mode_en = 0x40009d2c ); +PROVIDE ( rom_write_dac_gain2 = 0x4000a210 ); +PROVIDE ( rom_write_gain_mem = 0x400094bc ); +PROVIDE ( rom_write_pll_cap_mem = 0x4000ba58 ); +PROVIDE ( rom_write_rfpll_sdm = 0x4000aed4 ); +PROVIDE ( rom_wr_rf_freq_mem = 0x4000b2f0 ); +PROVIDE ( roundup2 = 0x4001bcd0 ); +PROVIDE ( rtc_boot_control = 0x4001002c ); +PROVIDE ( rtc_get_reset_reason = 0x4000ff58 ); +PROVIDE ( rtc_get_wakeup_cause = 0x4000ff7c ); +PROVIDE ( rtc_select_apb_bridge = 0x400100a0 ); +PROVIDE ( s_cdcacm_old_rts = 0x3ffffd34 ); +PROVIDE ( SelectSpiFunction = 0x40015d08 ); +PROVIDE ( SelectSpiQIO = 0x40015b88 ); +PROVIDE ( SendMsg = 0x40012d0c ); +PROVIDE ( send_packet = 0x40012cc8 ); +PROVIDE ( set_rtc_memory_crc = 0x40010010 ); +PROVIDE ( SetSpiDrvs = 0x40015c18 ); +PROVIDE ( sig_matrix = 0x3ffffd57 ); +PROVIDE ( software_reset = 0x40010068 ); +PROVIDE ( software_reset_cpu = 0x40010080 ); +PROVIDE ( SPI_block_erase = 0x4001623c ); +PROVIDE ( spi_cache_mode_switch = 0x40016a00 ); +PROVIDE ( SPI_chip_erase = 0x400161b8 ); +PROVIDE ( SPIClkConfig = 0x400170a0 ); +PROVIDE ( SPI_Common_Command = 0x400162e8 ); +PROVIDE ( spi_common_set_flash_cs_timing = 0x40016c0c ); +PROVIDE ( spi_dummy_len_fix = 0x40015b50 ); +PROVIDE ( SPI_Encrypt_Write = 0x400177e0 ); +PROVIDE ( SPI_Encrypt_Write_Dest = 0x400176cc ); +PROVIDE ( SPIEraseArea = 0x40017470 ); +PROVIDE ( SPIEraseBlock = 0x4001710c ); +PROVIDE ( SPIEraseChip = 0x400170ec ); +PROVIDE ( SPIEraseSector = 0x4001716c ); +PROVIDE ( esp_rom_spiflash_attach = 0x40017004 ); +PROVIDE ( spi_flash_boot_attach = 0x40016fc0 ); +PROVIDE ( spi_flash_check_suspend_cb = 0x3ffffd58 ); +PROVIDE ( SPI_flashchip_data = 0x3ffffd3c ); +PROVIDE ( spi_flash_set_check_suspend_cb = 0x40015b3c ); +PROVIDE ( SPI_init = 0x40016ce8 ); +PROVIDE ( SPILock = 0x40016ed4 ); +PROVIDE ( SPIMasterReadModeCnfig = 0x40017014 ); +PROVIDE ( SPI_page_program = 0x400165a8 ); +PROVIDE ( SPIParamCfg = 0x40017500 ); +PROVIDE ( SPIRead = 0x4001728c ); +PROVIDE ( SPI_read_data = 0x40015ed8 ); +PROVIDE ( SPIReadModeCnfig = 0x40016f1c ); +PROVIDE ( SPI_read_status = 0x40016084 ); +PROVIDE ( SPI_read_status_high = 0x40016284 ); +PROVIDE ( SPI_sector_erase = 0x400161ec ); +PROVIDE ( spi_slave_download = 0x4001998c ); +PROVIDE ( spi_slave_rom_check_conn = 0x40019724 ); +PROVIDE ( spi_slave_rom_init = 0x40019774 ); +PROVIDE ( spi_slave_rom_init_hw = 0x40019b5c ); +PROVIDE ( spi_slave_rom_intr_enable = 0x40019b3c ); +PROVIDE ( spi_slave_rom_rxdma_load = 0x40019da8 ); +PROVIDE ( spi_slave_rom_txdma_load = 0x40019e3c ); +PROVIDE ( SPIUnlock = 0x40016e88 ); +PROVIDE ( SPI_user_command_read = 0x40015fc8 ); +PROVIDE ( SPI_Wait_Idle = 0x40016680 ); +PROVIDE ( SPI_WakeUp = 0x400160f4 ); +PROVIDE ( SPIWrite = 0x400171cc ); +PROVIDE ( SPI_write_enable = 0x4001655c ); +PROVIDE ( SPI_Write_Encrypt_Disable = 0x40017694 ); +PROVIDE ( SPI_Write_Encrypt_Enable = 0x40017678 ); +PROVIDE ( SPI_write_status = 0x400162a4 ); +PROVIDE ( __stack = 0x3fffe710 ); +PROVIDE ( _stack_sentry = 0x3fffc410 ); +PROVIDE ( _start = 0x4000726c ); +PROVIDE ( _stext = 0x40007118 ); +PROVIDE ( string0_descr = 0x3ffaeeae ); +PROVIDE ( str_manu_descr = 0x3ffaee9a ); +PROVIDE ( str_prod_descr = 0x3ffaee88 ); +PROVIDE ( str_serial_descr = 0x3ffaee84 ); +PROVIDE ( rom_usb_osglue = 0x3ffffcdc ); +PROVIDE ( _SyscallException = 0x4000732a ); +PROVIDE ( syscall_table_ptr_pro = 0x3ffffd78 ); +PROVIDE ( tdefl_compress = 0x400041dc ); +PROVIDE ( tdefl_compress_buffer = 0x40004938 ); +PROVIDE ( tdefl_compress_mem_to_mem = 0x40004a50 ); +PROVIDE ( tdefl_compress_mem_to_output = 0x40004a30 ); +PROVIDE ( tdefl_get_adler32 = 0x40004a28 ); +PROVIDE ( tdefl_get_prev_return_status = 0x40004a20 ); +PROVIDE ( tdefl_init = 0x40004954 ); +PROVIDE ( tdefl_write_image_to_png_file_in_memory = 0x40004a64 ); +PROVIDE ( tdefl_write_image_to_png_file_in_memory_ex = 0x40004a58 ); +PROVIDE ( _text_end = 0x4001bed0 ); +PROVIDE ( _text_start = 0x40007118 ); +PROVIDE ( tinfl_decompress = 0x40003000 ); +PROVIDE ( tinfl_decompress_mem_to_callback = 0x400041a8 ); +PROVIDE ( tinfl_decompress_mem_to_mem = 0x40004168 ); +PROVIDE ( uart_acm_dev = 0x3ffffcf8 ); +PROVIDE ( uartAttach = 0x40012890 ); +PROVIDE ( uart_baudrate_detect = 0x400128f0 ); +PROVIDE ( uart_buff_switch = 0x40012d64 ); +PROVIDE ( UartConnCheck = 0x40011ab4 ); +PROVIDE ( UartConnectProc = 0x40011da8 ); +PROVIDE ( UartDev = 0x3ffffcfc ); +PROVIDE ( uart_div_modify = 0x40012984 ); +PROVIDE ( uart_div_reinit = 0x400129d0 ); +PROVIDE ( UartDwnLdProc = 0x400121ac ); +PROVIDE ( UartGetCmdLn = 0x40012f28 ); +PROVIDE ( Uart_Init = 0x40012a04 ); +PROVIDE ( Uart_Init_USB = 0x40012818 ); +PROVIDE ( UartRegReadProc = 0x40011df8 ); +PROVIDE ( UartRegWriteProc = 0x40011db8 ); +PROVIDE ( uart_rx_intr_handler = 0x40012690 ); +PROVIDE ( uart_rx_one_char = 0x40012bf0 ); +PROVIDE ( uart_rx_one_char_block = 0x40012b9c ); +PROVIDE ( uart_rx_readbuff = 0x40012d1c ); +PROVIDE ( UartRxString = 0x40012c84 ); +PROVIDE ( UartSecureDwnLdProc = 0x40012464 ); +PROVIDE ( UartSetBaudProc = 0x40011e54 ); +PROVIDE ( UartSpiAttachProc = 0x40011e0c ); +PROVIDE ( UartSpiReadProc = 0x40011e28 ); +PROVIDE ( uart_tx_flush = 0x40012b40 ); +PROVIDE ( uart_tx_one_char = 0x40012b10 ); +PROVIDE ( uart_tx_one_char2 = 0x40012b28 ); +PROVIDE ( uart_tx_switch = 0x400128e4 ); +PROVIDE ( uart_tx_wait_idle = 0x40012b6c ); +PROVIDE ( uart_usb_enable_reset_on_rts = 0x40012858 ); +PROVIDE ( Uart_USB_Send_Testament = 0x400127d8 ); +PROVIDE ( usb_cancel_transfer = 0x40015200 ); +PROVIDE ( usb_data_stuff = 0x3ffacc88 ); +PROVIDE ( usb_dc_attach = 0x40013ecc ); +PROVIDE ( usb_dc_check_poll_for_interrupts = 0x40014980 ); +PROVIDE ( usb_dc_detach = 0x40014010 ); +PROVIDE ( usb_dc_ep_check_cap = 0x40014094 ); +PROVIDE ( usb_dc_ep_clear_stall = 0x400142f0 ); +PROVIDE ( usb_dc_ep_configure = 0x400140d8 ); +PROVIDE ( usb_dc_ep_disable = 0x400144ec ); +PROVIDE ( usb_dc_ep_enable = 0x4001442c ); +PROVIDE ( usb_dc_ep_flush = 0x400145b8 ); +PROVIDE ( usb_dc_ep_halt = 0x4001435c ); +PROVIDE ( usb_dc_ep_is_stalled = 0x400143bc ); +PROVIDE ( usb_dc_ep_mps = 0x40014958 ); +PROVIDE ( usb_dc_ep_read = 0x400148d8 ); +PROVIDE ( usb_dc_ep_read_continue = 0x40014898 ); +PROVIDE ( usb_dc_ep_read_wait = 0x400147bc ); +PROVIDE ( usb_dc_ep_set_callback = 0x40014910 ); +PROVIDE ( usb_dc_ep_set_stall = 0x40014290 ); +PROVIDE ( usb_dc_ep_write = 0x40014684 ); +PROVIDE ( usb_dc_ep_write_would_block = 0x40014624 ); +PROVIDE ( usb_dc_prepare_persist = 0x40013bec ); +PROVIDE ( usb_dc_reset = 0x40014044 ); +PROVIDE ( usb_dc_set_address = 0x4001405c ); +PROVIDE ( usb_dc_set_status_callback = 0x4001494c ); +PROVIDE ( usb_deconfig = 0x40014fa8 ); +PROVIDE ( usb_dev_get_configuration = 0x40014f4c ); +PROVIDE ( usb_dev_resume = 0x40014f38 ); +PROVIDE ( usb_dfu_force_detach = 0x400155b0 ); +PROVIDE ( usb_dfu_init = 0x40015598 ); +PROVIDE ( usb_dfu_set_detach_cb = 0x400152dc ); +PROVIDE ( usb_disable = 0x40015058 ); +PROVIDE ( usb_dw_isr_handler = 0x40013c48 ); +PROVIDE ( usb_enable = 0x40014fc8 ); +PROVIDE ( usb_ep_clear_stall = 0x400150c8 ); +PROVIDE ( usb_ep_read_continue = 0x400150f0 ); +PROVIDE ( usb_ep_read_wait = 0x400150d8 ); +PROVIDE ( usb_ep_set_stall = 0x400150b8 ); +PROVIDE ( usb_get_descriptor = 0x400149c0 ); +PROVIDE ( usb_read = 0x400150a0 ); +PROVIDE ( usb_set_config = 0x40014f64 ); +PROVIDE ( usb_set_current_descriptor = 0x400149a8 ); +PROVIDE ( usb_transfer = 0x40015150 ); +PROVIDE ( usb_transfer_ep_callback = 0x40015100 ); +PROVIDE ( usb_transfer_sync = 0x40015250 ); +PROVIDE ( usb_write = 0x40015088 ); +PROVIDE ( usb_write_would_block = 0x40015078 ); +PROVIDE ( user_code_start = 0x3fffe714 ); +PROVIDE ( _UserExceptionVector = 0x40000340 ); +PROVIDE ( _UserExceptionVector_text_end = 0x40000357 ); +PROVIDE ( _UserExceptionVector_text_start = 0x40000340 ); +PROVIDE ( VerifyFlashMd5Proc = 0x40012004 ); +PROVIDE ( Wait_SPI_Idle = 0x40016188 ); +PROVIDE ( _WindowOverflow12 = 0x40000100 ); +PROVIDE ( _WindowOverflow4 = 0x40000000 ); +PROVIDE ( _WindowOverflow8 = 0x40000080 ); +PROVIDE ( _WindowUnderflow12 = 0x40000140 ); +PROVIDE ( _WindowUnderflow4 = 0x40000040 ); +PROVIDE ( _WindowUnderflow8 = 0x400000c0 ); +PROVIDE ( _WindowVectors_text_end = 0x40000170 ); +PROVIDE ( _WindowVectors_text_start = 0x40000000 ); +PROVIDE ( __XT_EXCEPTION_DESCS__ = 0x3ffaff2c ); +PROVIDE ( __XT_EXCEPTION_DESCS_END__ = 0x3ffaff2c ); +PROVIDE ( __XT_EXCEPTION_TABLE__ = 0x3ffafe3a ); +PROVIDE ( xthal_bcopy = 0x4001a918 ); +PROVIDE ( xthal_copy123 = 0x4001a9ac ); +PROVIDE ( xthal_get_ccompare = 0x4001aabc ); +PROVIDE ( xthal_get_ccount = 0x4001aa90 ); +PROVIDE ( xthal_get_interrupt = 0x4001aadc ); +PROVIDE ( Xthal_intlevel = 0x3ffaf06c ); +PROVIDE ( xthal_memcpy = 0x4001a93c ); +PROVIDE ( xthal_set_ccompare = 0x4001aa98 ); +PROVIDE ( xthal_set_intclear = 0x4001aae4 ); +PROVIDE ( xthals_hw_configid0 = 0xc2ecfafe ); +PROVIDE ( xthals_hw_configid1 = 0x224787b1 ); +PROVIDE ( xthals_release_major = 0x00002ee0 ); +PROVIDE ( xthals_release_minor = 0x00000009 ); +PROVIDE ( _xtos_alloca_handler = 0x40000010 ); +PROVIDE ( xtos_cause3_handler = 0x40007370 ); +PROVIDE ( xtos_c_handler_table = 0x3fffec78 ); +PROVIDE ( xtos_c_wrapper_handler = 0x40007380 ); +PROVIDE ( _xtos_enabled = 0x3fffed80 ); +PROVIDE ( xtos_exc_handler_table = 0x3fffeb78 ); +PROVIDE ( xtos_interrupt_mask_table = 0x3fffee88 ); +PROVIDE ( xtos_interrupt_table = 0x3fffed88 ); +PROVIDE ( _xtos_ints_off = 0x4001a3e0 ); +PROVIDE ( _xtos_ints_on = 0x4001a3bc ); +PROVIDE ( _xtos_intstruct = 0x3fffed80 ); +PROVIDE ( _xtos_l1int_handler = 0x400073ec ); +PROVIDE ( xtos_p_none = 0x4001a8a0 ); +PROVIDE ( _xtos_restore_intlevel = 0x400074cc ); +PROVIDE ( _xtos_return_from_exc = 0x4001a8a8 ); +PROVIDE ( _xtos_set_exception_handler = 0x400072b4 ); +PROVIDE ( _xtos_set_interrupt_handler = 0x4001a380 ); +PROVIDE ( _xtos_set_interrupt_handler_arg = 0x4001a344 ); +PROVIDE ( _xtos_set_intlevel = 0x4001a8c0 ); +PROVIDE ( _xtos_set_min_intlevel = 0x4001a8dc ); +PROVIDE ( _xtos_set_vpri = 0x400074d8 ); +PROVIDE ( _xtos_syscall_handler = 0x400072fc ); +PROVIDE ( xtos_unhandled_exception = 0x4001a900 ); +PROVIDE ( xtos_unhandled_interrupt = 0x4001a910 ); +PROVIDE ( _xtos_vectors_ref_ = 0x00000000 ); +PROVIDE ( _xtos_vpri_enabled = 0x3fffed84 ); +PROVIDE ( memchr = 0x4001ab24 ); +PROVIDE ( memcmp = 0x4001ab40 ); +PROVIDE ( memcpy = 0x4001aba8 ); +PROVIDE ( memmove = 0x4001acb0 ); +PROVIDE ( memrchr = 0x4001acec ); +PROVIDE ( memset = 0x4001ad3c ); +PROVIDE ( strchr = 0x4001adb0 ); +PROVIDE ( strcmp = 0x40007be4 ); +PROVIDE ( strcpy = 0x40007cfc ); +PROVIDE ( strlcpy = 0x4001adf8 ); +PROVIDE ( strncpy = 0x40007f20 ); +PROVIDE ( strlen = 0x40007e08 ); +PROVIDE ( strnlen = 0x4001ae9c ); diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/src/Make.defs b/boards/xtensa/esp32s2/esp32s2-saola-1/src/Make.defs new file mode 100644 index 00000000000..ee82d34d362 --- /dev/null +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/src/Make.defs @@ -0,0 +1,73 @@ +############################################################################ +# boards/xtensa/esp32s2/esp32s2-saola-1/src/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +SCRIPTDIR = $(BOARD_DIR)$(DELIM)scripts + +CONFIGFILE = $(TOPDIR)$(DELIM)include$(DELIM)nuttx$(DELIM)config.h + +CSRCS = esp32s2_boot.c esp32s2_bringup.c + +ifeq ($(CONFIG_LIB_BOARDCTL),y) +CSRCS += esp32s2_appinit.c +ifeq ($(CONFIG_BOARDCTL_RESET),y) +CSRCS += esp32s2_reset.c +endif +endif + +ifeq ($(CONFIG_ESP32S2_SPI),y) +CSRCS += esp32s2_spi.c +endif + +ifeq ($(CONFIG_ESP32S2_SPIFLASH),y) +CSRCS += esp32s2_spiflash.c +endif + +ifeq ($(CONFIG_DEV_GPIO),y) +CSRCS += esp32s2_gpio.c +endif + +ifeq ($(CONFIG_USERLED),y) +CSRCS += esp32s2_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += esp32s2_buttons.c +endif + +SCRIPTIN = $(SCRIPTDIR)$(DELIM)esp32s2.template.ld +SCRIPTOUT = $(SCRIPTDIR)$(DELIM)esp32s2_out.ld + +.PHONY = context distclean + +$(SCRIPTOUT): $(SCRIPTIN) $(CONFIGFILE) + $(Q) $(CC) -isystem $(TOPDIR)/include -C -P -x c -E $(SCRIPTIN) -o $@ + +context:: $(SCRIPTOUT) + +distclean:: + $(call DELFILE, $(SCRIPTOUT)) + $(call DELFILE, $(TOPDIR)/esp32s2_qemu_img.bin) + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += $(shell $(INCDIR) "$(CC)" $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board) + diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2-saola-1.h b/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2-saola-1.h new file mode 100644 index 00000000000..7356602c3a2 --- /dev/null +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2-saola-1.h @@ -0,0 +1,140 @@ +/**************************************************************************** + * boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2-saola-1.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_XTENSA_ESP32S2_ESP32S2_CORE_SRC_ESP32S2_CORE_H +#define __BOARDS_XTENSA_ESP32S2_ESP32S2_CORE_SRC_ESP32S2_CORE_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* ESP32S2-DevKitC GPIOs ****************************************************/ + +/* BOOT Button */ + +#define BUTTON_BOOT 0 + +/* LED + * + * This is an externally connected LED used for testing. + */ + +#define GPIO_LED1 2 + +/* MCP2515 Interrupt pin */ + +#define GPIO_MCP2515_IRQ 22 + +/* TIMERS */ + +#define TIMER0 0 +#define TIMER1 1 +#define TIMER2 2 +#define TIMER3 3 + +/* ONESHOT */ + +#define ONESHOT_TIMER 1 +#define ONESHOT_RESOLUTION_US 1 + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32s2_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + * CONFIG_BOARD_LATE_INITIALIZE=y && CONFIG_LIB_BOARDCTL=y : + * Called from the NSH library via board_app_initialize() + * + ****************************************************************************/ + +int esp32s2_bringup(void); + +/**************************************************************************** + * Name: esp32s2_mmcsd_initialize + * + * Description: + * Initialize SPI-based SD card and card detect thread. + ****************************************************************************/ + +int esp32s2_mmcsd_initialize(int minor); + +/**************************************************************************** + * Name: esp32s2_spiflash_init + * + * Description: + * Initialize the SPIFLASH and register the MTD device. + ****************************************************************************/ + +int esp32s2_spiflash_init(void); + +/**************************************************************************** + * Name: esp32s2_spiflash_encrypt_test + * + * Description: + * Test ESP32S2 SPI Flash driver read/write with encryption. + * + * Input Parameters: + * None + * + * Returned Value: + * None. + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32S2_SPIFLASH_ENCRYPTION_TEST +void esp32s2_spiflash_encrypt_test(void); +#endif + +/**************************************************************************** + * Name: esp32s2_gpio_init + ****************************************************************************/ + +#ifdef CONFIG_DEV_GPIO +int esp32s2_gpio_init(void); +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_XTENSA_ESP32S2_ESP32S2_CORE_SRC_ESP32S2_CORE_H */ diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_appinit.c b/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_appinit.c new file mode 100644 index 00000000000..94eef2d5d4b --- /dev/null +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_appinit.c @@ -0,0 +1,80 @@ +/**************************************************************************** + * boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_appinit.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "esp32s2-saola-1.h" + +#ifdef CONFIG_LIB_BOARDCTL + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform application specific initialization. This function is never + * called directly from application code, but only indirectly via the + * (non-standard) boardctl() interface using the command BOARDIOC_INIT. + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initialization logic and the + * matching application logic. The value could be such things as a + * mode enumeration value, a set of DIP switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ +#ifdef CONFIG_BOARD_LATE_INITIALIZE + /* Board initialization already performed by board_late_initialize() */ + + return OK; +#else + /* Perform board-specific initialization */ + + return esp32s2_bringup(); +#endif +} + +#endif /* CONFIG_LIB_BOARDCTL */ diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_boot.c b/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_boot.c new file mode 100644 index 00000000000..857ba140354 --- /dev/null +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_boot.c @@ -0,0 +1,83 @@ +/**************************************************************************** + * boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_boot.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include + +#include "esp32s2-saola-1.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32s2_board_initialize + * + * Description: + * All ESP32 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void esp32s2_board_initialize(void) +{ +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + esp32s2_bringup(); +} +#endif diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_bringup.c b/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_bringup.c new file mode 100644 index 00000000000..171172eb672 --- /dev/null +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_bringup.c @@ -0,0 +1,110 @@ +/**************************************************************************** + * boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_bringup.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#ifdef CONFIG_USERLED +# include +#endif + +#ifdef CONFIG_INPUT_BUTTONS +# include +#endif + +#include "esp32s2-saola-1.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32s2_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + * CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_LIB_BOARDCTL=y : + * Called from the NSH library + * + ****************************************************************************/ + +int esp32s2_bringup(void) +{ + int ret; + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); + } +#endif + +#ifdef CONFIG_FS_TMPFS + /* Mount the tmpfs file system */ + + ret = nx_mount(NULL, CONFIG_LIBC_TMPDIR, "tmpfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount tmpfs at %s: %d\n", + CONFIG_LIBC_TMPDIR, ret); + } +#endif + +#ifdef CONFIG_DEV_GPIO + ret = esp32s2_gpio_init(); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize GPIO Driver: %d\n", ret); + return ret; + } +#endif + + /* If we got here then perhaps not all initialization was successful, but + * at least enough succeeded to bring-up NSH with perhaps reduced + * capabilities. + */ + + UNUSED(ret); + return OK; +} diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_gpio.c b/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_gpio.c new file mode 100644 index 00000000000..4752479c871 --- /dev/null +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_gpio.c @@ -0,0 +1,397 @@ +/**************************************************************************** + * boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_gpio.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include + +#include + +#include "esp32s2-saola-1.h" +#include "esp32s2_gpio.h" +#include "hardware/esp32s2_gpio_sigmap.h" + +#if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if !defined(CONFIG_ESP32S2_GPIO_IRQ) && BOARD_NGPIOINT > 0 +# error "NGPIOINT is > 0 and GPIO interrupts aren't enabled" +#endif + +/* Output pins. GPIO15 is used as an example, any other outputs could be + * used. + */ + +#define GPIO_OUT1 15 + +/* Input pins. GPIO18 is used as an example, any other inputs could be + * used. + */ + +#define GPIO_IN1 18 + +/* Interrupt pins. GPIO20 is used as an example, any other inputs could be + * used. + */ + +#define GPIO_IRQPIN1 20 + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct esp32s2gpio_dev_s +{ + struct gpio_dev_s gpio; + uint8_t id; +}; + +struct esp32s2gpint_dev_s +{ + struct esp32s2gpio_dev_s esp32s2gpio; + pin_interrupt_t callback; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +#if BOARD_NGPIOOUT > 0 +static int gpout_read(FAR struct gpio_dev_s *dev, FAR bool *value); +static int gpout_write(FAR struct gpio_dev_s *dev, bool value); +#endif + +#if BOARD_NGPIOIN > 0 +static int gpin_read(FAR struct gpio_dev_s *dev, FAR bool *value); +#endif + +#if BOARD_NGPIOINT > 0 +static int gpint_read(FAR struct gpio_dev_s *dev, FAR bool *value); +static int gpint_attach(FAR struct gpio_dev_s *dev, + pin_interrupt_t callback); +static int gpint_enable(FAR struct gpio_dev_s *dev, bool enable); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#if BOARD_NGPIOOUT > 0 +static const struct gpio_operations_s gpout_ops = +{ + .go_read = gpout_read, + .go_write = gpout_write, + .go_attach = NULL, + .go_enable = NULL, +}; + +/* This array maps the GPIO pins used as OUTPUT */ + +static const uint32_t g_gpiooutputs[BOARD_NGPIOOUT] = +{ + GPIO_OUT1 +}; + +static struct esp32s2gpio_dev_s g_gpout[BOARD_NGPIOOUT]; +#endif + +#if BOARD_NGPIOIN > 0 +static const struct gpio_operations_s gpin_ops = +{ + .go_read = gpin_read, + .go_write = NULL, + .go_attach = NULL, + .go_enable = NULL, +}; + +/* This array maps the GPIO pins used as INTERRUPT INPUTS */ + +static const uint32_t g_gpioinputs[BOARD_NGPIOIN] = +{ + GPIO_IN1 +}; + +static struct esp32s2gpio_dev_s g_gpin[BOARD_NGPIOIN]; +#endif + +#if BOARD_NGPIOINT > 0 +static const struct gpio_operations_s gpint_ops = +{ + .go_read = gpint_read, + .go_write = NULL, + .go_attach = gpint_attach, + .go_enable = gpint_enable, +}; + +/* This array maps the GPIO pins used as INTERRUPT INPUTS */ + +static const uint32_t g_gpiointinputs[BOARD_NGPIOINT] = +{ + GPIO_IRQPIN1, +}; + +static struct esp32s2gpint_dev_s g_gpint[BOARD_NGPIOINT]; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: gpout_read + ****************************************************************************/ + +#if BOARD_NGPIOOUT > 0 +static int gpout_read(FAR struct gpio_dev_s *dev, FAR bool *value) +{ + FAR struct esp32s2gpio_dev_s *esp32s2gpio = + (FAR struct esp32s2gpio_dev_s *)dev; + + DEBUGASSERT(esp32s2gpio != NULL && value != NULL); + DEBUGASSERT(esp32s2gpio->id < BOARD_NGPIOOUT); + gpioinfo("Reading...\n"); + + *value = esp32s2_gpioread(g_gpiooutputs[esp32s2gpio->id]); + return OK; +} + +/**************************************************************************** + * Name: gpout_write + ****************************************************************************/ + +static int gpout_write(FAR struct gpio_dev_s *dev, bool value) +{ + FAR struct esp32s2gpio_dev_s *esp32s2gpio = + (FAR struct esp32s2gpio_dev_s *)dev; + + DEBUGASSERT(esp32s2gpio != NULL); + DEBUGASSERT(esp32s2gpio->id < BOARD_NGPIOOUT); + gpioinfo("Writing %d\n", (int)value); + + esp32s2_gpiowrite(g_gpiooutputs[esp32s2gpio->id], value); + return OK; +} +#endif + +/**************************************************************************** + * Name: gpin_read + ****************************************************************************/ + +#if BOARD_NGPIOIN > 0 +static int gpin_read(FAR struct gpio_dev_s *dev, FAR bool *value) +{ + FAR struct esp32s2gpio_dev_s *esp32s2gpio = + (FAR struct esp32s2gpio_dev_s *)dev; + + DEBUGASSERT(esp32s2gpio != NULL && value != NULL); + DEBUGASSERT(esp32s2gpio->id < BOARD_NGPIOIN); + gpioinfo("Reading... pin %d\n", g_gpioinputs[esp32s2gpio->id]); + + *value = esp32s2_gpioread(g_gpioinputs[esp32s2gpio->id]); + return OK; +} +#endif + +/**************************************************************************** + * Name: esp32s2gpio_interrupt + ****************************************************************************/ + +#if BOARD_NGPIOINT > 0 +static int esp32s2gpio_interrupt(int irq, void *context, void *arg) +{ + FAR struct esp32s2gpint_dev_s *esp32s2gpint = + (FAR struct esp32s2gpint_dev_s *)arg; + + DEBUGASSERT(esp32s2gpint != NULL && esp32s2gpint->callback != NULL); + gpioinfo("Interrupt! callback=%p\n", esp32s2gpint->callback); + + esp32s2gpint->callback(&esp32s2gpint->esp32s2gpio.gpio, + esp32s2gpint->esp32s2gpio.id); + return OK; +} + +/**************************************************************************** + * Name: gpint_read + ****************************************************************************/ + +static int gpint_read(FAR struct gpio_dev_s *dev, FAR bool *value) +{ + FAR struct esp32s2gpint_dev_s *esp32s2gpint = + (FAR struct esp32s2gpint_dev_s *)dev; + + DEBUGASSERT(esp32s2gpint != NULL && value != NULL); + DEBUGASSERT(esp32s2gpint->esp32s2gpio.id < BOARD_NGPIOINT); + gpioinfo("Reading int pin...\n"); + + *value = esp32s2_gpioread(g_gpiointinputs[esp32s2gpint->esp32s2gpio.id]); + return OK; +} + +/**************************************************************************** + * Name: gpint_attach + ****************************************************************************/ + +static int gpint_attach(FAR struct gpio_dev_s *dev, + pin_interrupt_t callback) +{ + FAR struct esp32s2gpint_dev_s *esp32s2gpint = + (FAR struct esp32s2gpint_dev_s *)dev; + int irq = ESP32S2_PIN2IRQ(g_gpiointinputs[esp32s2gpint->esp32s2gpio.id]); + int ret; + + gpioinfo("Attaching the callback\n"); + + /* Make sure the interrupt is disabled */ + + esp32s2_gpioirqdisable(irq); + ret = irq_attach(irq, + esp32s2gpio_interrupt, + &g_gpint[esp32s2gpint->esp32s2gpio.id]); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: gpint_attach() failed: %d\n", ret); + return ret; + } + + gpioinfo("Attach %p\n", callback); + esp32s2gpint->callback = callback; + return OK; +} + +/**************************************************************************** + * Name: gpint_enable + ****************************************************************************/ + +static int gpint_enable(FAR struct gpio_dev_s *dev, bool enable) +{ + FAR struct esp32s2gpint_dev_s *esp32s2gpint = + (FAR struct esp32s2gpint_dev_s *)dev; + int irq = ESP32S2_PIN2IRQ(g_gpiointinputs[esp32s2gpint->esp32s2gpio.id]); + + if (enable) + { + if (esp32s2gpint->callback != NULL) + { + gpioinfo("Enabling the interrupt\n"); + + /* Configure the interrupt for rising edge */ + + esp32s2_gpioirqenable(irq, RISING); + } + } + else + { + gpioinfo("Disable the interrupt\n"); + esp32s2_gpioirqdisable(irq); + } + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32s2_gpio_init + ****************************************************************************/ + +int esp32s2_gpio_init(void) +{ + int i; + int pincount = 0; + +#if BOARD_NGPIOOUT > 0 + for (i = 0; i < BOARD_NGPIOOUT; i++) + { + /* Setup and register the GPIO pin */ + + g_gpout[i].gpio.gp_pintype = GPIO_OUTPUT_PIN; + g_gpout[i].gpio.gp_ops = &gpout_ops; + g_gpout[i].id = i; + gpio_pin_register(&g_gpout[i].gpio, pincount); + + /* Configure the pins that will be used as output */ + + esp32s2_gpio_matrix_out(g_gpiooutputs[i], SIG_GPIO_OUT_IDX, 0, 0); + esp32s2_configgpio(g_gpiooutputs[i], OUTPUT_FUNCTION_3); + esp32s2_gpiowrite(g_gpiooutputs[i], 0); + + pincount++; + } +#endif + + pincount = 0; + +#if BOARD_NGPIOIN > 0 + for (i = 0; i < BOARD_NGPIOIN; i++) + { + /* Setup and register the GPIO pin */ + + g_gpin[i].gpio.gp_pintype = GPIO_INPUT_PIN; + g_gpin[i].gpio.gp_ops = &gpin_ops; + g_gpin[i].id = i; + gpio_pin_register(&g_gpin[i].gpio, pincount); + + /* Configure the pins that will be used as INPUT */ + + esp32s2_configgpio(g_gpioinputs[i], INPUT_FUNCTION_3); + + pincount++; + } +#endif + + pincount = 0; + +#if BOARD_NGPIOINT > 0 + for (i = 0; i < BOARD_NGPIOINT; i++) + { + /* Setup and register the GPIO pin */ + + g_gpint[i].esp32s2gpio.gpio.gp_pintype = GPIO_INTERRUPT_PIN; + g_gpint[i].esp32s2gpio.gpio.gp_ops = &gpint_ops; + g_gpint[i].esp32s2gpio.id = i; + gpio_pin_register(&g_gpint[i].esp32s2gpio.gpio, pincount); + + /* Configure the pins that will be used as interrupt input */ + + esp32s2_configgpio(g_gpiointinputs[i], INPUT_FUNCTION_3 | PULLDOWN); + + pincount++; + } +#endif + + return OK; +} +#endif /* CONFIG_DEV_GPIO && !CONFIG_GPIO_LOWER_HALF */ diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_reset.c b/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_reset.c new file mode 100644 index 00000000000..8593574aae9 --- /dev/null +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_reset.c @@ -0,0 +1,63 @@ +/**************************************************************************** + * boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_reset.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#ifdef CONFIG_BOARDCTL_RESET + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_reset + * + * Description: + * Reset board. Support for this function is required by board-level + * logic if CONFIG_BOARDCTL_RESET is selected. + * + * Input Parameters: + * status - Status information provided with the reset event. This + * meaning of this status information is board-specific. If not + * used by a board, the value zero may be provided in calls to + * board_reset(). + * + * Returned Value: + * If this function returns, then it was not possible to power-off the + * board due to some constraints. The return value in this case is a + * board-specific reason for the failure to shutdown. + * + ****************************************************************************/ + +int board_reset(int status) +{ + up_systemreset(); + + return 0; +} + +#endif /* CONFIG_BOARDCTL_RESET */