diff --git a/arch/risc-v/src/esp32c3/Kconfig b/arch/risc-v/src/esp32c3/Kconfig index 824dea8878f..2822bb88214 100644 --- a/arch/risc-v/src/esp32c3/Kconfig +++ b/arch/risc-v/src/esp32c3/Kconfig @@ -157,6 +157,10 @@ config ESP32C3_UART bool default n +config ESP32C3_I2C + bool + default n + config ESP32C3_TIMER bool default n @@ -182,6 +186,11 @@ config ESP32C3_UART1 select ESP32C3_UART select UART1_SERIALDRIVER +config ESP32C3_I2C0 + bool "I2C 0" + default n + select ESP32C3_I2C + config ESP32C3_TIMER0 bool "54-bit Timer 0 (Group 0 Timer 0)" default n @@ -223,7 +232,26 @@ config ESP32C3_RWDT to have the RTC module reset, please, use the Timers' Module WDTs. They will only reset Main System. -endmenu +endmenu # ESP32-C3 Peripheral Support + +menu "I2C Configuration" + depends on ESP32C3_I2C + +if ESP32C3_I2C0 + +config ESP32C3_I2C0_SCLPIN + int "I2C0 SCL Pin" + default 6 + range 0 21 + +config ESP32C3_I2C0_SDAPIN + int "I2C0 SDA Pin" + default 5 + range 0 21 + +endif # ESP32C3_I2C0 + +endmenu # I2C configuration menu "UART configuration" depends on ESP32C3_UART diff --git a/arch/risc-v/src/esp32c3/Make.defs b/arch/risc-v/src/esp32c3/Make.defs index dc2db38e660..37f5b2421fa 100644 --- a/arch/risc-v/src/esp32c3/Make.defs +++ b/arch/risc-v/src/esp32c3/Make.defs @@ -59,6 +59,10 @@ ifeq ($(CONFIG_ESP32C3_UART),y) CHIP_CSRCS += esp32c3_serial.c endif +ifeq ($(CONFIG_ESP32C3_I2C),y) +CHIP_CSRCS += esp32c3_i2c.c +endif + ifeq ($(CONFIG_ESP32C3_WDT),y) CHIP_CSRCS += esp32c3_wdt.c ifeq ($(CONFIG_WATCHDOG),y) diff --git a/arch/risc-v/src/esp32c3/esp32c3_i2c.c b/arch/risc-v/src/esp32c3/esp32c3_i2c.c new file mode 100644 index 00000000000..ded1aa34238 --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3_i2c.c @@ -0,0 +1,1131 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/esp32c3_i2c.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifdef CONFIG_ESP32C3_I2C + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include + +#include "esp32c3_i2c.h" +#include "esp32c3_irq.h" +#include "esp32c3_gpio.h" + +#include "riscv_arch.h" +#include "hardware/esp32c3_gpio_sigmap.h" +#include "hardware/esp32c3_i2c.h" +#include "hardware/esp32c3_soc.h" +#include "hardware/esp32c3_system.h" + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/* Helper for applying the mask for a given register field. + * Mask is determined by the macros suffixed with _V and _S from the + * peripheral register description. + */ + +#define I2C_VALUE_MASK(_val, _field) ((_val & (_field##_V)) << (_field##_S)) + +/* Command format */ + +#define I2C_BASE_CMD(_cmd, _check_ack) (((_cmd) << 11) + \ + ((_check_ack) << 8)) + +#define I2C_SEND_CMD(_cmd, _check_ack, _bytes) (((_cmd) << 11) + \ + ((_check_ack) << 8) + \ + (_bytes)) + +#define I2C_RECV_CMD(_cmd, _ack_val, _bytes) (((_cmd) << 11) + \ + ((_ack_val) << 10) + \ + (_bytes)) + +/* I2C hardware FIFO depth */ + +#define I2C_FIFO_SIZE (32) + +/* Number of bus cycles filtered by default */ + +#define I2C_FILTER_CYC_NUM_DEF (7) + +/* I2C default clock frequency */ + +#define I2C_CLK_FREQ_DEF (100 * 1000) + +/* Mask for the interrupt errors */ + +#define I2C_INT_ERR_MASK (I2C_NACK_INT_ENA_M | \ + I2C_TIME_OUT_INT_ENA_M | \ + I2C_ARBITRATION_LOST_INT_ENA_M) + +/* I2C state */ + +enum esp32c3_i2cstate_e +{ + I2CSTATE_IDLE = 0, + I2CSTATE_PROC, + I2CSTATE_STOP, + I2CSTATE_FINISH, + I2CSTATE_ERROR +}; + +/* I2C hardware command */ + +enum i2c_opmode_e +{ + I2C_CMD_RESTART = 6, /* I2C restart command */ + I2C_CMD_WRITE = 1, /* I2C write command */ + I2C_CMD_READ = 3, /* I2C read command */ + I2C_CMD_STOP = 2, /* I2C stop command */ + I2C_CMD_END = 4 /* I2C end command */ +}; + +/* I2C Device hardware configuration */ + +struct esp32c3_i2c_config_s +{ + uint32_t clk_freq; /* Clock frequency */ + + uint8_t scl_pin; /* GPIO configuration for SCL as SCL */ + uint8_t sda_pin; /* GPIO configuration for SDA as SDA */ + + uint8_t periph; /* Peripheral ID */ + uint8_t irq; /* Interrupt ID */ + + uint32_t clk_bit; /* Clock enable bit */ + uint32_t rst_bit; /* I2C reset bit */ + + uint32_t scl_insig; /* I2C SCL input signal index */ + uint32_t scl_outsig; /* I2C SCL output signal index */ + + uint32_t sda_insig; /* I2C SDA input signal index */ + uint32_t sda_outsig; /* I2C SDA output signal index */ +}; + +/* I2C Device Private Data */ + +struct esp32c3_i2c_priv_s +{ + const struct i2c_ops_s *ops; /* Standard I2C operations */ + + uint32_t id; /* I2C instance */ + + /* Port configuration */ + + const struct esp32c3_i2c_config_s *config; + int refs; /* Reference count */ + sem_t sem_excl; /* Mutual exclusion semaphore */ + sem_t sem_isr; /* Interrupt wait semaphore */ + + /* I2C work state (see enum esp32c3_i2cstate_e) */ + + volatile enum esp32c3_i2cstate_e i2cstate; + + struct i2c_msg_s *msgv; /* Message list */ + + uint8_t msgid; /* Current message ID */ + ssize_t bytes; /* Processed data bytes */ + + int cpuint; /* CPU interrupt assigned to this I2C */ + + uint32_t error; /* I2C transform error */ + + bool ready_read; /* If I2C is ready for receiving data */ + + uint32_t clk_freq; /* Current I2C Clock frequency */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static void esp32c3_i2c_init_clock(struct esp32c3_i2c_priv_s *priv, + uint32_t clock); +static void esp32c3_i2c_init(struct esp32c3_i2c_priv_s *priv); +static void esp32c3_i2c_deinit(struct esp32c3_i2c_priv_s *priv); +static int esp32c3_i2c_transfer(struct i2c_master_s *dev, + struct i2c_msg_s *msgs, + int count); +#ifdef CONFIG_I2C_RESET +static int esp32c3_i2c_reset(struct i2c_master_s *dev); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* I2C interface */ + +static const struct i2c_ops_s esp32c3_i2c_ops = +{ + .transfer = esp32c3_i2c_transfer +#ifdef CONFIG_I2C_RESET + , .reset = esp32c3_i2c_reset +#endif +}; + +#ifdef CONFIG_ESP32C3_I2C0 + +/* I2C device structure */ + +static const struct esp32c3_i2c_config_s esp32c3_i2c0_config = +{ + .clk_freq = I2C_CLK_FREQ_DEF, + .scl_pin = CONFIG_ESP32C3_I2C0_SCLPIN, + .sda_pin = CONFIG_ESP32C3_I2C0_SDAPIN, + .periph = ESP32C3_PERIPH_I2C_EXT0, + .irq = ESP32C3_IRQ_I2C_EXT0, + .clk_bit = SYSTEM_I2C_EXT0_CLK_EN, + .rst_bit = SYSTEM_I2C_EXT0_RST, + .scl_insig = I2CEXT0_SCL_IN_IDX, + .scl_outsig = I2CEXT0_SCL_OUT_IDX, + .sda_insig = I2CEXT0_SDA_IN_IDX, + .sda_outsig = I2CEXT0_SDA_OUT_IDX +}; + +static struct esp32c3_i2c_priv_s esp32c3_i2c0_priv = +{ + .ops = &esp32c3_i2c_ops, + .id = 0, + .config = &esp32c3_i2c0_config, + .refs = 0, + .i2cstate = I2CSTATE_IDLE, + .msgv = NULL, + .msgid = 0, + .bytes = 0, + .cpuint = -ENOMEM, + .error = 0, + .ready_read = false, + .clk_freq = 0 +}; + +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_i2c_reset_fifo + * + * Description: + * Reset I2C RX and TX hardware FIFO. + * + * Parameters: + * priv - Pointer to the internal driver state structure. + * + ****************************************************************************/ + +static void esp32c3_i2c_reset_fifo(struct esp32c3_i2c_priv_s *priv) +{ + uint32_t bits = (I2C_TX_FIFO_RST_M | I2C_RX_FIFO_RST_M); + + modifyreg32(I2C_FIFO_CONF_REG(priv->id), 0, bits); + modifyreg32(I2C_FIFO_CONF_REG(priv->id), bits, 0); +} + +/**************************************************************************** + * Name: esp32c3_i2c_intr_enable + * + * Description: + * Enable I2C interrupts. + * + * Parameters: + * priv - Pointer to the internal driver state structure. + * + ****************************************************************************/ + +static void esp32c3_i2c_intr_enable(struct esp32c3_i2c_priv_s *priv) +{ + putreg32(UINT32_MAX, I2C_INT_CLR_REG(priv->id)); + + putreg32(I2C_TRANS_COMPLETE_INT_ENA_M | I2C_END_DETECT_INT_ENA_M | + I2C_INT_ERR_MASK, I2C_INT_ENA_REG(priv->id)); +} + +/**************************************************************************** + * Name: esp32c3_i2c_intr_disable + * + * Description: + * Disable I2C interrupts. + * + * Parameters: + * priv - Pointer to the internal driver state structure. + * + ****************************************************************************/ + +static void esp32c3_i2c_intr_disable(struct esp32c3_i2c_priv_s *priv) +{ + putreg32(0, I2C_INT_ENA_REG(priv->id)); + + putreg32(UINT32_MAX, I2C_INT_CLR_REG(priv->id)); +} + +/**************************************************************************** + * Name: esp32c3_i2c_sendstart + * + * Description: + * Send I2C start signal. + * + * Parameters: + * priv - Pointer to the internal driver state structure. + * + ****************************************************************************/ + +static void esp32c3_i2c_sendstart(struct esp32c3_i2c_priv_s *priv) +{ + struct i2c_msg_s *msg = &priv->msgv[priv->msgid]; + + /* Write I2C command registers */ + + putreg32(I2C_BASE_CMD(I2C_CMD_RESTART, 0), I2C_COMD0_REG(priv->id)); + putreg32(I2C_SEND_CMD(I2C_CMD_WRITE, 1, 1), I2C_COMD1_REG(priv->id)); + putreg32(I2C_BASE_CMD(I2C_CMD_END, 0), I2C_COMD2_REG(priv->id)); + + /* Write data to FIFO register */ + + putreg32((msg->addr << 1) | (msg->flags & I2C_M_READ), + I2C_DATA_REG(priv->id)); + + /* Enable I2C master TX interrupt */ + + esp32c3_i2c_intr_enable(priv); + + /* Update I2C configuration */ + + modifyreg32(I2C_CTR_REG(priv->id), 0, I2C_CONF_UPGATE_M); + + /* Configure the I2C to trigger a transaction */ + + modifyreg32(I2C_CTR_REG(priv->id), 0, I2C_TRANS_START_M); +} + +/**************************************************************************** + * Name: esp32c3_i2c_senddata + * + * Description: + * Send I2C data. + * + * Parameters: + * priv - Pointer to the internal driver state structure. + * + ****************************************************************************/ + +static void esp32c3_i2c_senddata(struct esp32c3_i2c_priv_s *priv) +{ + struct i2c_msg_s *msg = &priv->msgv[priv->msgid]; + int n = msg->length - priv->bytes; + + n = n < I2C_FIFO_SIZE ? n : I2C_FIFO_SIZE; + + putreg32(I2C_SEND_CMD(I2C_CMD_WRITE, 1, n), I2C_COMD0_REG(priv->id)); + putreg32(I2C_BASE_CMD(I2C_CMD_END, 0), I2C_COMD1_REG(priv->id)); + + for (int i = 0; i < n; i++) + { + putreg32(msg->buffer[priv->bytes + i], I2C_DATA_REG(priv->id)); + } + + priv->bytes += n; + + /* Enable I2C master TX interrupt */ + + esp32c3_i2c_intr_enable(priv); + + /* Update I2C configuration */ + + modifyreg32(I2C_CTR_REG(priv->id), 0, I2C_CONF_UPGATE_M); + + /* Configure the I2C to trigger a transaction */ + + modifyreg32(I2C_CTR_REG(priv->id), 0, I2C_TRANS_START_M); +} + +/**************************************************************************** + * Name: esp32c3_i2c_recvdata + * + * Description: + * Receive I2C data. + * + * Parameters: + * priv - Pointer to the internal driver state structure. + * + ****************************************************************************/ + +static void esp32c3_i2c_recvdata(struct esp32c3_i2c_priv_s *priv) +{ + struct i2c_msg_s *msg = &priv->msgv[priv->msgid]; + uint32_t cmd = getreg32(I2C_COMD0_REG(priv->id)); + uint8_t n = cmd & 0xff; + uint32_t data = 0; + + for (int i = 0; i < n; i++) + { + data = getreg32(I2C_DATA_REG(priv->id)); + msg->buffer[priv->bytes + i] = data & 0xff; + } + + priv->bytes += n; +} + +/**************************************************************************** + * Name: esp32c3_i2c_startrecv + * + * Description: + * Configure I2C to prepare receiving data and it will create an interrupt + * to receive real data. + * + * Parameters: + * priv - Pointer to the internal driver state structure. + * + ****************************************************************************/ + +static void esp32c3_i2c_startrecv(struct esp32c3_i2c_priv_s *priv) +{ + int ack_value; + struct i2c_msg_s *msg = &priv->msgv[priv->msgid]; + int n = msg->length - priv->bytes; + + if (n > 1) + { + n -= 1; + n = n < I2C_FIFO_SIZE ? n : I2C_FIFO_SIZE; + ack_value = 0; + } + else + { + ack_value = 1; + } + + putreg32(I2C_RECV_CMD(I2C_CMD_READ, ack_value, n), + I2C_COMD0_REG(priv->id)); + putreg32(I2C_BASE_CMD(I2C_CMD_END, 0), I2C_COMD1_REG(priv->id)); + + /* Enable I2C master RX interrupt */ + + esp32c3_i2c_intr_enable(priv); + + /* Update I2C configuration */ + + modifyreg32(I2C_CTR_REG(priv->id), 0, I2C_CONF_UPGATE_M); + + /* Configure the I2C to trigger a transaction */ + + modifyreg32(I2C_CTR_REG(priv->id), 0, I2C_TRANS_START_M); +} + +/**************************************************************************** + * Name: esp32c3_i2c_sendstop + * + * Description: + * Send I2C STOP signal. + * + * Parameters: + * priv - Pointer to the internal driver state structure. + * + ****************************************************************************/ + +static void esp32c3_i2c_sendstop(struct esp32c3_i2c_priv_s *priv) +{ + putreg32(I2C_BASE_CMD(I2C_CMD_STOP, 0), I2C_COMD0_REG(priv->id)); + + /* Enable I2C master TX interrupt */ + + esp32c3_i2c_intr_enable(priv); + + /* Update I2C configuration */ + + modifyreg32(I2C_CTR_REG(priv->id), 0, I2C_CONF_UPGATE_M); + + /* Configure the I2C to trigger a transaction */ + + modifyreg32(I2C_CTR_REG(priv->id), 0, I2C_TRANS_START_M); +} + +/**************************************************************************** + * Name: esp32c3_i2c_init_clock + * + * Description: + * Initialize I2C hardware clock. + * + * Parameters: + * priv - Pointer to the internal driver state structure. + * bus_freq - Clock frequency of the I2C bus in Hz. + * + ****************************************************************************/ + +static void esp32c3_i2c_init_clock(struct esp32c3_i2c_priv_s *priv, + uint32_t bus_freq) +{ + if (bus_freq == priv->clk_freq) + { + return ; + } + + uint32_t reg_value = 0; + uint32_t scl_wait_high = 0; + uint32_t scl_high = 0; + uint32_t timeout_cycles = 0; + uint32_t source_clk = XTAL_CLK_FREQ; + uint32_t clkm_div = (source_clk / (bus_freq * 1024)) + 1; + uint32_t sclk_freq = source_clk / clkm_div; + uint32_t half_cycle = sclk_freq / bus_freq / 2; + + reg_value = I2C_VALUE_MASK((clkm_div - 1), I2C_SCLK_DIV_NUM); + modifyreg32(I2C_CLK_CONF_REG(priv->id), + I2C_SCLK_SEL_M | I2C_SCLK_DIV_NUM_M, reg_value); + + putreg32(half_cycle - 1, I2C_SCL_LOW_PERIOD_REG(priv->id)); + + /* By default, scl_wait_high must be less than scl_high. + * A time compensation is needed for when the bus frequency is higher + * than 50K. + */ + + scl_wait_high = (bus_freq <= 50000) ? 0 : (half_cycle / 8); + scl_high = half_cycle - scl_wait_high; + + reg_value = I2C_VALUE_MASK(scl_high, I2C_SCL_HIGH_PERIOD); + reg_value |= I2C_VALUE_MASK(scl_wait_high, I2C_SCL_WAIT_HIGH_PERIOD); + putreg32(reg_value, I2C_SCL_HIGH_PERIOD_REG(priv->id)); + + putreg32(half_cycle / 4, I2C_SDA_HOLD_REG(priv->id)); + + /* scl_wait_high < sda_sample <= scl_high */ + + putreg32(half_cycle / 2, I2C_SDA_SAMPLE_REG(priv->id)); + + putreg32(half_cycle, I2C_SCL_RSTART_SETUP_REG(priv->id)); + putreg32(half_cycle, I2C_SCL_STOP_SETUP_REG(priv->id)); + putreg32(half_cycle - 1, I2C_SCL_START_HOLD_REG(priv->id)); + putreg32(half_cycle, I2C_SCL_STOP_HOLD_REG(priv->id)); + + /* By default, we set the timeout value to about 10 bus cycles + * log(20*half_cycle)/log(2) = log(half_cycle)/log(2) + log(20)/log(2) + */ + + timeout_cycles = sizeof(half_cycle) * 8; + timeout_cycles -= __builtin_clz(5 * half_cycle); + timeout_cycles += 2; + + reg_value = I2C_TIME_OUT_EN_M; + reg_value |= I2C_VALUE_MASK(timeout_cycles, I2C_TIME_OUT_REG); + putreg32(reg_value, I2C_TO_REG(priv->id)); + + priv->clk_freq = bus_freq; +} + +/**************************************************************************** + * Name: esp32c3_i2c_init + * + * Description: + * Initialize I2C hardware. + * + * Parameters: + * priv - Pointer to the internal driver state structure. + * + ****************************************************************************/ + +static void esp32c3_i2c_init(struct esp32c3_i2c_priv_s *priv) +{ + const struct esp32c3_i2c_config_s *config = priv->config; + + /* Configure GPIO signals for I2C SCL and SDA pins */ + + esp32c3_gpiowrite(config->scl_pin, 1); + esp32c3_gpiowrite(config->sda_pin, 1); + + esp32c3_configgpio(config->scl_pin, INPUT_PULLUP | OUTPUT_OPEN_DRAIN); + esp32c3_gpio_matrix_out(config->scl_pin, config->scl_outsig, 0, 0); + esp32c3_gpio_matrix_in(config->scl_pin, config->scl_insig, 0); + + esp32c3_configgpio(config->sda_pin, INPUT_PULLUP | OUTPUT_OPEN_DRAIN); + esp32c3_gpio_matrix_out(config->sda_pin, config->sda_outsig, 0, 0); + esp32c3_gpio_matrix_in(config->sda_pin, config->sda_insig, 0); + + /* Enable I2C hardware */ + + modifyreg32(SYSTEM_PERIP_CLK_EN0_REG, 0, config->clk_bit); + modifyreg32(SYSTEM_PERIP_RST_EN0_REG, config->rst_bit, 0); + + /* Disable I2C interrupts */ + + esp32c3_i2c_intr_disable(priv); + + /* Initialize I2C Master */ + + putreg32(I2C_MS_MODE_M | I2C_CLK_EN_M | + I2C_SCL_FORCE_OUT_M | I2C_SDA_FORCE_OUT_M, + I2C_CTR_REG(priv->id)); + + /* Set FIFO mode */ + + modifyreg32(I2C_FIFO_CONF_REG(priv->id), I2C_NONFIFO_EN_M, 0); + + /* Ensure I2C data mode is set to MSB */ + + modifyreg32(I2C_CTR_REG(priv->id), + (I2C_TX_LSB_FIRST_M | I2C_RX_LSB_FIRST_M), 0); + + esp32c3_i2c_reset_fifo(priv); + + /* Configure the hardware filter function */ + + putreg32(I2C_SCL_FILTER_EN_M | I2C_SDA_FILTER_EN_M | + I2C_VALUE_MASK(I2C_FILTER_CYC_NUM_DEF, + I2C_SCL_FILTER_THRES) | + I2C_VALUE_MASK(I2C_FILTER_CYC_NUM_DEF, + I2C_SDA_FILTER_THRES), + I2C_FILTER_CFG_REG(priv->id)); + + /* Initialize I2C bus clock */ + + esp32c3_i2c_init_clock(priv, config->clk_freq); +} + +/**************************************************************************** + * Name: esp32c3_i2c_deinit + * + * Description: + * Disable I2C hardware. + * + * Parameters: + * priv - Pointer to the internal driver state structure. + * + ****************************************************************************/ + +static void esp32c3_i2c_deinit(struct esp32c3_i2c_priv_s *priv) +{ + const struct esp32c3_i2c_config_s *config = priv->config; + + priv->clk_freq = 0; + + modifyreg32(SYSTEM_PERIP_RST_EN0_REG, 0, config->rst_bit); + modifyreg32(SYSTEM_PERIP_CLK_EN0_REG, config->clk_bit, 0); +} + +/**************************************************************************** + * Name: esp32c3_i2c_reset_fsmc + * + * Description: + * Reset I2C hardware state machine and registers. + * + * Parameters: + * priv - Pointer to the internal driver state structure. + * + ****************************************************************************/ + +static void esp32c3_i2c_reset_fsmc(struct esp32c3_i2c_priv_s *priv) +{ + esp32c3_i2c_deinit(priv); + esp32c3_i2c_init(priv); +} + +/**************************************************************************** + * Name: esp32c3_i2c_sem_waitdone + * + * Description: + * Wait for a transfer to complete. + * + * Parameters: + * priv - Pointer to the internal driver state structure. + * + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned on + * failure. + * + ****************************************************************************/ + +static int esp32c3_i2c_sem_waitdone(struct esp32c3_i2c_priv_s *priv) +{ + int ret; + struct timespec abstime; + + clock_gettime(CLOCK_REALTIME, &abstime); + + abstime.tv_sec += 10; + abstime.tv_nsec += 0; + + ret = nxsem_timedwait_uninterruptible(&priv->sem_isr, &abstime); + + return ret; +} + +/**************************************************************************** + * Name: esp32c3_i2c_sem_wait + * + * Description: + * Take the exclusive access, waiting as necessary. + * + * Parameters: + * priv - Pointer to the internal driver state structure. + * + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned on + * failure. + * + ****************************************************************************/ + +static int esp32c3_i2c_sem_wait(struct esp32c3_i2c_priv_s *priv) +{ + return nxsem_wait_uninterruptible(&priv->sem_excl); +} + +/**************************************************************************** + * Name: esp32c3_i2c_sem_post + * + * Description: + * Release the mutual exclusion semaphore. + * + * Parameters: + * priv - Pointer to the internal driver state structure. + * + ****************************************************************************/ + +static void esp32c3_i2c_sem_post(struct esp32c3_i2c_priv_s *priv) +{ + nxsem_post(&priv->sem_excl); +} + +/**************************************************************************** + * Name: esp32c3_i2c_sem_destroy + * + * Description: + * Destroy semaphores. + * + * Parameters: + * priv - Pointer to the internal driver state structure. + * + ****************************************************************************/ + +static void esp32c3_i2c_sem_destroy(struct esp32c3_i2c_priv_s *priv) +{ + nxsem_destroy(&priv->sem_excl); + nxsem_destroy(&priv->sem_isr); +} + +/**************************************************************************** + * Name: esp32c3_i2c_sem_init + * + * Description: + * Initialize semaphores. + * + * Parameters: + * priv - Pointer to the internal driver state structure. + * + ****************************************************************************/ + +static inline void esp32c3_i2c_sem_init(struct esp32c3_i2c_priv_s *priv) +{ + nxsem_init(&priv->sem_excl, 0, 1); + + /* This semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + + nxsem_init(&priv->sem_isr, 0, 0); + nxsem_set_protocol(&priv->sem_isr, SEM_PRIO_NONE); +} + +/**************************************************************************** + * Device Driver Operations + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_i2c_transfer + * + * Description: + * Generic I2C transfer function. + * + * Parameters: + * dev - Device-specific state data + * msgs - A pointer to a set of message descriptors + * count - The number of transfers to perform + * + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned on + * failure. + * + ****************************************************************************/ + +static int esp32c3_i2c_transfer(struct i2c_master_s *dev, + struct i2c_msg_s *msgs, + int count) +{ + int ret = OK; + struct esp32c3_i2c_priv_s *priv = (struct esp32c3_i2c_priv_s *)dev; + + i2cinfo("Starting transfer request of %d message(s):\n", count); + + DEBUGASSERT(count > 0); + + ret = esp32c3_i2c_sem_wait(priv); + if (ret < 0) + { + return ret; + } + + if (priv->i2cstate != I2CSTATE_IDLE) + { + esp32c3_i2c_reset_fsmc(priv); + priv->i2cstate = I2CSTATE_IDLE; + } + + priv->msgv = msgs; + + for (int i = 0; i < count; i++) + { + esp32c3_i2c_reset_fifo(priv); + + priv->bytes = 0; + priv->msgid = i; + priv->ready_read = false; + priv->error = 0; + priv->i2cstate = I2CSTATE_PROC; + + i2cinfo("Sending message %" PRIu8 "...\n", priv->msgid); + + esp32c3_i2c_init_clock(priv, msgs[i].frequency); + + esp32c3_i2c_sendstart(priv); + + if (esp32c3_i2c_sem_waitdone(priv) < 0) + { + i2cinfo("Message %" PRIu8 " timed out.\n", priv->msgid); + ret = -ETIMEDOUT; + break; + } + else + { + if (priv->error != 0) + { + i2cinfo("Transfer error %" PRIu32 "\n", priv->error); + ret = -EIO; + break; + } + else + { + priv->i2cstate = I2CSTATE_IDLE; + ret = OK; + } + } + + i2cinfo("Message %" PRIu8 " transfer complete.\n", priv->msgid); + } + + esp32c3_i2c_sem_post(priv); + + return ret; +} + +/**************************************************************************** + * Name: esp32c3_i2c_reset + * + * Description: + * Perform an I2C bus reset in an attempt to break loose stuck I2C devices. + * + * Parameters: + * dev - Device-specific state data + * + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned on + * failure. + * + ****************************************************************************/ + +#ifdef CONFIG_I2C_RESET +static int esp32c3_i2c_reset(struct i2c_master_s *dev) +{ + irqstate_t flags; + struct esp32c3_i2c_priv_s *priv = (struct esp32c3_i2c_priv_s *)dev; + + DEBUGASSERT(dev); + + DEBUGASSERT(priv->refs > 0); + + flags = enter_critical_section(); + + esp32c3_i2c_reset_fsmc(priv); + + priv->i2cstate = I2CSTATE_IDLE; + priv->msgid = 0; + priv->bytes = 0; + priv->ready_read = false; + + leave_critical_section(flags); + + return OK; +} +#endif + +/**************************************************************************** + * Name: esp32c3_i2c_irq + * + * Description: + * This is the common I2C interrupt handler. It will be invoked when an + * interrupt is received on the device. + * + * Parameters: + * cpuint - CPU interrupt index + * context - Context data from the ISR + * arg - Opaque pointer to the internal driver state structure. + * + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned on + * failure. + * + ****************************************************************************/ + +static int esp32c3_i2c_irq(int cpuint, void *context, void *arg) +{ + struct esp32c3_i2c_priv_s *priv = (struct esp32c3_i2c_priv_s *)arg; + struct i2c_msg_s *msg = &priv->msgv[priv->msgid]; + + uint32_t status = getreg32(I2C_INT_STATUS_REG(priv->id)); + putreg32(status, I2C_INT_CLR_REG(priv->id)); + + if (I2C_INT_ERR_MASK & status) + { + priv->error = status & I2C_INT_ERR_MASK; + priv->i2cstate = I2CSTATE_ERROR; + esp32c3_i2c_intr_disable(priv); + nxsem_post(&priv->sem_isr); + } + else + { + if (priv->i2cstate == I2CSTATE_PROC) + { + if (msg->flags & I2C_M_READ) + { + if (priv->ready_read) + { + esp32c3_i2c_recvdata(priv); + + priv->ready_read = false; + } + + if (priv->bytes == msg->length) + { + esp32c3_i2c_sendstop(priv); + + priv->i2cstate = I2CSTATE_FINISH; + } + else + { + esp32c3_i2c_startrecv(priv); + + priv->ready_read = true; + } + } + else + { + esp32c3_i2c_senddata(priv); + + if (priv->bytes == msg->length) + { + priv->i2cstate = I2CSTATE_STOP; + } + } + } + else if (priv->i2cstate == I2CSTATE_STOP) + { + esp32c3_i2c_sendstop(priv); + + priv->i2cstate = I2CSTATE_FINISH; + } + else if (priv->i2cstate == I2CSTATE_FINISH) + { + nxsem_post(&priv->sem_isr); + } + } + + return 0; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_i2cbus_initialize + * + * Description: + * Initialize the selected I2C port. And return a pointer to an unique + * instance of struct i2c_master_s. This function may be called to obtain + * multiple instances of the interface, each of which may be set up with a + * different frequency and slave address. + * + * Parameters: + * port - Port number of the I2C interface to be initialized. + * + * Returned Value: + * Pointer to valid I2C device structure is returned on success. + * A NULL pointer is returned on failure. + * + ****************************************************************************/ + +struct i2c_master_s *esp32c3_i2cbus_initialize(int port) +{ + int ret; + irqstate_t flags; + struct esp32c3_i2c_priv_s *priv; + const struct esp32c3_i2c_config_s *config; + + switch (port) + { +#ifdef CONFIG_ESP32C3_I2C0 + case 0: + priv = &esp32c3_i2c0_priv; + break; +#endif + default: + return NULL; + } + + config = priv->config; + + flags = enter_critical_section(); + + if ((volatile int)priv->refs++ != 0) + { + leave_critical_section(flags); + + i2cinfo("Returning previously initialized I2C bus. " + "Handler: %" PRIxPTR "\n", (uintptr_t)priv); + + return (struct i2c_master_s *)priv; + } + + if (priv->cpuint != -ENOMEM) + { + /* Disable the provided CPU Interrupt to configure it. */ + + up_disable_irq(priv->cpuint); + } + + priv->cpuint = esp32c3_request_irq(config->periph, + ESP32C3_INT_PRIO_DEF, + ESP32C3_INT_LEVEL); + if (priv->cpuint < 0) + { + /* Failed to allocate a CPU interrupt of this type. */ + + leave_critical_section(flags); + + return NULL; + } + + ret = irq_attach(config->irq, esp32c3_i2c_irq, priv); + if (ret != OK) + { + /* Failed to attach IRQ, so CPU interrupt must be freed. */ + + esp32c3_free_cpuint(config->periph); + priv->cpuint = -ENOMEM; + leave_critical_section(flags); + + return NULL; + } + + /* Enable the CPU interrupt that is linked to the I2C device. */ + + up_enable_irq(priv->cpuint); + + esp32c3_i2c_sem_init(priv); + + esp32c3_i2c_init(priv); + + leave_critical_section(flags); + + i2cinfo("I2C bus initialized! Handler: %" PRIxPTR "\n", (uintptr_t)priv); + + return (struct i2c_master_s *)priv; +} + +/**************************************************************************** + * Name: esp32c3_i2cbus_uninitialize + * + * Description: + * De-initialize the selected I2C port and power down the device. + * + * Parameters: + * dev - Device structure as returned by + * esp32c3_i2cbus_initialize() + * + * Returned Value: + * OK is returned on success. ERROR is returned when internal reference + * count mismatches or dev points to invalid hardware device. + * + ****************************************************************************/ + +int esp32c3_i2cbus_uninitialize(struct i2c_master_s *dev) +{ + irqstate_t flags; + struct esp32c3_i2c_priv_s *priv = (struct esp32c3_i2c_priv_s *)dev; + + DEBUGASSERT(dev); + + if (priv->refs == 0) + { + return ERROR; + } + + flags = enter_critical_section(); + + if (--priv->refs) + { + leave_critical_section(flags); + return OK; + } + + leave_critical_section(flags); + + up_disable_irq(priv->cpuint); + esp32c3_free_cpuint(priv->config->periph); + priv->cpuint = -ENOMEM; + + esp32c3_i2c_deinit(priv); + + esp32c3_i2c_sem_destroy(priv); + + return OK; +} + +#endif /* CONFIG_ESP32C3_I2C */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_i2c.h b/arch/risc-v/src/esp32c3/esp32c3_i2c.h new file mode 100644 index 00000000000..115e7d0d135 --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3_i2c.h @@ -0,0 +1,94 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/esp32c3_i2c.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_I2C_H +#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_I2C_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_i2cbus_initialize + * + * Description: + * Initialize the selected I2C port. And return a pointer to an unique + * instance of struct i2c_master_s. This function may be called to obtain + * multiple instances of the interface, each of which may be set up with a + * different frequency and slave address. + * + * Input Parameters: + * port - Port number of the I2C interface to be initialized. + * + * Returned Value: + * Pointer to valid I2C device structure is returned on success. + * A NULL pointer is returned on failure. + * + ****************************************************************************/ + +struct i2c_master_s *esp32c3_i2cbus_initialize(int port); + +/**************************************************************************** + * Name: esp32c3_i2cbus_uninitialize + * + * Description: + * De-initialize the selected I2C port and power down the device. + * + * Input Parameters: + * dev - Device structure as returned by + * esp32c3_i2cbus_initialize() + * + * Returned Value: + * OK is returned on success. ERROR is returned when internal reference + * count mismatches or dev points to invalid hardware device. + * + ****************************************************************************/ + +int esp32c3_i2cbus_uninitialize(struct i2c_master_s *dev); + +#ifdef __cplusplus +} +#endif +#undef EXTERN + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_I2C_H */ diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_i2c.h b/arch/risc-v/src/esp32c3/hardware/esp32c3_i2c.h new file mode 100644 index 00000000000..90836487d94 --- /dev/null +++ b/arch/risc-v/src/esp32c3/hardware/esp32c3_i2c.h @@ -0,0 +1,1226 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/hardware/esp32c3_i2c.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_I2C_H +#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_I2C_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32c3_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define I2C_SCL_LOW_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x0) + +/* I2C_SCL_LOW_PERIOD : R/W ;bitpos:[8:0] ;default: 9'b0 ; */ + +#define I2C_SCL_LOW_PERIOD 0x000001FF +#define I2C_SCL_LOW_PERIOD_M ((I2C_SCL_LOW_PERIOD_V)<<(I2C_SCL_LOW_PERIOD_S)) +#define I2C_SCL_LOW_PERIOD_V 0x1FF +#define I2C_SCL_LOW_PERIOD_S 0 + +#define I2C_CTR_REG(i) (REG_I2C_BASE(i) + 0x4) + +/* I2C_ADDR_BROADCASTING_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */ + +#define I2C_ADDR_BROADCASTING_EN (BIT(14)) +#define I2C_ADDR_BROADCASTING_EN_M (BIT(14)) +#define I2C_ADDR_BROADCASTING_EN_V 0x1 +#define I2C_ADDR_BROADCASTING_EN_S 14 + +/* I2C_ADDR_10BIT_RW_CHECK_EN : R/W ;bitpos:[13] ;default: 1'b0 ; */ + +#define I2C_ADDR_10BIT_RW_CHECK_EN (BIT(13)) +#define I2C_ADDR_10BIT_RW_CHECK_EN_M (BIT(13)) +#define I2C_ADDR_10BIT_RW_CHECK_EN_V 0x1 +#define I2C_ADDR_10BIT_RW_CHECK_EN_S 13 + +/* I2C_SLV_TX_AUTO_START_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ + +#define I2C_SLV_TX_AUTO_START_EN (BIT(12)) +#define I2C_SLV_TX_AUTO_START_EN_M (BIT(12)) +#define I2C_SLV_TX_AUTO_START_EN_V 0x1 +#define I2C_SLV_TX_AUTO_START_EN_S 12 + +/* I2C_CONF_UPGATE : WT ;bitpos:[11] ;default: 1'b0 ; */ + +#define I2C_CONF_UPGATE (BIT(11)) +#define I2C_CONF_UPGATE_M (BIT(11)) +#define I2C_CONF_UPGATE_V 0x1 +#define I2C_CONF_UPGATE_S 11 + +/* I2C_FSM_RST : WT ;bitpos:[10] ;default: 1'b0 ; */ + +#define I2C_FSM_RST (BIT(10)) +#define I2C_FSM_RST_M (BIT(10)) +#define I2C_FSM_RST_V 0x1 +#define I2C_FSM_RST_S 10 + +/* I2C_ARBITRATION_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */ + +#define I2C_ARBITRATION_EN (BIT(9)) +#define I2C_ARBITRATION_EN_M (BIT(9)) +#define I2C_ARBITRATION_EN_V 0x1 +#define I2C_ARBITRATION_EN_S 9 + +/* I2C_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ + +#define I2C_CLK_EN (BIT(8)) +#define I2C_CLK_EN_M (BIT(8)) +#define I2C_CLK_EN_V 0x1 +#define I2C_CLK_EN_S 8 + +/* I2C_RX_LSB_FIRST : R/W ;bitpos:[7] ;default: 1'h0 ; */ + +#define I2C_RX_LSB_FIRST (BIT(7)) +#define I2C_RX_LSB_FIRST_M (BIT(7)) +#define I2C_RX_LSB_FIRST_V 0x1 +#define I2C_RX_LSB_FIRST_S 7 + +/* I2C_TX_LSB_FIRST : R/W ;bitpos:[6] ;default: 1'b0 ; */ + +#define I2C_TX_LSB_FIRST (BIT(6)) +#define I2C_TX_LSB_FIRST_M (BIT(6)) +#define I2C_TX_LSB_FIRST_V 0x1 +#define I2C_TX_LSB_FIRST_S 6 + +/* I2C_TRANS_START : WT ;bitpos:[5] ;default: 1'b0 ; */ + +#define I2C_TRANS_START (BIT(5)) +#define I2C_TRANS_START_M (BIT(5)) +#define I2C_TRANS_START_V 0x1 +#define I2C_TRANS_START_S 5 + +/* I2C_MS_MODE : R/W ;bitpos:[4] ;default: 1'b0 ; */ + +#define I2C_MS_MODE (BIT(4)) +#define I2C_MS_MODE_M (BIT(4)) +#define I2C_MS_MODE_V 0x1 +#define I2C_MS_MODE_S 4 + +/* I2C_RX_FULL_ACK_LEVEL : R/W ;bitpos:[3] ;default: 1'b1 ; */ + +#define I2C_RX_FULL_ACK_LEVEL (BIT(3)) +#define I2C_RX_FULL_ACK_LEVEL_M (BIT(3)) +#define I2C_RX_FULL_ACK_LEVEL_V 0x1 +#define I2C_RX_FULL_ACK_LEVEL_S 3 + +/* I2C_SAMPLE_SCL_LEVEL : R/W ;bitpos:[2] ;default: 1'b0 ; */ + +#define I2C_SAMPLE_SCL_LEVEL (BIT(2)) +#define I2C_SAMPLE_SCL_LEVEL_M (BIT(2)) +#define I2C_SAMPLE_SCL_LEVEL_V 0x1 +#define I2C_SAMPLE_SCL_LEVEL_S 2 + +/* I2C_SCL_FORCE_OUT : R/W ;bitpos:[1] ;default: 1'b1 ; */ + +#define I2C_SCL_FORCE_OUT (BIT(1)) +#define I2C_SCL_FORCE_OUT_M (BIT(1)) +#define I2C_SCL_FORCE_OUT_V 0x1 +#define I2C_SCL_FORCE_OUT_S 1 + +/* I2C_SDA_FORCE_OUT : R/W ;bitpos:[0] ;default: 1'b1 ; */ + +#define I2C_SDA_FORCE_OUT (BIT(0)) +#define I2C_SDA_FORCE_OUT_M (BIT(0)) +#define I2C_SDA_FORCE_OUT_V 0x1 +#define I2C_SDA_FORCE_OUT_S 0 + +#define I2C_SR_REG(i) (REG_I2C_BASE(i) + 0x8) + +/* I2C_SCL_STATE_LAST : RO ;bitpos:[30:28] ;default: 3'b0 ; */ + +#define I2C_SCL_STATE_LAST 0x00000007 +#define I2C_SCL_STATE_LAST_M ((I2C_SCL_STATE_LAST_V)<<(I2C_SCL_STATE_LAST_S)) +#define I2C_SCL_STATE_LAST_V 0x7 +#define I2C_SCL_STATE_LAST_S 28 + +/* I2C_SCL_MAIN_STATE_LAST : RO ;bitpos:[26:24] ;default: 3'b0 ; */ + +#define I2C_SCL_MAIN_STATE_LAST 0x00000007 +#define I2C_SCL_MAIN_STATE_LAST_M ((I2C_SCL_MAIN_STATE_LAST_V)<<(I2C_SCL_MAIN_STATE_LAST_S)) +#define I2C_SCL_MAIN_STATE_LAST_V 0x7 +#define I2C_SCL_MAIN_STATE_LAST_S 24 + +/* I2C_TXFIFO_CNT : RO ;bitpos:[23:18] ;default: 6'b0 ; */ + +#define I2C_TXFIFO_CNT 0x0000003F +#define I2C_TXFIFO_CNT_M ((I2C_TXFIFO_CNT_V)<<(I2C_TXFIFO_CNT_S)) +#define I2C_TXFIFO_CNT_V 0x3F +#define I2C_TXFIFO_CNT_S 18 + +/* I2C_STRETCH_CAUSE : RO ;bitpos:[15:14] ;default: 2'h3 ; */ + +#define I2C_STRETCH_CAUSE 0x00000003 +#define I2C_STRETCH_CAUSE_M ((I2C_STRETCH_CAUSE_V)<<(I2C_STRETCH_CAUSE_S)) +#define I2C_STRETCH_CAUSE_V 0x3 +#define I2C_STRETCH_CAUSE_S 14 + +/* I2C_RXFIFO_CNT : RO ;bitpos:[13:8] ;default: 6'b0 ; */ + +#define I2C_RXFIFO_CNT 0x0000003F +#define I2C_RXFIFO_CNT_M ((I2C_RXFIFO_CNT_V)<<(I2C_RXFIFO_CNT_S)) +#define I2C_RXFIFO_CNT_V 0x3F +#define I2C_RXFIFO_CNT_S 8 + +/* I2C_SLAVE_ADDRESSED : RO ;bitpos:[5] ;default: 1'b0 ; */ + +#define I2C_SLAVE_ADDRESSED (BIT(5)) +#define I2C_SLAVE_ADDRESSED_M (BIT(5)) +#define I2C_SLAVE_ADDRESSED_V 0x1 +#define I2C_SLAVE_ADDRESSED_S 5 + +/* I2C_BUS_BUSY : RO ;bitpos:[4] ;default: 1'b0 ; */ + +#define I2C_BUS_BUSY (BIT(4)) +#define I2C_BUS_BUSY_M (BIT(4)) +#define I2C_BUS_BUSY_V 0x1 +#define I2C_BUS_BUSY_S 4 + +/* I2C_ARB_LOST : RO ;bitpos:[3] ;default: 1'b0 ; */ + +#define I2C_ARB_LOST (BIT(3)) +#define I2C_ARB_LOST_M (BIT(3)) +#define I2C_ARB_LOST_V 0x1 +#define I2C_ARB_LOST_S 3 + +/* I2C_SLAVE_RW : RO ;bitpos:[1] ;default: 1'b0 ; */ + +#define I2C_SLAVE_RW (BIT(1)) +#define I2C_SLAVE_RW_M (BIT(1)) +#define I2C_SLAVE_RW_V 0x1 +#define I2C_SLAVE_RW_S 1 + +/* I2C_RESP_REC : RO ;bitpos:[0] ;default: 1'b0 ; */ + +#define I2C_RESP_REC (BIT(0)) +#define I2C_RESP_REC_M (BIT(0)) +#define I2C_RESP_REC_V 0x1 +#define I2C_RESP_REC_S 0 + +#define I2C_TO_REG(i) (REG_I2C_BASE(i) + 0xC) + +/* I2C_TIME_OUT_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */ + +#define I2C_TIME_OUT_EN (BIT(5)) +#define I2C_TIME_OUT_EN_M (BIT(5)) +#define I2C_TIME_OUT_EN_V 0x1 +#define I2C_TIME_OUT_EN_S 5 + +/* I2C_TIME_OUT_REG : R/W ;bitpos:[4:0] ;default: 5'h10 ; */ + +#define I2C_TIME_OUT_REG 0x0000001F +#define I2C_TIME_OUT_REG_M ((I2C_TIME_OUT_VALUE_V)<<(I2C_TIME_OUT_VALUE_S)) +#define I2C_TIME_OUT_REG_V 0x1F +#define I2C_TIME_OUT_REG_S 0 + +#define I2C_SLAVE_ADDR_REG(i) (REG_I2C_BASE(i) + 0x10) + +/* I2C_ADDR_10BIT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ + +#define I2C_ADDR_10BIT_EN (BIT(31)) +#define I2C_ADDR_10BIT_EN_M (BIT(31)) +#define I2C_ADDR_10BIT_EN_V 0x1 +#define I2C_ADDR_10BIT_EN_S 31 + +/* I2C_SLAVE_ADDR : R/W ;bitpos:[14:0] ;default: 15'b0 ; */ + +#define I2C_SLAVE_ADDR 0x00007FFF +#define I2C_SLAVE_ADDR_M ((I2C_SLAVE_ADDR_V)<<(I2C_SLAVE_ADDR_S)) +#define I2C_SLAVE_ADDR_V 0x7FFF +#define I2C_SLAVE_ADDR_S 0 + +#define I2C_FIFO_ST_REG(i) (REG_I2C_BASE(i) + 0x14) + +/* I2C_SLAVE_RW_POINT : RO ;bitpos:[29:22] ;default: 8'b0 ; */ + +#define I2C_SLAVE_RW_POINT 0x000000FF +#define I2C_SLAVE_RW_POINT_M ((I2C_SLAVE_RW_POINT_V)<<(I2C_SLAVE_RW_POINT_S)) +#define I2C_SLAVE_RW_POINT_V 0xFF +#define I2C_SLAVE_RW_POINT_S 22 + +/* I2C_TXFIFO_WADDR : RO ;bitpos:[19:15] ;default: 5'b0 ; */ + +#define I2C_TXFIFO_WADDR 0x0000001F +#define I2C_TXFIFO_WADDR_M ((I2C_TXFIFO_WADDR_V)<<(I2C_TXFIFO_WADDR_S)) +#define I2C_TXFIFO_WADDR_V 0x1F +#define I2C_TXFIFO_WADDR_S 15 + +/* I2C_TXFIFO_RADDR : RO ;bitpos:[14:10] ;default: 5'b0 ; */ + +#define I2C_TXFIFO_RADDR 0x0000001F +#define I2C_TXFIFO_RADDR_M ((I2C_TXFIFO_RADDR_V)<<(I2C_TXFIFO_RADDR_S)) +#define I2C_TXFIFO_RADDR_V 0x1F +#define I2C_TXFIFO_RADDR_S 10 + +/* I2C_RXFIFO_WADDR : RO ;bitpos:[9:5] ;default: 5'b0 ; */ + +#define I2C_RXFIFO_WADDR 0x0000001F +#define I2C_RXFIFO_WADDR_M ((I2C_RXFIFO_WADDR_V)<<(I2C_RXFIFO_WADDR_S)) +#define I2C_RXFIFO_WADDR_V 0x1F +#define I2C_RXFIFO_WADDR_S 5 + +/* I2C_RXFIFO_RADDR : RO ;bitpos:[4:0] ;default: 5'b0 ; */ + +#define I2C_RXFIFO_RADDR 0x0000001F +#define I2C_RXFIFO_RADDR_M ((I2C_RXFIFO_RADDR_V)<<(I2C_RXFIFO_RADDR_S)) +#define I2C_RXFIFO_RADDR_V 0x1F +#define I2C_RXFIFO_RADDR_S 0 + +#define I2C_FIFO_CONF_REG(i) (REG_I2C_BASE(i) + 0x18) + +/* I2C_FIFO_PRT_EN : R/W ;bitpos:[14] ;default: 1'b1 ; */ + +#define I2C_FIFO_PRT_EN (BIT(14)) +#define I2C_FIFO_PRT_EN_M (BIT(14)) +#define I2C_FIFO_PRT_EN_V 0x1 +#define I2C_FIFO_PRT_EN_S 14 + +/* I2C_TX_FIFO_RST : R/W ;bitpos:[13] ;default: 1'b0 ; */ + +#define I2C_TX_FIFO_RST (BIT(13)) +#define I2C_TX_FIFO_RST_M (BIT(13)) +#define I2C_TX_FIFO_RST_V 0x1 +#define I2C_TX_FIFO_RST_S 13 + +/* I2C_RX_FIFO_RST : R/W ;bitpos:[12] ;default: 1'b0 ; */ + +#define I2C_RX_FIFO_RST (BIT(12)) +#define I2C_RX_FIFO_RST_M (BIT(12)) +#define I2C_RX_FIFO_RST_V 0x1 +#define I2C_RX_FIFO_RST_S 12 + +/* I2C_FIFO_ADDR_CFG_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ + +#define I2C_FIFO_ADDR_CFG_EN (BIT(11)) +#define I2C_FIFO_ADDR_CFG_EN_M (BIT(11)) +#define I2C_FIFO_ADDR_CFG_EN_V 0x1 +#define I2C_FIFO_ADDR_CFG_EN_S 11 + +/* I2C_NONFIFO_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ + +#define I2C_NONFIFO_EN (BIT(10)) +#define I2C_NONFIFO_EN_M (BIT(10)) +#define I2C_NONFIFO_EN_V 0x1 +#define I2C_NONFIFO_EN_S 10 + +/* I2C_TXFIFO_WM_THRHD : R/W ;bitpos:[9:5] ;default: 5'h4 ; */ + +#define I2C_TXFIFO_WM_THRHD 0x0000001F +#define I2C_TXFIFO_WM_THRHD_M ((I2C_TXFIFO_WM_THRHD_V)<<(I2C_TXFIFO_WM_THRHD_S)) +#define I2C_TXFIFO_WM_THRHD_V 0x1F +#define I2C_TXFIFO_WM_THRHD_S 5 + +/* I2C_RXFIFO_WM_THRHD : R/W ;bitpos:[4:0] ;default: 5'hb ; */ + +#define I2C_RXFIFO_WM_THRHD 0x0000001F +#define I2C_RXFIFO_WM_THRHD_M ((I2C_RXFIFO_WM_THRHD_V)<<(I2C_RXFIFO_WM_THRHD_S)) +#define I2C_RXFIFO_WM_THRHD_V 0x1F +#define I2C_RXFIFO_WM_THRHD_S 0 + +#define I2C_DATA_REG(i) (REG_I2C_BASE(i) + 0x1C) + +/* I2C_FIFO_RDATA : RO ;bitpos:[7:0] ;default: 8'b0 ; */ + +#define I2C_FIFO_RDATA 0x000000FF +#define I2C_FIFO_RDATA_M ((I2C_FIFO_RDATA_V)<<(I2C_FIFO_RDATA_S)) +#define I2C_FIFO_RDATA_V 0xFF +#define I2C_FIFO_RDATA_S 0 + +#define I2C_INT_RAW_REG(i) (REG_I2C_BASE(i) + 0x20) + +/* I2C_GENERAL_CALL_INT_RAW : R/SS/WTC ;bitpos:[17] ;default: 1'b0 ; */ + +#define I2C_GENERAL_CALL_INT_RAW (BIT(17)) +#define I2C_GENERAL_CALL_INT_RAW_M (BIT(17)) +#define I2C_GENERAL_CALL_INT_RAW_V 0x1 +#define I2C_GENERAL_CALL_INT_RAW_S 17 + +/* I2C_SLAVE_STRETCH_INT_RAW : R/SS/WTC ;bitpos:[16] ;default: 1'b0 ; */ + +#define I2C_SLAVE_STRETCH_INT_RAW (BIT(16)) +#define I2C_SLAVE_STRETCH_INT_RAW_M (BIT(16)) +#define I2C_SLAVE_STRETCH_INT_RAW_V 0x1 +#define I2C_SLAVE_STRETCH_INT_RAW_S 16 + +/* I2C_DET_START_INT_RAW : R/SS/WTC ;bitpos:[15] ;default: 1'b0 ; */ + +#define I2C_DET_START_INT_RAW (BIT(15)) +#define I2C_DET_START_INT_RAW_M (BIT(15)) +#define I2C_DET_START_INT_RAW_V 0x1 +#define I2C_DET_START_INT_RAW_S 15 + +/* I2C_SCL_MAIN_ST_TO_INT_RAW : R/SS/WTC ;bitpos:[14] ;default: 1'b0 ; */ + +#define I2C_SCL_MAIN_ST_TO_INT_RAW (BIT(14)) +#define I2C_SCL_MAIN_ST_TO_INT_RAW_M (BIT(14)) +#define I2C_SCL_MAIN_ST_TO_INT_RAW_V 0x1 +#define I2C_SCL_MAIN_ST_TO_INT_RAW_S 14 + +/* I2C_SCL_ST_TO_INT_RAW : R/SS/WTC ;bitpos:[13] ;default: 1'b0 ; */ + +#define I2C_SCL_ST_TO_INT_RAW (BIT(13)) +#define I2C_SCL_ST_TO_INT_RAW_M (BIT(13)) +#define I2C_SCL_ST_TO_INT_RAW_V 0x1 +#define I2C_SCL_ST_TO_INT_RAW_S 13 + +/* I2C_RXFIFO_UDF_INT_RAW : R/SS/WTC ;bitpos:[12] ;default: 1'b0 ; */ + +#define I2C_RXFIFO_UDF_INT_RAW (BIT(12)) +#define I2C_RXFIFO_UDF_INT_RAW_M (BIT(12)) +#define I2C_RXFIFO_UDF_INT_RAW_V 0x1 +#define I2C_RXFIFO_UDF_INT_RAW_S 12 + +/* I2C_TXFIFO_OVF_INT_RAW : R/SS/WTC ;bitpos:[11] ;default: 1'b0 ; */ + +#define I2C_TXFIFO_OVF_INT_RAW (BIT(11)) +#define I2C_TXFIFO_OVF_INT_RAW_M (BIT(11)) +#define I2C_TXFIFO_OVF_INT_RAW_V 0x1 +#define I2C_TXFIFO_OVF_INT_RAW_S 11 + +/* I2C_NACK_INT_RAW : R/SS/WTC ;bitpos:[10] ;default: 1'b0 ; */ + +#define I2C_NACK_INT_RAW (BIT(10)) +#define I2C_NACK_INT_RAW_M (BIT(10)) +#define I2C_NACK_INT_RAW_V 0x1 +#define I2C_NACK_INT_RAW_S 10 + +/* I2C_TRANS_START_INT_RAW : R/SS/WTC ;bitpos:[9] ;default: 1'b0 ; */ + +#define I2C_TRANS_START_INT_RAW (BIT(9)) +#define I2C_TRANS_START_INT_RAW_M (BIT(9)) +#define I2C_TRANS_START_INT_RAW_V 0x1 +#define I2C_TRANS_START_INT_RAW_S 9 + +/* I2C_TIME_OUT_INT_RAW : R/SS/WTC ;bitpos:[8] ;default: 1'b0 ; */ + +#define I2C_TIME_OUT_INT_RAW (BIT(8)) +#define I2C_TIME_OUT_INT_RAW_M (BIT(8)) +#define I2C_TIME_OUT_INT_RAW_V 0x1 +#define I2C_TIME_OUT_INT_RAW_S 8 + +/* I2C_TRANS_COMPLETE_INT_RAW : R/SS/WTC ;bitpos:[7] ;default: 1'b0 ; */ + +#define I2C_TRANS_COMPLETE_INT_RAW (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_RAW_M (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_RAW_V 0x1 +#define I2C_TRANS_COMPLETE_INT_RAW_S 7 + +/* I2C_MST_TXFIFO_UDF_INT_RAW : R/SS/WTC ;bitpos:[6] ;default: 1'b0 ; */ + +#define I2C_MST_TXFIFO_UDF_INT_RAW (BIT(6)) +#define I2C_MST_TXFIFO_UDF_INT_RAW_M (BIT(6)) +#define I2C_MST_TXFIFO_UDF_INT_RAW_V 0x1 +#define I2C_MST_TXFIFO_UDF_INT_RAW_S 6 + +/* I2C_ARBITRATION_LOST_INT_RAW : R/SS/WTC ;bitpos:[5] ;default: 1'b0 ; */ + +#define I2C_ARBITRATION_LOST_INT_RAW (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_RAW_M (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_RAW_V 0x1 +#define I2C_ARBITRATION_LOST_INT_RAW_S 5 + +/* I2C_BYTE_TRANS_DONE_INT_RAW : R/SS/WTC ;bitpos:[4] ;default: 1'b0 ; */ + +#define I2C_BYTE_TRANS_DONE_INT_RAW (BIT(4)) +#define I2C_BYTE_TRANS_DONE_INT_RAW_M (BIT(4)) +#define I2C_BYTE_TRANS_DONE_INT_RAW_V 0x1 +#define I2C_BYTE_TRANS_DONE_INT_RAW_S 4 + +/* I2C_END_DETECT_INT_RAW : R/SS/WTC ;bitpos:[3] ;default: 1'b0 ; */ + +#define I2C_END_DETECT_INT_RAW (BIT(3)) +#define I2C_END_DETECT_INT_RAW_M (BIT(3)) +#define I2C_END_DETECT_INT_RAW_V 0x1 +#define I2C_END_DETECT_INT_RAW_S 3 + +/* I2C_RXFIFO_OVF_INT_RAW : R/SS/WTC ;bitpos:[2] ;default: 1'b0 ; */ + +#define I2C_RXFIFO_OVF_INT_RAW (BIT(2)) +#define I2C_RXFIFO_OVF_INT_RAW_M (BIT(2)) +#define I2C_RXFIFO_OVF_INT_RAW_V 0x1 +#define I2C_RXFIFO_OVF_INT_RAW_S 2 + +/* I2C_TXFIFO_WM_INT_RAW : R/SS/WTC ;bitpos:[1] ;default: 1'b1 ; */ + +#define I2C_TXFIFO_WM_INT_RAW (BIT(1)) +#define I2C_TXFIFO_WM_INT_RAW_M (BIT(1)) +#define I2C_TXFIFO_WM_INT_RAW_V 0x1 +#define I2C_TXFIFO_WM_INT_RAW_S 1 + +/* I2C_RXFIFO_WM_INT_RAW : R/SS/WTC ;bitpos:[0] ;default: 1'b0 ; */ + +#define I2C_RXFIFO_WM_INT_RAW (BIT(0)) +#define I2C_RXFIFO_WM_INT_RAW_M (BIT(0)) +#define I2C_RXFIFO_WM_INT_RAW_V 0x1 +#define I2C_RXFIFO_WM_INT_RAW_S 0 + +#define I2C_INT_CLR_REG(i) (REG_I2C_BASE(i) + 0x24) + +/* I2C_GENERAL_CALL_INT_CLR : WT ;bitpos:[17] ;default: 1'b0 ; */ + +#define I2C_GENERAL_CALL_INT_CLR (BIT(17)) +#define I2C_GENERAL_CALL_INT_CLR_M (BIT(17)) +#define I2C_GENERAL_CALL_INT_CLR_V 0x1 +#define I2C_GENERAL_CALL_INT_CLR_S 17 + +/* I2C_SLAVE_STRETCH_INT_CLR : WT ;bitpos:[16] ;default: 1'b0 ; */ + +#define I2C_SLAVE_STRETCH_INT_CLR (BIT(16)) +#define I2C_SLAVE_STRETCH_INT_CLR_M (BIT(16)) +#define I2C_SLAVE_STRETCH_INT_CLR_V 0x1 +#define I2C_SLAVE_STRETCH_INT_CLR_S 16 + +/* I2C_DET_START_INT_CLR : WT ;bitpos:[15] ;default: 1'b0 ; */ + +#define I2C_DET_START_INT_CLR (BIT(15)) +#define I2C_DET_START_INT_CLR_M (BIT(15)) +#define I2C_DET_START_INT_CLR_V 0x1 +#define I2C_DET_START_INT_CLR_S 15 + +/* I2C_SCL_MAIN_ST_TO_INT_CLR : WT ;bitpos:[14] ;default: 1'b0 ; */ + +#define I2C_SCL_MAIN_ST_TO_INT_CLR (BIT(14)) +#define I2C_SCL_MAIN_ST_TO_INT_CLR_M (BIT(14)) +#define I2C_SCL_MAIN_ST_TO_INT_CLR_V 0x1 +#define I2C_SCL_MAIN_ST_TO_INT_CLR_S 14 + +/* I2C_SCL_ST_TO_INT_CLR : WT ;bitpos:[13] ;default: 1'b0 ; */ + +#define I2C_SCL_ST_TO_INT_CLR (BIT(13)) +#define I2C_SCL_ST_TO_INT_CLR_M (BIT(13)) +#define I2C_SCL_ST_TO_INT_CLR_V 0x1 +#define I2C_SCL_ST_TO_INT_CLR_S 13 + +/* I2C_RXFIFO_UDF_INT_CLR : WT ;bitpos:[12] ;default: 1'b0 ; */ + +#define I2C_RXFIFO_UDF_INT_CLR (BIT(12)) +#define I2C_RXFIFO_UDF_INT_CLR_M (BIT(12)) +#define I2C_RXFIFO_UDF_INT_CLR_V 0x1 +#define I2C_RXFIFO_UDF_INT_CLR_S 12 + +/* I2C_TXFIFO_OVF_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */ + +#define I2C_TXFIFO_OVF_INT_CLR (BIT(11)) +#define I2C_TXFIFO_OVF_INT_CLR_M (BIT(11)) +#define I2C_TXFIFO_OVF_INT_CLR_V 0x1 +#define I2C_TXFIFO_OVF_INT_CLR_S 11 + +/* I2C_NACK_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */ + +#define I2C_NACK_INT_CLR (BIT(10)) +#define I2C_NACK_INT_CLR_M (BIT(10)) +#define I2C_NACK_INT_CLR_V 0x1 +#define I2C_NACK_INT_CLR_S 10 + +/* I2C_TRANS_START_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */ + +#define I2C_TRANS_START_INT_CLR (BIT(9)) +#define I2C_TRANS_START_INT_CLR_M (BIT(9)) +#define I2C_TRANS_START_INT_CLR_V 0x1 +#define I2C_TRANS_START_INT_CLR_S 9 + +/* I2C_TIME_OUT_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */ + +#define I2C_TIME_OUT_INT_CLR (BIT(8)) +#define I2C_TIME_OUT_INT_CLR_M (BIT(8)) +#define I2C_TIME_OUT_INT_CLR_V 0x1 +#define I2C_TIME_OUT_INT_CLR_S 8 + +/* I2C_TRANS_COMPLETE_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */ + +#define I2C_TRANS_COMPLETE_INT_CLR (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_CLR_M (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_CLR_V 0x1 +#define I2C_TRANS_COMPLETE_INT_CLR_S 7 + +/* I2C_MST_TXFIFO_UDF_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */ + +#define I2C_MST_TXFIFO_UDF_INT_CLR (BIT(6)) +#define I2C_MST_TXFIFO_UDF_INT_CLR_M (BIT(6)) +#define I2C_MST_TXFIFO_UDF_INT_CLR_V 0x1 +#define I2C_MST_TXFIFO_UDF_INT_CLR_S 6 + +/* I2C_ARBITRATION_LOST_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */ + +#define I2C_ARBITRATION_LOST_INT_CLR (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_CLR_M (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_CLR_V 0x1 +#define I2C_ARBITRATION_LOST_INT_CLR_S 5 + +/* I2C_BYTE_TRANS_DONE_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ + +#define I2C_BYTE_TRANS_DONE_INT_CLR (BIT(4)) +#define I2C_BYTE_TRANS_DONE_INT_CLR_M (BIT(4)) +#define I2C_BYTE_TRANS_DONE_INT_CLR_V 0x1 +#define I2C_BYTE_TRANS_DONE_INT_CLR_S 4 + +/* I2C_END_DETECT_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */ + +#define I2C_END_DETECT_INT_CLR (BIT(3)) +#define I2C_END_DETECT_INT_CLR_M (BIT(3)) +#define I2C_END_DETECT_INT_CLR_V 0x1 +#define I2C_END_DETECT_INT_CLR_S 3 + +/* I2C_RXFIFO_OVF_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */ + +#define I2C_RXFIFO_OVF_INT_CLR (BIT(2)) +#define I2C_RXFIFO_OVF_INT_CLR_M (BIT(2)) +#define I2C_RXFIFO_OVF_INT_CLR_V 0x1 +#define I2C_RXFIFO_OVF_INT_CLR_S 2 + +/* I2C_TXFIFO_WM_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */ + +#define I2C_TXFIFO_WM_INT_CLR (BIT(1)) +#define I2C_TXFIFO_WM_INT_CLR_M (BIT(1)) +#define I2C_TXFIFO_WM_INT_CLR_V 0x1 +#define I2C_TXFIFO_WM_INT_CLR_S 1 + +/* I2C_RXFIFO_WM_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */ + +#define I2C_RXFIFO_WM_INT_CLR (BIT(0)) +#define I2C_RXFIFO_WM_INT_CLR_M (BIT(0)) +#define I2C_RXFIFO_WM_INT_CLR_V 0x1 +#define I2C_RXFIFO_WM_INT_CLR_S 0 + +#define I2C_INT_ENA_REG(i) (REG_I2C_BASE(i) + 0x28) + +/* I2C_GENERAL_CALL_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ + +#define I2C_GENERAL_CALL_INT_ENA (BIT(17)) +#define I2C_GENERAL_CALL_INT_ENA_M (BIT(17)) +#define I2C_GENERAL_CALL_INT_ENA_V 0x1 +#define I2C_GENERAL_CALL_INT_ENA_S 17 + +/* I2C_SLAVE_STRETCH_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ + +#define I2C_SLAVE_STRETCH_INT_ENA (BIT(16)) +#define I2C_SLAVE_STRETCH_INT_ENA_M (BIT(16)) +#define I2C_SLAVE_STRETCH_INT_ENA_V 0x1 +#define I2C_SLAVE_STRETCH_INT_ENA_S 16 + +/* I2C_DET_START_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ + +#define I2C_DET_START_INT_ENA (BIT(15)) +#define I2C_DET_START_INT_ENA_M (BIT(15)) +#define I2C_DET_START_INT_ENA_V 0x1 +#define I2C_DET_START_INT_ENA_S 15 + +/* I2C_SCL_MAIN_ST_TO_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ + +#define I2C_SCL_MAIN_ST_TO_INT_ENA (BIT(14)) +#define I2C_SCL_MAIN_ST_TO_INT_ENA_M (BIT(14)) +#define I2C_SCL_MAIN_ST_TO_INT_ENA_V 0x1 +#define I2C_SCL_MAIN_ST_TO_INT_ENA_S 14 + +/* I2C_SCL_ST_TO_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ + +#define I2C_SCL_ST_TO_INT_ENA (BIT(13)) +#define I2C_SCL_ST_TO_INT_ENA_M (BIT(13)) +#define I2C_SCL_ST_TO_INT_ENA_V 0x1 +#define I2C_SCL_ST_TO_INT_ENA_S 13 + +/* I2C_RXFIFO_UDF_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ + +#define I2C_RXFIFO_UDF_INT_ENA (BIT(12)) +#define I2C_RXFIFO_UDF_INT_ENA_M (BIT(12)) +#define I2C_RXFIFO_UDF_INT_ENA_V 0x1 +#define I2C_RXFIFO_UDF_INT_ENA_S 12 + +/* I2C_TXFIFO_OVF_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ + +#define I2C_TXFIFO_OVF_INT_ENA (BIT(11)) +#define I2C_TXFIFO_OVF_INT_ENA_M (BIT(11)) +#define I2C_TXFIFO_OVF_INT_ENA_V 0x1 +#define I2C_TXFIFO_OVF_INT_ENA_S 11 + +/* I2C_NACK_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ + +#define I2C_NACK_INT_ENA (BIT(10)) +#define I2C_NACK_INT_ENA_M (BIT(10)) +#define I2C_NACK_INT_ENA_V 0x1 +#define I2C_NACK_INT_ENA_S 10 + +/* I2C_TRANS_START_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ + +#define I2C_TRANS_START_INT_ENA (BIT(9)) +#define I2C_TRANS_START_INT_ENA_M (BIT(9)) +#define I2C_TRANS_START_INT_ENA_V 0x1 +#define I2C_TRANS_START_INT_ENA_S 9 + +/* I2C_TIME_OUT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ + +#define I2C_TIME_OUT_INT_ENA (BIT(8)) +#define I2C_TIME_OUT_INT_ENA_M (BIT(8)) +#define I2C_TIME_OUT_INT_ENA_V 0x1 +#define I2C_TIME_OUT_INT_ENA_S 8 + +/* I2C_TRANS_COMPLETE_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ + +#define I2C_TRANS_COMPLETE_INT_ENA (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_ENA_M (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_ENA_V 0x1 +#define I2C_TRANS_COMPLETE_INT_ENA_S 7 + +/* I2C_MST_TXFIFO_UDF_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ + +#define I2C_MST_TXFIFO_UDF_INT_ENA (BIT(6)) +#define I2C_MST_TXFIFO_UDF_INT_ENA_M (BIT(6)) +#define I2C_MST_TXFIFO_UDF_INT_ENA_V 0x1 +#define I2C_MST_TXFIFO_UDF_INT_ENA_S 6 + +/* I2C_ARBITRATION_LOST_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ + +#define I2C_ARBITRATION_LOST_INT_ENA (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_ENA_M (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_ENA_V 0x1 +#define I2C_ARBITRATION_LOST_INT_ENA_S 5 + +/* I2C_BYTE_TRANS_DONE_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ + +#define I2C_BYTE_TRANS_DONE_INT_ENA (BIT(4)) +#define I2C_BYTE_TRANS_DONE_INT_ENA_M (BIT(4)) +#define I2C_BYTE_TRANS_DONE_INT_ENA_V 0x1 +#define I2C_BYTE_TRANS_DONE_INT_ENA_S 4 + +/* I2C_END_DETECT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ + +#define I2C_END_DETECT_INT_ENA (BIT(3)) +#define I2C_END_DETECT_INT_ENA_M (BIT(3)) +#define I2C_END_DETECT_INT_ENA_V 0x1 +#define I2C_END_DETECT_INT_ENA_S 3 + +/* I2C_RXFIFO_OVF_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ + +#define I2C_RXFIFO_OVF_INT_ENA (BIT(2)) +#define I2C_RXFIFO_OVF_INT_ENA_M (BIT(2)) +#define I2C_RXFIFO_OVF_INT_ENA_V 0x1 +#define I2C_RXFIFO_OVF_INT_ENA_S 2 + +/* I2C_TXFIFO_WM_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ + +#define I2C_TXFIFO_WM_INT_ENA (BIT(1)) +#define I2C_TXFIFO_WM_INT_ENA_M (BIT(1)) +#define I2C_TXFIFO_WM_INT_ENA_V 0x1 +#define I2C_TXFIFO_WM_INT_ENA_S 1 + +/* I2C_RXFIFO_WM_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ + +#define I2C_RXFIFO_WM_INT_ENA (BIT(0)) +#define I2C_RXFIFO_WM_INT_ENA_M (BIT(0)) +#define I2C_RXFIFO_WM_INT_ENA_V 0x1 +#define I2C_RXFIFO_WM_INT_ENA_S 0 + +#define I2C_INT_STATUS_REG(i) (REG_I2C_BASE(i) + 0x2C) + +/* I2C_GENERAL_CALL_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ + +#define I2C_GENERAL_CALL_INT_ST (BIT(17)) +#define I2C_GENERAL_CALL_INT_ST_M (BIT(17)) +#define I2C_GENERAL_CALL_INT_ST_V 0x1 +#define I2C_GENERAL_CALL_INT_ST_S 17 + +/* I2C_SLAVE_STRETCH_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ + +#define I2C_SLAVE_STRETCH_INT_ST (BIT(16)) +#define I2C_SLAVE_STRETCH_INT_ST_M (BIT(16)) +#define I2C_SLAVE_STRETCH_INT_ST_V 0x1 +#define I2C_SLAVE_STRETCH_INT_ST_S 16 + +/* I2C_DET_START_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ + +#define I2C_DET_START_INT_ST (BIT(15)) +#define I2C_DET_START_INT_ST_M (BIT(15)) +#define I2C_DET_START_INT_ST_V 0x1 +#define I2C_DET_START_INT_ST_S 15 + +/* I2C_SCL_MAIN_ST_TO_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ + +#define I2C_SCL_MAIN_ST_TO_INT_ST (BIT(14)) +#define I2C_SCL_MAIN_ST_TO_INT_ST_M (BIT(14)) +#define I2C_SCL_MAIN_ST_TO_INT_ST_V 0x1 +#define I2C_SCL_MAIN_ST_TO_INT_ST_S 14 + +/* I2C_SCL_ST_TO_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ + +#define I2C_SCL_ST_TO_INT_ST (BIT(13)) +#define I2C_SCL_ST_TO_INT_ST_M (BIT(13)) +#define I2C_SCL_ST_TO_INT_ST_V 0x1 +#define I2C_SCL_ST_TO_INT_ST_S 13 + +/* I2C_RXFIFO_UDF_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ + +#define I2C_RXFIFO_UDF_INT_ST (BIT(12)) +#define I2C_RXFIFO_UDF_INT_ST_M (BIT(12)) +#define I2C_RXFIFO_UDF_INT_ST_V 0x1 +#define I2C_RXFIFO_UDF_INT_ST_S 12 + +/* I2C_TXFIFO_OVF_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ + +#define I2C_TXFIFO_OVF_INT_ST (BIT(11)) +#define I2C_TXFIFO_OVF_INT_ST_M (BIT(11)) +#define I2C_TXFIFO_OVF_INT_ST_V 0x1 +#define I2C_TXFIFO_OVF_INT_ST_S 11 + +/* I2C_NACK_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ + +#define I2C_NACK_INT_ST (BIT(10)) +#define I2C_NACK_INT_ST_M (BIT(10)) +#define I2C_NACK_INT_ST_V 0x1 +#define I2C_NACK_INT_ST_S 10 + +/* I2C_TRANS_START_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ + +#define I2C_TRANS_START_INT_ST (BIT(9)) +#define I2C_TRANS_START_INT_ST_M (BIT(9)) +#define I2C_TRANS_START_INT_ST_V 0x1 +#define I2C_TRANS_START_INT_ST_S 9 + +/* I2C_TIME_OUT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ + +#define I2C_TIME_OUT_INT_ST (BIT(8)) +#define I2C_TIME_OUT_INT_ST_M (BIT(8)) +#define I2C_TIME_OUT_INT_ST_V 0x1 +#define I2C_TIME_OUT_INT_ST_S 8 + +/* I2C_TRANS_COMPLETE_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ + +#define I2C_TRANS_COMPLETE_INT_ST (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_ST_M (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_ST_V 0x1 +#define I2C_TRANS_COMPLETE_INT_ST_S 7 + +/* I2C_MST_TXFIFO_UDF_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ + +#define I2C_MST_TXFIFO_UDF_INT_ST (BIT(6)) +#define I2C_MST_TXFIFO_UDF_INT_ST_M (BIT(6)) +#define I2C_MST_TXFIFO_UDF_INT_ST_V 0x1 +#define I2C_MST_TXFIFO_UDF_INT_ST_S 6 + +/* I2C_ARBITRATION_LOST_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ + +#define I2C_ARBITRATION_LOST_INT_ST (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_ST_M (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_ST_V 0x1 +#define I2C_ARBITRATION_LOST_INT_ST_S 5 + +/* I2C_BYTE_TRANS_DONE_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ + +#define I2C_BYTE_TRANS_DONE_INT_ST (BIT(4)) +#define I2C_BYTE_TRANS_DONE_INT_ST_M (BIT(4)) +#define I2C_BYTE_TRANS_DONE_INT_ST_V 0x1 +#define I2C_BYTE_TRANS_DONE_INT_ST_S 4 + +/* I2C_END_DETECT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ + +#define I2C_END_DETECT_INT_ST (BIT(3)) +#define I2C_END_DETECT_INT_ST_M (BIT(3)) +#define I2C_END_DETECT_INT_ST_V 0x1 +#define I2C_END_DETECT_INT_ST_S 3 + +/* I2C_RXFIFO_OVF_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ + +#define I2C_RXFIFO_OVF_INT_ST (BIT(2)) +#define I2C_RXFIFO_OVF_INT_ST_M (BIT(2)) +#define I2C_RXFIFO_OVF_INT_ST_V 0x1 +#define I2C_RXFIFO_OVF_INT_ST_S 2 + +/* I2C_TXFIFO_WM_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ + +#define I2C_TXFIFO_WM_INT_ST (BIT(1)) +#define I2C_TXFIFO_WM_INT_ST_M (BIT(1)) +#define I2C_TXFIFO_WM_INT_ST_V 0x1 +#define I2C_TXFIFO_WM_INT_ST_S 1 + +/* I2C_RXFIFO_WM_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ + +#define I2C_RXFIFO_WM_INT_ST (BIT(0)) +#define I2C_RXFIFO_WM_INT_ST_M (BIT(0)) +#define I2C_RXFIFO_WM_INT_ST_V 0x1 +#define I2C_RXFIFO_WM_INT_ST_S 0 + +#define I2C_SDA_HOLD_REG(i) (REG_I2C_BASE(i) + 0x30) + +/* I2C_SDA_HOLD_TIME : R/W ;bitpos:[8:0] ;default: 9'b0 ; */ + +#define I2C_SDA_HOLD_TIME 0x000001FF +#define I2C_SDA_HOLD_TIME_M ((I2C_SDA_HOLD_TIME_V)<<(I2C_SDA_HOLD_TIME_S)) +#define I2C_SDA_HOLD_TIME_V 0x1FF +#define I2C_SDA_HOLD_TIME_S 0 + +#define I2C_SDA_SAMPLE_REG(i) (REG_I2C_BASE(i) + 0x34) + +/* I2C_SDA_SAMPLE_TIME : R/W ;bitpos:[8:0] ;default: 9'b0 ; */ + +#define I2C_SDA_SAMPLE_TIME 0x000001FF +#define I2C_SDA_SAMPLE_TIME_M ((I2C_SDA_SAMPLE_TIME_V)<<(I2C_SDA_SAMPLE_TIME_S)) +#define I2C_SDA_SAMPLE_TIME_V 0x1FF +#define I2C_SDA_SAMPLE_TIME_S 0 + +#define I2C_SCL_HIGH_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x38) + +/* I2C_SCL_WAIT_HIGH_PERIOD : R/W ;bitpos:[15:9] ;default: 7'b0 ; */ + +#define I2C_SCL_WAIT_HIGH_PERIOD 0x0000007F +#define I2C_SCL_WAIT_HIGH_PERIOD_M ((I2C_SCL_WAIT_HIGH_PERIOD_V)<<(I2C_SCL_WAIT_HIGH_PERIOD_S)) +#define I2C_SCL_WAIT_HIGH_PERIOD_V 0x7F +#define I2C_SCL_WAIT_HIGH_PERIOD_S 9 + +/* I2C_SCL_HIGH_PERIOD : R/W ;bitpos:[8:0] ;default: 9'b0 ; */ + +#define I2C_SCL_HIGH_PERIOD 0x000001FF +#define I2C_SCL_HIGH_PERIOD_M ((I2C_SCL_HIGH_PERIOD_V)<<(I2C_SCL_HIGH_PERIOD_S)) +#define I2C_SCL_HIGH_PERIOD_V 0x1FF +#define I2C_SCL_HIGH_PERIOD_S 0 + +#define I2C_SCL_START_HOLD_REG(i) (REG_I2C_BASE(i) + 0x40) + +/* I2C_SCL_START_HOLD_TIME : R/W ;bitpos:[8:0] ;default: 9'b1000 ; */ + +#define I2C_SCL_START_HOLD_TIME 0x000001FF +#define I2C_SCL_START_HOLD_TIME_M ((I2C_SCL_START_HOLD_TIME_V)<<(I2C_SCL_START_HOLD_TIME_S)) +#define I2C_SCL_START_HOLD_TIME_V 0x1FF +#define I2C_SCL_START_HOLD_TIME_S 0 + +#define I2C_SCL_RSTART_SETUP_REG(i) (REG_I2C_BASE(i) + 0x44) + +/* I2C_SCL_RSTART_SETUP_TIME : R/W ;bitpos:[8:0] ;default: 9'b1000 ; */ + +#define I2C_SCL_RSTART_SETUP_TIME 0x000001FF +#define I2C_SCL_RSTART_SETUP_TIME_M ((I2C_SCL_RSTART_SETUP_TIME_V)<<(I2C_SCL_RSTART_SETUP_TIME_S)) +#define I2C_SCL_RSTART_SETUP_TIME_V 0x1FF +#define I2C_SCL_RSTART_SETUP_TIME_S 0 + +#define I2C_SCL_STOP_HOLD_REG(i) (REG_I2C_BASE(i) + 0x48) + +/* I2C_SCL_STOP_HOLD_TIME : R/W ;bitpos:[8:0] ;default: 9'b1000 ; */ + +#define I2C_SCL_STOP_HOLD_TIME 0x000001FF +#define I2C_SCL_STOP_HOLD_TIME_M ((I2C_SCL_STOP_HOLD_TIME_V)<<(I2C_SCL_STOP_HOLD_TIME_S)) +#define I2C_SCL_STOP_HOLD_TIME_V 0x1FF +#define I2C_SCL_STOP_HOLD_TIME_S 0 + +#define I2C_SCL_STOP_SETUP_REG(i) (REG_I2C_BASE(i) + 0x4C) + +/* I2C_SCL_STOP_SETUP_TIME : R/W ;bitpos:[8:0] ;default: 9'b1000 ; */ + +#define I2C_SCL_STOP_SETUP_TIME 0x000001FF +#define I2C_SCL_STOP_SETUP_TIME_M ((I2C_SCL_STOP_SETUP_TIME_V)<<(I2C_SCL_STOP_SETUP_TIME_S)) +#define I2C_SCL_STOP_SETUP_TIME_V 0x1FF +#define I2C_SCL_STOP_SETUP_TIME_S 0 + +#define I2C_FILTER_CFG_REG(i) (REG_I2C_BASE(i) + 0x50) + +/* I2C_SDA_FILTER_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */ + +#define I2C_SDA_FILTER_EN (BIT(9)) +#define I2C_SDA_FILTER_EN_M (BIT(9)) +#define I2C_SDA_FILTER_EN_V 0x1 +#define I2C_SDA_FILTER_EN_S 9 + +/* I2C_SCL_FILTER_EN : R/W ;bitpos:[8] ;default: 1'b1 ; */ + +#define I2C_SCL_FILTER_EN (BIT(8)) +#define I2C_SCL_FILTER_EN_M (BIT(8)) +#define I2C_SCL_FILTER_EN_V 0x1 +#define I2C_SCL_FILTER_EN_S 8 + +/* I2C_SDA_FILTER_THRES : R/W ;bitpos:[7:4] ;default: 4'b0 ; */ + +#define I2C_SDA_FILTER_THRES 0x0000000F +#define I2C_SDA_FILTER_THRES_M ((I2C_SDA_FILTER_THRES_V)<<(I2C_SDA_FILTER_THRES_S)) +#define I2C_SDA_FILTER_THRES_V 0xF +#define I2C_SDA_FILTER_THRES_S 4 + +/* I2C_SCL_FILTER_THRES : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ + +#define I2C_SCL_FILTER_THRES 0x0000000F +#define I2C_SCL_FILTER_THRES_M ((I2C_SCL_FILTER_THRES_V)<<(I2C_SCL_FILTER_THRES_S)) +#define I2C_SCL_FILTER_THRES_V 0xF +#define I2C_SCL_FILTER_THRES_S 0 + +#define I2C_CLK_CONF_REG(i) (REG_I2C_BASE(i) + 0x54) + +/* I2C_SCLK_ACTIVE : R/W ;bitpos:[21] ;default: 1'b1 ; */ + +#define I2C_SCLK_ACTIVE (BIT(21)) +#define I2C_SCLK_ACTIVE_M (BIT(21)) +#define I2C_SCLK_ACTIVE_V 0x1 +#define I2C_SCLK_ACTIVE_S 21 + +/* I2C_SCLK_SEL : R/W ;bitpos:[20] ;default: 1'b0 ; */ + +#define I2C_SCLK_SEL (BIT(20)) +#define I2C_SCLK_SEL_M (BIT(20)) +#define I2C_SCLK_SEL_V 0x1 +#define I2C_SCLK_SEL_S 20 + +/* I2C_SCLK_DIV_B : R/W ;bitpos:[19:14] ;default: 6'b0 ; */ + +#define I2C_SCLK_DIV_B 0x0000003F +#define I2C_SCLK_DIV_B_M ((I2C_SCLK_DIV_B_V)<<(I2C_SCLK_DIV_B_S)) +#define I2C_SCLK_DIV_B_V 0x3F +#define I2C_SCLK_DIV_B_S 14 + +/* I2C_SCLK_DIV_A : R/W ;bitpos:[13:8] ;default: 6'b0 ; */ + +#define I2C_SCLK_DIV_A 0x0000003F +#define I2C_SCLK_DIV_A_M ((I2C_SCLK_DIV_A_V)<<(I2C_SCLK_DIV_A_S)) +#define I2C_SCLK_DIV_A_V 0x3F +#define I2C_SCLK_DIV_A_S 8 + +/* I2C_SCLK_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'b0 ; */ + +#define I2C_SCLK_DIV_NUM 0x000000FF +#define I2C_SCLK_DIV_NUM_M ((I2C_SCLK_DIV_NUM_V)<<(I2C_SCLK_DIV_NUM_S)) +#define I2C_SCLK_DIV_NUM_V 0xFF +#define I2C_SCLK_DIV_NUM_S 0 + +#define I2C_COMD0_REG(i) (REG_I2C_BASE(i) + 0x58) + +/* I2C_COMMAND0_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */ + +#define I2C_COMMAND0_DONE (BIT(31)) +#define I2C_COMMAND0_DONE_M (BIT(31)) +#define I2C_COMMAND0_DONE_V 0x1 +#define I2C_COMMAND0_DONE_S 31 + +/* I2C_COMMAND0 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ + +#define I2C_COMMAND0 0x00003FFF +#define I2C_COMMAND0_M ((I2C_COMMAND0_V)<<(I2C_COMMAND0_S)) +#define I2C_COMMAND0_V 0x3FFF +#define I2C_COMMAND0_S 0 + +#define I2C_COMD1_REG(i) (REG_I2C_BASE(i) + 0x5C) + +/* I2C_COMMAND1_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */ + +#define I2C_COMMAND1_DONE (BIT(31)) +#define I2C_COMMAND1_DONE_M (BIT(31)) +#define I2C_COMMAND1_DONE_V 0x1 +#define I2C_COMMAND1_DONE_S 31 + +/* I2C_COMMAND1 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ + +#define I2C_COMMAND1 0x00003FFF +#define I2C_COMMAND1_M ((I2C_COMMAND1_V)<<(I2C_COMMAND1_S)) +#define I2C_COMMAND1_V 0x3FFF +#define I2C_COMMAND1_S 0 + +#define I2C_COMD2_REG(i) (REG_I2C_BASE(i) + 0x60) + +/* I2C_COMMAND2_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */ + +#define I2C_COMMAND2_DONE (BIT(31)) +#define I2C_COMMAND2_DONE_M (BIT(31)) +#define I2C_COMMAND2_DONE_V 0x1 +#define I2C_COMMAND2_DONE_S 31 + +/* I2C_COMMAND2 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ + +#define I2C_COMMAND2 0x00003FFF +#define I2C_COMMAND2_M ((I2C_COMMAND2_V)<<(I2C_COMMAND2_S)) +#define I2C_COMMAND2_V 0x3FFF +#define I2C_COMMAND2_S 0 + +#define I2C_COMD3_REG(i) (REG_I2C_BASE(i) + 0x64) + +/* I2C_COMMAND3_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */ + +#define I2C_COMMAND3_DONE (BIT(31)) +#define I2C_COMMAND3_DONE_M (BIT(31)) +#define I2C_COMMAND3_DONE_V 0x1 +#define I2C_COMMAND3_DONE_S 31 + +/* I2C_COMMAND3 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ + +#define I2C_COMMAND3 0x00003FFF +#define I2C_COMMAND3_M ((I2C_COMMAND3_V)<<(I2C_COMMAND3_S)) +#define I2C_COMMAND3_V 0x3FFF +#define I2C_COMMAND3_S 0 + +#define I2C_COMD4_REG(i) (REG_I2C_BASE(i) + 0x68) + +/* I2C_COMMAND4_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */ + +#define I2C_COMMAND4_DONE (BIT(31)) +#define I2C_COMMAND4_DONE_M (BIT(31)) +#define I2C_COMMAND4_DONE_V 0x1 +#define I2C_COMMAND4_DONE_S 31 + +/* I2C_COMMAND4 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ + +#define I2C_COMMAND4 0x00003FFF +#define I2C_COMMAND4_M ((I2C_COMMAND4_V)<<(I2C_COMMAND4_S)) +#define I2C_COMMAND4_V 0x3FFF +#define I2C_COMMAND4_S 0 + +#define I2C_COMD5_REG(i) (REG_I2C_BASE(i) + 0x6C) + +/* I2C_COMMAND5_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */ + +#define I2C_COMMAND5_DONE (BIT(31)) +#define I2C_COMMAND5_DONE_M (BIT(31)) +#define I2C_COMMAND5_DONE_V 0x1 +#define I2C_COMMAND5_DONE_S 31 + +/* I2C_COMMAND5 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ + +#define I2C_COMMAND5 0x00003FFF +#define I2C_COMMAND5_M ((I2C_COMMAND5_V)<<(I2C_COMMAND5_S)) +#define I2C_COMMAND5_V 0x3FFF +#define I2C_COMMAND5_S 0 + +#define I2C_COMD6_REG(i) (REG_I2C_BASE(i) + 0x70) + +/* I2C_COMMAND6_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */ + +#define I2C_COMMAND6_DONE (BIT(31)) +#define I2C_COMMAND6_DONE_M (BIT(31)) +#define I2C_COMMAND6_DONE_V 0x1 +#define I2C_COMMAND6_DONE_S 31 + +/* I2C_COMMAND6 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ + +#define I2C_COMMAND6 0x00003FFF +#define I2C_COMMAND6_M ((I2C_COMMAND6_V)<<(I2C_COMMAND6_S)) +#define I2C_COMMAND6_V 0x3FFF +#define I2C_COMMAND6_S 0 + +#define I2C_COMD7_REG(i) (REG_I2C_BASE(i) + 0x74) + +/* I2C_COMMAND7_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */ + +#define I2C_COMMAND7_DONE (BIT(31)) +#define I2C_COMMAND7_DONE_M (BIT(31)) +#define I2C_COMMAND7_DONE_V 0x1 +#define I2C_COMMAND7_DONE_S 31 + +/* I2C_COMMAND7 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ + +#define I2C_COMMAND7 0x00003FFF +#define I2C_COMMAND7_M ((I2C_COMMAND7_V)<<(I2C_COMMAND7_S)) +#define I2C_COMMAND7_V 0x3FFF +#define I2C_COMMAND7_S 0 + +#define I2C_SCL_ST_TIME_OUT_REG(i) (REG_I2C_BASE(i) + 0x78) + +/* I2C_SCL_ST_TO_REG : R/W ;bitpos:[4:0] ;default: 5'h10 ; */ + +#define I2C_SCL_ST_TO_REG 0x0000001F +#define I2C_SCL_ST_TO_REG_M ((I2C_SCL_ST_TO_REG_V)<<(I2C_SCL_ST_TO_REG_S)) +#define I2C_SCL_ST_TO_REG_V 0x1F +#define I2C_SCL_ST_TO_REG_S 0 + +#define I2C_SCL_MAIN_ST_TIME_OUT_REG(i) (REG_I2C_BASE(i) + 0x7C) + +/* I2C_SCL_MAIN_ST_TO_REG : R/W ;bitpos:[4:0] ;default: 5'h10 ; */ + +#define I2C_SCL_MAIN_ST_TO_REG 0x0000001F +#define I2C_SCL_MAIN_ST_TO_REG_M ((I2C_SCL_MAIN_ST_TO_REG_V)<<(I2C_SCL_MAIN_ST_TO_REG_S)) +#define I2C_SCL_MAIN_ST_TO_REG_V 0x1F +#define I2C_SCL_MAIN_ST_TO_REG_S 0 + +#define I2C_SCL_SP_CONF_REG(i) (REG_I2C_BASE(i) + 0x80) + +/* I2C_SDA_PD_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ + +#define I2C_SDA_PD_EN (BIT(7)) +#define I2C_SDA_PD_EN_M (BIT(7)) +#define I2C_SDA_PD_EN_V 0x1 +#define I2C_SDA_PD_EN_S 7 + +/* I2C_SCL_PD_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */ + +#define I2C_SCL_PD_EN (BIT(6)) +#define I2C_SCL_PD_EN_M (BIT(6)) +#define I2C_SCL_PD_EN_V 0x1 +#define I2C_SCL_PD_EN_S 6 + +/* I2C_SCL_RST_SLV_NUM : R/W ;bitpos:[5:1] ;default: 5'b0 ; */ + +#define I2C_SCL_RST_SLV_NUM 0x0000001F +#define I2C_SCL_RST_SLV_NUM_M ((I2C_SCL_RST_SLV_NUM_V)<<(I2C_SCL_RST_SLV_NUM_S)) +#define I2C_SCL_RST_SLV_NUM_V 0x1F +#define I2C_SCL_RST_SLV_NUM_S 1 + +/* I2C_SCL_RST_SLV_EN : R/W/SC ;bitpos:[0] ;default: 1'b0 ; */ + +#define I2C_SCL_RST_SLV_EN (BIT(0)) +#define I2C_SCL_RST_SLV_EN_M (BIT(0)) +#define I2C_SCL_RST_SLV_EN_V 0x1 +#define I2C_SCL_RST_SLV_EN_S 0 + +#define I2C_SCL_STRETCH_CONF_REG(i) (REG_I2C_BASE(i) + 0x84) + +/* I2C_SLAVE_BYTE_ACK_LVL : R/W ;bitpos:[13] ;default: 1'b0 ; */ + +#define I2C_SLAVE_BYTE_ACK_LVL (BIT(13)) +#define I2C_SLAVE_BYTE_ACK_LVL_M (BIT(13)) +#define I2C_SLAVE_BYTE_ACK_LVL_V 0x1 +#define I2C_SLAVE_BYTE_ACK_LVL_S 13 + +/* I2C_SLAVE_BYTE_ACK_CTL_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ + +#define I2C_SLAVE_BYTE_ACK_CTL_EN (BIT(12)) +#define I2C_SLAVE_BYTE_ACK_CTL_EN_M (BIT(12)) +#define I2C_SLAVE_BYTE_ACK_CTL_EN_V 0x1 +#define I2C_SLAVE_BYTE_ACK_CTL_EN_S 12 + +/* I2C_SLAVE_SCL_STRETCH_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */ + +#define I2C_SLAVE_SCL_STRETCH_CLR (BIT(11)) +#define I2C_SLAVE_SCL_STRETCH_CLR_M (BIT(11)) +#define I2C_SLAVE_SCL_STRETCH_CLR_V 0x1 +#define I2C_SLAVE_SCL_STRETCH_CLR_S 11 + +/* I2C_SLAVE_SCL_STRETCH_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ + +#define I2C_SLAVE_SCL_STRETCH_EN (BIT(10)) +#define I2C_SLAVE_SCL_STRETCH_EN_M (BIT(10)) +#define I2C_SLAVE_SCL_STRETCH_EN_V 0x1 +#define I2C_SLAVE_SCL_STRETCH_EN_S 10 + +/* I2C_STRETCH_PROTECT_NUM : R/W ;bitpos:[9:0] ;default: 10'b0 ; */ + +#define I2C_STRETCH_PROTECT_NUM 0x000003FF +#define I2C_STRETCH_PROTECT_NUM_M ((I2C_STRETCH_PROTECT_NUM_V)<<(I2C_STRETCH_PROTECT_NUM_S)) +#define I2C_STRETCH_PROTECT_NUM_V 0x3FF +#define I2C_STRETCH_PROTECT_NUM_S 0 + +#define I2C_DATE_REG(i) (REG_I2C_BASE(i) + 0xF8) + +/* I2C_DATE : R/W ;bitpos:[31:0] ;default: 32'h20070201 ; */ + +#define I2C_DATE 0xFFFFFFFF +#define I2C_DATE_M ((I2C_DATE_V)<<(I2C_DATE_S)) +#define I2C_DATE_V 0xFFFFFFFF +#define I2C_DATE_S 0 + +#define I2C_TXFIFO_START_ADDR_REG(i) (REG_I2C_BASE(i) + 0x100) + +#define I2C_RXFIFO_START_ADDR_REG(i) (REG_I2C_BASE(i) + 0x180) + +#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_I2C_H */