diff --git a/arch/risc-v/Kconfig b/arch/risc-v/Kconfig index 416fe2eeb87..5e45b252942 100644 --- a/arch/risc-v/Kconfig +++ b/arch/risc-v/Kconfig @@ -126,7 +126,7 @@ config ARCH_CHIP_ESP32C6 select ARCH_RV_ISA_A select ARCH_RV_ISA_C select ARCH_VECNOTIRQ - select ARCH_HAVE_BOOTLOADER + select ARCH_HAVE_BOOTLOADER if !ESPRESSIF_SIMPLE_BOOT select ARCH_HAVE_MPU select ARCH_HAVE_RESET select ARCH_HAVE_RNG diff --git a/arch/risc-v/src/common/espressif/Kconfig b/arch/risc-v/src/common/espressif/Kconfig index d7aa8236f1c..2d58edfe5f0 100644 --- a/arch/risc-v/src/common/espressif/Kconfig +++ b/arch/risc-v/src/common/espressif/Kconfig @@ -156,7 +156,7 @@ menu "Bootloader and Image Configuration" config ESPRESSIF_SIMPLE_BOOT bool depends on !ESPRESSIF_BOOTLOADER_MCUBOOT - default y if ESPRESSIF_ESP32C3 + default y if ESPRESSIF_ESP32C3 || ESPRESSIF_ESP32C6 config ESPRESSIF_BOOTLOADER_MCUBOOT bool "Enable MCUboot-bootable format" diff --git a/arch/risc-v/src/common/espressif/Make.defs b/arch/risc-v/src/common/espressif/Make.defs index dabc97ce133..edd69192f37 100644 --- a/arch/risc-v/src/common/espressif/Make.defs +++ b/arch/risc-v/src/common/espressif/Make.defs @@ -95,7 +95,7 @@ endif ESP_HAL_3RDPARTY_REPO = esp-hal-3rdparty ifndef ESP_HAL_3RDPARTY_VERSION - ESP_HAL_3RDPARTY_VERSION = 7951b5b282384ec43858a28ddfabbef7b6b326cb + ESP_HAL_3RDPARTY_VERSION = ca8717cdfa8754caa684a44949070b8da4b6048a endif ifndef ESP_HAL_3RDPARTY_URL diff --git a/arch/risc-v/src/common/espressif/esp_start.c b/arch/risc-v/src/common/espressif/esp_start.c index e8243809a5e..1d84219a788 100644 --- a/arch/risc-v/src/common/espressif/esp_start.c +++ b/arch/risc-v/src/common/espressif/esp_start.c @@ -276,13 +276,15 @@ static int map_rom_segments(uint32_t app_drom_start, uint32_t app_drom_vaddr, * is later invalidated by the elf2image command. */ - if (IS_DROM(segment_hdr.load_addr)) + if (IS_DROM(segment_hdr.load_addr) && + segment_hdr.load_addr == (uint32_t)_image_drom_vma) { app_drom_start = offset + sizeof(esp_image_segment_header_t); app_drom_start_aligned = app_drom_start & MMU_FLASH_MASK; } - if (IS_IROM(segment_hdr.load_addr)) + if (IS_IROM(segment_hdr.load_addr) && + segment_hdr.load_addr == (uint32_t)_image_irom_vma) { app_irom_start = offset + sizeof(esp_image_segment_header_t); app_irom_start_aligned = app_irom_start & MMU_FLASH_MASK; diff --git a/arch/risc-v/src/esp32c6/hal_esp32c6.mk b/arch/risc-v/src/esp32c6/hal_esp32c6.mk index 0752da95b25..e377053595f 100644 --- a/arch/risc-v/src/esp32c6/hal_esp32c6.mk +++ b/arch/risc-v/src/esp32c6/hal_esp32c6.mk @@ -52,6 +52,15 @@ INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/compone INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/spi_flash/include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/spi_flash/include/spi_flash +ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y) + INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/include + INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/private_include + INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/bootloader_flash/include + INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/spi_flash/include + INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/spi_flash/include/spi_flash + INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_app_format/include +endif + # Linker scripts ARCHSCRIPT += $(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_rom/$(CHIP_SERIES)/ld/$(CHIP_SERIES).rom.ld @@ -84,6 +93,7 @@ CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHI CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES)/pmu_param.c CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES)/pmu_sleep.c CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES)/rtc_clk.c +CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES)/rtc_clk_init.c CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES)/rtc_time.c CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES)/sar_periph_ctrl.c CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES)/systimer.c @@ -102,8 +112,12 @@ CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/lp_timer_hal.c CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/rmt_hal.c CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/timer_hal.c CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/timer_hal_iram.c +CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/cache_hal.c +CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/mpu_hal.c +CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/mmu_hal.c CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/uart_hal.c CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/uart_hal_iram.c +CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/wdt_hal_iram.c CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/$(CHIP_SERIES)/clk_tree_hal.c CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/$(CHIP_SERIES)/efuse_hal.c CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/$(CHIP_SERIES)/modem_clock_hal.c @@ -113,3 +127,33 @@ CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/riscv/interrupt.c CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/soc/$(CHIP_SERIES)/gpio_periph.c CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/soc/$(CHIP_SERIES)/ledc_periph.c CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/soc/$(CHIP_SERIES)/rmt_periph.c + +ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y) + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/nuttx/src/bootloader_banner_wrap.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/bootloader_console.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/bootloader_console_loader.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/${CHIP_SERIES}/bootloader_${CHIP_SERIES}.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/bootloader_init.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/bootloader_common.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/bootloader_common_loader.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/bootloader_flash/src/bootloader_flash.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_${CHIP_SERIES}.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/bootloader_clock_init.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/bootloader_clock_loader.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/bootloader_efuse.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/bootloader_mem.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/bootloader_random.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/bootloader_random_${CHIP_SERIES}.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/esp_image_format.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/${CHIP_SERIES}/bootloader_soc.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/${CHIP_SERIES}/bootloader_sha.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/flash_encrypt.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/soc/${CHIP_SERIES}/uart_periph.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_rom/patches/esp_rom_uart.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_rom/patches/esp_rom_sys.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_rom/patches/esp_rom_spiflash.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/efuse/src/esp_efuse_fields.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/efuse/src/efuse_controller/keys/with_key_purposes/esp_efuse_api_key.c + + LDFLAGS += --wrap=bootloader_print_banner +endif diff --git a/boards/risc-v/esp32c6/common/scripts/esp32c6_flat_memory.ld b/boards/risc-v/esp32c6/common/scripts/esp32c6_flat_memory.ld index 153fe079a7f..6abb97699e1 100644 --- a/boards/risc-v/esp32c6/common/scripts/esp32c6_flat_memory.ld +++ b/boards/risc-v/esp32c6/common/scripts/esp32c6_flat_memory.ld @@ -34,11 +34,9 @@ #define SRAM_IRAM_START 0x40800000 #define SRAM_DRAM_START 0x40800000 -#define I_D_SRAM_OFFSET (SRAM_IRAM_START - SRAM_DRAM_START) - /* 2nd stage bootloader iram_loader_seg start address */ -#define SRAM_DRAM_END (0x4086e610 - I_D_SRAM_OFFSET) +#define SRAM_DRAM_END (0x4086e610) #define SRAM_IRAM_ORG (SRAM_IRAM_START) #define SRAM_DRAM_ORG (SRAM_DRAM_START) @@ -54,6 +52,13 @@ MEMORY { +#ifdef CONFIG_ESPRESSIF_SIMPLE_BOOT + /* The 0x20 offset is a convenience for the app binary image generation */ + + ROM (R) : org = 0x20, + len = IDRAM0_2_SEG_SIZE - 0x20 +#endif + /* Below values assume the flash cache is on, and have the blocks this * uses subtracted from the length of the various regions. The 'data access * port' dram/drom regions map to the same iram/irom regions but are diff --git a/boards/risc-v/esp32c6/common/scripts/esp32c6_simple_boot_sections.ld b/boards/risc-v/esp32c6/common/scripts/esp32c6_simple_boot_sections.ld new file mode 100644 index 00000000000..fc903daf01f --- /dev/null +++ b/boards/risc-v/esp32c6/common/scripts/esp32c6_simple_boot_sections.ld @@ -0,0 +1,411 @@ +/**************************************************************************** + * boards/risc-v/esp32c6/common/scripts/esp32c6_simple_boot_sections.ld + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Default entry point: */ + +ENTRY(__start); + +SECTIONS +{ + .iram0.text : + { + _iram_start = ABSOLUTE(.); + + /* Vectors go to start of IRAM */ + + KEEP(*(.exception_vectors.text)); + . = ALIGN(4); + + *(.iram1) + *(.iram1.*) + *libsched.a:irq_dispatch.*(.text .text.* .literal .literal.*) + + *libarch.a:*brownout.*(.text .text.* .literal .literal.*) + *libarch.a:*cpu.*(.text .text.* .literal .literal.*) + *libarch.a:*gpio_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*periph_ctrl.*(.text .text.* .literal .literal.*) + *libarch.a:*clk.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_clk.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_clk_tree.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_clk_tree_common.*(.text .text.* .literal .literal.*) + *libarch.a:*clk_tree_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*pmu_init.*(.text .text.* .literal .literal.*) + *libarch.a:*modem_clock.*(.text .text.* .literal .literal.*) + *libarch.a:*regi2c_ctrl.*(.text .text.* .literal .literal.*) + *libarch.a:*gpio_periph.*(.text .text.* .literal .literal.*) + *libarch.a:*modem_clock_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_rom_systimer.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_rom_wdt.*(.text .text.* .literal .literal.*) + *libarch.a:*ocode_init.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_rom_regi2c_esp32c6.*(.text .text.* .literal .literal.*) + *libarch.a:*rtc_clk.*(.text .text.* .literal .literal.*) + *libarch.a:*rtc_clk_init.*(.text .text.* .literal .literal.*) + *libarch.a:*pmu_sleep.*(.text .text.* .literal .literal.*) + *libarch.a:*pmu_param.*(.text .text.* .literal .literal.*) + *libarch.a:*rtc_time.*(.text .text.* .literal .literal.*) + *libarch.a:*systimer.*(.text .text.* .literal .literal.*) + *libarch.a:*systimer_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*uart_hal_iram.*(.text .text.* .literal .literal.*) + *libarch.a:*wdt_hal_iram.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_banner_wrap.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_init.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_common.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_common_loader.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_console.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_console_loader.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_esp32c6.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_flash.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_flash_config_esp32c6.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_clock_init.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_clock_loader.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_efuse.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_panic.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_mem.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_random.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_random_esp32c6.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_image_format.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_soc.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_sha.*(.text .text.* .literal .literal.*) + *libarch.a:*flash_encrypt.*(.text .text.* .literal .literal.*) + *libarch.a:*cache_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*uart_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*mpu_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*mmu_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*uart_periph.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_rom_uart.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_rom_sys.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_rom_spiflash.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_efuse_fields.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_efuse_api_key.*(.text .text.* .literal .literal.*) + *libarch.a:*efuse_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*log.*(.text .text.* .literal .literal.*) + *libarch.a:*log_noos.*(.text .text.* .literal .literal.*) + *libarch.a:esp_spiflash.*(.literal .text .literal.* .text.*) + + esp_head.*(.literal .text .literal.* .text.*) + esp_start.*(.literal .text .literal.* .text.*) + + } >iram0_0_seg AT > ROM + + /* Marks the end of IRAM code segment */ + + .iram0.text_end (NOLOAD) : + { + . = ALIGN (16); + } >iram0_0_seg + + .iram0.data : + { + . = ALIGN(16); + *(.iram.data) + *(.iram.data*) + } >iram0_0_seg + + .iram0.bss (NOLOAD) : + { + . = ALIGN(16); + *(.iram.bss) + *(.iram.bss*) + + . = ALIGN(16); + _iram_end = ABSOLUTE(.); + } >iram0_0_seg + + /* This section is required to skip .iram0.text area because iram0_0_seg + * and dram0_0_seg reflect the same address space on different buses. + */ + + .dram0.dummy (NOLOAD): + { + . = ORIGIN(dram0_0_seg) + _iram_end - _iram_start; + } >dram0_0_seg + + /* Shared RAM */ + + .dram0.bss (NOLOAD) : + { + . = ALIGN (8); + _bss_start = ABSOLUTE(.); + _sbss = ABSOLUTE(.); + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + *(.dynbss) + *(.bss) + *(.bss.*) + *(.share.mem) + *(.gnu.linkonce.b.*) + *(COMMON) + + . = ALIGN (8); + _ebss = ABSOLUTE(.); + _bss_end = ABSOLUTE(.); + } >dram0_0_seg + + .noinit (NOLOAD): + { + /* This section contains data that is not initialized during load, + * or during the application's initialization sequence. + */ + + *(.noinit) + *(.noinit.*) + } >dram0_0_seg + + .dram0.data : + { + . = ALIGN (16); + _data_start = ABSOLUTE(.); + _sdata = ABSOLUTE(.); + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + *(.data1) + __global_pointer$ = . + 0x800; + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + *(.jcr) + *(.dram1) + *(.dram1.*) + *libsched.a:irq_dispatch.*(.rodata .rodata.*) + + *libarch.a:*brownout.*(.rodata .rodata.*) + *libarch.a:*cpu.*(.rodata .rodata.*) + *libarch.a:*gpio_hal.*(.rodata .rodata.*) + *libarch.a:*periph_ctrl.*(.rodata .rodata.*) + *libarch.a:*clk.*(.rodata .rodata.*) + *libarch.a:*esp_clk.*(.rodata .rodata.*) + *libarch.a:*esp_clk_tree.*(.rodata .rodata.*) + *libarch.a:*esp_clk_tree_common.*(.rodata .rodata.*) + *libarch.a:*clk_tree_hal.*(.rodata .rodata.*) + *libarch.a:*pmu_init.*(.rodata .rodata.*) + *libarch.a:*modem_clock.*(.rodata .rodata.*) + *libarch.a:*regi2c_ctrl.*(.rodata .rodata.*) + *libarch.a:*gpio_periph.*(.rodata .rodata.*) + *libarch.a:*modem_clock_hal.*(.rodata .rodata.*) + *libarch.a:*esp_rom_systimer.*(.rodata .rodata.*) + *libarch.a:*esp_rom_wdt.*(.rodata .rodata.*) + *libarch.a:*ocode_init.*(.rodata .rodata.*) + *libarch.a:*esp_rom_regi2c_esp32c6.*(.rodata .rodata.*) + *libarch.a:*rtc_clk.*(.rodata .rodata.*) + *libarch.a:*rtc_clk_init.*(.rodata .rodata.*) + *libarch.a:*pmu_param.*(.rodata .rodata.*) + *libarch.a:*pmu_sleep.*(.rodata .rodata.*) + *libarch.a:*rtc_time.*(.rodata .rodata.*) + *libarch.a:*systimer.*(.rodata .rodata.*) + *libarch.a:*systimer_hal.*(.rodata .rodata.*) + *libarch.a:*uart_hal_iram.*(.rodata .rodata.*) + *libarch.a:*wdt_hal_iram.*(.rodata .rodata.*) + *libarch.a:*bootloader_banner_wrap.*(.rodata .rodata.*) + *libarch.a:*bootloader_init.*(.rodata .rodata.*) + *libarch.a:*bootloader_common.*(.rodata .rodata.*) + *libarch.a:*bootloader_common_loader.*(.rodata .rodata.*) + *libarch.a:*bootloader_console.*(.rodata .rodata.*) + *libarch.a:*bootloader_console_loader.*(.rodata .rodata.*) + *libarch.a:*bootloader_esp32c6.*(.rodata .rodata.*) + *libarch.a:*bootloader_flash.*(.rodata .rodata.*) + *libarch.a:*bootloader_flash_config_esp32c6.*(.rodata .rodata.*) + *libarch.a:*bootloader_clock_init.*(.rodata .rodata.*) + *libarch.a:*bootloader_clock_loader.*(.rodata .rodata.*) + *libarch.a:*bootloader_efuse.*(.rodata .rodata.*) + *libarch.a:*bootloader_panic.*(.rodata .rodata.*) + *libarch.a:*bootloader_mem.*(.rodata .rodata.*) + *libarch.a:*bootloader_random.*(.rodata .rodata.*) + *libarch.a:*bootloader_random_esp32c6.*(.rodata .rodata.*) + *libarch.a:*esp_image_format.*(.rodata .rodata.*) + *libarch.a:*bootloader_soc.*(.rodata .rodata.*) + *libarch.a:*bootloader_sha.*(.rodata .rodata.*) + *libarch.a:*flash_encrypt.*(.rodata .rodata.*) + *libarch.a:*cache_hal.*(.rodata .rodata.*) + *libarch.a:*uart_hal.*(.rodata .rodata.*) + *libarch.a:*mpu_hal.*(.rodata .rodata.*) + *libarch.a:*mmu_hal.*(.rodata .rodata.*) + *libarch.a:*uart_periph.*(.rodata .rodata.*) + *libarch.a:*esp_rom_uart.*(.rodata .rodata.*) + *libarch.a:*esp_rom_sys.*(.rodata .rodata.*) + *libarch.a:*esp_rom_spiflash.*(.rodata .rodata.*) + *libarch.a:*esp_efuse_fields.*(.rodata .rodata.*) + *libarch.a:*esp_efuse_api_key.*(.rodata .rodata.*) + *libarch.a:*efuse_hal.*(.rodata .rodata.*) + *libarch.a:*log.*(.rodata .rodata.*) + *libarch.a:*log_noos.*(.rodata .rodata.*) + *libarch.a:esp_spiflash.*(.rodata .rodata.*) + + esp_head.*(.rodata .rodata.*) + esp_start.*(.rodata .rodata.*) + + . = ALIGN(4); + _edata = ABSOLUTE(.); + _data_end = ABSOLUTE(.); + + /* Heap starts at the end of .data */ + + _sheap = ABSOLUTE(.); + } >dram0_0_seg AT > ROM + + _image_irom_vma = ADDR(.flash.text); + _image_irom_lma = LOADADDR(.flash.text); + _image_irom_size = SIZEOF(.flash.text); + + .flash.text_dummy (NOLOAD) : + { + . = ALIGN(0x10000); + } > ROM + + .flash.text : + { + _stext = .; + + *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) + *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.fini.literal) + *(.fini) + *(.gnu.version) + _etext = .; + + /* Similar to _iram_start, this symbol goes here so it is + * resolved by addr2line in preference to the first symbol in + * the flash.text segment. + */ + + _flash_cache_start = ABSOLUTE(0); + } >default_code_seg AT > ROM + + .flash_rodata_dummy (NOLOAD) : + { + . += SIZEOF(.flash.text); + . = ALIGN(0x10000); + } >default_rodata_seg AT > ROM + + _image_drom_vma = ADDR(.flash.rodata); + _image_drom_lma = LOADADDR(.flash.rodata); + _image_drom_size = SIZEOF(.flash.rodata); + + .flash.rodata : + { + _srodata = ABSOLUTE(.); + + *(.rodata) + *(.rodata.*) + + *(.srodata.*) + + *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.gnu.linkonce.r.*) + *(.rodata1) + __XT_EXCEPTION_TABLE_ = ABSOLUTE(.); + *(.xt_except_table) + *(.gcc_except_table .gcc_except_table.*) + *(.gnu.linkonce.e.*) + *(.gnu.version_r) + . = (. + 3) & ~ 3; + __eh_frame = ABSOLUTE(.); + KEEP(*(.eh_frame)) + . = (. + 7) & ~ 3; + + /* C++ constructor and destructor tables: + * RISC-V GCC is configured with --enable-initfini-array so it emits an + * .init_array section instead. + */ + + _sinit = ABSOLUTE(.); + KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array.*)) + KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array)) + _einit = ABSOLUTE(.); + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + + /* C++ exception handlers table: */ + + __XT_EXCEPTION_DESCS_ = ABSOLUTE(.); + *(.xt_except_desc) + *(.gnu.linkonce.h.*) + __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); + *(.xt_except_desc_end) + *(.dynamic) + *(.gnu.version_d) + _erodata = ABSOLUTE(.); + + /* Literals are also RO data. */ + + _lit4_start = ABSOLUTE(.); + *(*.lit4) + *(.lit4.*) + *(.gnu.linkonce.lit4.*) + _lit4_end = ABSOLUTE(.); + . = ALIGN(4); + } >default_rodata_seg AT > ROM + + /* RTC fast memory holds RTC wake stub code !*/ + + .rtc.text : + { + . = ALIGN(4); + *(.rtc.literal .rtc.text) + } >rtc_iram_seg + + /* RTC BSS section. */ + + .rtc.bss (NOLOAD) : + { + *(.rtc.bss) + } >rtc_iram_seg + + /* RTC data section holds RTC wake stub data/rodata. */ + + .rtc.data : + { + *(.rtc.data) + *(.rtc.rodata) + } >rtc_iram_seg + + /* This section holds RTC data that should have fixed addresses. + * The data are not initialized at power-up and are retained during deep sleep. + */ + .rtc_reserved (NOLOAD): + { + . = ALIGN(4); + _rtc_reserved_start = ABSOLUTE(.); + /* New data can only be added here to ensure existing data are not moved. + Because data have adhered to the end of the segment and code is relied on it. + >> put new data here << */ + + *(.rtc_timer_data_in_rtc_mem .rtc_timer_data_in_rtc_mem.*) + KEEP(*(.bootloader_data_rtc_mem .bootloader_data_rtc_mem.*)) + _rtc_reserved_end = ABSOLUTE(.); + } > rtc_reserved_seg + + _rtc_reserved_length = _rtc_reserved_end - _rtc_reserved_start; + ASSERT((_rtc_reserved_length <= LENGTH(rtc_reserved_seg)), + "RTC reserved segment data does not fit.") + +} + diff --git a/boards/risc-v/esp32c6/esp32c6-devkit/scripts/Make.defs b/boards/risc-v/esp32c6/esp32c6-devkit/scripts/Make.defs index 772e0680956..38fa38b762e 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkit/scripts/Make.defs +++ b/boards/risc-v/esp32c6/esp32c6-devkit/scripts/Make.defs @@ -31,9 +31,13 @@ CHIP_SERIES = $(patsubst "%",%,$(CONFIG_ESPRESSIF_CHIP_SERIES)) # pick the common linker scripts. ARCHSCRIPT += $(BOARD_COMMON_DIR)/scripts/$(CHIP_SERIES)_aliases.ld - ARCHSCRIPT += $(call FINDSCRIPT,$(CHIP_SERIES)_flat_memory.ld) -ARCHSCRIPT += $(call FINDSCRIPT,$(CHIP_SERIES)_legacy_sections.ld) + +ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y) + ARCHSCRIPT += $(call FINDSCRIPT,$(CHIP_SERIES)_simple_boot_sections.ld) +else + ARCHSCRIPT += $(call FINDSCRIPT,$(CHIP_SERIES)_legacy_sections.ld) +endif ARCHPICFLAGS = -fpic