diff --git a/ChangeLog b/ChangeLog
index 54450842549..2c2c129ff2b 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -5408,3 +5408,7 @@
 	  conversions from physical to virtual addresses (2013-8-14).
 	* arch/arm/src/sama5/sam_ohci.c:  Add D cache contols and conversion
 	  between physical and virtual address (2013-8-14).
+	* arch/arm/src/stm32/stm32_spi.c:  nbits() interface extended to
+	  control bit order as well as bit width (from Teemu Pirinen)
+	  (2013-8-16)
+
diff --git a/arch/arm/src/stm32/stm32_spi.c b/arch/arm/src/stm32/stm32_spi.c
index 9bb072419cd..1f50d9e23d0 100644
--- a/arch/arm/src/stm32/stm32_spi.c
+++ b/arch/arm/src/stm32/stm32_spi.c
@@ -200,7 +200,7 @@ struct stm32_spidev_s
   sem_t            exclsem;    /* Held while chip is selected for mutual exclusion */
   uint32_t         frequency;  /* Requested clock frequency */
   uint32_t         actual;     /* Actual clock frequency */
-  uint8_t          nbits;      /* Width of word in bits (8 or 16) */
+  int8_t           nbits;      /* Width of word in bits (8 or 16) */
   uint8_t          mode;       /* Mode 0,1,2,3 */
 #endif
 };
@@ -1153,14 +1153,24 @@ static void spi_setbits(FAR struct spi_dev_s *dev, int nbits)
 
       switch (nbits)
         {
+        case -8:
+          setbits = SPI_CR1_LSBFIRST;
+          clrbits = SPI_CR1_DFF;
+          break;
+
         case 8:
           setbits = 0;
-          clrbits = SPI_CR1_DFF;
+          clrbits = SPI_CR1_DFF|SPI_CR1_LSBFIRST;
+          break;
+
+        case -16:
+          setbits = SPI_CR1_DFF|SPI_CR1_LSBFIRST;
+          clrbits = 0;
           break;
 
         case 16:
           setbits = SPI_CR1_DFF;
-          clrbits = 0;
+          clrbits = SPI_CR1_LSBFIRST;
           break;
 
         default: