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https://github.com/apache/nuttx.git
synced 2026-06-05 15:58:59 +08:00
SAMD20: Now runs, but no serial output
This commit is contained in:
@@ -96,11 +96,11 @@
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*/
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*/
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#define GPIO_PULL_SHIFT (20) /* Bits 20-21: Pull-up/down resistor control */
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#define GPIO_PULL_SHIFT (20) /* Bits 20-21: Pull-up/down resistor control */
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#define GPIO_PULL_MASK (3 << GPIO_FUNC_SHIFT)
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#define GPIO_PULL_MASK (3 << GPIO_PULL_SHIFT)
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# define GPIO_PULL_NONE (0 << GPIO_FUNC_SHIFT)
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# define GPIO_PULL_NONE (0 << GPIO_PULL_SHIFT)
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# define GPIO_PULL_UP (1 << GPIO_FUNC_SHIFT)
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# define GPIO_PULL_UP (1 << GPIO_PULL_SHIFT)
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# define GPIO_PULL_DOWN (2 << GPIO_FUNC_SHIFT)
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# define GPIO_PULL_DOWN (2 << GPIO_PULL_SHIFT)
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# define GPIO_PULL_BUSKEEPER (3 << GPIO_FUNC_SHIFT)
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# define GPIO_PULL_BUSKEEPER (3 << GPIO_PULL_SHIFT)
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/* Peripheral Function
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/* Peripheral Function
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*
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*
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@@ -116,21 +116,21 @@ sam_wait_synchronization(const struct sam_usart_config_s * const config)
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static inline void
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static inline void
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sam_gclk_configure(const struct sam_usart_config_s * const config)
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sam_gclk_configure(const struct sam_usart_config_s * const config)
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{
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{
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uint8_t regval;
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uint16_t regval;
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uint8_t glckcore;
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uint8_t glckcore;
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/* Set up the SERCOMn_GCLK_ID_CORE clock */
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/* Set up the SERCOMn_GCLK_ID_CORE clock */
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glckcore = (uint8_t)SERCOM_GCLK_ID_CORE(config->sercom);
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glckcore = (uint8_t)SERCOM_GCLK_ID_CORE(config->sercom);
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regval = (glckcore << GCLK_CLKCTRL_ID_SHIFT);
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regval = ((uint16_t)glckcore << GCLK_CLKCTRL_ID_SHIFT);
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/* Select and disable generic clock channel */
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/* Select and disable generic clock channel */
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putreg8(regval, SAM_GCLK_CLKCTRL);
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putreg16(regval, SAM_GCLK_CLKCTRL);
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/* Wait for clock to become disabled */
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/* Wait for clock to become disabled */
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while ((getreg8(SAM_GCLK_CLKCTRL) & GCLK_CLKCTRL_CLKEN) != 0);
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while ((getreg16(SAM_GCLK_CLKCTRL) & GCLK_CLKCTRL_CLKEN) != 0);
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/* Select the SERCOMn_GCLK_ID_CORE clock generator */
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/* Select the SERCOMn_GCLK_ID_CORE clock generator */
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@@ -147,12 +147,12 @@ sam_gclk_configure(const struct sam_usart_config_s * const config)
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/* Write the new configuration */
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/* Write the new configuration */
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putreg8(regval, SAM_GCLK_CLKCTRL);
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putreg16(regval, SAM_GCLK_CLKCTRL);
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/* Enable the GCLK */
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/* Enable the GCLK */
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regval |= GCLK_CLKCTRL_CLKEN;
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regval |= GCLK_CLKCTRL_CLKEN;
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putreg8(regval, SAM_GCLK_CLKCTRL);
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putreg16(regval, SAM_GCLK_CLKCTRL);
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/* Set up the SERCOM_GCLK_ID_SLOW clock */
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/* Set up the SERCOM_GCLK_ID_SLOW clock */
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@@ -160,11 +160,11 @@ sam_gclk_configure(const struct sam_usart_config_s * const config)
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/* Select and disable generic clock channel */
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/* Select and disable generic clock channel */
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putreg8(regval, SAM_GCLK_CLKCTRL);
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putreg16(regval, SAM_GCLK_CLKCTRL);
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/* Wait for clock to become disabled */
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/* Wait for clock to become disabled */
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while ((getreg8(SAM_GCLK_CLKCTRL) & GCLK_CLKCTRL_CLKEN) != 0);
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while ((getreg16(SAM_GCLK_CLKCTRL) & GCLK_CLKCTRL_CLKEN) != 0);
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/* Select the SERCOM_GCLK_ID_SLOW clock generator */
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/* Select the SERCOM_GCLK_ID_SLOW clock generator */
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@@ -181,12 +181,12 @@ sam_gclk_configure(const struct sam_usart_config_s * const config)
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/* Write the new configuration */
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/* Write the new configuration */
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putreg8(regval, SAM_GCLK_CLKCTRL);
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putreg16(regval, SAM_GCLK_CLKCTRL);
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/* Enable the GCLK */
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/* Enable the GCLK */
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regval |= GCLK_CLKCTRL_CLKEN;
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regval |= GCLK_CLKCTRL_CLKEN;
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putreg8(regval, SAM_GCLK_CLKCTRL);
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putreg16(regval, SAM_GCLK_CLKCTRL);
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}
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}
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#endif
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#endif
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@@ -317,7 +317,7 @@ sam_usart_configure(const struct sam_usart_config_s * const config)
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/* Write configuration to CTRLA */
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/* Write configuration to CTRLA */
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putreg32(ctrlb, config->base + SAM_USART_CTRLA_OFFSET);
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putreg32(ctrla, config->base + SAM_USART_CTRLA_OFFSET);
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return OK;
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return OK;
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}
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}
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#endif
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#endif
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@@ -146,7 +146,7 @@ static inline void sam_configinput(uintptr_t base, port_pinset_t pinset)
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{
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{
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/* Select the upper half word and adjust the bit setting */
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/* Select the upper half word and adjust the bit setting */
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regval = PORT_WRCONFIG_HWSEL;
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regval |= PORT_WRCONFIG_HWSEL;
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pin -= 16;
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pin -= 16;
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}
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}
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@@ -243,7 +243,7 @@ static inline void sam_configoutput(uintptr_t base, port_pinset_t pinset)
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{
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{
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/* Select the upper half word and adjust the bit setting */
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/* Select the upper half word and adjust the bit setting */
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regval = PORT_WRCONFIG_HWSEL;
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regval |= PORT_WRCONFIG_HWSEL;
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pin -= 16;
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pin -= 16;
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}
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}
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@@ -320,7 +320,7 @@ static inline void sam_configperiph(uintptr_t base, port_pinset_t pinset)
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{
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{
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/* Select the upper half word and adjust the bit setting */
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/* Select the upper half word and adjust the bit setting */
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regval = PORT_WRCONFIG_HWSEL;
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regval |= PORT_WRCONFIG_HWSEL;
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pin -= 16;
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pin -= 16;
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}
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}
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@@ -329,7 +329,7 @@ static inline void sam_configperiph(uintptr_t base, port_pinset_t pinset)
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/* Set the pin function */
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/* Set the pin function */
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func = (pinset & PORT_FUNC_MASK) >> PORT_FUNC_SHIFT;
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func = (pinset & PORT_FUNC_MASK) >> PORT_FUNC_SHIFT;
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regval = (func << PORT_WRCONFIG_PMUX_SHIFT);
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regval |= (func << PORT_WRCONFIG_PMUX_SHIFT);
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/* Check for pull-up/down selection */
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/* Check for pull-up/down selection */
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@@ -401,7 +401,7 @@ static inline void sam_configreset(uintptr_t base, port_pinset_t pinset)
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{
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{
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/* Select the upper half word and adjust the bit setting */
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/* Select the upper half word and adjust the bit setting */
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regval = PORT_WRCONFIG_HWSEL;
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regval |= PORT_WRCONFIG_HWSEL;
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pin -= 16;
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pin -= 16;
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}
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}
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@@ -106,10 +106,10 @@
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*/
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*/
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#define PORT_PULL_SHIFT (20) /* Bits 20-21: Pull-up/down resistor control */
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#define PORT_PULL_SHIFT (20) /* Bits 20-21: Pull-up/down resistor control */
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#define PORT_PULL_MASK (3 << PORT_FUNC_SHIFT)
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#define PORT_PULL_MASK (3 << PORT_PULL_SHIFT)
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# define PORT_PULL_NONE (0 << PORT_FUNC_SHIFT)
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# define PORT_PULL_NONE (0 << PORT_PULL_SHIFT)
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# define PORT_PULL_UP (1 << PORT_FUNC_SHIFT)
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# define PORT_PULL_UP (1 << PORT_PULL_SHIFT)
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# define PORT_PULL_DOWN (2 << PORT_FUNC_SHIFT)
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# define PORT_PULL_DOWN (2 << PORT_PULL_SHIFT)
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/* Peripheral Function
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/* Peripheral Function
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*
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*
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@@ -660,15 +660,21 @@ static int sam_usart5_interrupt(int irq, void *context)
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static int sam_setup(struct uart_dev_s *dev)
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static int sam_setup(struct uart_dev_s *dev)
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{
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{
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int ret = 0;
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#ifndef CONFIG_SUPPRESS_UART_CONFIG
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#ifndef CONFIG_SUPPRESS_UART_CONFIG
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struct sam_dev_s *priv = (struct sam_dev_s*)dev->priv;
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struct sam_dev_s *priv = (struct sam_dev_s*)dev->priv;
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/* Configure the SERCOM as a USART */
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/* Configure the SERCOM as a USART. Don't reconfigure the console UART;
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* that was already done in sam_lowputc.c.
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*/
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return sam_usart_initialize(priv->config);
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if (!dev->isconsole)
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#else
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{
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return OK;
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ret = sam_usart_initialize(priv->config);
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}
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#endif
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#endif
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return ret;
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}
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}
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/****************************************************************************
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/****************************************************************************
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@@ -676,7 +682,7 @@ static int sam_setup(struct uart_dev_s *dev)
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*
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*
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* Description:
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* Description:
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* Disable the USART. This method is called when the serial port is
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* Disable the USART. This method is called when the serial port is
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* closed
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* closed. The exception is the serial console which is never shutdown.
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*
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*
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****************************************************************************/
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****************************************************************************/
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@@ -685,11 +691,15 @@ static void sam_shutdown(struct uart_dev_s *dev)
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struct sam_dev_s *priv = (struct sam_dev_s*)dev->priv;
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struct sam_dev_s *priv = (struct sam_dev_s*)dev->priv;
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/* Resetting the SERCOM restores all registers to the reget state and
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/* Resetting the SERCOM restores all registers to the reget state and
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* disables the SERCOM.
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* disables the SERCOM. Ignore any requests to shutown the console
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* device (shouldn't happen).
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*/
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*/
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if (!dev->isconsole)
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{
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sam_usart_reset(priv->config);
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sam_usart_reset(priv->config);
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}
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}
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}
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/****************************************************************************
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/****************************************************************************
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* Name: sam_attach
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* Name: sam_attach
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@@ -743,7 +753,13 @@ static void sam_detach(struct uart_dev_s *dev)
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struct sam_dev_s *priv = (struct sam_dev_s*)dev->priv;
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struct sam_dev_s *priv = (struct sam_dev_s*)dev->priv;
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const struct sam_usart_config_s * const config = priv->config;
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const struct sam_usart_config_s * const config = priv->config;
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/* Disable interrupts at the SERCOM device and at the NVIC */
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sam_disableallints(priv);
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up_disable_irq(config->irq);
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up_disable_irq(config->irq);
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/* Detach the interrupt handler */
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irq_detach(config->irq);
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irq_detach(config->irq);
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}
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}
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@@ -933,6 +949,10 @@ static bool sam_txempty(struct uart_dev_s *dev)
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* serial console will be available during bootup. This must be called
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* serial console will be available during bootup. This must be called
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* before sam_serialinit.
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* before sam_serialinit.
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*
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*
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* NOTE: On this platform up_earlyserialinit() does not really do
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* anything of consequence and probably could be eliminated with little
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* effort.
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*
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****************************************************************************/
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****************************************************************************/
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void up_earlyserialinit(void)
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void up_earlyserialinit(void)
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@@ -956,11 +976,10 @@ void up_earlyserialinit(void)
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sam_disableallints(TTYS5_DEV.priv);
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sam_disableallints(TTYS5_DEV.priv);
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#endif
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#endif
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/* Configuration whichever one is the console */
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/* Mark the serial console (if any) */
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#ifdef HAVE_SERIAL_CONSOLE
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#ifdef HAVE_SERIAL_CONSOLE
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CONSOLE_DEV.isconsole = true;
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CONSOLE_DEV.isconsole = true;
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sam_setup(&CONSOLE_DEV);
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#endif
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#endif
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}
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}
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@@ -406,7 +406,7 @@ Serial Consoles
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SERCOM4 is available on connectors EXT1 and EXT3
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SERCOM4 is available on connectors EXT1 and EXT3
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PIN EXT1 EXT3 GPIO Function
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PIN EXT1 EXT3 GPIO Function
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---- ---- ------ -----------
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---- ---- ---- ------------------
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13 PB09 PB13 SERCOM4 / USART RX
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13 PB09 PB13 SERCOM4 / USART RX
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14 PB08 PB12 SERCOM4 / USART TX
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14 PB08 PB12 SERCOM4 / USART TX
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19 19 GND
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19 19 GND
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@@ -59,6 +59,7 @@
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* OSC8M Output = 8MHz
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* OSC8M Output = 8MHz
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* `- GCLK1 Input = 8MHz Prescaler = 1 output = 8MHz
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* `- GCLK1 Input = 8MHz Prescaler = 1 output = 8MHz
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* `- DFLL Input = 8MHz Multiplier = 6 output = 48MHz
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* `- DFLL Input = 8MHz Multiplier = 6 output = 48MHz
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* `- GCLK0 Input = 48MHz Prescaler = 1 output = 48MHz
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* `- PM Input = 48Mhz CPU divider = 1 CPU frequency = 48MHz
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* `- PM Input = 48Mhz CPU divider = 1 CPU frequency = 48MHz
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* APBA divider = 1 APBA frequency = 48MHz
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* APBA divider = 1 APBA frequency = 48MHz
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* APBB divider = 1 APBB frequency = 48MHz
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* APBB divider = 1 APBB frequency = 48MHz
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