xtensa/esp32: Added Timer Support

arch/xtensa/include/esp32/irq.h

@@ -181,8 +181,9 @@
  *   0x03c0     Double exception
  *
  * REVISIT: In more architectures supported by NuttX, exception errors
- * tie into the normal interrupt handling via special IRQ numbers.  I
+ * tie into the normal interrupt handling via special IRQ numbers.
- * is still to be determined what will be done for the ESP32.
+ * It is still to be determined what will be done for the ESP32.
+ *
  */
 
 /* IRQ numbers for internal interrupts that are dispatched like peripheral

arch/xtensa/src/esp32/Kconfig

@@ -31,6 +31,10 @@ config ESP32_UART
 	bool
 	default n
 
+config ESP32_TIMER
+	bool
+	default n
+
 config ESP32_BT
 	bool "Bluetooth"
 	default n
@@ -160,32 +164,32 @@ config XTENSA_TIMER2
 	default n
 
 config ESP32_TIMER0
-	bool "64-bit Timer 0"
+	bool "64-bit Timer 0 (Group 0 Timer 0)"
 	default n
-	depends on EXPERIMENTAL
+	select ESP32_TIMER
 	---help---
-		No yet implemented
+		Enables Timer
 
 config ESP32_TIMER1
-	bool "64-bit Timer 1"
+	bool "64-bit Timer 1 (Group 0 Timer 1)"
 	default n
-	depends on EXPERIMENTAL
+	select ESP32_TIMER
 	---help---
-		No yet implemented
+		Enables Timer
 
 config ESP32_TIMER2
-	bool "64-bit Timer 2"
+	bool "64-bit Timer 2 (Group 1 Timer 0)"
 	default n
-	depends on EXPERIMENTAL
+	select ESP32_TIMER
 	---help---
-		No yet implemented
+		Enables Timer
 
 config ESP32_TIMER3
-	bool "64-bit Timer 3"
+	bool "64-bit Timer 3 (Group 1 Timer 1)"
 	default n
-	depends on EXPERIMENTAL
+	select ESP32_TIMER
 	---help---
-		No yet implemented
+		Enables Timer
 
 config ESP32_MWDT0
 	bool "Timer 0 Watchdog"

arch/xtensa/src/esp32/Make.defs

@@ -138,6 +138,13 @@ ifeq ($(CONFIG_ESP32_RNG),y)
 CMN_CSRCS += esp32_rng.c
 endif
 
+ifeq ($(CONFIG_ESP32_TIMER),y)
+CHIP_CSRCS += esp32_tim.c
+ifeq ($(CONFIG_TIMER),y)
+CHIP_CSRCS += esp32_tim_lowerhalf.c
+endif
+endif
+
 ifeq ($(CONFIG_ARCH_USE_MODULE_TEXT),y)
 CHIP_CSRCS += esp32_modtext.c
 CMN_ASRCS += xtensa_loadstore.S

arch/xtensa/src/esp32/esp32_cpuint.c

@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/xtensa/src/esp32/esp32_irq.c
+ * arch/xtensa/src/esp32/esp32_cpuint.c
  *
  *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
@@ -242,7 +242,7 @@ static int esp32_alloc_cpuint(uint32_t intmask)
   int cpuint;
   int ret = -ENOMEM;
 
-  /* Check if there are is CPU interrupts with the requested properties
+  /* Check if there are CPU interrupts with the requested properties
    * available.
    */
 
@@ -416,7 +416,7 @@ void up_disable_irq(int cpuint)
  * Name: up_enable_irq
  *
  * Description:
- *   Ensable the CPU interrupt specified by 'cpuint'
+ *   Enable the CPU interrupt specified by 'cpuint'
  *
  ****************************************************************************/
 
@@ -504,7 +504,7 @@ int esp32_alloc_edgeint(int priority)
  * Name:  esp32_free_cpuint
  *
  * Description:
- *   Free a previoulsy allocated CPU interrupt
+ *   Free a previously allocated CPU interrupt
  *
  * Input Parameters:
  *   The CPU interrupt number to be freed
@@ -551,7 +551,7 @@ void esp32_free_cpuint(int cpuint)
  *
  * Input Parameters:
  *   cpu      - The CPU to receive the interrupt 0=PRO CPU 1=APP CPU
- *   periphid - The peripheral number from ira.h to be assigned to
+ *   periphid - The peripheral number from irq.h to be assigned to
  *              a CPU interrupt.
  *   cpuint   - The CPU interrupt to receive the peripheral interrupt
  *              assignment.

arch/xtensa/src/esp32/esp32_cpuint.h

@@ -144,7 +144,7 @@ void esp32_free_cpuint(int cpuint);
  *
  * Input Parameters:
  *   cpu      - The CPU to receive the interrupt 0=PRO CPU 1=APP CPU
- *   periphid - The peripheral number from ira.h to be assigned to
+ *   periphid - The peripheral number from irq.h to be assigned to
  *              a CPU interrupt.
  *   cpuint   - The CPU interrupt to receive the peripheral interrupt
  *              assignment.

arch/xtensa/src/esp32/esp32_tim.h

@@ -0,0 +1,127 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32/esp32_tim.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_SRC_ESP32_ESP32_TIM_H
+#define __ARCH_XTENSA_SRC_ESP32_ESP32_TIM_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+
+#include <nuttx/irq.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Helpers ******************************************************************/
+
+#define ESP32_TIM_START(d)                         ((d)->ops->start(d))
+#define ESP32_TIM_STOP(d)                          ((d)->ops->stop(d))
+#define ESP32_TIM_CLEAR(d)                         ((d)->ops->clear(d))
+#define ESP32_TIM_CONFIGURE(d, p, m, c, av, a, ar) ((d)->ops->configure(d, m, c, av, a, ar))
+#define ESP32_TIM_SETMODE(d, m)                    ((d)->ops->setmode(d, m))
+#define ESP32_TIM_SETPRE(d, p)                     ((d)->ops->setpre(d, p))
+#define ESP32_TIM_GETCONFIG(d, v)                  ((d)->ops->getconfig(d, v))
+#define ESP32_TIM_GETCTR(d, v)                     ((d)->ops->getcounter(d, v))
+#define ESP32_TIM_SETCTR(d, v)                     ((d)->ops->setcounter(d, v))
+#define ESP32_TIM_GETALRVL(d, v)                   ((d)->ops->getalarmvalue(d, v))
+#define ESP32_TIM_SETALRVL(d, v)                   ((d)->ops->setalarmvalue(d, v))
+#define ESP32_TIM_SETALRM(d, e)                    ((d)->ops->setalarm(d, e))
+#define ESP32_TIM_SETARLD(d, e)                    ((d)->ops->setautoreload(d, e))
+#define ESP32_TIM_SETISR(d, hnd, arg)              ((d)->ops->setisr(d, hnd, arg))
+#define ESP32_TIM_ENABLEINT(d)                     ((d)->ops->enableint(d))
+#define ESP32_TIM_DISABLEINT(d)                    ((d)->ops->disableint(d))
+#define ESP32_TIM_CHECKINT(d)                      ((d)->ops->checkint(d))
+#define ESP32_TIM_ACKINT(d)                        ((d)->ops->ackint(d))
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/* Timer mode */
+
+enum esp32_tim_mode_e
+{
+  ESP32_TIM_MODE_DOWN,
+  ESP32_TIM_MODE_UP,
+};
+
+/* ESP32 TIM device */
+
+struct esp32_tim_dev_s
+{
+  struct esp32_tim_ops_s *ops;
+};
+
+/* ESP32 TIM ops */
+
+/* This is a struct containing the pointers to the timer operations */
+
+struct esp32_tim_ops_s
+{
+  /* Timer tasks */
+
+  CODE int (*start)(FAR struct esp32_tim_dev_s *dev);
+  CODE int (*stop)(FAR struct esp32_tim_dev_s *dev);
+  CODE int (*clear)(FAR struct esp32_tim_dev_s *dev);
+
+  /* Timer configuration */
+
+  CODE int (*configure)(FAR struct esp32_tim_dev_s *dev, uint16_t pre,
+                        uint8_t mode, uint64_t counter_value,
+                        uint64_t alarm_value, bool alarm,
+                        bool autoreload);
+
+  /* Timer operations */
+
+  CODE int (*setmode)(FAR struct esp32_tim_dev_s *dev, uint8_t mode);
+  CODE int (*setpre)(FAR struct esp32_tim_dev_s *dev, uint16_t pre);
+  CODE int (*getconfig)(FAR struct esp32_tim_dev_s *dev, uint32_t *value);
+  CODE int (*getcounter)(FAR struct esp32_tim_dev_s *dev, uint64_t *value);
+  CODE int (*setcounter)(FAR struct esp32_tim_dev_s *dev, uint64_t value);
+  CODE int (*getalarmvalue)(FAR struct esp32_tim_dev_s *dev,
+                            uint64_t *value);
+  CODE int (*setalarmvalue)(FAR struct esp32_tim_dev_s *dev, uint64_t value);
+  CODE int (*setalarm)(FAR struct esp32_tim_dev_s *dev, bool enable);
+  CODE int (*setautoreload)(FAR struct esp32_tim_dev_s *dev, bool enable);
+
+  /* Timer interrupts */
+
+  CODE int (*setisr)(FAR struct esp32_tim_dev_s *dev, xcpt_t handler,
+                     FAR void * arg);
+  CODE int (*enableint)(FAR struct esp32_tim_dev_s *dev);
+  CODE int (*disableint)(FAR struct esp32_tim_dev_s *dev);
+  CODE int (*checkint)(FAR struct esp32_tim_dev_s *dev);
+  CODE int (*ackint)(FAR struct esp32_tim_dev_s *dev);
+};
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+FAR struct esp32_tim_dev_s *esp32_tim_init(int timer);
+int esp32_tim_deinit(FAR struct esp32_tim_dev_s *dev);
+
+#endif /* __ARCH_XTENSA_SRC_ESP32_ESP32_TIM_H */

arch/xtensa/src/esp32/esp32_tim_lowerhalf.h

@@ -0,0 +1,42 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32/esp32_tim_lowerhalf.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_SRC_ESP32_ESP32_TIM_LOWERHALF_H
+#define __ARCH_XTENSA_SRC_ESP32_ESP32_TIM_LOWERHALF_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <esp32_tim.h>
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32_timer_initialize
+ ****************************************************************************/
+
+int esp32_timer_initialize(FAR const char *devpath, uint8_t timer);
+
+#endif /* __ARCH_XTENSA_SRC_ESP32_ESP32_TIM_LOWERHALF_H */

arch/xtensa/src/esp32/hardware/esp32_soc.h

@@ -198,6 +198,7 @@
 #define TIMER_CLK_FREQ                          (80000000 >> 4) /* 80MHz divided by 16 */
 #define SPI_CLK_DIV                             4
 #define TICKS_PER_US_ROM                        26              /* CPU is 80MHz */
+#define TB_CLK_FREQ                             APB_CLK_FREQ
 
 #define DR_REG_DPORT_BASE                       0x3ff00000
 #define DR_REG_UART_BASE                        0x3ff40000

boards/xtensa/esp32/esp32-core/configs/timer/defconfig

@@ -0,0 +1,54 @@
+#
+# This file is autogenerated: PLEASE DO NOT EDIT IT.
+#
+# You can use "make menuconfig" to make any modifications to the installed .config file.
+# You can then do "make savedefconfig" to generate a new defconfig file that includes your
+# modifications.
+#
+# CONFIG_NSH_ARGCAT is not set
+# CONFIG_NSH_CMDOPT_HEXDUMP is not set
+# CONFIG_NSH_CMDPARMS is not set
+CONFIG_ARCH="xtensa"
+CONFIG_ARCH_BOARD="esp32-core"
+CONFIG_ARCH_BOARD_ESP32CORE=y
+CONFIG_ARCH_CHIP="esp32"
+CONFIG_ARCH_CHIP_ESP32=y
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_ARCH_XTENSA=y
+CONFIG_BOARD_LOOPSPERMSEC=16717
+CONFIG_BUILTIN=y
+CONFIG_ESP32_TIMER0=y
+CONFIG_ESP32_TIMER1=y
+CONFIG_ESP32_TIMER2=y
+CONFIG_ESP32_TIMER3=y
+CONFIG_ESP32_UART0=y
+CONFIG_EXAMPLES_TIMER=y
+CONFIG_FS_PROCFS=y
+CONFIG_HAVE_CXX=y
+CONFIG_HAVE_CXXINITIALIZE=y
+CONFIG_IDLETHREAD_STACKSIZE=3072
+CONFIG_INTELHEX_BINARY=y
+CONFIG_MAX_TASKS=16
+CONFIG_MM_REGIONS=2
+CONFIG_NFILE_DESCRIPTORS=8
+CONFIG_NSH_ARCHINIT=y
+CONFIG_NSH_BUILTIN_APPS=y
+CONFIG_NSH_FILEIOSIZE=512
+CONFIG_NSH_LINELEN=64
+CONFIG_NSH_READLINE=y
+CONFIG_PREALLOC_TIMERS=4
+CONFIG_RAM_SIZE=114688
+CONFIG_RAM_START=0x20000000
+CONFIG_RAW_BINARY=y
+CONFIG_RR_INTERVAL=200
+CONFIG_SCHED_WAITPID=y
+CONFIG_SDCLONE_DISABLE=y
+CONFIG_SPI=y
+CONFIG_START_DAY=6
+CONFIG_START_MONTH=12
+CONFIG_START_YEAR=2011
+CONFIG_SYSTEM_NSH=y
+CONFIG_TIMER=y
+CONFIG_TIMER_ARCH=y
+CONFIG_UART0_SERIAL_CONSOLE=y
+CONFIG_USER_ENTRYPOINT="nsh_main"

boards/xtensa/esp32/esp32-core/src/Makefile

@@ -60,6 +60,12 @@ ifeq ($(CONFIG_ESP32_SPIFLASH),y)
 CSRCS += esp32_spiflash.c
 endif
 
+ifeq ($(CONFIG_TIMER),y)
+ifeq ($(CONFIG_ESP32_TIMER),y)
+CSRCS += esp32_timer.c
+endif
+endif
+
 SCRIPTIN = $(SCRIPTDIR)$(DELIM)esp32.template.ld
 SCRIPTOUT = $(SCRIPTDIR)$(DELIM)esp32_out.ld
 

boards/xtensa/esp32/esp32-core/src/esp32-core.h

@@ -95,6 +95,17 @@ int esp32_mmcsd_initialize(int minor);
  ****************************************************************************/
 
 int esp32_spiflash_init(void);
+/****************************************************************************
+ * Name: esp32_timer_driver_setup
+ *
+ * Description:
+ *   Initialize TIMER driver.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_TIMER
+int esp32_timer_driver_setup(FAR const char *devpath, int timer);
+#endif
 
 #endif /* __ASSEMBLY__ */
 #endif /* __BOARDS_XTENSA_ESP32_ESP32_CORE_SRC_ESP32_CORE_H */

boards/xtensa/esp32/esp32-core/src/esp32_bringup.c

@@ -42,6 +42,11 @@
 #include <sys/types.h>
 #include <sys/mount.h>
 #include <syslog.h>
+#include <debug.h>
+
+#ifdef CONFIG_TIMER
+#  include <nuttx/timers/timer.h>
+#endif
 
 #include "esp32-core.h"
 
@@ -49,6 +54,22 @@
  * Pre-processor Definitions
  ****************************************************************************/
 
+#ifdef CONFIG_ESP32_TIMER0
+#define ESP32_TIMER0 (0)
+#endif
+
+#ifdef CONFIG_ESP32_TIMER1
+#define ESP32_TIMER1 (1)
+#endif
+
+#ifdef CONFIG_ESP32_TIMER2
+#define ESP32_TIMER2 (2)
+#endif
+
+#ifdef CONFIG_ESP32_TIMER3
+#define ESP32_TIMER3 (3)
+#endif
+
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -94,6 +115,49 @@ int esp32_bringup(void)
   ret = esp32_spiflash_init();
 #endif
 
+#ifdef CONFIG_TIMER
+  /* Configure TIMER driver */
+#ifdef CONFIG_ESP32_TIMER0
+  ret = esp32_timer_driver_setup("/dev/timer0", ESP32_TIMER0);
+  if (ret < 0)
+    {
+      syslog(LOG_ERR,
+             "ERROR: Failed to initialize timer driver: %d\n",
+             ret);
+    }
+#endif
+
+#ifdef CONFIG_ESP32_TIMER1
+  ret = esp32_timer_driver_setup("/dev/timer1", ESP32_TIMER1);
+  if (ret < 0)
+    {
+      syslog(LOG_ERR,
+             "ERROR: Failed to initialize timer driver: %d\n",
+             ret);
+    }
+#endif
+
+#ifdef CONFIG_ESP32_TIMER2
+  ret = esp32_timer_driver_setup("/dev/timer2", ESP32_TIMER2);
+  if (ret < 0)
+    {
+      syslog(LOG_ERR,
+             "ERROR: Failed to initialize timer driver: %d\n",
+             ret);
+    }
+#endif
+
+#ifdef CONFIG_ESP32_TIMER3
+  ret = esp32_timer_driver_setup("/dev/timer3", ESP32_TIMER3);
+  if (ret < 0)
+    {
+      syslog(LOG_ERR,
+             "ERROR: Failed to initialize timer driver: %d\n",
+             ret);
+    }
+#endif
+#endif
+
   /* If we got here then perhaps not all initialization was successful, but
    * at least enough succeeded to bring-up NSH with perhaps reduced
    * capabilities.

boards/xtensa/esp32/esp32-core/src/esp32_timer.c

@@ -0,0 +1,58 @@
+/****************************************************************************
+ * boards/xtensa/esp32/esp32-core/src/esp32_timer.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/timers/timer.h>
+
+#include <debug.h>
+
+#include "esp32_tim_lowerhalf.h"
+
+#include "esp32-core.h"
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32_timer_driver_setup
+ *
+ * Description:
+ *   Configure the timer driver.
+ *
+ * Input Parameters:
+ *   devpath - The full path to the timer device.  This should be of the
+ *             form /dev/timerX
+ *   timer   - The timer's number.
+ *
+ * Returned Value:
+ *   Zero (OK) is returned on success; A negated errno value is returned
+ *   to indicate the nature of any failure.
+ *
+ ****************************************************************************/
+
+int esp32_timer_driver_setup(FAR const char *devpath, int timer)
+{
+  return esp32_timer_initialize(devpath, timer);
+}

include/nuttx/timers/timer.h

@@ -235,7 +235,7 @@ extern "C"
  *   initialization.
  *
  * Input Parameters:
- *   dev path - The full path to the driver to be registers in the NuttX
+ *   dev path - The full path to the driver to be registered in the NuttX
  *     pseudo-filesystem.  The recommended convention is to name all timer
  *     drivers as "/dev/timer0", "/dev/timer1", etc.  where the driver
  *     path differs only in the "minor" number at the end of the device name.