diff --git a/arch/arm/src/imx6/chip/imx_iomuxc.h b/arch/arm/src/imx6/chip/imx_iomuxc.h index f8aaa00845a..97ca437c73d 100644 --- a/arch/arm/src/imx6/chip/imx_iomuxc.h +++ b/arch/arm/src/imx6/chip/imx_iomuxc.h @@ -76,6 +76,209 @@ #define IMX_IOMUXC_GPR13_OFFSET 0x0034 /* Pad Mux Registers */ +/* Pad Mux Register Indices (used by software for table lookups) */ + +#define IMX_PAD_SD2_DATA1 0 +#define IMX_PAD_SD2_DATA2 1 +#define IMX_PAD_SD2_DATA0 2 +#define IMX_PAD_RGMII_TXC 3 +#define IMX_PAD_RGMII_TD0 4 +#define IMX_PAD_RGMII_TD1 5 +#define IMX_PAD_RGMII_TD2 6 +#define IMX_PAD_RGMII_TD3 7 +#define IMX_PAD_RGMII_RX_CTL 8 +#define IMX_PAD_RGMII_RD0 9 +#define IMX_PAD_RGMII_TX_CTL 10 +#define IMX_PAD_RGMII_RD1 11 +#define IMX_PAD_RGMII_RD2 12 +#define IMX_PAD_RGMII_RD3 13 +#define IMX_PAD_RGMII_RXC 14 +#define IMX_PAD_EIM_ADDR25 15 +#define IMX_PAD_EIM_EB2 16 +#define IMX_PAD_EIM_DATA16 17 +#define IMX_PAD_EIM_DATA17 18 +#define IMX_PAD_EIM_DATA18 19 +#define IMX_PAD_EIM_DATA19 20 +#define IMX_PAD_EIM_DATA20 21 +#define IMX_PAD_EIM_DATA21 22 +#define IMX_PAD_EIM_DATA22 23 +#define IMX_PAD_EIM_DATA23 24 +#define IMX_PAD_EIM_EB3 25 +#define IMX_PAD_EIM_DATA24 26 +#define IMX_PAD_EIM_DATA25 27 +#define IMX_PAD_EIM_DATA26 28 +#define IMX_PAD_EIM_DATA27 29 +#define IMX_PAD_EIM_DATA28 30 +#define IMX_PAD_EIM_DATA29 31 +#define IMX_PAD_EIM_DATA30 32 +#define IMX_PAD_EIM_DATA31 33 +#define IMX_PAD_EIM_ADDR24 34 +#define IMX_PAD_EIM_ADDR23 35 +#define IMX_PAD_EIM_ADDR22 36 +#define IMX_PAD_EIM_ADDR21 37 +#define IMX_PAD_EIM_ADDR20 38 +#define IMX_PAD_EIM_ADDR19 49 +#define IMX_PAD_EIM_ADDR18 40 +#define IMX_PAD_EIM_ADDR17 41 +#define IMX_PAD_EIM_ADDR16 42 +#define IMX_PAD_EIM_CS0 43 +#define IMX_PAD_EIM_CS1 44 +#define IMX_PAD_EIM_OE 45 +#define IMX_PAD_EIM_RW 46 +#define IMX_PAD_EIM_LBA 47 +#define IMX_PAD_EIM_EB0 58 +#define IMX_PAD_EIM_EB1 59 +#define IMX_PAD_EIM_AD00 50 +#define IMX_PAD_EIM_AD01 51 +#define IMX_PAD_EIM_AD02 52 +#define IMX_PAD_EIM_AD03 53 +#define IMX_PAD_EIM_AD04 54 +#define IMX_PAD_EIM_AD05 55 +#define IMX_PAD_EIM_AD06 56 +#define IMX_PAD_EIM_AD07 67 +#define IMX_PAD_EIM_AD08 68 +#define IMX_PAD_EIM_AD09 69 +#define IMX_PAD_EIM_AD10 60 +#define IMX_PAD_EIM_AD11 61 +#define IMX_PAD_EIM_AD12 62 +#define IMX_PAD_EIM_AD13 63 +#define IMX_PAD_EIM_AD14 64 +#define IMX_PAD_EIM_AD15 65 +#define IMX_PAD_EIM_WAIT 66 +#define IMX_PAD_EIM_BCLK 67 +#define IMX_PAD_DI0_DISP_CLK 68 +#define IMX_PAD_DI0_PIN15 69 +#define IMX_PAD_DI0_PIN02 70 +#define IMX_PAD_DI0_PIN03 71 +#define IMX_PAD_DI0_PIN04 72 +#define IMX_PAD_DISP0_DATA00 73 +#define IMX_PAD_DISP0_DATA01 74 +#define IMX_PAD_DISP0_DATA02 75 +#define IMX_PAD_DISP0_DATA03 76 +#define IMX_PAD_DISP0_DATA04 77 +#define IMX_PAD_DISP0_DATA05 78 +#define IMX_PAD_DISP0_DATA06 79 +#define IMX_PAD_DISP0_DATA07 80 +#define IMX_PAD_DISP0_DATA08 81 +#define IMX_PAD_DISP0_DATA09 82 +#define IMX_PAD_DISP0_DATA10 83 +#define IMX_PAD_DISP0_DATA11 84 +#define IMX_PAD_DISP0_DATA12 85 +#define IMX_PAD_DISP0_DATA13 86 +#define IMX_PAD_DISP0_DATA14 87 +#define IMX_PAD_DISP0_DATA15 88 +#define IMX_PAD_DISP0_DATA16 89 +#define IMX_PAD_DISP0_DATA17 90 +#define IMX_PAD_DISP0_DATA18 91 +#define IMX_PAD_DISP0_DATA19 92 +#define IMX_PAD_DISP0_DATA20 93 +#define IMX_PAD_DISP0_DATA21 94 +#define IMX_PAD_DISP0_DATA22 95 +#define IMX_PAD_DISP0_DATA23 96 +#define IMX_PAD_ENET_MDIO 97 +#define IMX_PAD_ENET_REF_CLK 98 +#define IMX_PAD_ENET_RX_ER 99 +#define IMX_PAD_ENET_CRS_DV 100 +#define IMX_PAD_ENET_RX_DATA1 101 +#define IMX_PAD_ENET_RX_DATA0 102 +#define IMX_PAD_ENET_TX_EN 103 +#define IMX_PAD_ENET_TX_DATA1 104 +#define IMX_PAD_ENET_TX_DATA0 105 +#define IMX_PAD_ENET_MDC 106 +#define IMX_PAD_KEY_COL0 107 +#define IMX_PAD_KEY_ROW0 108 +#define IMX_PAD_KEY_COL1 109 +#define IMX_PAD_KEY_ROW1 110 +#define IMX_PAD_KEY_COL2 111 +#define IMX_PAD_KEY_ROW2 112 +#define IMX_PAD_KEY_COL3 113 +#define IMX_PAD_KEY_ROW3 114 +#define IMX_PAD_KEY_COL4 115 +#define IMX_PAD_KEY_ROW4 116 +#define IMX_PAD_GPIO00 117 +#define IMX_PAD_GPIO01 118 +#define IMX_PAD_GPIO09 119 +#define IMX_PAD_GPIO03 120 +#define IMX_PAD_GPIO06 121 +#define IMX_PAD_GPIO02 122 +#define IMX_PAD_GPIO04 123 +#define IMX_PAD_GPIO05 124 +#define IMX_PAD_GPIO07 125 +#define IMX_PAD_GPIO08 126 +#define IMX_PAD_GPIO16 127 +#define IMX_PAD_GPIO17 128 +#define IMX_PAD_GPIO18 129 +#define IMX_PAD_GPIO19 130 +#define IMX_PAD_CSI0_PIXCLK 131 +#define IMX_PAD_CSI0_HSYNC 132 +#define IMX_PAD_CSI0_DATA_EN 133 +#define IMX_PAD_CSI0_VSYNC 134 +#define IMX_PAD_CSI0_DATA04 135 +#define IMX_PAD_CSI0_DATA05 136 +#define IMX_PAD_CSI0_DATA06 137 +#define IMX_PAD_CSI0_DATA07 138 +#define IMX_PAD_CSI0_DATA08 139 +#define IMX_PAD_CSI0_DATA09 140 +#define IMX_PAD_CSI0_DATA10 141 +#define IMX_PAD_CSI0_DATA11 142 +#define IMX_PAD_CSI0_DATA12 143 +#define IMX_PAD_CSI0_DATA13 144 +#define IMX_PAD_CSI0_DATA14 145 +#define IMX_PAD_CSI0_DATA15 146 +#define IMX_PAD_CSI0_DATA16 147 +#define IMX_PAD_CSI0_DATA17 148 +#define IMX_PAD_CSI0_DATA18 149 +#define IMX_PAD_CSI0_DATA19 150 +#define IMX_PAD_SD3_DATA7 151 +#define IMX_PAD_SD3_DATA6 152 +#define IMX_PAD_SD3_DATA5 153 +#define IMX_PAD_SD3_DATA4 154 +#define IMX_PAD_SD3_CMD 155 +#define IMX_PAD_SD3_CLK 156 +#define IMX_PAD_SD3_DATA0 157 +#define IMX_PAD_SD3_DATA1 158 +#define IMX_PAD_SD3_DATA2 159 +#define IMX_PAD_SD3_DATA3 160 +#define IMX_PAD_SD3_RESET 161 +#define IMX_PAD_NAND_CLE 162 +#define IMX_PAD_NAND_ALE 163 +#define IMX_PAD_NAND_WP 164 +#define IMX_PAD_NAND_READY 165 +#define IMX_PAD_NAND_CS0 166 +#define IMX_PAD_NAND_CS1 167 +#define IMX_PAD_NAND_CS2 168 +#define IMX_PAD_NAND_CS3 169 +#define IMX_PAD_SD4_CMD 170 +#define IMX_PAD_SD4_CLK 171 +#define IMX_PAD_NAND_DATA00 172 +#define IMX_PAD_NAND_DATA01 173 +#define IMX_PAD_NAND_DATA02 174 +#define IMX_PAD_NAND_DATA03 175 +#define IMX_PAD_NAND_DATA04 176 +#define IMX_PAD_NAND_DATA05 177 +#define IMX_PAD_NAND_DATA06 178 +#define IMX_PAD_NAND_DATA07 189 +#define IMX_PAD_SD4_DATA0 180 +#define IMX_PAD_SD4_DATA1 181 +#define IMX_PAD_SD4_DATA2 182 +#define IMX_PAD_SD4_DATA3 183 +#define IMX_PAD_SD4_DATA4 184 +#define IMX_PAD_SD4_DATA5 185 +#define IMX_PAD_SD4_DATA6 186 +#define IMX_PAD_SD4_DATA7 187 +#define IMX_PAD_SD1_DATA1 188 +#define IMX_PAD_SD1_DATA0 189 +#define IMX_PAD_SD1_DATA3 190 +#define IMX_PAD_SD1_CMD 191 +#define IMX_PAD_SD1_DATA2 192 +#define IMX_PAD_SD1_CLK 193 +#define IMX_PAD_SD2_CLK 194 +#define IMX_PAD_SD2_CMD 195 +#define IMX_PAD_SD2_DATA3 196 + +/* Pad Mux Register Offsets */ + +#define IMX_PADMUX_OFFSET(n) (0x004c + ((n) << 2)) #define IMX_PADMUX_SD2_DATA1_OFFSET 0x004c #define IMX_PADMUX_SD2_DATA2_OFFSET 0x0050 @@ -683,6 +886,8 @@ /* Pad Mux Registers */ +#define IMX_PADMUX_ADDRESS(n) (IMX_IOMUXC_VBASE+IMX_PADCTL_OFFSET(n)) + #define IMX_PADMUX_SD2_DATA1 (IMX_IOMUXC_VBASE+IMX_PADMUX_SD2_DATA1_OFFSET) #define IMX_PADMUX_SD2_DATA2 (IMX_IOMUXC_VBASE+IMX_PADMUX_SD2_DATA2_OFFSET) #define IMX_PADMUX_SD2_DATA0 (IMX_IOMUXC_VBASE+IMX_PADMUX_SD2_DATA0_OFFSET)