diff --git a/arch/arm/src/imxrt/Make.defs b/arch/arm/src/imxrt/Make.defs index 9b5b7932eae..2eea410a04c 100644 --- a/arch/arm/src/imxrt/Make.defs +++ b/arch/arm/src/imxrt/Make.defs @@ -96,8 +96,8 @@ endif CHIP_ASRCS = CHIP_CSRCS = imxrt_allocateheap.c imxrt_start.c imxrt_clockconfig.c -CHIP_CSRCS += imxrt_irq.c imxrt_clrpend.c imxrt_gpio.c imxrt_wdog.c -CHIP_CSRCS += imxrt_iomuxc.c imxrt_serial.c imxrt_lowputc.c +CHIP_CSRCS += imxrt_periphclks.c imxrt_irq.c imxrt_clrpend.c imxrt_gpio.c +CHIP_CSRCS += imxrt_wdog.c imxrt_iomuxc.c imxrt_serial.c imxrt_lowputc.c # Configuration-dependent i.MX RT files diff --git a/arch/arm/src/imxrt/chip/imxrt_ccm.h b/arch/arm/src/imxrt/chip/imxrt_ccm.h index 6337b1c5286..806bc2a8f86 100644 --- a/arch/arm/src/imxrt/chip/imxrt_ccm.h +++ b/arch/arm/src/imxrt/chip/imxrt_ccm.h @@ -184,7 +184,7 @@ /* Bits 6-31: Reserved */ /* Clock Switcher Register */ -#define CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0) /* Bit 0: Selects source to generate pll3_sw_clk */ +#define CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0) /* Bit 0: Selects source to generate pll3_sw_clk */ /* Arm Clock Root Register */ @@ -581,6 +581,10 @@ #define CCM_CG_RUN (1) /* Clock is on in run mode, but off in WAIT and STOP modes */ #define CCM_CG_ALL (3) /* Clock is on during all modes, except STOP mode. */ +#define CCM_CCGRX_CG_SHIFT(r) ((r) << 1) +#define CCM_CCGRX_CG_MASK(r) (0x3 << CCM_CCGRX_CG_SHIFT(r)) +# define CCM_CCGRX_CG(r,v) ((uint32_t)(v) << CCM_CCGRX_CG_SHIFT(r)) + #define CCM_CCGRX_CG0_SHIFT (0) #define CCM_CCGRX_CG0_MASK (0x3 << CCM_CCGRX_CG0_SHIFT) # define CCM_CCGRX_CG0(n) ((uint32_t)(n) << CCM_CCGRX_CG0_SHIFT) @@ -630,7 +634,122 @@ #define CCM_CCGRX_CG15_MASK (0x3 << CCM_CCGRX_CG15_SHIFT) # define CCM_CCGRX_CG15(n) ((uint32_t)(n) << CCM_CCGRX_CG15_SHIFT) -/* Module Enable Overide Register */ +/* Macros used by imxrt_periphclks.h */ + +#define CCM_CCGR_GPIO2 IMXRT_CCM_CCGR0, 15 +#define CCM_CCGR_LPUART2 IMXRT_CCM_CCGR0, 14 +#define CCM_CCGR_GPT2_SERIAL IMXRT_CCM_CCGR0, 13 +#define CCM_CCGR_GPT2_BUS IMXRT_CCM_CCGR0, 12 +#define CCM_CCGR_TRACE IMXRT_CCM_CCGR0, 11 +#define CCM_CCGR_CAN2_SERIAL IMXRT_CCM_CCGR0, 10 +#define CCM_CCGR_CAN2 IMXRT_CCM_CCGR0, 9 +#define CCM_CCGR_CAN1_SERIAL IMXRT_CCM_CCGR0, 8 +#define CCM_CCGR_CAN1 IMXRT_CCM_CCGR0, 7 +#define CCM_CCGR_LPUART3 IMXRT_CCM_CCGR0, 6 +#define CCM_CCGR_DCP IMXRT_CCM_CCGR0, 5 +#define CCM_CCGR_MQS IMXRT_CCM_CCGR0, 2 +#define CCM_CCGR_AIPS_TZ2 IMXRT_CCM_CCGR0, 1 +#define CCM_CCGR_AIPS_TZ1 IMXRT_CCM_CCGR0, 0 + +#define CCM_CCGR_CSU IMXRT_CCM_CCGR1, 14 +#define CCM_CCGR_GPIO1 IMXRT_CCM_CCGR1, 13 +#define CCM_CCGR_LPUART4 IMXRT_CCM_CCGR1, 12 +#define CCM_CCGR_GPT_SERIAL IMXRT_CCM_CCGR1, 11 +#define CCM_CCGR_GPT_BUS IMXRT_CCM_CCGR1, 10 +#define CCM_CCGR_ADC1 IMXRT_CCM_CCGR1, 8 +#define CCM_CCGR_AOI2 IMXRT_CCM_CCGR1, 7 +#define CCM_CCGR_PIT IMXRT_CCM_CCGR1, 6 +#define CCM_CCGR_ENET IMXRT_CCM_CCGR1, 5 +#define CCM_CCGR_ADC2 IMXRT_CCM_CCGR1, 4 +#define CCM_CCGR_LPSPI4 IMXRT_CCM_CCGR1, 3 +#define CCM_CCGR_LPSPI3 IMXRT_CCM_CCGR1, 2 +#define CCM_CCGR_LPSPI2 IMXRT_CCM_CCGR1, 1 +#define CCM_CCGR_LPSPI1 IMXRT_CCM_CCGR1, 0 + +#define CCM_CCGR_PXP IMXRT_CCM_CCGR2, 15 +#define CCM_CCGR_LCD IMXRT_CCM_CCGR2, 14 +#define CCM_CCGR_GPIO3 IMXRT_CCM_CCGR2, 13 +#define CCM_CCGR_XBAR2 IMXRT_CCM_CCGR2, 12 +#define CCM_CCGR_XBAR1 IMXRT_CCM_CCGR2, 11 +#define CCM_CCGR_IPMUX3 IMXRT_CCM_CCGR2, 10 +#define CCM_CCGR_IPMUX2 IMXRT_CCM_CCGR2, 9 +#define CCM_CCGR_IPMUX1 IMXRT_CCM_CCGR2, 8 +#define CCM_CCGR_XBAR3 IMXRT_CCM_CCGR2, 7 +#define CCM_CCGR_OCOTP_CTRL IMXRT_CCM_CCGR2, 6 +#define CCM_CCGR_LPI2C3 IMXRT_CCM_CCGR2, 5 +#define CCM_CCGR_LPI2C2 IMXRT_CCM_CCGR2, 4 +#define CCM_CCGR_LPI2C1 IMXRT_CCM_CCGR2, 3 +#define CCM_CCGR_IOMUXC_SNVS IMXRT_CCM_CCGR2, 2 +#define CCM_CCGR_CSI IMXRT_CCM_CCGR2, 1 + +#define CCM_CCGR_IOMUXC_SNVS_GPR IMXRT_CCM_CCGR3, 15 +#define CCM_CCGR_OCRAM IMXRT_CCM_CCGR3, 14 +#define CCM_CCGR_ACMP4 IMXRT_CCM_CCGR3, 13 +#define CCM_CCGR_ACMP3 IMXRT_CCM_CCGR3, 12 +#define CCM_CCGR_ACMP2 IMXRT_CCM_CCGR3, 11 +#define CCM_CCGR_ACMP1 IMXRT_CCM_CCGR3, 10 +#define CCM_CCGR_FLEXRAM IMXRT_CCM_CCGR3, 9 +#define CCM_CCGR_WDOG1 IMXRT_CCM_CCGR3, 8 +#define CCM_CCGR_EWM IMXRT_CCM_CCGR3, 7 +#define CCM_CCGR_GPIO4 IMXRT_CCM_CCGR3, 6 +#define CCM_CCGR_LCDIF_PIX IMXRT_CCM_CCGR3, 5 +#define CCM_CCGR_AOI1 IMXRT_CCM_CCGR3, 4 +#define CCM_CCGR_LPUART6 IMXRT_CCM_CCGR3, 3 +#define CCM_CCGR_SEMC IMXRT_CCM_CCGR3, 2 +#define CCM_CCGR_LPUART5 IMXRT_CCM_CCGR3, 1 +#define CCM_CCGR_FLEXIO2 IMXRT_CCM_CCGR3, 0 + +#define CCM_CCGR_ENC4 IMXRT_CCM_CCGR4, 15 +#define CCM_CCGR_ENC3 IMXRT_CCM_CCGR4, 14 +#define CCM_CCGR_ENC2 IMXRT_CCM_CCGR4, 13 +#define CCM_CCGR_ENC1 IMXRT_CCM_CCGR4, 12 +#define CCM_CCGR_PWM4 IMXRT_CCM_CCGR4, 11 +#define CCM_CCGR_PWM3 IMXRT_CCM_CCGR4, 10 +#define CCM_CCGR_PWM2 IMXRT_CCM_CCGR4, 9 +#define CCM_CCGR_PWM1 IMXRT_CCM_CCGR4, 8 +#define CCM_CCGR_SIM_EMS IMXRT_CCM_CCGR4, 7 +#define CCM_CCGR_SIM_M IMXRT_CCM_CCGR4, 6 +#define CCM_CCGR_TSC_DIG IMXRT_CCM_CCGR4, 5 +#define CCM_CCGR_SIM_M7 IMXRT_CCM_CCGR4, 4 +#define CCM_CCGR_BEE IMXRT_CCM_CCGR4, 3 +#define CCM_CCGR_IOMUXC_GPR IMXRT_CCM_CCGR4, 2 +#define CCM_CCGR_IOMUXC IMXRT_CCM_CCGR4, 1 + +#define CCM_CCGR_SNVS_LP IMXRT_CCM_CCGR5, 15 +#define CCM_CCGR_SNVS_HP IMXRT_CCM_CCGR5, 14 +#define CCM_CCGR_LPUART7 IMXRT_CCM_CCGR5, 13 +#define CCM_CCGR_LPUART1 IMXRT_CCM_CCGR5, 12 +#define CCM_CCGR_SAI3 IMXRT_CCM_CCGR5, 11 +#define CCM_CCGR_SAI2 IMXRT_CCM_CCGR5, 10 +#define CCM_CCGR_SAI1 IMXRT_CCM_CCGR5, 9 +#define CCM_CCGR_SIM_MAIN IMXRT_CCM_CCGR5, 8 +#define CCM_CCGR_SPDIF IMXRT_CCM_CCGR5, 7 +#define CCM_CCGR_AIPSTZ4 IMXRT_CCM_CCGR5, 6 +#define CCM_CCGR_WDOG2 IMXRT_CCM_CCGR5, 5 +#define CCM_CCGR_KPP IMXRT_CCM_CCGR5, 4 +#define CCM_CCGR_DMA IMXRT_CCM_CCGR5, 3 +#define CCM_CCGR_WDOG3 IMXRT_CCM_CCGR5, 2 +#define CCM_CCGR_FLEXIO1 IMXRT_CCM_CCGR5, 1 +#define CCM_CCGR_ROM IMXRT_CCM_CCGR5, 0 + +#define CCM_CCGR_TIMER3 IMXRT_CCM_CCGR6, 15 +#define CCM_CCGR_TIMER2 IMXRT_CCM_CCGR6, 14 +#define CCM_CCGR_TIMER1 IMXRT_CCM_CCGR6, 13 +#define CCM_CCGR_LPI2C4_SERIAL IMXRT_CCM_CCGR6, 12 +#define CCM_CCGR_ANADIG IMXRT_CCM_CCGR6, 11 +#define CCM_CCGR_SIM_PER IMXRT_CCM_CCGR6, 10 +#define CCM_CCGR_AIPS_TZ3 IMXRT_CCM_CCGR6, 9 +#define CCM_CCGR_TIMER4 IMXRT_CCM_CCGR6, 8 +#define CCM_CCGR_LPUART8 IMXRT_CCM_CCGR6, 7 +#define CCM_CCGR_TRNG IMXRT_CCM_CCGR6, 6 +#define CCM_CCGR_FLEXSPI IMXRT_CCM_CCGR6, 5 +#define CCM_CCGR_IPMUX4 IMXRT_CCM_CCGR6, 4 +#define CCM_CCGR_DCDC IMXRT_CCM_CCGR6, 3 +#define CCM_CCGR_USDHC2 IMXRT_CCM_CCGR6, 2 +#define CCM_CCGR_USDHC1 IMXRT_CCM_CCGR6, 1 +#define CCM_CCGR_USBOH3 IMXRT_CCM_CCGR6, 0 + +/* Module Enable Override Register */ /* Bits 0-4: Reserved */ #define CCM_CMEOR_MOD_EN_OV_GPT (1 << 5) /* Bit 5: Overide clock enable signal from GPT */ diff --git a/arch/arm/src/imxrt/imxrt_edma.c b/arch/arm/src/imxrt/imxrt_edma.c index 2fdcf07edfe..8db84067eb5 100644 --- a/arch/arm/src/imxrt/imxrt_edma.c +++ b/arch/arm/src/imxrt/imxrt_edma.c @@ -57,6 +57,7 @@ #include "chip.h" #include "chip/imxrt_edma.h" #include "chip/imxrt_dmamux.h" +#include "imxrt_periphclks.h" #include "imxrt_edma.h" #ifdef CONFIG_IMXRT_EDMA @@ -358,9 +359,11 @@ void weak_function up_dmainitialize(void) dmainfo("Initialize eDMA\n"); - /* Enable peripheral clock */ + /* Enable peripheral clocking to eDMA and DMAMUX modules */ - /* Enable data structures */ + imxrt_clockrun_dma(); + + /* Initialize data structures */ memset(&g_edma, 0, sizeof()); for (i = 0; i < IMXRT_EDMA_NCHANNELS; i++) @@ -424,13 +427,20 @@ void weak_function up_dmainitialize(void) /**************************************************************************** * Name: imxrt_dmachannel * - * Allocate a DMA channel. This function sets aside a DMA channel then - * gives the caller exclusive access to the DMA channel. + * Allocate a DMA channel. This function sets aside a DMA channel, + * initializes the DMAMUX for the channel, then gives the caller exclusive + * access to the DMA channel. * - * The naming convention in all of the DMA interfaces is that one side is - * the 'peripheral' and the other is 'memory'. However, the interface - * could still be used if, for example, both sides were memory although - * the naming would be awkward. + * Input Parameters: + * dmamux - DMAMUX configuration see DMAMUX channel configuration register + * bit-field definitions in chip/imxrt_dmamux.h. Settings include: + * + * DMAMUX_CHCFG_SOURCE Chip-specific DMA source (required) + * DMAMUX_CHCFG_AON DMA Channel Always Enable (optional) + * DMAMUX_CHCFG_TRIG DMA Channel Trigger Enable (optional) + * DMAMUX_CHCFG_ENBL DMA Mux Channel Enable (required) + * + * A value of zero will disable the DMAMUX channel. * * Returned Value: * If a DMA channel is available, this function returns a non-NULL, void* @@ -438,7 +448,7 @@ void weak_function up_dmainitialize(void) * ****************************************************************************/ -DMA_HANDLE imxrt_dmachannel(void) +DMA_HANDLE imxrt_dmachannel(uint32_t dmamux) { struct imxrt_dmach_s *dmach; unsigned int chndx; @@ -450,6 +460,8 @@ DMA_HANDLE imxrt_dmachannel(void) for (chndx = 0; chndx < SAM_NDMACHAN; chndx++) { struct imxrt_dmach_s *candidate = &g_edma.dmach[chndx]; + uintptr_t regaddr; + if (!candidate->inuse) { dmach = candidate; @@ -457,9 +469,16 @@ DMA_HANDLE imxrt_dmachannel(void) dmach->state = IMXRT_DMA_IDLE; /* Clear any pending interrupts on the channel */ +#warning Missing Logic /* Disable the channel. */ +#warning Missing Logic + /* Set the DMAMUX register associated with this channel */ + + DEBUASSERT(chndx == dmach->chan); + regaddr = IMXRT_DMAMUX_CHCF(chndx); + putreg32(dmamux, regaddr); break; } } @@ -496,6 +515,7 @@ DMA_HANDLE imxrt_dmachannel(void) void imxrt_dmafree(DMA_HANDLE handle) { struct imxrt_dmach_s *dmach = (struct imxrt_dmach_s *)handle; + uintptr_t regaddr; dmainfo("dmach: %p\n", dmach); DEBUGASSERT(dmach != NULL && dmach->inuse && dmach->state != IMXRT_DMA_ACTIVE); @@ -507,6 +527,11 @@ void imxrt_dmafree(DMA_HANDLE handle) dmach->flags = 0; dmach->inuse = false; /* No longer in use */ dmach->state = IMXRT_DMA_IDLE; /* Better not be active! */ + + /* Disable the associated DMAMUX */ + + regaddr = IMXRT_DMAMUX_CHCF(chndx); + putreg32(0, regaddr); } /************************************************************************************ diff --git a/arch/arm/src/imxrt/imxrt_edma.h b/arch/arm/src/imxrt/imxrt_edma.h index 2a5d47b5f32..e82e62f61b6 100644 --- a/arch/arm/src/imxrt/imxrt_edma.h +++ b/arch/arm/src/imxrt/imxrt_edma.h @@ -49,7 +49,7 @@ * Pre-processor Definitions ************************************************************************************/ -/* DMA ******************************************************************************/ +/* eDMA Configuration ***************************************************************/ /* Flags used to characterize the DMA channel. The naming convention is that one * side is the peripheral and the other is memory (however, the interface could still @@ -202,25 +202,31 @@ extern "C" * Public Function Prototypes ************************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: imxrt_dmachannel * - * Description: - * Allocate a DMA channel. This function sets aside a DMA channel then gives the - * caller exclusive access to the DMA channel. + * Allocate a DMA channel. This function sets aside a DMA channel, + * initializes the DMAMUX for the channel, then gives the caller exclusive + * access to the DMA channel. * - * The naming convention in all of the DMA interfaces is that one side is the - * 'peripheral' and the other is 'memory'. However, the interface could still - * be used if, for example, both sides were memory although the naming would be - * awkward. + * Input Parameters: + * dmamux - DMAMUX configuration see DMAMUX channel configuration register + * bit-field definitions in chip/imxrt_dmamux.h. Settings include: + * + * DMAMUX_CHCFG_SOURCE Chip-specific DMA source (required) + * DMAMUX_CHCFG_AON DMA Channel Always Enable (optional) + * DMAMUX_CHCFG_TRIG DMA Channel Trigger Enable (optional) + * DMAMUX_CHCFG_ENBL DMA Mux Channel Enable (required) + * + * A value of zero will disable the DMAMUX channel. * * Returned Value: - * If a DMA channel is available, this function returns a non-NULL, void* DMA - * channel handle. NULL is returned on any failure. + * If a DMA channel is available, this function returns a non-NULL, void* + * DMA channel handle. NULL is returned on any failure. * - ************************************************************************************/ + ****************************************************************************/ -DMA_HANDLE imxrt_dmachannel(void); +DMA_HANDLE imxrt_dmachannel(uint32_t dmamux); /************************************************************************************ * Name: imxrt_dmafree diff --git a/arch/arm/src/imxrt/imxrt_lowputc.c b/arch/arm/src/imxrt/imxrt_lowputc.c index 47943e6debd..03ac8802dbb 100644 --- a/arch/arm/src/imxrt/imxrt_lowputc.c +++ b/arch/arm/src/imxrt/imxrt_lowputc.c @@ -50,6 +50,7 @@ #include "chip/imxrt_ccm.h" #include "chip/imxrt_lpuart.h" #include "imxrt_config.h" +#include "imxrt_periphclks.h" #include "imxrt_iomuxc.h" #include "imxrt_gpio.h" #include "imxrt_lowputc.h" @@ -169,63 +170,37 @@ static const struct uart_config_s g_console_config = void imxrt_lpuart_clock_enable (uint32_t base) { - uint32_t regval; - if (base == IMXRT_LPUART1_BASE) { - regval = getreg32(IMXRT_CCM_CCGR5); - regval &= ~ CCM_CCGRX_CG12_MASK; - regval |= (CCM_CG_ALL << CCM_CCGRX_CG12_SHIFT); - putreg32(regval, IMXRT_CCM_CCGR5); + imxrt_clockall_lpuart1(); } else if (base == IMXRT_LPUART2_BASE) { - regval = getreg32(IMXRT_CCM_CCGR0); - regval &= ~ CCM_CCGRX_CG14_MASK; - regval |= (CCM_CG_ALL << CCM_CCGRX_CG14_SHIFT); - putreg32(regval, IMXRT_CCM_CCGR0); + imxrt_clockall_lpuart2(); } else if (base == IMXRT_LPUART3_BASE) { - regval = getreg32(IMXRT_CCM_CCGR0); - regval &= ~ CCM_CCGRX_CG6_MASK; - regval |= (CCM_CG_ALL << CCM_CCGRX_CG6_SHIFT); - putreg32(regval, IMXRT_CCM_CCGR0); + imxrt_clockall_lpuart3(); } else if (base == IMXRT_LPUART4_BASE) { - regval = getreg32(IMXRT_CCM_CCGR1); - regval &= ~ CCM_CCGRX_CG12_MASK; - regval |= (CCM_CG_ALL << CCM_CCGRX_CG12_SHIFT); - putreg32(regval, IMXRT_CCM_CCGR1); + imxrt_clockall_lpuart4(); } else if (base == IMXRT_LPUART5_BASE) { - regval = getreg32(IMXRT_CCM_CCGR3); - regval &= ~ CCM_CCGRX_CG1_MASK; - regval |= (CCM_CG_ALL << CCM_CCGRX_CG1_SHIFT); - putreg32(regval, IMXRT_CCM_CCGR3); + imxrt_clockall_lpuart5(); } else if (base == IMXRT_LPUART6_BASE) { - regval = getreg32(IMXRT_CCM_CCGR3); - regval &= ~ CCM_CCGRX_CG4_MASK; - regval |= (CCM_CG_ALL << CCM_CCGRX_CG4_SHIFT); - putreg32(regval, IMXRT_CCM_CCGR3); + imxrt_clockall_lpuart6(); } else if (base == IMXRT_LPUART7_BASE) { - regval = getreg32(IMXRT_CCM_CCGR5); - regval &= ~ CCM_CCGRX_CG13_MASK; - regval |= (CCM_CG_ALL << CCM_CCGRX_CG13_SHIFT); - putreg32(regval, IMXRT_CCM_CCGR5); + imxrt_clockall_lpuart7(); } else if (base == IMXRT_LPUART8_BASE) { - regval = getreg32(IMXRT_CCM_CCGR6); - regval &= ~ CCM_CCGRX_CG7_MASK; - regval |= (CCM_CG_ALL << CCM_CCGRX_CG7_SHIFT); - putreg32(regval, IMXRT_CCM_CCGR6); + imxrt_clockall_lpuart8(); } } diff --git a/arch/arm/src/imxrt/imxrt_periphclks.c b/arch/arm/src/imxrt/imxrt_periphclks.c new file mode 100644 index 00000000000..9b3706d52ad --- /dev/null +++ b/arch/arm/src/imxrt/imxrt_periphclks.c @@ -0,0 +1,72 @@ +/**************************************************************************** + * arch/arm/src/imxrt/imxrt_periphclks.c + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Janne Rosberg + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "up_arch.h" +#include "imxrt_periphclks.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_periphclk_configure + * + * Description: + * Configure a peripheral clock by modifying the appropriate field in the + * appropriate CCRGR register. + * + * Input Parameters: + * regaddr - The CCMD CCGR register to be modified + * index - The index of the field to be modified + * value - The new value of the field + * + * Returned Value: + * None + * + ****************************************************************************/ + +void imxrt_periphclk_configure(uintptr_t regaddr, unsigned int index, + unsigned int value) +{ + modifyreg32(regaddr, CCM_CCGRX_CG_MASK(index), CCM_CCGRX_CG(index, value)); +} diff --git a/arch/arm/src/imxrt/imxrt_periphclks.h b/arch/arm/src/imxrt/imxrt_periphclks.h new file mode 100644 index 00000000000..37bc0710f68 --- /dev/null +++ b/arch/arm/src/imxrt/imxrt_periphclks.h @@ -0,0 +1,402 @@ +/******************************************************************************************** + * arch/arm/src/imxrt/imxrt_periphclks.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *********************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMXRT_IMXRT_PERIPHCLKS_H +#define __ARCH_ARM_SRC_IMXRT_IMXRT_PERIPHCLKS_H + +/******************************************************************************************** + * Included Files + *********************************************************************************************/ + +#include +#include +#include "chip/imxrt_ccm.h" + +/******************************************************************************************** + * Pre-processor Definitions + *********************************************************************************************/ + +/* Clock is off during all modes. Stop enter hardware handshake is disabled. */ + +#define imxrt_clockoff_acmp1() imxrt_periphclk_configure(CCM_CCGR_ACMP1, CCM_CG_OFF) +#define imxrt_clockoff_acmp2() imxrt_periphclk_configure(CCM_CCGR_ACMP2, CCM_CG_OFF) +#define imxrt_clockoff_acmp3() imxrt_periphclk_configure(CCM_CCGR_ACMP3, CCM_CG_OFF) +#define imxrt_clockoff_acmp4() imxrt_periphclk_configure(CCM_CCGR_ACMP4, CCM_CG_OFF) +#define imxrt_clockoff_adc1() imxrt_periphclk_configure(CCM_CCGR_ADC1, CCM_CG_OFF) +#define imxrt_clockoff_adc2() imxrt_periphclk_configure(CCM_CCGR_ADC2, CCM_CG_OFF) +#define imxrt_clockoff_aips_tz1() imxrt_periphclk_configure(CCM_CCGR_AIPS_TZ1, CCM_CG_OFF) +#define imxrt_clockoff_aips_tz2() imxrt_periphclk_configure(CCM_CCGR_AIPS_TZ2, CCM_CG_OFF) +#define imxrt_clockoff_aips_tz3() imxrt_periphclk_configure(CCM_CCGR_AIPS_TZ3, CCM_CG_OFF) +#define imxrt_clockoff_aipstz4() imxrt_periphclk_configure(CCM_CCGR_AIPSTZ4, CCM_CG_OFF) +#define imxrt_clockoff_anadig() imxrt_periphclk_configure(CCM_CCGR_ANADIG, CCM_CG_OFF) +#define imxrt_clockoff_aoi1() imxrt_periphclk_configure(CCM_CCGR_AOI1, CCM_CG_OFF) +#define imxrt_clockoff_aoi2() imxrt_periphclk_configure(CCM_CCGR_AOI2, CCM_CG_OFF) +#define imxrt_clockoff_bee() imxrt_periphclk_configure(CCM_CCGR_BEE, CCM_CG_OFF) +#define imxrt_clockoff_can1() imxrt_periphclk_configure(CCM_CCGR_CAN1, CCM_CG_OFF) +#define imxrt_clockoff_can1_serial() imxrt_periphclk_configure(CCM_CCGR_CAN1_SERIAL, CCM_CG_OFF) +#define imxrt_clockoff_can2() imxrt_periphclk_configure(CCM_CCGR_CAN2, CCM_CG_OFF) +#define imxrt_clockoff_can2_serial() imxrt_periphclk_configure(CCM_CCGR_CAN2_SERIAL, CCM_CG_OFF) +#define imxrt_clockoff_csi() imxrt_periphclk_configure(CCM_CCGR_CSI, CCM_CG_OFF) +#define imxrt_clockoff_csu() imxrt_periphclk_configure(CCM_CCGR_CSU, CCM_CG_OFF) +#define imxrt_clockoff_dcdc() imxrt_periphclk_configure(CCM_CCGR_DCDC, CCM_CG_OFF) +#define imxrt_clockoff_dcp() imxrt_periphclk_configure(CCM_CCGR_DCP, CCM_CG_OFF) +#define imxrt_clockoff_dma() imxrt_periphclk_configure(CCM_CCGR_DMA, CCM_CG_OFF) +#define imxrt_clockoff_enc1() imxrt_periphclk_configure(CCM_CCGR_ENC1, CCM_CG_OFF) +#define imxrt_clockoff_enc2() imxrt_periphclk_configure(CCM_CCGR_ENC2, CCM_CG_OFF) +#define imxrt_clockoff_enc3() imxrt_periphclk_configure(CCM_CCGR_ENC3, CCM_CG_OFF) +#define imxrt_clockoff_enc4() imxrt_periphclk_configure(CCM_CCGR_ENC4, CCM_CG_OFF) +#define imxrt_clockoff_enet() imxrt_periphclk_configure(CCM_CCGR_ENET, CCM_CG_OFF) +#define imxrt_clockoff_ewm() imxrt_periphclk_configure(CCM_CCGR_EWM, CCM_CG_OFF) +#define imxrt_clockoff_flexio1() imxrt_periphclk_configure(CCM_CCGR_FLEXIO1, CCM_CG_OFF) +#define imxrt_clockoff_flexio2() imxrt_periphclk_configure(CCM_CCGR_FLEXIO2, CCM_CG_OFF) +#define imxrt_clockoff_flexram() imxrt_periphclk_configure(CCM_CCGR_FLEXRAM, CCM_CG_OFF) +#define imxrt_clockoff_flexspi() imxrt_periphclk_configure(CCM_CCGR_FLEXSPI, CCM_CG_OFF) +#define imxrt_clockoff_gpio1() imxrt_periphclk_configure(CCM_CCGR_GPIO1, CCM_CG_OFF) +#define imxrt_clockoff_gpio2() imxrt_periphclk_configure(CCM_CCGR_GPIO2, CCM_CG_OFF) +#define imxrt_clockoff_gpio3() imxrt_periphclk_configure(CCM_CCGR_GPIO3, CCM_CG_OFF) +#define imxrt_clockoff_gpio4() imxrt_periphclk_configure(CCM_CCGR_GPIO4, CCM_CG_OFF) +#define imxrt_clockoff_gpt_bus() imxrt_periphclk_configure(CCM_CCGR_GPT_BUS, CCM_CG_OFF) +#define imxrt_clockoff_gpt_serial() imxrt_periphclk_configure(CCM_CCGR_GPT_SERIAL, CCM_CG_OFF) +#define imxrt_clockoff_gpt2_bus() imxrt_periphclk_configure(CCM_CCGR_GPT2_BUS, CCM_CG_OFF) +#define imxrt_clockoff_gpt2_serial() imxrt_periphclk_configure(CCM_CCGR_GPT2_SERIAL, CCM_CG_OFF) +#define imxrt_clockoff_iomuxc() imxrt_periphclk_configure(CCM_CCGR_IOMUXC, CCM_CG_OFF) +#define imxrt_clockoff_iomuxc_gpr() imxrt_periphclk_configure(CCM_CCGR_IOMUXC_GPR, CCM_CG_OFF) +#define imxrt_clockoff_iomuxc_snvs() imxrt_periphclk_configure(CCM_CCGR_IOMUXC_SNVS, CCM_CG_OFF) +#define imxrt_clockoff_iomuxc_snvs_gpr() imxrt_periphclk_configure(CCM_CCGR_IOMUXC_SNVS_GPR, CCM_CG_OFF) +#define imxrt_clockoff_ipmux1() imxrt_periphclk_configure(CCM_CCGR_IPMUX1, CCM_CG_OFF) +#define imxrt_clockoff_ipmux2() imxrt_periphclk_configure(CCM_CCGR_IPMUX2, CCM_CG_OFF) +#define imxrt_clockoff_ipmux3() imxrt_periphclk_configure(CCM_CCGR_IPMUX3, CCM_CG_OFF) +#define imxrt_clockoff_ipmux4() imxrt_periphclk_configure(CCM_CCGR_IPMUX4, CCM_CG_OFF) +#define imxrt_clockoff_kpp() imxrt_periphclk_configure(CCM_CCGR_KPP, CCM_CG_OFF) +#define imxrt_clockoff_lcd() imxrt_periphclk_configure(CCM_CCGR_LCD, CCM_CG_OFF) +#define imxrt_clockoff_lcdif_pix() imxrt_periphclk_configure(CCM_CCGR_LCDIF_PIX, CCM_CG_OFF) +#define imxrt_clockoff_lpi2c1() imxrt_periphclk_configure(CCM_CCGR_LPI2C1, CCM_CG_OFF) +#define imxrt_clockoff_lpi2c2() imxrt_periphclk_configure(CCM_CCGR_LPI2C2, CCM_CG_OFF) +#define imxrt_clockoff_lpi2c3() imxrt_periphclk_configure(CCM_CCGR_LPI2C3, CCM_CG_OFF) +#define imxrt_clockoff_lpi2c4_serial() imxrt_periphclk_configure(CCM_CCGR_LPI2C4_SERIAL, CCM_CG_OFF) +#define imxrt_clockoff_lpspi1() imxrt_periphclk_configure(CCM_CCGR_LPSPI1, CCM_CG_OFF) +#define imxrt_clockoff_lpspi2() imxrt_periphclk_configure(CCM_CCGR_LPSPI2, CCM_CG_OFF) +#define imxrt_clockoff_lpspi3() imxrt_periphclk_configure(CCM_CCGR_LPSPI3, CCM_CG_OFF) +#define imxrt_clockoff_lpspi4() imxrt_periphclk_configure(CCM_CCGR_LPSPI4, CCM_CG_OFF) +#define imxrt_clockoff_lpuart1() imxrt_periphclk_configure(CCM_CCGR_LPUART1, CCM_CG_OFF) +#define imxrt_clockoff_lpuart2() imxrt_periphclk_configure(CCM_CCGR_LPUART2, CCM_CG_OFF) +#define imxrt_clockoff_lpuart3() imxrt_periphclk_configure(CCM_CCGR_LPUART3, CCM_CG_OFF) +#define imxrt_clockoff_lpuart4() imxrt_periphclk_configure(CCM_CCGR_LPUART4, CCM_CG_OFF) +#define imxrt_clockoff_lpuart5() imxrt_periphclk_configure(CCM_CCGR_LPUART5, CCM_CG_OFF) +#define imxrt_clockoff_lpuart6() imxrt_periphclk_configure(CCM_CCGR_LPUART6, CCM_CG_OFF) +#define imxrt_clockoff_lpuart7() imxrt_periphclk_configure(CCM_CCGR_LPUART7, CCM_CG_OFF) +#define imxrt_clockoff_lpuart8() imxrt_periphclk_configure(CCM_CCGR_LPUART8, CCM_CG_OFF) +#define imxrt_clockoff_mqs() imxrt_periphclk_configure(CCM_CCGR_MQS, CCM_CG_OFF) +#define imxrt_clockoff_ocotp_ctrl() imxrt_periphclk_configure(CCM_CCGR_OCOTP_CTRL, CCM_CG_OFF) +#define imxrt_clockoff_ocram() imxrt_periphclk_configure(CCM_CCGR_OCRAM, CCM_CG_OFF) +#define imxrt_clockoff_pit() imxrt_periphclk_configure(CCM_CCGR_PIT, CCM_CG_OFF) +#define imxrt_clockoff_pwm1() imxrt_periphclk_configure(CCM_CCGR_PWM1, CCM_CG_OFF) +#define imxrt_clockoff_pwm2() imxrt_periphclk_configure(CCM_CCGR_PWM2, CCM_CG_OFF) +#define imxrt_clockoff_pwm3() imxrt_periphclk_configure(CCM_CCGR_PWM3, CCM_CG_OFF) +#define imxrt_clockoff_pwm4() imxrt_periphclk_configure(CCM_CCGR_PWM4, CCM_CG_OFF) +#define imxrt_clockoff_pxp() imxrt_periphclk_configure(CCM_CCGR_PXP, CCM_CG_OFF) +#define imxrt_clockoff_rom() imxrt_periphclk_configure(CCM_CCGR_ROM, CCM_CG_OFF) +#define imxrt_clockoff_sai1() imxrt_periphclk_configure(CCM_CCGR_SAI1, CCM_CG_OFF) +#define imxrt_clockoff_sai2() imxrt_periphclk_configure(CCM_CCGR_SAI2, CCM_CG_OFF) +#define imxrt_clockoff_sai3() imxrt_periphclk_configure(CCM_CCGR_SAI3, CCM_CG_OFF) +#define imxrt_clockoff_semc() imxrt_periphclk_configure(CCM_CCGR_SEMC, CCM_CG_OFF) +#define imxrt_clockoff_sim_ems() imxrt_periphclk_configure(CCM_CCGR_SIM_EMS, CCM_CG_OFF) +#define imxrt_clockoff_sim_m() imxrt_periphclk_configure(CCM_CCGR_SIM_M, CCM_CG_OFF) +#define imxrt_clockoff_sim_m7() imxrt_periphclk_configure(CCM_CCGR_SIM_M7, CCM_CG_OFF) +#define imxrt_clockoff_sim_main() imxrt_periphclk_configure(CCM_CCGR_SIM_MAIN, CCM_CG_OFF) +#define imxrt_clockoff_sim_per() imxrt_periphclk_configure(CCM_CCGR_SIM_PER, CCM_CG_OFF) +#define imxrt_clockoff_snvs_hp() imxrt_periphclk_configure(CCM_CCGR_SNVS_HP, CCM_CG_OFF) +#define imxrt_clockoff_snvs_lp() imxrt_periphclk_configure(CCM_CCGR_SNVS_LP, CCM_CG_OFF) +#define imxrt_clockoff_spdif() imxrt_periphclk_configure(CCM_CCGR_SPDIF, CCM_CG_OFF) +#define imxrt_clockoff_timer1() imxrt_periphclk_configure(CCM_CCGR_TIMER1, CCM_CG_OFF) +#define imxrt_clockoff_timer2() imxrt_periphclk_configure(CCM_CCGR_TIMER2, CCM_CG_OFF) +#define imxrt_clockoff_timer3() imxrt_periphclk_configure(CCM_CCGR_TIMER3, CCM_CG_OFF) +#define imxrt_clockoff_timer4() imxrt_periphclk_configure(CCM_CCGR_TIMER4, CCM_CG_OFF) +#define imxrt_clockoff_trace() imxrt_periphclk_configure(CCM_CCGR_TRACE, CCM_CG_OFF) +#define imxrt_clockoff_trng() imxrt_periphclk_configure(CCM_CCGR_TRNG, CCM_CG_OFF) +#define imxrt_clockoff_tsc_dig() imxrt_periphclk_configure(CCM_CCGR_TSC_DIG, CCM_CG_OFF) +#define imxrt_clockoff_usboh3() imxrt_periphclk_configure(CCM_CCGR_USBOH3, CCM_CG_OFF) +#define imxrt_clockoff_usdhc1() imxrt_periphclk_configure(CCM_CCGR_USDHC1, CCM_CG_OFF) +#define imxrt_clockoff_usdhc2() imxrt_periphclk_configure(CCM_CCGR_USDHC2, CCM_CG_OFF) +#define imxrt_clockoff_wdog1() imxrt_periphclk_configure(CCM_CCGR_WDOG1, CCM_CG_OFF) +#define imxrt_clockoff_wdog2() imxrt_periphclk_configure(CCM_CCGR_WDOG2, CCM_CG_OFF) +#define imxrt_clockoff_wdog3() imxrt_periphclk_configure(CCM_CCGR_WDOG3, CCM_CG_OFF) +#define imxrt_clockoff_xbar1() imxrt_periphclk_configure(CCM_CCGR_XBAR1, CCM_CG_OFF) +#define imxrt_clockoff_xbar2() imxrt_periphclk_configure(CCM_CCGR_XBAR2, CCM_CG_OFF) +#define imxrt_clockoff_xbar3() imxrt_periphclk_configure(CCM_CCGR_XBAR3, CCM_CG_OFF) + +/* Clock is on in run mode, but off in WAIT and STOP modes. */ + +#define imxrt_clockrun_acmp1() imxrt_periphclk_configure(CCM_CCGR_ACMP1, CCM_CG_RUN) +#define imxrt_clockrun_acmp2() imxrt_periphclk_configure(CCM_CCGR_ACMP2, CCM_CG_RUN) +#define imxrt_clockrun_acmp3() imxrt_periphclk_configure(CCM_CCGR_ACMP3, CCM_CG_RUN) +#define imxrt_clockrun_acmp4() imxrt_periphclk_configure(CCM_CCGR_ACMP4, CCM_CG_RUN) +#define imxrt_clockrun_adc1() imxrt_periphclk_configure(CCM_CCGR_ADC1, CCM_CG_RUN) +#define imxrt_clockrun_adc2() imxrt_periphclk_configure(CCM_CCGR_ADC2, CCM_CG_RUN) +#define imxrt_clockrun_aips_tz1() imxrt_periphclk_configure(CCM_CCGR_AIPS_TZ1, CCM_CG_RUN) +#define imxrt_clockrun_aips_tz2() imxrt_periphclk_configure(CCM_CCGR_AIPS_TZ2, CCM_CG_RUN) +#define imxrt_clockrun_aips_tz3() imxrt_periphclk_configure(CCM_CCGR_AIPS_TZ3, CCM_CG_RUN) +#define imxrt_clockrun_aipstz4() imxrt_periphclk_configure(CCM_CCGR_AIPSTZ4, CCM_CG_RUN) +#define imxrt_clockrun_anadig() imxrt_periphclk_configure(CCM_CCGR_ANADIG, CCM_CG_RUN) +#define imxrt_clockrun_aoi1() imxrt_periphclk_configure(CCM_CCGR_AOI1, CCM_CG_RUN) +#define imxrt_clockrun_aoi2() imxrt_periphclk_configure(CCM_CCGR_AOI2, CCM_CG_RUN) +#define imxrt_clockrun_bee() imxrt_periphclk_configure(CCM_CCGR_BEE, CCM_CG_RUN) +#define imxrt_clockrun_can1() imxrt_periphclk_configure(CCM_CCGR_CAN1, CCM_CG_RUN) +#define imxrt_clockrun_can1_serial() imxrt_periphclk_configure(CCM_CCGR_CAN1_SERIAL, CCM_CG_RUN) +#define imxrt_clockrun_can2() imxrt_periphclk_configure(CCM_CCGR_CAN2, CCM_CG_RUN) +#define imxrt_clockrun_can2_serial() imxrt_periphclk_configure(CCM_CCGR_CAN2_SERIAL, CCM_CG_RUN) +#define imxrt_clockrun_csi() imxrt_periphclk_configure(CCM_CCGR_CSI, CCM_CG_RUN) +#define imxrt_clockrun_csu() imxrt_periphclk_configure(CCM_CCGR_CSU, CCM_CG_RUN) +#define imxrt_clockrun_dcdc() imxrt_periphclk_configure(CCM_CCGR_DCDC, CCM_CG_RUN) +#define imxrt_clockrun_dcp() imxrt_periphclk_configure(CCM_CCGR_DCP, CCM_CG_RUN) +#define imxrt_clockrun_dma() imxrt_periphclk_configure(CCM_CCGR_DMA, CCM_CG_RUN) +#define imxrt_clockrun_enc1() imxrt_periphclk_configure(CCM_CCGR_ENC1, CCM_CG_RUN) +#define imxrt_clockrun_enc2() imxrt_periphclk_configure(CCM_CCGR_ENC2, CCM_CG_RUN) +#define imxrt_clockrun_enc3() imxrt_periphclk_configure(CCM_CCGR_ENC3, CCM_CG_RUN) +#define imxrt_clockrun_enc4() imxrt_periphclk_configure(CCM_CCGR_ENC4, CCM_CG_RUN) +#define imxrt_clockrun_enet() imxrt_periphclk_configure(CCM_CCGR_ENET, CCM_CG_RUN) +#define imxrt_clockrun_ewm() imxrt_periphclk_configure(CCM_CCGR_EWM, CCM_CG_RUN) +#define imxrt_clockrun_flexio1() imxrt_periphclk_configure(CCM_CCGR_FLEXIO1, CCM_CG_RUN) +#define imxrt_clockrun_flexio2() imxrt_periphclk_configure(CCM_CCGR_FLEXIO2, CCM_CG_RUN) +#define imxrt_clockrun_flexram() imxrt_periphclk_configure(CCM_CCGR_FLEXRAM, CCM_CG_RUN) +#define imxrt_clockrun_flexspi() imxrt_periphclk_configure(CCM_CCGR_FLEXSPI, CCM_CG_RUN) +#define imxrt_clockrun_gpio1() imxrt_periphclk_configure(CCM_CCGR_GPIO1, CCM_CG_RUN) +#define imxrt_clockrun_gpio2() imxrt_periphclk_configure(CCM_CCGR_GPIO2, CCM_CG_RUN) +#define imxrt_clockrun_gpio3() imxrt_periphclk_configure(CCM_CCGR_GPIO3, CCM_CG_RUN) +#define imxrt_clockrun_gpio4() imxrt_periphclk_configure(CCM_CCGR_GPIO4, CCM_CG_RUN) +#define imxrt_clockrun_gpt_bus() imxrt_periphclk_configure(CCM_CCGR_GPT_BUS, CCM_CG_RUN) +#define imxrt_clockrun_gpt_serial() imxrt_periphclk_configure(CCM_CCGR_GPT_SERIAL, CCM_CG_RUN) +#define imxrt_clockrun_gpt2_bus() imxrt_periphclk_configure(CCM_CCGR_GPT2_BUS, CCM_CG_RUN) +#define imxrt_clockrun_gpt2_serial() imxrt_periphclk_configure(CCM_CCGR_GPT2_SERIAL, CCM_CG_RUN) +#define imxrt_clockrun_iomuxc() imxrt_periphclk_configure(CCM_CCGR_IOMUXC, CCM_CG_RUN) +#define imxrt_clockrun_iomuxc_gpr() imxrt_periphclk_configure(CCM_CCGR_IOMUXC_GPR, CCM_CG_RUN) +#define imxrt_clockrun_iomuxc_snvs() imxrt_periphclk_configure(CCM_CCGR_IOMUXC_SNVS, CCM_CG_RUN) +#define imxrt_clockrun_iomuxc_snvs_gpr() imxrt_periphclk_configure(CCM_CCGR_IOMUXC_SNVS_GPR, CCM_CG_RUN) +#define imxrt_clockrun_ipmux1() imxrt_periphclk_configure(CCM_CCGR_IPMUX1, CCM_CG_RUN) +#define imxrt_clockrun_ipmux2() imxrt_periphclk_configure(CCM_CCGR_IPMUX2, CCM_CG_RUN) +#define imxrt_clockrun_ipmux3() imxrt_periphclk_configure(CCM_CCGR_IPMUX3, CCM_CG_RUN) +#define imxrt_clockrun_ipmux4() imxrt_periphclk_configure(CCM_CCGR_IPMUX4, CCM_CG_RUN) +#define imxrt_clockrun_kpp() imxrt_periphclk_configure(CCM_CCGR_KPP, CCM_CG_RUN) +#define imxrt_clockrun_lcd() imxrt_periphclk_configure(CCM_CCGR_LCD, CCM_CG_RUN) +#define imxrt_clockrun_lcdif_pix() imxrt_periphclk_configure(CCM_CCGR_LCDIF_PIX, CCM_CG_RUN) +#define imxrt_clockrun_lpi2c1() imxrt_periphclk_configure(CCM_CCGR_LPI2C1, CCM_CG_RUN) +#define imxrt_clockrun_lpi2c2() imxrt_periphclk_configure(CCM_CCGR_LPI2C2, CCM_CG_RUN) +#define imxrt_clockrun_lpi2c3() imxrt_periphclk_configure(CCM_CCGR_LPI2C3, CCM_CG_RUN) +#define imxrt_clockrun_lpi2c4_serial() imxrt_periphclk_configure(CCM_CCGR_LPI2C4_SERIAL, CCM_CG_RUN) +#define imxrt_clockrun_lpspi1() imxrt_periphclk_configure(CCM_CCGR_LPSPI1, CCM_CG_RUN) +#define imxrt_clockrun_lpspi2() imxrt_periphclk_configure(CCM_CCGR_LPSPI2, CCM_CG_RUN) +#define imxrt_clockrun_lpspi3() imxrt_periphclk_configure(CCM_CCGR_LPSPI3, CCM_CG_RUN) +#define imxrt_clockrun_lpspi4() imxrt_periphclk_configure(CCM_CCGR_LPSPI4, CCM_CG_RUN) +#define imxrt_clockrun_lpuart1() imxrt_periphclk_configure(CCM_CCGR_LPUART1, CCM_CG_RUN) +#define imxrt_clockrun_lpuart2() imxrt_periphclk_configure(CCM_CCGR_LPUART2, CCM_CG_RUN) +#define imxrt_clockrun_lpuart3() imxrt_periphclk_configure(CCM_CCGR_LPUART3, CCM_CG_RUN) +#define imxrt_clockrun_lpuart4() imxrt_periphclk_configure(CCM_CCGR_LPUART4, CCM_CG_RUN) +#define imxrt_clockrun_lpuart5() imxrt_periphclk_configure(CCM_CCGR_LPUART5, CCM_CG_RUN) +#define imxrt_clockrun_lpuart6() imxrt_periphclk_configure(CCM_CCGR_LPUART6, CCM_CG_RUN) +#define imxrt_clockrun_lpuart7() imxrt_periphclk_configure(CCM_CCGR_LPUART7, CCM_CG_RUN) +#define imxrt_clockrun_lpuart8() imxrt_periphclk_configure(CCM_CCGR_LPUART8, CCM_CG_RUN) +#define imxrt_clockrun_mqs() imxrt_periphclk_configure(CCM_CCGR_MQS, CCM_CG_RUN) +#define imxrt_clockrun_ocotp_ctrl() imxrt_periphclk_configure(CCM_CCGR_OCOTP_CTRL, CCM_CG_RUN) +#define imxrt_clockrun_ocram() imxrt_periphclk_configure(CCM_CCGR_OCRAM, CCM_CG_RUN) +#define imxrt_clockrun_pit() imxrt_periphclk_configure(CCM_CCGR_PIT, CCM_CG_RUN) +#define imxrt_clockrun_pwm1() imxrt_periphclk_configure(CCM_CCGR_PWM1, CCM_CG_RUN) +#define imxrt_clockrun_pwm2() imxrt_periphclk_configure(CCM_CCGR_PWM2, CCM_CG_RUN) +#define imxrt_clockrun_pwm3() imxrt_periphclk_configure(CCM_CCGR_PWM3, CCM_CG_RUN) +#define imxrt_clockrun_pwm4() imxrt_periphclk_configure(CCM_CCGR_PWM4, CCM_CG_RUN) +#define imxrt_clockrun_pxp() imxrt_periphclk_configure(CCM_CCGR_PXP, CCM_CG_RUN) +#define imxrt_clockrun_rom() imxrt_periphclk_configure(CCM_CCGR_ROM, CCM_CG_RUN) +#define imxrt_clockrun_sai1() imxrt_periphclk_configure(CCM_CCGR_SAI1, CCM_CG_RUN) +#define imxrt_clockrun_sai2() imxrt_periphclk_configure(CCM_CCGR_SAI2, CCM_CG_RUN) +#define imxrt_clockrun_sai3() imxrt_periphclk_configure(CCM_CCGR_SAI3, CCM_CG_RUN) +#define imxrt_clockrun_semc() imxrt_periphclk_configure(CCM_CCGR_SEMC, CCM_CG_RUN) +#define imxrt_clockrun_sim_ems() imxrt_periphclk_configure(CCM_CCGR_SIM_EMS, CCM_CG_RUN) +#define imxrt_clockrun_sim_m() imxrt_periphclk_configure(CCM_CCGR_SIM_M, CCM_CG_RUN) +#define imxrt_clockrun_sim_m7() imxrt_periphclk_configure(CCM_CCGR_SIM_M7, CCM_CG_RUN) +#define imxrt_clockrun_sim_main() imxrt_periphclk_configure(CCM_CCGR_SIM_MAIN, CCM_CG_RUN) +#define imxrt_clockrun_sim_per() imxrt_periphclk_configure(CCM_CCGR_SIM_PER, CCM_CG_RUN) +#define imxrt_clockrun_snvs_hp() imxrt_periphclk_configure(CCM_CCGR_SNVS_HP, CCM_CG_RUN) +#define imxrt_clockrun_snvs_lp() imxrt_periphclk_configure(CCM_CCGR_SNVS_LP, CCM_CG_RUN) +#define imxrt_clockrun_spdif() imxrt_periphclk_configure(CCM_CCGR_SPDIF, CCM_CG_RUN) +#define imxrt_clockrun_timer1() imxrt_periphclk_configure(CCM_CCGR_TIMER1, CCM_CG_RUN) +#define imxrt_clockrun_timer2() imxrt_periphclk_configure(CCM_CCGR_TIMER2, CCM_CG_RUN) +#define imxrt_clockrun_timer3() imxrt_periphclk_configure(CCM_CCGR_TIMER3, CCM_CG_RUN) +#define imxrt_clockrun_timer4() imxrt_periphclk_configure(CCM_CCGR_TIMER4, CCM_CG_RUN) +#define imxrt_clockrun_trace() imxrt_periphclk_configure(CCM_CCGR_TRACE, CCM_CG_RUN) +#define imxrt_clockrun_trng() imxrt_periphclk_configure(CCM_CCGR_TRNG, CCM_CG_RUN) +#define imxrt_clockrun_tsc_dig() imxrt_periphclk_configure(CCM_CCGR_TSC_DIG, CCM_CG_RUN) +#define imxrt_clockrun_usboh3() imxrt_periphclk_configure(CCM_CCGR_USBOH3, CCM_CG_RUN) +#define imxrt_clockrun_usdhc1() imxrt_periphclk_configure(CCM_CCGR_USDHC1, CCM_CG_RUN) +#define imxrt_clockrun_usdhc2() imxrt_periphclk_configure(CCM_CCGR_USDHC2, CCM_CG_RUN) +#define imxrt_clockrun_wdog1() imxrt_periphclk_configure(CCM_CCGR_WDOG1, CCM_CG_RUN) +#define imxrt_clockrun_wdog2() imxrt_periphclk_configure(CCM_CCGR_WDOG2, CCM_CG_RUN) +#define imxrt_clockrun_wdog3() imxrt_periphclk_configure(CCM_CCGR_WDOG3, CCM_CG_RUN) +#define imxrt_clockrun_xbar1() imxrt_periphclk_configure(CCM_CCGR_XBAR1, CCM_CG_RUN) +#define imxrt_clockrun_xbar2() imxrt_periphclk_configure(CCM_CCGR_XBAR2, CCM_CG_RUN) +#define imxrt_clockrun_xbar3() imxrt_periphclk_configure(CCM_CCGR_XBAR3, CCM_CG_RUN) + +/* Clock is on during all modes, except STOP mode. */ + +#define imxrt_clockall_acmp1() imxrt_periphclk_configure(CCM_CCGR_ACMP1, CCM_CG_ALL) +#define imxrt_clockall_acmp2() imxrt_periphclk_configure(CCM_CCGR_ACMP2, CCM_CG_ALL) +#define imxrt_clockall_acmp3() imxrt_periphclk_configure(CCM_CCGR_ACMP3, CCM_CG_ALL) +#define imxrt_clockall_acmp4() imxrt_periphclk_configure(CCM_CCGR_ACMP4, CCM_CG_ALL) +#define imxrt_clockall_adc1() imxrt_periphclk_configure(CCM_CCGR_ADC1, CCM_CG_ALL) +#define imxrt_clockall_adc2() imxrt_periphclk_configure(CCM_CCGR_ADC2, CCM_CG_ALL) +#define imxrt_clockall_aips_tz1() imxrt_periphclk_configure(CCM_CCGR_AIPS_TZ1, CCM_CG_ALL) +#define imxrt_clockall_aips_tz2() imxrt_periphclk_configure(CCM_CCGR_AIPS_TZ2, CCM_CG_ALL) +#define imxrt_clockall_aips_tz3() imxrt_periphclk_configure(CCM_CCGR_AIPS_TZ3, CCM_CG_ALL) +#define imxrt_clockall_aipstz4() imxrt_periphclk_configure(CCM_CCGR_AIPSTZ4, CCM_CG_ALL) +#define imxrt_clockall_anadig() imxrt_periphclk_configure(CCM_CCGR_ANADIG, CCM_CG_ALL) +#define imxrt_clockall_aoi1() imxrt_periphclk_configure(CCM_CCGR_AOI1, CCM_CG_ALL) +#define imxrt_clockall_aoi2() imxrt_periphclk_configure(CCM_CCGR_AOI2, CCM_CG_ALL) +#define imxrt_clockall_bee() imxrt_periphclk_configure(CCM_CCGR_BEE, CCM_CG_ALL) +#define imxrt_clockall_can1() imxrt_periphclk_configure(CCM_CCGR_CAN1, CCM_CG_ALL) +#define imxrt_clockall_can1_serial() imxrt_periphclk_configure(CCM_CCGR_CAN1_SERIAL, CCM_CG_ALL) +#define imxrt_clockall_can2() imxrt_periphclk_configure(CCM_CCGR_CAN2, CCM_CG_ALL) +#define imxrt_clockall_can2_serial() imxrt_periphclk_configure(CCM_CCGR_CAN2_SERIAL, CCM_CG_ALL) +#define imxrt_clockall_csi() imxrt_periphclk_configure(CCM_CCGR_CSI, CCM_CG_ALL) +#define imxrt_clockall_csu() imxrt_periphclk_configure(CCM_CCGR_CSU, CCM_CG_ALL) +#define imxrt_clockall_dcdc() imxrt_periphclk_configure(CCM_CCGR_DCDC, CCM_CG_ALL) +#define imxrt_clockall_dcp() imxrt_periphclk_configure(CCM_CCGR_DCP, CCM_CG_ALL) +#define imxrt_clockall_dma() imxrt_periphclk_configure(CCM_CCGR_DMA, CCM_CG_ALL) +#define imxrt_clockall_enc1() imxrt_periphclk_configure(CCM_CCGR_ENC1, CCM_CG_ALL) +#define imxrt_clockall_enc2() imxrt_periphclk_configure(CCM_CCGR_ENC2, CCM_CG_ALL) +#define imxrt_clockall_enc3() imxrt_periphclk_configure(CCM_CCGR_ENC3, CCM_CG_ALL) +#define imxrt_clockall_enc4() imxrt_periphclk_configure(CCM_CCGR_ENC4, CCM_CG_ALL) +#define imxrt_clockall_enet() imxrt_periphclk_configure(CCM_CCGR_ENET, CCM_CG_ALL) +#define imxrt_clockall_ewm() imxrt_periphclk_configure(CCM_CCGR_EWM, CCM_CG_ALL) +#define imxrt_clockall_flexio1() imxrt_periphclk_configure(CCM_CCGR_FLEXIO1, CCM_CG_ALL) +#define imxrt_clockall_flexio2() imxrt_periphclk_configure(CCM_CCGR_FLEXIO2, CCM_CG_ALL) +#define imxrt_clockall_flexram() imxrt_periphclk_configure(CCM_CCGR_FLEXRAM, CCM_CG_ALL) +#define imxrt_clockall_flexspi() imxrt_periphclk_configure(CCM_CCGR_FLEXSPI, CCM_CG_ALL) +#define imxrt_clockall_gpio1() imxrt_periphclk_configure(CCM_CCGR_GPIO1, CCM_CG_ALL) +#define imxrt_clockall_gpio2() imxrt_periphclk_configure(CCM_CCGR_GPIO2, CCM_CG_ALL) +#define imxrt_clockall_gpio3() imxrt_periphclk_configure(CCM_CCGR_GPIO3, CCM_CG_ALL) +#define imxrt_clockall_gpio4() imxrt_periphclk_configure(CCM_CCGR_GPIO4, CCM_CG_ALL) +#define imxrt_clockall_gpt_bus() imxrt_periphclk_configure(CCM_CCGR_GPT_BUS, CCM_CG_ALL) +#define imxrt_clockall_gpt_serial() imxrt_periphclk_configure(CCM_CCGR_GPT_SERIAL, CCM_CG_ALL) +#define imxrt_clockall_gpt2_bus() imxrt_periphclk_configure(CCM_CCGR_GPT2_BUS, CCM_CG_ALL) +#define imxrt_clockall_gpt2_serial() imxrt_periphclk_configure(CCM_CCGR_GPT2_SERIAL, CCM_CG_ALL) +#define imxrt_clockall_iomuxc() imxrt_periphclk_configure(CCM_CCGR_IOMUXC, CCM_CG_ALL) +#define imxrt_clockall_iomuxc_gpr() imxrt_periphclk_configure(CCM_CCGR_IOMUXC_GPR, CCM_CG_ALL) +#define imxrt_clockall_iomuxc_snvs() imxrt_periphclk_configure(CCM_CCGR_IOMUXC_SNVS, CCM_CG_ALL) +#define imxrt_clockall_iomuxc_snvs_gpr() imxrt_periphclk_configure(CCM_CCGR_IOMUXC_SNVS_GPR, CCM_CG_ALL) +#define imxrt_clockall_ipmux1() imxrt_periphclk_configure(CCM_CCGR_IPMUX1, CCM_CG_ALL) +#define imxrt_clockall_ipmux2() imxrt_periphclk_configure(CCM_CCGR_IPMUX2, CCM_CG_ALL) +#define imxrt_clockall_ipmux3() imxrt_periphclk_configure(CCM_CCGR_IPMUX3, CCM_CG_ALL) +#define imxrt_clockall_ipmux4() imxrt_periphclk_configure(CCM_CCGR_IPMUX4, CCM_CG_ALL) +#define imxrt_clockall_kpp() imxrt_periphclk_configure(CCM_CCGR_KPP, CCM_CG_ALL) +#define imxrt_clockall_lcd() imxrt_periphclk_configure(CCM_CCGR_LCD, CCM_CG_ALL) +#define imxrt_clockall_lcdif_pix() imxrt_periphclk_configure(CCM_CCGR_LCDIF_PIX, CCM_CG_ALL) +#define imxrt_clockall_lpi2c1() imxrt_periphclk_configure(CCM_CCGR_LPI2C1, CCM_CG_ALL) +#define imxrt_clockall_lpi2c2() imxrt_periphclk_configure(CCM_CCGR_LPI2C2, CCM_CG_ALL) +#define imxrt_clockall_lpi2c3() imxrt_periphclk_configure(CCM_CCGR_LPI2C3, CCM_CG_ALL) +#define imxrt_clockall_lpi2c4_serial() imxrt_periphclk_configure(CCM_CCGR_LPI2C4_SERIAL, CCM_CG_ALL) +#define imxrt_clockall_lpspi1() imxrt_periphclk_configure(CCM_CCGR_LPSPI1, CCM_CG_ALL) +#define imxrt_clockall_lpspi2() imxrt_periphclk_configure(CCM_CCGR_LPSPI2, CCM_CG_ALL) +#define imxrt_clockall_lpspi3() imxrt_periphclk_configure(CCM_CCGR_LPSPI3, CCM_CG_ALL) +#define imxrt_clockall_lpspi4() imxrt_periphclk_configure(CCM_CCGR_LPSPI4, CCM_CG_ALL) +#define imxrt_clockall_lpuart1() imxrt_periphclk_configure(CCM_CCGR_LPUART1, CCM_CG_ALL) +#define imxrt_clockall_lpuart2() imxrt_periphclk_configure(CCM_CCGR_LPUART2, CCM_CG_ALL) +#define imxrt_clockall_lpuart3() imxrt_periphclk_configure(CCM_CCGR_LPUART3, CCM_CG_ALL) +#define imxrt_clockall_lpuart4() imxrt_periphclk_configure(CCM_CCGR_LPUART4, CCM_CG_ALL) +#define imxrt_clockall_lpuart5() imxrt_periphclk_configure(CCM_CCGR_LPUART5, CCM_CG_ALL) +#define imxrt_clockall_lpuart6() imxrt_periphclk_configure(CCM_CCGR_LPUART6, CCM_CG_ALL) +#define imxrt_clockall_lpuart7() imxrt_periphclk_configure(CCM_CCGR_LPUART7, CCM_CG_ALL) +#define imxrt_clockall_lpuart8() imxrt_periphclk_configure(CCM_CCGR_LPUART8, CCM_CG_ALL) +#define imxrt_clockall_mqs() imxrt_periphclk_configure(CCM_CCGR_MQS, CCM_CG_ALL) +#define imxrt_clockall_ocotp_ctrl() imxrt_periphclk_configure(CCM_CCGR_OCOTP_CTRL, CCM_CG_ALL) +#define imxrt_clockall_ocram() imxrt_periphclk_configure(CCM_CCGR_OCRAM, CCM_CG_ALL) +#define imxrt_clockall_pit() imxrt_periphclk_configure(CCM_CCGR_PIT, CCM_CG_ALL) +#define imxrt_clockall_pwm1() imxrt_periphclk_configure(CCM_CCGR_PWM1, CCM_CG_ALL) +#define imxrt_clockall_pwm2() imxrt_periphclk_configure(CCM_CCGR_PWM2, CCM_CG_ALL) +#define imxrt_clockall_pwm3() imxrt_periphclk_configure(CCM_CCGR_PWM3, CCM_CG_ALL) +#define imxrt_clockall_pwm4() imxrt_periphclk_configure(CCM_CCGR_PWM4, CCM_CG_ALL) +#define imxrt_clockall_pxp() imxrt_periphclk_configure(CCM_CCGR_PXP, CCM_CG_ALL) +#define imxrt_clockall_rom() imxrt_periphclk_configure(CCM_CCGR_ROM, CCM_CG_ALL) +#define imxrt_clockall_sai1() imxrt_periphclk_configure(CCM_CCGR_SAI1, CCM_CG_ALL) +#define imxrt_clockall_sai2() imxrt_periphclk_configure(CCM_CCGR_SAI2, CCM_CG_ALL) +#define imxrt_clockall_sai3() imxrt_periphclk_configure(CCM_CCGR_SAI3, CCM_CG_ALL) +#define imxrt_clockall_semc() imxrt_periphclk_configure(CCM_CCGR_SEMC, CCM_CG_ALL) +#define imxrt_clockall_sim_ems() imxrt_periphclk_configure(CCM_CCGR_SIM_EMS, CCM_CG_ALL) +#define imxrt_clockall_sim_m() imxrt_periphclk_configure(CCM_CCGR_SIM_M, CCM_CG_ALL) +#define imxrt_clockall_sim_m7() imxrt_periphclk_configure(CCM_CCGR_SIM_M7, CCM_CG_ALL) +#define imxrt_clockall_sim_main() imxrt_periphclk_configure(CCM_CCGR_SIM_MAIN, CCM_CG_ALL) +#define imxrt_clockall_sim_per() imxrt_periphclk_configure(CCM_CCGR_SIM_PER, CCM_CG_ALL) +#define imxrt_clockall_snvs_hp() imxrt_periphclk_configure(CCM_CCGR_SNVS_HP, CCM_CG_ALL) +#define imxrt_clockall_snvs_lp() imxrt_periphclk_configure(CCM_CCGR_SNVS_LP, CCM_CG_ALL) +#define imxrt_clockall_spdif() imxrt_periphclk_configure(CCM_CCGR_SPDIF, CCM_CG_ALL) +#define imxrt_clockall_timer1() imxrt_periphclk_configure(CCM_CCGR_TIMER1, CCM_CG_ALL) +#define imxrt_clockall_timer2() imxrt_periphclk_configure(CCM_CCGR_TIMER2, CCM_CG_ALL) +#define imxrt_clockall_timer3() imxrt_periphclk_configure(CCM_CCGR_TIMER3, CCM_CG_ALL) +#define imxrt_clockall_timer4() imxrt_periphclk_configure(CCM_CCGR_TIMER4, CCM_CG_ALL) +#define imxrt_clockall_trace() imxrt_periphclk_configure(CCM_CCGR_TRACE, CCM_CG_ALL) +#define imxrt_clockall_trng() imxrt_periphclk_configure(CCM_CCGR_TRNG, CCM_CG_ALL) +#define imxrt_clockall_tsc_dig() imxrt_periphclk_configure(CCM_CCGR_TSC_DIG, CCM_CG_ALL) +#define imxrt_clockall_usboh3() imxrt_periphclk_configure(CCM_CCGR_USBOH3, CCM_CG_ALL) +#define imxrt_clockall_usdhc1() imxrt_periphclk_configure(CCM_CCGR_USDHC1, CCM_CG_ALL) +#define imxrt_clockall_usdhc2() imxrt_periphclk_configure(CCM_CCGR_USDHC2, CCM_CG_ALL) +#define imxrt_clockall_wdog1() imxrt_periphclk_configure(CCM_CCGR_WDOG1, CCM_CG_ALL) +#define imxrt_clockall_wdog2() imxrt_periphclk_configure(CCM_CCGR_WDOG2, CCM_CG_ALL) +#define imxrt_clockall_wdog3() imxrt_periphclk_configure(CCM_CCGR_WDOG3, CCM_CG_ALL) +#define imxrt_clockall_xbar1() imxrt_periphclk_configure(CCM_CCGR_XBAR1, CCM_CG_ALL) +#define imxrt_clockall_xbar2() imxrt_periphclk_configure(CCM_CCGR_XBAR2, CCM_CG_ALL) +#define imxrt_clockall_xbar3() imxrt_periphclk_configure(CCM_CCGR_XBAR3, CCM_CG_ALL) + +/******************************************************************************************** + * Public Functions + *********************************************************************************************/ + +/******************************************************************************************** + * Name: imxrt_periphclk_configure + * + * Description: + * Configure a peripheral clock by modifying the appropriate field in the + * appropriate CCRGR register. + * + * Input Parameters: + * regaddr - The CCMD CCGR register to be modified + * index - The index of the field to be modified + * value - The new value of the field + * + * Returned Value: + * None + * + *********************************************************************************************/ + +void imxrt_periphclk_configure(uintptr_t regaddr, unsigned int index, + unsigned int value); + +#endif /* __ARCH_ARM_SRC_IMXRT_IMXRT_PERIPHCLKS_H */ diff --git a/configs/stm32f4discovery/README.txt b/configs/stm32f4discovery/README.txt index 526108ce15f..40f30e13162 100644 --- a/configs/stm32f4discovery/README.txt +++ b/configs/stm32f4discovery/README.txt @@ -1193,8 +1193,8 @@ Configuration Sub-directories This configuration is a variant of the NSH configuration used for demonstrating PCM audio using the CS43L22 stereo DAC/amplifier on board - the STM32F4 Discovery and the STM32 I2S DMA interface. In uses the - file player at apps/system/nxplayer. + the STM32F4 Discovery and the STM32 I2S DMA interface. It uses the + file player at apps/system/nxplayer. The serial console is on USART2. The original CS43L22 and STM32 I2S drivers were contribued by Taras Drozdovsky in May of 2017. The audio configuration was contributed by