From 0f1eef72feae79d1fabe33ea32387f654d2cce07 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 15 May 2015 09:30:25 -0600 Subject: [PATCH] SAML21: Flesh out SAML21 memory map --- arch/arm/src/samdl/chip/samd20_memorymap.h | 4 +- arch/arm/src/samdl/chip/saml21_memorymap.h | 57 ++++++++++++++++++++-- 2 files changed, 56 insertions(+), 5 deletions(-) diff --git a/arch/arm/src/samdl/chip/samd20_memorymap.h b/arch/arm/src/samdl/chip/samd20_memorymap.h index 9de006f1caa..99f8271ad50 100644 --- a/arch/arm/src/samdl/chip/samd20_memorymap.h +++ b/arch/arm/src/samdl/chip/samd20_memorymap.h @@ -75,7 +75,7 @@ #define SAM_PAC0_BASE 0x40000000 /* Peripheral Access Controller 0 */ #define SAM_PM_BASE 0x40000400 /* Power Manager */ #define SAM_SYSCTRL_BASE 0x40000800 /* System Controller */ -#define SAM_GCLK_BASE 0x40000C00 /* Generic Clock Controller */ +#define SAM_GCLK_BASE 0x40000c00 /* Generic Clock Controller */ #define SAM_WDT_BASE 0x40001000 /* Watchdog Timer */ #define SAM_RTC_BASE 0x40001400 /* Real-Time Counter */ #define SAM_EIC_BASE 0x40001800 /* External Interrupt Controller */ @@ -108,7 +108,7 @@ #define SAM_ADC_BASE 0x42004000 /* Analog-to-Digital Converter */ #define SAM_AC_BASE 0x42004400 /* Analog Comparator*/ #define SAM_DAC_BASE 0x42004800 /* Digital-to-Analog Converter */ -#define SAM_PTC_BASE 0x42004C00 /* Peripheral Touch Controller */ +#define SAM_PTC_BASE 0x42004c00 /* Peripheral Touch Controller */ /******************************************************************************************** * Public Types diff --git a/arch/arm/src/samdl/chip/saml21_memorymap.h b/arch/arm/src/samdl/chip/saml21_memorymap.h index 901f7086ee4..51d2b16e91a 100644 --- a/arch/arm/src/samdl/chip/saml21_memorymap.h +++ b/arch/arm/src/samdl/chip/saml21_memorymap.h @@ -53,18 +53,69 @@ ********************************************************************************************/ /* System Memory Map */ - -/* Calibration and Auxiliary Space */ - +#define SAM_FLASH_BASE 0x00000000 /* Embedded FLASH memory space (<= 256KB) */ +#define SAM_FLASHRWW_BASE 0x00400000 /* Embedded FLASH RWW memory space (<= 8KB) */ +#define SAM_SRAM_BASE 0x20000000 /* Embedded SRAM memory space (<= 32KB) */ +#define SAM_LPSRAM_BASE 0x30000000 /* Embedded low-power SRAM memory space (<= 8KB) */ +#define SAM_AHBA_BASE 0x40000000 /* AHB-APB Bridge A (64KB) */ +#define SAM_AHBB_BASE 0x41000000 /* AHB-APB Bridge B (64KB) */ +#define SAM_AHBC_BASE 0x42000000 /* AHB-APB Bridge C (64KB) */ +#define SAM_AHBD_BASE 0x43000000 /* AHB-APB Bridge D (64KB) */ +#define SAM_AHBE_BASE 0x44000000 /* AHB-APB Bridge D (64KB) */ +#define SAM_IOBUS_BASE 0x60000000 /* IOBUS (O.5KB) */ /* AHB-APB Bridge A */ +#define SAM_PM_BASE 0x40000000 /* Power Management */ +#define SAM_MCLK_BASE 0x40000400 /* Main Clock */ +#define SAM_OSCCTRL_BASE 0x40000c00 /* Oscillators Controller */ +#define SAM_OSC32KCTRL_BASE 0x40001000 /* 32KHz Oscillators Controller */ +#define SAM_SUPC_BASE 0x40001400 /* Supply Controller */ +#define SAM_GCLK_BASE 0x40001800 /* Generic Clock Controller */ +#define SAM_WDT_BASE 0x40001c00 /* Watchdog Timer */ +#define SAM_RTC_BASE 0x40002000 /* Real-Time Counter */ +#define SAM_EIC_BASE 0x40002400 /* External Interrupt Controller */ +#define SAM_PORT_BASE 0x40002800 /* Ports */ /* AHB-APB Bridge B */ +#define SAM_USB_BASE 0x41000000 /* Universal Serial Bus */ +#define SAM_DSU_BASE 0x41002000 /* Device Service Unit */ +#define SAM_NVMCTRL_BASE 0x41004000 /* Non-Volatile Memory Controller */ +#define SAM_MTD_BASE 0x41006000 /* ??? */ /* AHB-APB Bridge C */ +#define SAM_SERCOM0_BASE 0x42000000 /* Serial Communication Interface 0 */ +#define SAM_SERCOM1_BASE 0x42000400 /* Serial Communication Interface 1 */ +#define SAM_SERCOM2_BASE 0x42000800 /* Serial Communication Interface 2 */ +#define SAM_SERCOM3_BASE 0x42000c00 /* Serial Communication Interface 3 */ +#define SAM_SERCOM4_BASE 0x42001000 /* Serial Communication Interface 4 */ +#define SAM_TCC0_BASE 0x42001400 /* Timer/Counter Control 0 */ +#define SAM_TCC1_BASE 0x42001800 /* Timer/Counter Control 1 */ +#define SAM_TCC2_BASE 0x42001c00 /* Timer/Counter Control 2 */ +#define SAM_TC0_BASE 0x42002000 /* Timer/Counter 0 */ +#define SAM_TC1_BASE 0x42002400 /* Timer/Counter 1 */ +#define SAM_TC2_BASE 0x42002800 /* Timer/Counter 2 */ +#define SAM_TC3_BASE 0x42002c00 /* Timer/Counter 3 */ +#define SAM_DAC_BASE 0x42003000 /* Digital-to-Analog Converter */ +#define SAM_AES_BASE 0x42003400 /* Advanced Encryption Standard */ +#define SAM_TRNG_BASE 0x42003800 /* True Random Number Generator */ + +/* AHB-APB Bridge D */ + +#define SAM_SERCOM5_BASE 0x43000400 /* Serial Communication Interface 5 */ +#define SAM_TC4_BASE 0x43000800 /* Timer/Counter 4 */ +#define SAM_ADC_BASE 0x43000c00 /* Analog-to-Digital Converter */ +#define SAM_AC_BASE 0x43001000 /* Analog Comparator */ +#define SAM_PTC_BASE 0x43001400 /* Peripheral Touch Controller */ +#define SAM_OPAMP_BASE 0x43001800 /* OpAmps */ +#define SAM_CCL_BASE 0x43001c00 /* Configurable Custom Logic */ + +/* AHB-APB Bridge E */ + +#define SAM_PAC_BASE 0x44000000 /* Peripheral Access Controller */ +#define SAM_DMAC_BASE 0x44000400 /* DMA Controller */ /******************************************************************************************** * Public Types