diff --git a/Documentation/platforms/risc-v/esp32c6/boards/esp32c6-devkitc/index.rst b/Documentation/platforms/risc-v/esp32c6/boards/esp32c6-devkitc/index.rst
index e9309ce10bb..fa5363ad3c6 100644
--- a/Documentation/platforms/risc-v/esp32c6/boards/esp32c6-devkitc/index.rst
+++ b/Documentation/platforms/risc-v/esp32c6/boards/esp32c6-devkitc/index.rst
@@ -154,6 +154,13 @@ You can scan for all I2C devices using the following command::
 
     nsh> i2c dev 0x00 0x7f
 
+mcuboot_nsh
+--------------------
+
+This configuration is the same as the ``nsh`` configuration, but it generates the application
+image in a format that can be used by MCUboot. It also makes the ``make bootloader`` command to
+build the MCUboot bootloader image using the Espressif HAL.
+
 nsh
 ---
 
diff --git a/Documentation/platforms/risc-v/esp32c6/boards/esp32c6-devkitm/index.rst b/Documentation/platforms/risc-v/esp32c6/boards/esp32c6-devkitm/index.rst
index d07b0709592..1a71ac55664 100644
--- a/Documentation/platforms/risc-v/esp32c6/boards/esp32c6-devkitm/index.rst
+++ b/Documentation/platforms/risc-v/esp32c6/boards/esp32c6-devkitm/index.rst
@@ -138,6 +138,13 @@ You can scan for all I2C devices using the following command::
 
     nsh> i2c dev 0x00 0x7f
 
+mcuboot_nsh
+--------------------
+
+This configuration is the same as the ``nsh`` configuration, but it generates the application
+image in a format that can be used by MCUboot. It also makes the ``make bootloader`` command to
+build the MCUboot bootloader image using the Espressif HAL.
+
 nsh
 ---
 
diff --git a/Documentation/platforms/risc-v/esp32c6/index.rst b/Documentation/platforms/risc-v/esp32c6/index.rst
index b4dc9b5ca95..9642de6fcc5 100644
--- a/Documentation/platforms/risc-v/esp32c6/index.rst
+++ b/Documentation/platforms/risc-v/esp32c6/index.rst
@@ -82,6 +82,24 @@ require any specific configuration (it is selectable by default if no other
 of 2nd stage bootloaders, the commands ``make bootloader`` and the ``ESPTOOL_BINDIR``
 option (for the ``make flash``) are kept (and ignored if Simple Boot is used).
 
+If other features are required, an externally-built 2nd stage bootloader is needed.
+The bootloader is built using the ``make bootloader`` command. This command generates
+the firmware in the ``nuttx`` folder. The ``ESPTOOL_BINDIR`` is used in the
+``make flash`` command to specify the path to the bootloader. For compatibility
+among other SoCs and future options of 2nd stage bootloaders, the commands
+``make bootloader`` and the ``ESPTOOL_BINDIR`` option (for the ``make flash``)
+can be used even if no externally-built 2nd stage bootloader
+is being built (they will be ignored if Simple Boot is used, for instance)::
+
+  $ make bootloader
+
+.. note:: It is recommended that if this is the first time you are using the board with NuttX to
+   perform a complete SPI FLASH erase.
+
+    .. code-block:: console
+
+      $ esptool.py erase_flash
+
 Building and flashing
 ---------------------
 
diff --git a/arch/risc-v/src/common/espressif/Kconfig b/arch/risc-v/src/common/espressif/Kconfig
index 36dab91aad8..355766e36c8 100644
--- a/arch/risc-v/src/common/espressif/Kconfig
+++ b/arch/risc-v/src/common/espressif/Kconfig
@@ -164,14 +164,14 @@ config ESPRESSIF_SIMPLE_BOOT
 config ESPRESSIF_BOOTLOADER_MCUBOOT
 	bool "Enable MCUboot-bootable format"
 	select ESPRESSIF_HAVE_OTA_PARTITION
-	depends on ESPRESSIF_ESP32C3
+	depends on !ESPRESSIF_ESP32H2
 	---help---
 		Enables the Espressif port of MCUboot to be used as 2nd stage bootloader.
 
 config ESPRESSIF_MCUBOOT_VERSION
 	string "MCUboot version"
 	depends on ESPRESSIF_BOOTLOADER_MCUBOOT
-	default "aa7e2b1faae623dbe01bbc6094e71ab44ec9d80a"
+	default "9c99326b9756dbcc35b524636d99ed5f3e6cb29b"
 
 choice ESPRESSIF_ESPTOOL_TARGET_SLOT
 	prompt "Target slot for image flashing"
diff --git a/boards/risc-v/esp32c6/common/scripts/esp32c6_flat_memory.ld b/boards/risc-v/esp32c6/common/scripts/esp32c6_flat_memory.ld
index 9660b328216..db28c6ed220 100644
--- a/boards/risc-v/esp32c6/common/scripts/esp32c6_flat_memory.ld
+++ b/boards/risc-v/esp32c6/common/scripts/esp32c6_flat_memory.ld
@@ -50,9 +50,32 @@
 
 #define DRAM0_0_SEG_LEN       I_D_SRAM_SIZE
 
+#ifdef CONFIG_ESPRESSIF_FLASH_2M
+#  define FLASH_SIZE        0x200000
+#elif defined (CONFIG_ESPRESSIF_FLASH_4M)
+#  define FLASH_SIZE        0x400000
+#elif defined (CONFIG_ESPRESSIF_FLASH_8M)
+#  define FLASH_SIZE        0x800000
+#elif defined (CONFIG_ESPRESSIF_FLASH_16M)
+#  define FLASH_SIZE        0x1000000
+#endif
+
 MEMORY
 {
-#ifdef CONFIG_ESPRESSIF_SIMPLE_BOOT
+#ifdef CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT
+  /* The origin values for "metadata" and "ROM" memory regions are the actual
+   * load addresses.
+   *
+   * NOTE: The memory region starting from 0x0 with length represented by
+   * CONFIG_ESPRESSIF_APP_MCUBOOT_HEADER_SIZE is reserved for the MCUboot header,
+   * which will be prepended to the binary file by the "imgtool" during the
+   * signing of firmware image.
+   */
+
+  metadata (RX) :        org = CONFIG_ESPRESSIF_APP_MCUBOOT_HEADER_SIZE, len = 0x20
+  ROM (RX) :             org = ORIGIN(metadata) + LENGTH(metadata),
+                         len = FLASH_SIZE - ORIGIN(ROM)
+#elif defined (CONFIG_ESPRESSIF_SIMPLE_BOOT)
   ROM (R) :              org = ORIGIN(ROM),
                          len = IDRAM0_2_SEG_SIZE
 #endif
@@ -65,9 +88,12 @@ MEMORY
 
   iram0_0_seg (RX) :      org = SRAM_IRAM_ORG, len = I_D_SRAM_SIZE
 
-  /* Flash mapped instruction data.
-   *
-   * The 0x20 offset is a convenience for the app binary image generation.
+  /* Flash mapped instruction data. */
+
+#ifdef CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT
+  irom_seg    (RX) :      org = 0x42000000, len = FLASH_SIZE /* IDRAM0_2_SEG_SIZE */
+#else
+  /* The 0x20 offset is a convenience for the app binary image generation.
    * Flash cache has 64KB pages. The .bin file which is flashed to the chip
    * has a 0x18 byte file header, and each segment has a 0x08 byte segment
    * header. Setting this offset makes it simple to meet the flash cache MMU's
@@ -75,6 +101,7 @@ MEMORY
    */
 
   irom_seg    (RX) :      org = 0x42000000, len = IDRAM0_2_SEG_SIZE
+#endif
 
   /* Shared data RAM, excluding memory reserved for ROM bss/data/stack.
    * Enabling Bluetooth & Trace Memory features in menuconfig will decrease
@@ -83,9 +110,26 @@ MEMORY
 
   dram0_0_seg (RW) :      org = SRAM_DRAM_ORG, len = DRAM0_0_SEG_LEN
 
-  /* Flash mapped constant data.
-   *
-   * The 0x20 offset is a convenience for the app binary image generation.
+  /* Flash mapped constant data. */
+
+#ifdef CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT
+  /* The DROM segment origin is offset by 0x40 for mirroring the actual ROM
+   * image layout:
+   *    0x0  - 0x1F : MCUboot header
+   *    0x20 - 0x3F : Application image metadata section
+   *    0x40 onwards: ROM code and data
+   * This is required to meet the following constraint from the external
+   * flash MMU:
+   *    VMA % 64KB == LMA % 64KB
+   * i.e. the lower 16 bits of both the virtual address (address seen by the
+   * CPU) and the load address (physical address of the external flash) must
+   * be equal.
+   */
+
+  drom_seg    (R) :      org = 0x42000000 + ORIGIN(ROM),
+                         len = FLASH_SIZE - ORIGIN(ROM)
+#else
+  /* The 0x20 offset is a convenience for the app binary image generation.
    * Flash cache has 64KB pages. The .bin file which is flashed to the chip
    * has a 0x18 byte file header, and each segment has a 0x08 byte segment
    * header. Setting this offset makes it simple to meet the flash cache MMU's
@@ -93,6 +137,7 @@ MEMORY
    */
 
   drom_seg    (R) :       org = 0x42000000, len = IDRAM0_2_SEG_SIZE
+#endif
 
   /* RTC fast memory (executable). Persists over deep sleep. */
 
diff --git a/boards/risc-v/esp32c6/common/scripts/esp32c6_simple_boot_sections.ld b/boards/risc-v/esp32c6/common/scripts/esp32c6_sections.ld
similarity index 91%
rename from boards/risc-v/esp32c6/common/scripts/esp32c6_simple_boot_sections.ld
rename to boards/risc-v/esp32c6/common/scripts/esp32c6_sections.ld
index 4b6f5aa1c82..f928e009a61 100644
--- a/boards/risc-v/esp32c6/common/scripts/esp32c6_simple_boot_sections.ld
+++ b/boards/risc-v/esp32c6/common/scripts/esp32c6_sections.ld
@@ -1,5 +1,5 @@
 /****************************************************************************
- * boards/risc-v/esp32c6/common/scripts/esp32c6_simple_boot_sections.ld
+ * boards/risc-v/esp32c6/common/scripts/esp32c6_sections.ld
  *
  * Licensed to the Apache Software Foundation (ASF) under one or more
  * contributor license agreements.  See the NOTICE file distributed with
@@ -18,12 +18,47 @@
  *
  ****************************************************************************/
 
+#include "common.ld"
+
 /* Default entry point: */
 
 ENTRY(__start);
 
 SECTIONS
 {
+#ifdef CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT
+  .metadata :
+  {
+    /* Magic for load header */
+
+    LONG(0xace637d3)
+
+    /* Application entry point address */
+
+    KEEP(*(.entry_addr))
+
+    /* IRAM metadata:
+     * - Destination address (VMA) for IRAM region
+     * - Flash offset (LMA) for start of IRAM region
+     * - Size of IRAM region
+     */
+
+    LONG(ADDR(.iram0.text))
+    LONG(LOADADDR(.iram0.text))
+    LONG(SIZEOF(.iram0.text))
+
+    /* DRAM metadata:
+     * - Destination address (VMA) for DRAM region
+     * - Flash offset (LMA) for start of DRAM region
+     * - Size of DRAM region
+     */
+
+    LONG(ADDR(.dram0.data))
+    LONG(LOADADDR(.dram0.data))
+    LONG(SIZEOF(.dram0.data))
+  } >metadata
+#endif
+
   .iram0.text :
   {
     _iram_start = ABSOLUTE(.);
@@ -35,6 +70,7 @@ SECTIONS
 
     *(.iram1)
     *(.iram1.*)
+#ifdef CONFIG_ESPRESSIF_SIMPLE_BOOT
     *libsched.a:irq_dispatch.*(.text .text.* .literal .literal.*)
 
     *libarch.a:*brownout.*(.text .text.* .literal .literal.*)
@@ -98,6 +134,12 @@ SECTIONS
     *libarch.a:*log.*(.text .text.* .literal .literal.*)
     *libarch.a:*log_noos.*(.text .text.* .literal .literal.*)
     *libarch.a:esp_spiflash.*(.literal .text .literal.* .text.*)
+#else
+    *libarch.a:*cache_hal.*(.text .text.* .literal .literal.*)
+    *libarch.a:*mpu_hal.*(.text .text.* .literal .literal.*)
+    *libarch.a:*mmu_hal.*(.text .text.* .literal .literal.*)
+    *libarch.a:esp_spiflash.*(.literal .text .literal.* .text.*)
+#endif
 
     esp_head.*(.literal .text .literal.* .text.*)
     esp_start.*(.literal .text .literal.* .text.*)
@@ -147,7 +189,7 @@ SECTIONS
     /* This section contains data that is not initialized during load,
      * or during the application's initialization sequence.
      */
-
+    . = ALIGN(8);
     *(.noinit)
     *(.noinit.*)
   } >dram0_0_seg
@@ -171,6 +213,7 @@ SECTIONS
     *(.jcr)
     *(.dram1)
     *(.dram1.*)
+#ifdef CONFIG_ESPRESSIF_SIMPLE_BOOT
     *libsched.a:irq_dispatch.*(.rodata .rodata.*)
 
     *libarch.a:*brownout.*(.rodata .rodata.*)
@@ -234,6 +277,12 @@ SECTIONS
     *libarch.a:*log.*(.rodata .rodata.*)
     *libarch.a:*log_noos.*(.rodata .rodata.*)
     *libarch.a:esp_spiflash.*(.rodata .rodata.*)
+#else
+    *libarch.a:*cache_hal.*(.rodata .rodata.*)
+    *libarch.a:*mpu_hal.*(.rodata .rodata.*)
+    *libarch.a:*mmu_hal.*(.rodata .rodata.*)
+    *libarch.a:esp_spiflash.*(.rodata .rodata.*)
+#endif
 
     esp_head.*(.rodata .rodata.*)
     esp_start.*(.rodata .rodata.*)
@@ -279,7 +328,7 @@ SECTIONS
     . = ALIGN(0x10000);
     } > ROM
 
-  .flash.text :
+  .flash.text : ALIGN(0xFFFF)
   {
     _stext = .;
     _instruction_reserved_start = ABSOLUTE(.);  /* This is a symbol marking the flash.text start, this can be used for mmu driver to maintain virtual address */
@@ -324,7 +373,7 @@ SECTIONS
     . = ALIGN(ALIGNOF(.flash.rodata));
   } >default_rodata_seg
 
-  .flash.rodata :
+  .flash.rodata : ALIGN(0xFFFF)
   {
     _srodata = ABSOLUTE(.);
 
diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/mcuboot_nsh/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/mcuboot_nsh/defconfig
new file mode 100644
index 00000000000..5468e359942
--- /dev/null
+++ b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/mcuboot_nsh/defconfig
@@ -0,0 +1,49 @@
+#
+# This file is autogenerated: PLEASE DO NOT EDIT IT.
+#
+# You can use "make menuconfig" to make any modifications to the installed .config file.
+# You can then do "make savedefconfig" to generate a new defconfig file that includes your
+# modifications.
+#
+# CONFIG_NSH_ARGCAT is not set
+# CONFIG_NSH_CMDOPT_HEXDUMP is not set
+CONFIG_ARCH="risc-v"
+CONFIG_ARCH_BOARD="esp32c6-devkitc"
+CONFIG_ARCH_BOARD_COMMON=y
+CONFIG_ARCH_BOARD_ESP32C6_DEVKITC=y
+CONFIG_ARCH_CHIP="esp32c6"
+CONFIG_ARCH_CHIP_ESP32C6=y
+CONFIG_ARCH_CHIP_ESP32C6WROOM1=y
+CONFIG_ARCH_INTERRUPTSTACK=2048
+CONFIG_ARCH_RISCV=y
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_BOARDCTL_RESET=y
+CONFIG_BOARD_LOOPSPERMSEC=15000
+CONFIG_BUILTIN=y
+CONFIG_DEV_ZERO=y
+CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT=y
+CONFIG_ESPRESSIF_ESP32C6=y
+CONFIG_FS_PROCFS=y
+CONFIG_IDLETHREAD_STACKSIZE=2048
+CONFIG_INIT_ENTRYPOINT="nsh_main"
+CONFIG_INTELHEX_BINARY=y
+CONFIG_LIBC_PERROR_STDOUT=y
+CONFIG_LIBC_STRERROR=y
+CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6
+CONFIG_NSH_ARCHINIT=y
+CONFIG_NSH_BUILTIN_APPS=y
+CONFIG_NSH_FILEIOSIZE=512
+CONFIG_NSH_READLINE=y
+CONFIG_NSH_STRERROR=y
+CONFIG_PREALLOC_TIMERS=0
+CONFIG_RR_INTERVAL=200
+CONFIG_SCHED_BACKTRACE=y
+CONFIG_SCHED_WAITPID=y
+CONFIG_START_DAY=29
+CONFIG_START_MONTH=11
+CONFIG_START_YEAR=2019
+CONFIG_SYSTEM_DUMPSTACK=y
+CONFIG_SYSTEM_NSH=y
+CONFIG_TESTING_GETPRIME=y
+CONFIG_TESTING_OSTEST=y
+CONFIG_UART0_SERIAL_CONSOLE=y
diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/scripts/Make.defs b/boards/risc-v/esp32c6/esp32c6-devkitc/scripts/Make.defs
index 0402a2c36f2..6fc1bcc91c0 100644
--- a/boards/risc-v/esp32c6/esp32c6-devkitc/scripts/Make.defs
+++ b/boards/risc-v/esp32c6/esp32c6-devkitc/scripts/Make.defs
@@ -34,7 +34,9 @@ ARCHSCRIPT += $(BOARD_COMMON_DIR)/scripts/$(CHIP_SERIES)_aliases.ld
 ARCHSCRIPT += $(call FINDSCRIPT,$(CHIP_SERIES)_flat_memory.ld)
 
 ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y)
-  ARCHSCRIPT += $(call FINDSCRIPT,$(CHIP_SERIES)_simple_boot_sections.ld)
+  ARCHSCRIPT += $(call FINDSCRIPT,$(CHIP_SERIES)_sections.ld)
+else ifeq ($(CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT),y)
+  ARCHSCRIPT += $(call FINDSCRIPT,$(CHIP_SERIES)_sections.ld)
 else
   ARCHSCRIPT += $(call FINDSCRIPT,$(CHIP_SERIES)_legacy_sections.ld)
 endif
diff --git a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/mcuboot_nsh/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/mcuboot_nsh/defconfig
new file mode 100644
index 00000000000..2bc41aec38c
--- /dev/null
+++ b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/mcuboot_nsh/defconfig
@@ -0,0 +1,49 @@
+#
+# This file is autogenerated: PLEASE DO NOT EDIT IT.
+#
+# You can use "make menuconfig" to make any modifications to the installed .config file.
+# You can then do "make savedefconfig" to generate a new defconfig file that includes your
+# modifications.
+#
+# CONFIG_NSH_ARGCAT is not set
+# CONFIG_NSH_CMDOPT_HEXDUMP is not set
+CONFIG_ARCH="risc-v"
+CONFIG_ARCH_BOARD="esp32c6-devkitm"
+CONFIG_ARCH_BOARD_COMMON=y
+CONFIG_ARCH_BOARD_ESP32C6_DEVKITM=y
+CONFIG_ARCH_CHIP="esp32c6"
+CONFIG_ARCH_CHIP_ESP32C6=y
+CONFIG_ARCH_CHIP_ESP32C6MINI1=y
+CONFIG_ARCH_INTERRUPTSTACK=2048
+CONFIG_ARCH_RISCV=y
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_BOARDCTL_RESET=y
+CONFIG_BOARD_LOOPSPERMSEC=15000
+CONFIG_BUILTIN=y
+CONFIG_DEV_ZERO=y
+CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT=y
+CONFIG_ESPRESSIF_ESP32C6=y
+CONFIG_FS_PROCFS=y
+CONFIG_IDLETHREAD_STACKSIZE=2048
+CONFIG_INIT_ENTRYPOINT="nsh_main"
+CONFIG_INTELHEX_BINARY=y
+CONFIG_LIBC_PERROR_STDOUT=y
+CONFIG_LIBC_STRERROR=y
+CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6
+CONFIG_NSH_ARCHINIT=y
+CONFIG_NSH_BUILTIN_APPS=y
+CONFIG_NSH_FILEIOSIZE=512
+CONFIG_NSH_READLINE=y
+CONFIG_NSH_STRERROR=y
+CONFIG_PREALLOC_TIMERS=0
+CONFIG_RR_INTERVAL=200
+CONFIG_SCHED_BACKTRACE=y
+CONFIG_SCHED_WAITPID=y
+CONFIG_START_DAY=29
+CONFIG_START_MONTH=11
+CONFIG_START_YEAR=2019
+CONFIG_SYSTEM_DUMPSTACK=y
+CONFIG_SYSTEM_NSH=y
+CONFIG_TESTING_GETPRIME=y
+CONFIG_TESTING_OSTEST=y
+CONFIG_UART0_SERIAL_CONSOLE=y
diff --git a/boards/risc-v/esp32c6/esp32c6-devkitm/scripts/Make.defs b/boards/risc-v/esp32c6/esp32c6-devkitm/scripts/Make.defs
index c8c8cea774c..eaf2bfdb7f6 100644
--- a/boards/risc-v/esp32c6/esp32c6-devkitm/scripts/Make.defs
+++ b/boards/risc-v/esp32c6/esp32c6-devkitm/scripts/Make.defs
@@ -33,8 +33,10 @@ CHIP_SERIES = $(patsubst "%",%,$(CONFIG_ESPRESSIF_CHIP_SERIES))
 ARCHSCRIPT += $(BOARD_COMMON_DIR)/scripts/$(CHIP_SERIES)_aliases.ld
 ARCHSCRIPT += $(call FINDSCRIPT,$(CHIP_SERIES)_flat_memory.ld)
 
-ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y)
-  ARCHSCRIPT += $(call FINDSCRIPT,$(CHIP_SERIES)_simple_boot_sections.ld)
+ifeq ($(CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT),y)
+  ARCHSCRIPT += $(call FINDSCRIPT,$(CHIP_SERIES)_sections.ld)
+else ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y)
+  ARCHSCRIPT += $(call FINDSCRIPT,$(CHIP_SERIES)_sections.ld)
 else
   ARCHSCRIPT += $(call FINDSCRIPT,$(CHIP_SERIES)_legacy_sections.ld)
 endif
diff --git a/tools/esp32c6/Config.mk b/tools/esp32c6/Config.mk
deleted file mode 100644
index 181d90a6e86..00000000000
--- a/tools/esp32c6/Config.mk
+++ /dev/null
@@ -1,77 +0,0 @@
-############################################################################
-# tools/esp32c6/Config.mk
-#
-# Licensed to the Apache Software Foundation (ASF) under one or more
-# contributor license agreements.  See the NOTICE file distributed with
-# this work for additional information regarding copyright ownership.  The
-# ASF licenses this file to you under the Apache License, Version 2.0 (the
-# "License"); you may not use this file except in compliance with the
-# License.  You may obtain a copy of the License at
-#
-#   http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
-# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
-# License for the specific language governing permissions and limitations
-# under the License.
-#
-############################################################################
-
-# These are the macros that will be used in the NuttX make system to compile
-# and assemble source files and to insert the resulting object files into an
-# archive.  These replace the default definitions at tools/Config.mk
-
-ifdef ESPTOOL_BINDIR
-	BL_OFFSET=0x0
-	PT_OFFSET=0x8000
-	BOOTLOADER=$(ESPTOOL_BINDIR)/bootloader.bin
-	PARTITION_TABLE=$(ESPTOOL_BINDIR)/partition-table.bin
-	FLASH_BL=$(BL_OFFSET) $(BOOTLOADER)
-	FLASH_PT=$(PT_OFFSET) $(PARTITION_TABLE)
-endif
-
-ifeq ($(CONFIG_ESP32C6_FLASH_2M),y)
-	FLASH_SIZE="2MB"
-else ifeq ($(CONFIG_ESP32C6_FLASH_4M),y)
-	FLASH_SIZE="4MB"
-else ifeq ($(CONFIG_ESP32C6_FLASH_8M),y)
-	FLASH_SIZE="8MB"
-else ifeq ($(CONFIG_ESP32C6_FLASH_16M),y)
-	FLASH_SIZE="16MB"
-endif
-
-# POSTBUILD -- Perform post build operations
-
-define POSTBUILD
-	$(Q) echo "MKIMAGE: ESP32-C6 binary"
-	$(Q) if ! esptool.py version 1>/dev/null 2>&1; then \
-		echo ""; \
-		echo "esptool.py not found.  Please run: \"pip install esptool==4.8.dev4\""; \
-		echo "Or run: \"make -C $(TOPDIR)/tools/esp32c6\" to install all IDF tools."; \
-		echo ""; \
-		echo "Run make again to create the nuttx.bin image."; \
-		exit 1; \
-	fi
-	$(Q) if [ -z $(FLASH_SIZE) ]; then \
-		echo "Missing Flash memory size configuration for the ESP32-C6 chip."; \
-		exit 1; \
-	fi
-	esptool.py --chip esp32c6 elf2image --flash_mode dio --flash_size $(FLASH_SIZE) -o nuttx.bin nuttx
-	$(Q) echo "Generated: nuttx.bin (ESP32-C6 compatible)"
-endef
-
-# ESPTOOL_BAUD -- Serial port baud rate used when flashing/reading via esptool.py
-
-ESPTOOL_BAUD ?= 921600
-
-# DOWNLOAD -- Download binary image via esptool.py
-
-define DOWNLOAD
-	$(Q) if [ -z $(ESPTOOL_PORT) ]; then \
-		echo "DOWNLOAD error: Missing serial port device argument."; \
-		echo "USAGE: make download ESPTOOL_PORT=<port> [ ESPTOOL_BAUD=<baud> ]"; \
-		exit 1; \
-	fi
-	esptool.py --chip esp32c6 --port $(ESPTOOL_PORT) --baud $(ESPTOOL_BAUD) write_flash $(FLASH_BL) $(FLASH_PT) 0x10000 $(1).bin
-endef