diff --git a/arch/arm/src/armv8-m/arm_initialstate.c b/arch/arm/src/armv8-m/arm_initialstate.c
index bb92eb19693..89e6101475a 100644
--- a/arch/arm/src/armv8-m/arm_initialstate.c
+++ b/arch/arm/src/armv8-m/arm_initialstate.c
@@ -155,7 +155,7 @@ void up_initial_state(struct tcb_s *tcb)
 
 #if !defined(CONFIG_ARMV8M_LAZYFPU) && defined(CONFIG_ARCH_FPU)
 
-  xcp->regs[REG_FPSCR] = 0;      /* REVISIT: Initial FPSCR should be configurable */
+  xcp->regs[REG_FPSCR] |= ARMV8M_FPSCR_LTPSIZE_NONE;
   xcp->regs[REG_FP_RESERVED] = 0;
 
 #endif /* !CONFIG_ARMV8M_LAZYFPU && CONFIG_ARCH_FPU */
diff --git a/arch/arm/src/armv8-m/psr.h b/arch/arm/src/armv8-m/psr.h
index f97890ef46c..8944bf12b52 100644
--- a/arch/arm/src/armv8-m/psr.h
+++ b/arch/arm/src/armv8-m/psr.h
@@ -89,11 +89,12 @@
 #define ARMV8M_FPSCR_IDC           (1 << 7)  /* Bit 7: Input Denormal */
 
 #define ARMV8M_FPSCR_LTPSIZE_SHIFT 16        /* Bits 16-18: Vector element size */
-#define ARMV8M_FPSCR_LTPSIZE_8BIT  (0x0 << ARMV8M_FPSCR_RM_SHIFT)
-#define ARMV8M_FPSCR_LTPSIZE_16BIT (0x1 << ARMV8M_FPSCR_RM_SHIFT)
-#define ARMV8M_FPSCR_LTPSIZE_32BIT (0x2 << ARMV8M_FPSCR_RM_SHIFT)
-#define ARMV8M_FPSCR_LTPSIZE_DONE  (0x3 << ARMV8M_FPSCR_RM_SHIFT)
-#define ARMV8M_FPSCR_LTPSIZE_MASK  (0x7 << ARMV8M_FPSCR_RM_SHIFT)
+#define ARMV8M_FPSCR_LTPSIZE_8BIT  (0x0 << ARMV8M_FPSCR_LTPSIZE_SHIFT)
+#define ARMV8M_FPSCR_LTPSIZE_16BIT (0x1 << ARMV8M_FPSCR_LTPSIZE_SHIFT)
+#define ARMV8M_FPSCR_LTPSIZE_32BIT (0x2 << ARMV8M_FPSCR_LTPSIZE_SHIFT)
+#define ARMV8M_FPSCR_LTPSIZE_64BIT (0x3 << ARMV8M_FPSCR_LTPSIZE_SHIFT)
+#define ARMV8M_FPSCR_LTPSIZE_NONE  (0x4 << ARMV8M_FPSCR_LTPSIZE_SHIFT)
+#define ARMV8M_FPSCR_LTPSIZE_MASK  (0x7 << ARMV8M_FPSCR_LTPSIZE_SHIFT)
 
 #define ARMV8M_FPSCR_FZ16          (1 << 19) /* Bit 19: Flush-to-zero mode(half-precision) */