diff --git a/ChangeLog b/ChangeLog
index 06eba68671d..8f3cefa8ffc 100755
--- a/ChangeLog
+++ b/ChangeLog
@@ -12295,3 +12295,83 @@
Matthias Renner (2016-07-08).
* drivers/pipe: Add missing configuration for pipe ring buffer size.
From Frank Benkert (2016-07-08).
+ * STM32L4: Fix incorrect clock setup for LPTIM1. From ziggurat29
+ (2016-07-08).
+ * nucleo-l476rg and stm32lf76vg-disco: Define timer clock frequencies on
+ STM32L4-based boards. From ziggurat29 (2016-07-08).
+ * STM32L4: Add support for tickless OS, and incidentally timers, pwm,
+ oneshot, free-running.... From ziggurat29 (2016-07-08).
+ * SAM3/4 I2C: Fix reversed logic in twi_startmessage(). From Wolfgang
+ Reissnegger (2016-07-09).
+ * VFS ioctl(). Per comments from David Sidrane, file_ioctl() should not
+ return succeed if the ioctl method is not supported. It probably
+ should return ENOTTY in that case (2016-07-09).
+ * libm: This change should significantly improve the performance of
+ single precision floating point math library functions. The vast
+ majority of changes have to do with preventing the compiler from
+ needlessly promoting floats to doubles, performing the calculation
+ with doubles, only to demote the result to float. These changes only
+ affect the math lib functions that return float. From David Alessio
+ (2016-07-11).
+ * STM32F4 Discovery: Add FPU support for ostest for the STM32F4Discovery
+ platform. From David Alessio (2016-07-11).
+ * Build system: Remove the includes/apps link to apps/include. It is
+ no longer used. From Sebastien Lorquet (2016-07-11).
+ * printf(): If there are no streams, let printf() fall back to use
+ syslog() for output (2016-07-11).
+ * Qemu-i486: Fix qemu-i486/ostest/Make.defs test for M32. From Heath
+ Petersen (2016-07-12).
+ * UART 16550: Handle when CONFIG_SERIAL_UART_ARCH_IOCTL is not enabled.
+ From Heath Petersen (2016-07-12).
+ * Kinetis Ethernet: Add support for the KSZ8081 PHY (2016-07-12).
+ * SST26 Driver: Before accessing the sst26 flash, the "Global Unlock"
+ command must me executed, which I do in the sst26 driver. BUT re-
+ reading the datasheet, the WREN instruction is required to enable the
+ execution of this command. This was not done. I have no idea how the
+ driver currently works except by chance. The writes should never
+ happen at all, the flash is half-enabled! From Sebastien Lorquet
+ (2016-07-12).
+ * Freedom K64F: Add a networking NSH configuration. (2016-07-12).
+ * N25Qxx Driver: Alter the notion of 'blocksize' to be equivalent to
+ 'flash write page size' in order to align with assumptions in the
+ smartfs driver (at least, maybe other things do as well). Correct a
+ bug that was previously masked by having blocksize=eraseblocksize
+ which would cause buffer overflows and delicious hardfaults. Trivial
+ spelling changes in comments, etc. From ziggurat29 (2016-07-12).
+ * STM32L476 Discovery: Update stm32l476 disco to include init code for
+ smartfs and nxffs for cases where those fs are included in build.
+ From ziggurat29 (2016-07-12).
+ * Kinetis Ethernet and Freedom-K64F: Freedcom-K64F PHY address was
+ wrong. Modified Ethernet driver to try all PHY addresses and then
+ only fail if the driver cannot find a usable PHY address. MDIO pin
+ must have an internal pull-up on the Freedom-K64F (2016-07-12).
+ * Kinetis Ethernet: Add support for CONFIG_NET_NOINTS (2016-07-12).
+ * SmartFS: Fix a 32-byte memory leak. From Ken Pettit (2016-07-12).
+ * Freedom-K64F: SDHC is now enabled in the nsh configuration (but does
+ not work)Add hooks for automounter; Change NSH configuration to use
+ Windows (2016-07-13).
+ * SAMV7 USBHS Device: This change solves a problem which causes data
+ loss while sending data via USB. This problem is caused by an incorrect
+ handling of the endpoint state in the USB driver sam_usbdevhs. This
+ leads under some circumstances to situations in which an DMA transfer
+ is setup while a previous DMA transfer is currently active. Amongst
+ other things I introduced the new endpoint state USBHS_EPSTATE_SENDING_DMA
+ for the fix. To reproduce the problem, I used a program which send as
+ many data as possible via a CDC/ACM device and verified the received
+ data on the PC. From Stefan Kolb (2016-07-13).
+ * STM32: Fix bug in oneshot timer. From Max Neklyudov (2016-07-13).
+ * STM32L4: Port foward bugfix from stm32 of oneshot timer. From
+ ziggurat29 (2016-07-13).
+ * STM32 and EFM32: I'm using syslog through ITM. In this case
+ syslog_channel function is call before RAM initialisation in
+ stm32_clockconfig. But syslog channel uses a global variable that is
+ reset to default by the RAM initialization. From Pierre-noel
+ Bouteville (2016-07-14).
+ * LPC43xx SPIFI: If CONFIG_SPIFI_SECTOR512 undefined, lpc43_bwrite
+ doesn't do actual write (probably copy/paste errors). Still not sure
+ about current state of lpc43_spifi implementation, but for me NXFFS
+ works with this patch. From Vytautas Lukenskas (2016-07-14).
+ * SMART MTD layer: Fixes freesector logic error when sectorsPerBlk=256,
+ adds DEBUGASSERT for invalid geometry and additional memory debug
+ logic. Also fixes the dangling pointer on error bug. From Ken
+ Pettit (2016-07-14).
diff --git a/Documentation/NuttShell.html b/Documentation/NuttShell.html
index 90e0764a791..7af455d577e 100644
--- a/Documentation/NuttShell.html
+++ b/Documentation/NuttShell.html
@@ -8,7 +8,7 @@
NuttShell (NSH)
- Last Updated: February 8, 2016
+ Last Updated: July 20, 2016
|
@@ -3277,7 +3277,7 @@ nsh>
mkfifo |
- CONFIG_NFILE_DESCRIPTORS > 0 |
+ CONFIG_NFILE_DESCRIPTORS > 0 && CONFIG_PIPES |
CONFIG_NSH_DISABLE_MKFIFO |
diff --git a/Documentation/NuttxPortingGuide.html b/Documentation/NuttxPortingGuide.html
index d36ca6f2104..bf32596fef0 100644
--- a/Documentation/NuttxPortingGuide.html
+++ b/Documentation/NuttxPortingGuide.html
@@ -4439,7 +4439,7 @@ void board_autoled_off(int led);
- Interface Definition.
- The header file for the NuttX PWM driver reside at
include/nuttx/pwm.h.
+ The header file for the NuttX PWM driver reside at include/nuttx/drivers/pwm.h.
This header file includes both the application level interface to the PWM driver as well as the interface between the "upper half" and "lower half" drivers.
The PWM module uses a standard character driver framework.
However, since the PWM driver is a devices control interface and not a data transfer interface,
@@ -4472,7 +4472,7 @@ void board_autoled_off(int led);
- Interface Definition.
- The header file for the NuttX CAN driver reside at
include/nuttx/can.h.
+ The header file for the NuttX CAN driver resides at include/nuttx/drivers/can.h.
This header file includes both the application level interface to the CAN driver as well as the interface between the "upper half" and "lower half" drivers.
The CAN module uses a standard character driver framework.
diff --git a/Kconfig b/Kconfig
index c174c16e4cb..31f6f54629c 100644
--- a/Kconfig
+++ b/Kconfig
@@ -339,10 +339,10 @@ config ARCH_MATH_H
default n
---help---
There is also a re-directing version of math.h in the source tree.
- However, it resides out-of-the-way at include/nuttx/math.h because it
+ However, it resides out-of-the-way at include/nuttx/lib/math.h because it
conflicts too often with the system math.h. If ARCH_MATH_H=y is
defined, however, the top-level makefile will copy the redirecting
- math.h header file from include/nuttx/math.h to include/math.h. math.h
+ math.h header file from include/nuttx/lib/math.h to include/math.h. math.h
will then include the architecture-specific version of math.h that you
must provide at nuttx/arch/>architecture/include/stdarg.h
If ARCH_STDARG_H=y is defined, the top-level makefile will copy the
- re-directing stdarg.h header file from include/nuttx/stdarg.h to
+ re-directing stdarg.h header file from include/nuttx/lib/stdarg.h to
include/stdarg.h. So for the architectures that cannot use their
toolchain's stdarg.h file, they can use this alternative by defining
ARCH_STDARG_H=y and providing. If ARCH_STDARG_H, is not defined, then
diff --git a/Makefile.unix b/Makefile.unix
index a117f171fc1..bb249788974 100644
--- a/Makefile.unix
+++ b/Makefile.unix
@@ -183,16 +183,16 @@ BIN = nuttx$(EXEEXT)
all: $(BIN)
.PHONY: context clean_context check_context export subdir_clean clean subdir_distclean distclean apps_clean apps_distclean
-# Target used to copy include/nuttx/math.h. If CONFIG_ARCH_MATH_H is
+# Target used to copy include/nuttx/lib/math.h. If CONFIG_ARCH_MATH_H is
# defined, then there is an architecture specific math.h header file
# that will be included indirectly from include/math.h. But first, we
# have to copy math.h from include/nuttx/. to include/. Logic within
-# include/nuttx/math.h will hand the redirection to the architecture-
+# include/nuttx/lib/math.h will hand the redirection to the architecture-
# specific math.h header file.
#
# If the CONFIG_LIBM is defined, the Rhombus libm will be built at libc/math.
# Definitions and prototypes for the Rhombus libm are also contained in
-# include/nuttx/math.h and so the file must also be copied in that case.
+# include/nuttx/lib/math.h and so the file must also be copied in that case.
#
# If neither CONFIG_ARCH_MATH_H nor CONFIG_LIBM is defined, then no math.h
# header file will be provided. You would want that behavior if (1) you
@@ -208,8 +208,8 @@ endif
endif
ifeq ($(NEED_MATH_H),y)
-include/math.h: include/nuttx/math.h
- $(Q) cp -f include/nuttx/math.h include/math.h
+include/math.h: include/nuttx/lib/math.h
+ $(Q) cp -f include/nuttx/lib/math.h include/math.h
else
include/math.h:
endif
@@ -221,20 +221,20 @@ endif
# the settings in this float.h are actually correct for your platform!
ifeq ($(CONFIG_ARCH_FLOAT_H),y)
-include/float.h: include/nuttx/float.h
- $(Q) cp -f include/nuttx/float.h include/float.h
+include/float.h: include/nuttx/lib/float.h
+ $(Q) cp -f include/nuttx/lib/float.h include/float.h
else
include/float.h:
endif
-# Target used to copy include/nuttx/stdarg.h. If CONFIG_ARCH_STDARG_H is
+# Target used to copy include/nuttx/lib/stdarg.h. If CONFIG_ARCH_STDARG_H is
# defined, then there is an architecture specific stdarg.h header file
-# that will be included indirectly from include/stdarg.h. But first, we
+# that will be included indirectly from include/lib/stdarg.h. But first, we
# have to copy stdarg.h from include/nuttx/. to include/.
ifeq ($(CONFIG_ARCH_STDARG_H),y)
-include/stdarg.h: include/nuttx/stdarg.h
- $(Q) cp -f include/nuttx/stdarg.h include/stdarg.h
+include/stdarg.h: include/nuttx/lib/stdarg.h
+ $(Q) cp -f include/nuttx/lib/stdarg.h include/stdarg.h
else
include/stdarg.h:
endif
diff --git a/README.txt b/README.txt
index 4c12dca85ac..8991f5d870a 100644
--- a/README.txt
+++ b/README.txt
@@ -321,13 +321,13 @@ Notes about Header Files
If you have a custom, architecture specific math.h header file, then
that header file should be placed at arch//include/math.h. There
- is a stub math.h header file located at include/nuttx/math.h. This stub
+ is a stub math.h header file located at include/nuttx/lib/math.h. This stub
header file can be used to "redirect" the inclusion to an architecture-
specific math.h header file. If you add an architecture specific math.h
header file then you should also define CONFIG_ARCH_MATH_H=y in your
NuttX Configuration file. If CONFIG_ARCH_MATH_H is selected, then the
top-level Makefile will copy the stub math.h header file from
- include/nuttx/math.h to include/math.h where it will become the system
+ include/nuttx/lib/math.h to include/math.h where it will become the system
math.h header file. The stub math.h header file does nothing other
than to include that architecture-specific math.h header file as the
system math.h header file.
diff --git a/TODO b/TODO
index bbc8f7657ac..9d3309122dc 100644
--- a/TODO
+++ b/TODO
@@ -1,4 +1,4 @@
-NuttX TODO List (Last updated July 3, 2016)
+NuttX TODO List (Last updated July 20, 2016)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
This file summarizes known NuttX bugs, limitations, inconsistencies with
@@ -447,6 +447,7 @@ o Kernel/Protected Build
mkfatfs mkfatfs
mkrd ramdisk_register()
ping icmp_ping()
+ mount foreach_mountpoint()
The busybox mkfatfs does not involve any OS calls; it does
its job by simply opening the block driver (using open/xopen)
@@ -1399,6 +1400,15 @@ o File system / Generic drivers (fs/, drivers/)
socket structures. There really should be one array that
is a union of file and socket descriptors. Then socket and
file descriptors could lie in the same range.
+
+ Another example of how the current implementation limits
+ functionality: I recently started an implement of the FILEMAX
+ (using pctl() instead sysctl()). My objective was to be able
+ to control the number of available file descriptors on a task-
+ by-task basis. The complexity due to the partitioning of
+ desciptor space in a range for file descriptors and a range
+ for socket descriptors made this feature nearly impossible to
+ implement.
Status: Open
Priority: Low
diff --git a/arch/arm/include/lpc17xx/lpc176x_irq.h b/arch/arm/include/lpc17xx/lpc176x_irq.h
index 248c5c47d66..b844b33d652 100644
--- a/arch/arm/include/lpc17xx/lpc176x_irq.h
+++ b/arch/arm/include/lpc17xx/lpc176x_irq.h
@@ -147,7 +147,7 @@
* 42
*/
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC17_GPIOIRQ
# define LPC17_VALID_GPIOINT0 (0x7fff8ffful) /* GPIO port 0 interrupt set */
# define LPC17_VALID_GPIOINT2 (0x00003ffful) /* GPIO port 2 interrupt set */
diff --git a/arch/arm/include/lpc17xx/lpc178x_irq.h b/arch/arm/include/lpc17xx/lpc178x_irq.h
index 76c74904528..52ed1731a5c 100644
--- a/arch/arm/include/lpc17xx/lpc178x_irq.h
+++ b/arch/arm/include/lpc17xx/lpc178x_irq.h
@@ -166,7 +166,7 @@
* 42
*/
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC17_GPIOIRQ
# define LPC17_VALID_GPIOINT0 (0xfffffffful) /* GPIO port 0 interrupt set */
# define LPC17_VALID_GPIOINT2 (0xfffffffful) /* GPIO port 2 interrupt set */
diff --git a/arch/arm/include/samdl/samd20_irq.h b/arch/arm/include/samdl/samd20_irq.h
index 01361e8e00e..709fddaeac8 100644
--- a/arch/arm/include/samdl/samd20_irq.h
+++ b/arch/arm/include/samdl/samd20_irq.h
@@ -81,7 +81,7 @@
/* GPIO interrupts. Up to 16 pins may be configured to support interrupts */
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_SAMDL_GPIOIRQ
# define SAM_IRQ_EXTINT0 (SAM_IRQ_NIRQS+0) /* External interrupt 0 */
# define SAM_IRQ_EXTINT1 (SAM_IRQ_NIRQS+1) /* External interrupt 1 */
# define SAM_IRQ_EXTINT2 (SAM_IRQ_NIRQS+2) /* External interrupt 2 */
diff --git a/arch/arm/include/samdl/samd21_irq.h b/arch/arm/include/samdl/samd21_irq.h
index 2ea4db82579..7b5c633ef62 100644
--- a/arch/arm/include/samdl/samd21_irq.h
+++ b/arch/arm/include/samdl/samd21_irq.h
@@ -88,7 +88,7 @@
/* GPIO interrupts. Up to 16 pins may be configured to support interrupts */
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_SAMDL_GPIOIRQ
# define SAM_IRQ_EXTINT0 (SAM_IRQ_NIRQS+0) /* External interrupt 0 */
# define SAM_IRQ_EXTINT1 (SAM_IRQ_NIRQS+1) /* External interrupt 1 */
# define SAM_IRQ_EXTINT2 (SAM_IRQ_NIRQS+2) /* External interrupt 2 */
diff --git a/arch/arm/include/samdl/saml21_irq.h b/arch/arm/include/samdl/saml21_irq.h
index 9622a032152..24c774dbd0f 100644
--- a/arch/arm/include/samdl/saml21_irq.h
+++ b/arch/arm/include/samdl/saml21_irq.h
@@ -89,7 +89,7 @@
/* GPIO interrupts. Up to 16 pins may be configured to support interrupts */
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_SAMDL_GPIOIRQ
# define SAM_IRQ_EXTINT0 (SAM_IRQ_NIRQS+0) /* External interrupt 0 */
# define SAM_IRQ_EXTINT1 (SAM_IRQ_NIRQS+1) /* External interrupt 1 */
# define SAM_IRQ_EXTINT2 (SAM_IRQ_NIRQS+2) /* External interrupt 2 */
diff --git a/arch/arm/src/armv7-r/arm_doirq.c b/arch/arm/src/armv7-r/arm_doirq.c
index fdf392d3384..5d492f5ddc7 100644
--- a/arch/arm/src/armv7-r/arm_doirq.c
+++ b/arch/arm/src/armv7-r/arm_doirq.c
@@ -52,22 +52,6 @@
#include "group/group.h"
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
/****************************************************************************
* Public Functions
****************************************************************************/
diff --git a/arch/arm/src/common/up_initialize.c b/arch/arm/src/common/up_initialize.c
index 6b5117adf1b..a97cd40a92e 100644
--- a/arch/arm/src/common/up_initialize.c
+++ b/arch/arm/src/common/up_initialize.c
@@ -44,14 +44,16 @@
#include
#include
#include
-#include
+#include
#include
#include
#include
#include
#include
#include
+#include
#include
+#include
#include
@@ -158,21 +160,21 @@ void up_initialize(void)
up_irqinitialize();
+#ifdef CONFIG_PM
/* Initialize the power management subsystem. This MCU-specific function
* must be called *very* early in the initialization sequence *before* any
* other device drivers are initialized (since they may attempt to register
* with the power management subsystem).
*/
-#ifdef CONFIG_PM
up_pminitialize();
#endif
+#ifdef CONFIG_ARCH_DMA
/* Initialize the DMA subsystem if the weak function up_dmainitialize has been
* brought into the build
*/
-#ifdef CONFIG_ARCH_DMA
#ifdef CONFIG_HAVE_WEAKFUNCTIONS
if (up_dmainitialize)
#endif
@@ -196,6 +198,14 @@ void up_initialize(void)
devnull_register(); /* Standard /dev/null */
#endif
+#if defined(CONFIG_DEV_RANDOM)
+ devrandom_register(); /* Standard /dev/random */
+#endif
+
+#if defined(CONFIG_DEV_URANDOM)
+ devurandom_register(); /* Standard /dev/urandom */
+#endif
+
#if defined(CONFIG_DEV_ZERO)
devzero_register(); /* Standard /dev/zero */
#endif
@@ -228,22 +238,10 @@ void up_initialize(void)
ramlog_consoleinit();
#endif
- /* Initialize the HW crypto and /dev/crypto */
+#if CONFIG_NFILE_DESCRIPTORS > 0 && defined(CONFIG_PSEUDOTERM_SUSV1)
+ /* Register the master pseudo-terminal multiplexor device */
-#if defined(CONFIG_CRYPTO)
- up_cryptoinitialize();
-#endif
-
-#if CONFIG_NFILE_DESCRIPTORS > 0
-#if defined(CONFIG_CRYPTO_CRYPTODEV)
- devcrypto_register();
-#endif
-#endif
-
- /* Initialize the Random Number Generator (RNG) */
-
-#ifdef CONFIG_DEV_RANDOM
- up_rnginitialize();
+ (void)ptmx_register();
#endif
/* Early initialization of the system logging device. Some SYSLOG channel
@@ -253,6 +251,16 @@ void up_initialize(void)
syslog_initialize(SYSLOG_INIT_EARLY);
+#if defined(CONFIG_CRYPTO)
+ /* Initialize the HW crypto and /dev/crypto */
+
+ up_cryptoinitialize();
+#endif
+
+#if CONFIG_NFILE_DESCRIPTORS > 0 && defined(CONFIG_CRYPTO_CRYPTODEV)
+ devcrypto_register();
+#endif
+
#ifndef CONFIG_NETDEV_LATEINIT
/* Initialize the network */
diff --git a/arch/arm/src/common/up_internal.h b/arch/arm/src/common/up_internal.h
index feec4333558..36095a87a45 100644
--- a/arch/arm/src/common/up_internal.h
+++ b/arch/arm/src/common/up_internal.h
@@ -545,12 +545,6 @@ void up_usbuninitialize(void);
# define up_usbuninitialize()
#endif
-/* Random Number Generator (RNG) ********************************************/
-
-#ifdef CONFIG_DEV_RANDOM
-void up_rnginitialize(void);
-#endif
-
/* Debug ********************************************************************/
#ifdef CONFIG_STACK_COLORATION
void up_stack_color(FAR void *stackbase, size_t nbytes);
diff --git a/arch/arm/src/efm32/efm32_clockconfig.c b/arch/arm/src/efm32/efm32_clockconfig.c
index 5ecdf03c12f..aeef784326b 100644
--- a/arch/arm/src/efm32/efm32_clockconfig.c
+++ b/arch/arm/src/efm32/efm32_clockconfig.c
@@ -909,9 +909,6 @@ static inline void efm32_itm_syslog(void)
efm32_enable_auxhfrco();
- /* Then perform ARMv7-M ITM SYSLOG initialization */
-
- itm_syslog_initialize();
}
#else
# define efm32_itm_syslog()
diff --git a/arch/arm/src/efm32/efm32_irq.c b/arch/arm/src/efm32/efm32_irq.c
index 63a82b194ca..db5992dea7b 100644
--- a/arch/arm/src/efm32/efm32_irq.c
+++ b/arch/arm/src/efm32/efm32_irq.c
@@ -93,10 +93,6 @@ volatile uint32_t *g_current_regs[1];
extern uint32_t _vectors[];
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
/****************************************************************************
* Private Functions
****************************************************************************/
@@ -261,15 +257,9 @@ static int efm32_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
{
if (irq < NR_VECTORS)
{
- n = irq - EFM32_IRQ_INTERRUPTS;
+ n = irq - EFM32_IRQ_INTERRUPTS;
*regaddr = NVIC_IRQ_ENABLE(n) + offset;
-
- while (n >= 32)
- {
- n -= 32;
- }
-
- *bit = 1 << n;
+ *bit = (uint32_t)1 << (n & 0x1f);
}
else
{
diff --git a/arch/arm/src/efm32/efm32_pwm.c b/arch/arm/src/efm32/efm32_pwm.c
index b34d8aeb2ff..f07a3eed4b7 100644
--- a/arch/arm/src/efm32/efm32_pwm.c
+++ b/arch/arm/src/efm32/efm32_pwm.c
@@ -47,7 +47,7 @@
#include
#include
-#include
+#include
#include
#include "up_arch.h"
diff --git a/arch/arm/src/efm32/efm32_pwm.h b/arch/arm/src/efm32/efm32_pwm.h
index af46c3b6f8b..61e4f5f116d 100644
--- a/arch/arm/src/efm32/efm32_pwm.h
+++ b/arch/arm/src/efm32/efm32_pwm.h
@@ -39,7 +39,7 @@
/* The EFM32 does not have dedicated PWM hardware. Rather, pulsed output
* control is a capability of the EFM32 timers. The logic in this file
* implements the lower half of the standard, NuttX PWM interface using the
- * EFM32 timers. That interface is described in include/nuttx/pwm.h.
+ * EFM32 timers. That interface is described in include/nuttx/drivers/pwm.h.
*/
/****************************************************************************
diff --git a/arch/arm/src/efm32/efm32_start.c b/arch/arm/src/efm32/efm32_start.c
index f62e1461d51..59c45afaa32 100644
--- a/arch/arm/src/efm32/efm32_start.c
+++ b/arch/arm/src/efm32/efm32_start.c
@@ -275,6 +275,12 @@ void __start(void)
showprogress('C');
+#ifdef CONFIG_ARMV7M_ITMSYSLOG
+ /* Perform ARMv7-M ITM SYSLOG initialization */
+
+ itm_syslog_initialize();
+#endif
+
/* Perform early serial initialization */
up_earlyserialinit();
diff --git a/arch/arm/src/kinetis/Kconfig b/arch/arm/src/kinetis/Kconfig
index 6a0c0367657..853de44c7db 100644
--- a/arch/arm/src/kinetis/Kconfig
+++ b/arch/arm/src/kinetis/Kconfig
@@ -483,12 +483,12 @@ config KINETIS_FTM2_CHANNEL
menu "Kinetis GPIO Interrupt Configuration"
-config GPIO_IRQ
+config KINETIS_GPIOIRQ
bool "GPIO pin interrupts"
---help---
Enable support for interrupting GPIO pins
-if GPIO_IRQ
+if KINETIS_GPIOIRQ
config KINETIS_PORTAINTS
bool "GPIOA interrupts"
@@ -615,13 +615,6 @@ config KINETIS_SD4BIT_FREQ
Frequency to use for transferring data to/from an SD card using all four data lines.
endif
-
-config KINETIS_SDHC_DMAPRIO
- int "SDHC DMA priority"
- depends on SDIO_DMA
- ---help---
- SDHC DMA priority
-
endmenu # Kinetis SDHC Configuration
menu "Kinetis UART Configuration"
diff --git a/arch/arm/src/kinetis/Make.defs b/arch/arm/src/kinetis/Make.defs
index 662dd618737..9d4ea5083ab 100644
--- a/arch/arm/src/kinetis/Make.defs
+++ b/arch/arm/src/kinetis/Make.defs
@@ -103,7 +103,7 @@ ifeq ($(CONFIG_BUILD_PROTECTED),y)
CHIP_CSRCS += kinetis_userspace.c kinetis_mpuinit.c
endif
-ifeq ($(CONFIG_GPIO_IRQ),y)
+ifeq ($(CONFIG_KINETIS_GPIOIRQ),y)
CHIP_CSRCS += kinetis_pinirq.c
endif
diff --git a/arch/arm/src/kinetis/chip/kinetis_k60memorymap.h b/arch/arm/src/kinetis/chip/kinetis_k60memorymap.h
index 8b00303ef7b..135da475536 100644
--- a/arch/arm/src/kinetis/chip/kinetis_k60memorymap.h
+++ b/arch/arm/src/kinetis/chip/kinetis_k60memorymap.h
@@ -44,7 +44,7 @@
#include "chip.h"
-#ifdef KINETIS_K64
+#ifdef KINETIS_K60
/************************************************************************************
* Pre-processor Definitions
@@ -192,5 +192,5 @@
* Public Functions
************************************************************************************/
-#endif /* KINETIS_K64 */
+#endif /* KINETIS_K60 */
#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K60MEMORYMAP_H */
diff --git a/arch/arm/src/kinetis/kinetis.h b/arch/arm/src/kinetis/kinetis.h
index fccd4b90af7..bb02f01e92c 100644
--- a/arch/arm/src/kinetis/kinetis.h
+++ b/arch/arm/src/kinetis/kinetis.h
@@ -476,7 +476,7 @@ bool kinetis_gpioread(uint32_t pinset);
*
************************************************************************************/
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_KINETIS_GPIOIRQ
void kinetis_pinirqinitialize(void);
#else
# define kinetis_pinirqinitialize()
@@ -514,7 +514,7 @@ xcpt_t kinetis_pinirqattach(uint32_t pinset, xcpt_t pinisr);
*
************************************************************************************/
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_KINETIS_GPIOIRQ
void kinetis_pinirqenable(uint32_t pinset);
#else
# define kinetis_pinirqenable(pinset)
@@ -528,7 +528,7 @@ void kinetis_pinirqenable(uint32_t pinset);
*
************************************************************************************/
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_KINETIS_GPIOIRQ
void kinetis_pinirqdisable(uint32_t pinset);
#else
# define kinetis_pinirqdisable(pinset)
diff --git a/arch/arm/src/kinetis/kinetis_clockconfig.c b/arch/arm/src/kinetis/kinetis_clockconfig.c
index 2f703ea96e7..7d3d6ecb22a 100644
--- a/arch/arm/src/kinetis/kinetis_clockconfig.c
+++ b/arch/arm/src/kinetis/kinetis_clockconfig.c
@@ -39,8 +39,6 @@
#include
-#include
-
#include "up_arch.h"
#include "kinetis.h"
@@ -50,6 +48,8 @@
#include "chip/kinetis_llwu.h"
#include "chip/kinetis_pinmux.h"
+#include
+
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
diff --git a/arch/arm/src/kinetis/kinetis_enet.c b/arch/arm/src/kinetis/kinetis_enet.c
index 6c30bac4158..dc0be25e164 100644
--- a/arch/arm/src/kinetis/kinetis_enet.c
+++ b/arch/arm/src/kinetis/kinetis_enet.c
@@ -1840,7 +1840,7 @@ static inline int kinetis_initphy(struct kinetis_driver_s *priv)
phydata = 0xffff;
ret = kinetis_readmii(priv, phyaddr, MII_PHYID1, &phydata);
}
- while (ret >= 0 && phydata == 0xffff && ++retries < 3);
+ while ((ret < 0 || phydata == 0xffff) && ++retries < 3);
/* If we successfully read anything then break out, using this PHY address */
diff --git a/arch/arm/src/kinetis/kinetis_irq.c b/arch/arm/src/kinetis/kinetis_irq.c
index d2a04de3ae6..a969bbacd7a 100644
--- a/arch/arm/src/kinetis/kinetis_irq.c
+++ b/arch/arm/src/kinetis/kinetis_irq.c
@@ -439,7 +439,7 @@ void up_irqinitialize(void)
* configured pin interrupts.
*/
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_KINETIS_GPIOIRQ
kinetis_pinirqinitialize();
#endif
diff --git a/arch/arm/src/kinetis/kinetis_pinirq.c b/arch/arm/src/kinetis/kinetis_pinirq.c
index 919d51e67c9..cc5933e715a 100644
--- a/arch/arm/src/kinetis/kinetis_pinirq.c
+++ b/arch/arm/src/kinetis/kinetis_pinirq.c
@@ -52,7 +52,7 @@
#include "kinetis.h"
#include "chip/kinetis_port.h"
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_KINETIS_GPIOIRQ
/****************************************************************************
* Pre-processor Definitions
@@ -450,4 +450,4 @@ void kinetis_pinirqdisable(uint32_t pinset)
}
#endif /* HAVE_PORTINTS */
}
-#endif /* CONFIG_GPIO_IRQ */
+#endif /* CONFIG_KINETIS_GPIOIRQ */
diff --git a/arch/arm/src/kinetis/kinetis_pwm.c b/arch/arm/src/kinetis/kinetis_pwm.c
index 19de382634e..d4ccc74090c 100644
--- a/arch/arm/src/kinetis/kinetis_pwm.c
+++ b/arch/arm/src/kinetis/kinetis_pwm.c
@@ -49,7 +49,7 @@
#include
#include
-#include
+#include
#include
#include "up_internal.h"
diff --git a/arch/arm/src/kinetis/kinetis_sdhc.c b/arch/arm/src/kinetis/kinetis_sdhc.c
index afc85f59892..0f1197b6e7b 100644
--- a/arch/arm/src/kinetis/kinetis_sdhc.c
+++ b/arch/arm/src/kinetis/kinetis_sdhc.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/kinetis/kinetis_sdhc.c
*
- * Copyright (C) 2011-2012, 2014 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2011-2012, 2014, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -85,10 +85,6 @@
# define CONFIG_KINETIS_SDHC_PRIO NVIC_SYSH_PRIORITY_DEFAULT
#endif
-#ifndef CONFIG_KINETIS_SDHC_DMAPRIO
-# define CONFIG_KINETIS_SDHC_DMAPRIO DMA_CCR_PRIMED
-#endif
-
#ifndef CONFIG_DEBUG_MEMCARD_INFO
# undef CONFIG_SDIO_XFRDEBUG
#endif
diff --git a/arch/arm/src/kinetis/kinetis_usbdev.c b/arch/arm/src/kinetis/kinetis_usbdev.c
index d8d9512cabf..231fc014303 100644
--- a/arch/arm/src/kinetis/kinetis_usbdev.c
+++ b/arch/arm/src/kinetis/kinetis_usbdev.c
@@ -2738,7 +2738,7 @@ static int khci_interrupt(int irq, void *context)
#ifdef CONFIG_USBOTG
/* Session Request Protocol (SRP) Time Out Check */
- /* if USB OTG SRP is ready */
+ /* Check if USB OTG SRP is ready */
# warning "Missing logic"
{
/* Check if the 1 millisecond timer has expired */
@@ -2960,6 +2960,8 @@ x
}
}
+ UNUSED(otgir); /* May not be used, depending on above conditional logic */
+
/* Clear the pending USB interrupt. Goto is used in the above to assure
* that all interrupt exists pass through this logic.
*/
diff --git a/arch/arm/src/kl/Kconfig b/arch/arm/src/kl/Kconfig
index bfa40491538..7dd13a686b9 100644
--- a/arch/arm/src/kl/Kconfig
+++ b/arch/arm/src/kl/Kconfig
@@ -345,12 +345,12 @@ config KL_TPM2_CHANNEL
comment "Kinetis GPIO Interrupt Configuration"
-config GPIO_IRQ
+config KL_GPIOIRQ
bool "GPIO pin interrupts"
---help---
Enable support for interrupting GPIO pins
-if GPIO_IRQ
+if KL_GPIOIRQ
config KL_PORTAINTS
bool "GPIOA interrupts"
diff --git a/arch/arm/src/kl/Make.defs b/arch/arm/src/kl/Make.defs
index 105d267a73a..d7712f0983c 100644
--- a/arch/arm/src/kl/Make.defs
+++ b/arch/arm/src/kl/Make.defs
@@ -81,7 +81,7 @@ ifeq ($(CONFIG_BUILD_PROTECTED),y)
CHIP_CSRCS += kl_userspace.c
endif
-ifeq ($(CONFIG_GPIO_IRQ),y)
+ifeq ($(CONFIG_KL_GPIOIRQ),y)
CHIP_CSRCS += kl_gpioirq.c
endif
diff --git a/arch/arm/src/kl/kl_gpio.h b/arch/arm/src/kl/kl_gpio.h
index fc2cd7f37e9..0024e676086 100644
--- a/arch/arm/src/kl/kl_gpio.h
+++ b/arch/arm/src/kl/kl_gpio.h
@@ -386,7 +386,7 @@ xcpt_t kl_gpioirqattach(uint32_t pinset, xcpt_t pinisr);
*
************************************************************************************/
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_KL_GPIOIRQ
void kl_gpioirqenable(uint32_t pinset);
#else
# define kl_gpioirqenable(pinset)
@@ -400,7 +400,7 @@ void kl_gpioirqenable(uint32_t pinset);
*
************************************************************************************/
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_KL_GPIOIRQ
void kl_gpioirqdisable(uint32_t pinset);
#else
# define kl_gpioirqdisable(pinset)
diff --git a/arch/arm/src/kl/kl_gpioirq.c b/arch/arm/src/kl/kl_gpioirq.c
index 2b481bce3a2..61331343ccd 100644
--- a/arch/arm/src/kl/kl_gpioirq.c
+++ b/arch/arm/src/kl/kl_gpioirq.c
@@ -51,7 +51,7 @@
#include "chip/kl_port.h"
#include "kl_gpio.h"
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_KL_GPIOIRQ
/****************************************************************************
* Pre-processor Definitions
@@ -396,4 +396,4 @@ void kl_gpioirqdisable(uint32_t pinset)
}
#endif /* HAVE_PORTINTS */
}
-#endif /* CONFIG_GPIO_IRQ */
+#endif /* CONFIG_KL_GPIOIRQ */
diff --git a/arch/arm/src/kl/kl_irq.c b/arch/arm/src/kl/kl_irq.c
index b37f7afe1c9..94628f26bf7 100644
--- a/arch/arm/src/kl/kl_irq.c
+++ b/arch/arm/src/kl/kl_irq.c
@@ -248,7 +248,7 @@ void up_irqinitialize(void)
* configured pin interrupts.
*/
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_KL_GPIOIRQ
kl_gpioirqinitialize();
#endif
diff --git a/arch/arm/src/kl/kl_pwm.c b/arch/arm/src/kl/kl_pwm.c
index 6f3f6e40503..a34aa0f8175 100644
--- a/arch/arm/src/kl/kl_pwm.c
+++ b/arch/arm/src/kl/kl_pwm.c
@@ -48,7 +48,7 @@
#include
#include
-#include
+#include
#include
#include "up_internal.h"
diff --git a/arch/arm/src/lpc11xx/Kconfig b/arch/arm/src/lpc11xx/Kconfig
index 31a9711cf07..33ab254958b 100644
--- a/arch/arm/src/lpc11xx/Kconfig
+++ b/arch/arm/src/lpc11xx/Kconfig
@@ -237,7 +237,7 @@ config CAN_REGDEBUG
endmenu
-config GPIO_IRQ
+config LPC11_GPIOIRQ
bool "GPIO interrupt support"
default n
---help---
diff --git a/arch/arm/src/lpc11xx/Make.defs b/arch/arm/src/lpc11xx/Make.defs
index 041419c2488..a347d99946d 100644
--- a/arch/arm/src/lpc11xx/Make.defs
+++ b/arch/arm/src/lpc11xx/Make.defs
@@ -84,7 +84,7 @@ ifeq ($(CONFIG_BUILD_PROTECTED),y)
CHIP_CSRCS += lpc11_userspace.c
endif
-ifeq ($(CONFIG_GPIO_IRQ),y)
+ifeq ($(CONFIG_LPC11_GPIOIRQ),y)
CHIP_CSRCS += lpc11_gpioint.c
endif
diff --git a/arch/arm/src/lpc11xx/lpc111x_gpio.c b/arch/arm/src/lpc11xx/lpc111x_gpio.c
index 6a0718e11d7..cba1ee71734 100644
--- a/arch/arm/src/lpc11xx/lpc111x_gpio.c
+++ b/arch/arm/src/lpc11xx/lpc111x_gpio.c
@@ -79,7 +79,7 @@
* actually set up to interrupt until the interrupt is enabled.
*/
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC11_GPIOIRQ
uint64_t g_intedge0;
uint64_t g_intedge2;
#endif
@@ -295,7 +295,7 @@ static int lpc11_pullup(lpc11_pinset_t cfgset, unsigned int port,
*
****************************************************************************/
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC11_GPIOIRQ
static void lpc11_setintedge(unsigned int port, unsigned int pin,
unsigned int value)
{
@@ -323,7 +323,7 @@ static void lpc11_setintedge(unsigned int port, unsigned int pin,
*intedge &= ~((uint64_t)3 << shift);
*intedge |= ((uint64_t)value << shift);
}
-#endif /* CONFIG_GPIO_IRQ */
+#endif /* CONFIG_LPC11_GPIOIRQ */
/****************************************************************************
* Name: lpc11_setopendrain
@@ -453,7 +453,7 @@ static inline int lpc11_configinput(lpc11_pinset_t cfgset, unsigned int port,
/* Forget about any falling/rising edge interrupt enabled */
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC11_GPIOIRQ
lpc11_setintedge(port, pin, 0);
#endif
}
@@ -495,7 +495,7 @@ static inline int lpc11_configinterrupt(lpc11_pinset_t cfgset, unsigned int port
/* Then just remember the rising/falling edge interrupt enabled */
DEBUGASSERT(port == 0 || port == 2);
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC11_GPIOIRQ
lpc11_setintedge(port, pin, (cfgset & GPIO_EDGE_MASK) >> GPIO_EDGE_SHIFT);
#endif
return OK;
diff --git a/arch/arm/src/lpc11xx/lpc11_gpio.h b/arch/arm/src/lpc11xx/lpc11_gpio.h
index a0e1c2d8990..f77b748613e 100644
--- a/arch/arm/src/lpc11xx/lpc11_gpio.h
+++ b/arch/arm/src/lpc11xx/lpc11_gpio.h
@@ -88,7 +88,7 @@ extern "C"
* lpc11_gpioint.c, and lpc11_gpiodbg.c
*/
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC11_GPIOIRQ
EXTERN uint64_t g_intedge0;
EXTERN uint64_t g_intedge2;
#endif
@@ -108,7 +108,7 @@ EXTERN const uint32_t g_intbase[GPIO_NPORTS];
*
************************************************************************************/
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC11_GPIOIRQ
void lpc11_gpioirqinitialize(void);
#else
# define lpc11_gpioirqinitialize()
@@ -152,7 +152,7 @@ bool lpc11_gpioread(lpc11_pinset_t pinset);
*
************************************************************************************/
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC11_GPIOIRQ
void lpc11_gpioirqenable(int irq);
#else
# define lpc11_gpioirqenable(irq)
@@ -166,7 +166,7 @@ void lpc11_gpioirqenable(int irq);
*
************************************************************************************/
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC11_GPIOIRQ
void lpc11_gpioirqdisable(int irq);
#else
# define lpc11_gpioirqdisable(irq)
diff --git a/arch/arm/src/lpc11xx/lpc11_gpioint.c b/arch/arm/src/lpc11xx/lpc11_gpioint.c
index 4ce6b48c9ed..8aaefed1497 100644
--- a/arch/arm/src/lpc11xx/lpc11_gpioint.c
+++ b/arch/arm/src/lpc11xx/lpc11_gpioint.c
@@ -51,7 +51,7 @@
#include "chip.h"
#include "lpc11_gpio.h"
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC11_GPIOIRQ
/****************************************************************************
* Pre-processor Definitions
@@ -543,5 +543,5 @@ void lpc11_gpioirqdisable(int irq)
}
}
-#endif /* CONFIG_GPIO_IRQ */
+#endif /* CONFIG_LPC11_GPIOIRQ */
diff --git a/arch/arm/src/lpc11xx/lpc11_irq.c b/arch/arm/src/lpc11xx/lpc11_irq.c
index f861943bc0a..4399c582003 100644
--- a/arch/arm/src/lpc11xx/lpc11_irq.c
+++ b/arch/arm/src/lpc11xx/lpc11_irq.c
@@ -244,7 +244,7 @@ void up_irqinitialize(void)
* configured pin interrupts.
*/
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC11_GPIOIRQ
lpc11_gpioirqinitialize();
#endif
diff --git a/arch/arm/src/lpc11xx/lpc11_timer.c b/arch/arm/src/lpc11xx/lpc11_timer.c
index e742dc2de0b..a9ce65a073a 100644
--- a/arch/arm/src/lpc11xx/lpc11_timer.c
+++ b/arch/arm/src/lpc11xx/lpc11_timer.c
@@ -47,7 +47,7 @@
#include
#include
-#include
+#include
#include
#include "up_internal.h"
diff --git a/arch/arm/src/lpc17xx/Kconfig b/arch/arm/src/lpc17xx/Kconfig
index abfd205fedc..5038000d865 100644
--- a/arch/arm/src/lpc17xx/Kconfig
+++ b/arch/arm/src/lpc17xx/Kconfig
@@ -604,7 +604,7 @@ config LPC17_CAN_REGDEBUG
endmenu
-config GPIO_IRQ
+config LPC17_GPIOIRQ
bool "GPIO interrupt support"
default n
---help---
diff --git a/arch/arm/src/lpc17xx/Make.defs b/arch/arm/src/lpc17xx/Make.defs
index 919f70e7579..f1dd3cde114 100644
--- a/arch/arm/src/lpc17xx/Make.defs
+++ b/arch/arm/src/lpc17xx/Make.defs
@@ -133,7 +133,7 @@ ifeq ($(CONFIG_LPC17_EMC),y)
CHIP_CSRCS += lpc17_emc.c
endif
-ifeq ($(CONFIG_GPIO_IRQ),y)
+ifeq ($(CONFIG_LPC17_GPIOIRQ),y)
CHIP_CSRCS += lpc17_gpioint.c
endif
diff --git a/arch/arm/src/lpc17xx/lpc176x_gpio.c b/arch/arm/src/lpc17xx/lpc176x_gpio.c
index 7de2fd04bcc..b2b8e9805ab 100644
--- a/arch/arm/src/lpc17xx/lpc176x_gpio.c
+++ b/arch/arm/src/lpc17xx/lpc176x_gpio.c
@@ -78,7 +78,7 @@
* actually set up to interrupt until the interrupt is enabled.
*/
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC17_GPIOIRQ
uint64_t g_intedge0;
uint64_t g_intedge2;
#endif
@@ -300,7 +300,7 @@ static int lpc17_pullup(lpc17_pinset_t cfgset, unsigned int port,
*
****************************************************************************/
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC17_GPIOIRQ
static void lpc17_setintedge(unsigned int port, unsigned int pin,
unsigned int value)
{
@@ -328,7 +328,7 @@ static void lpc17_setintedge(unsigned int port, unsigned int pin,
*intedge &= ~((uint64_t)3 << shift);
*intedge |= ((uint64_t)value << shift);
}
-#endif /* CONFIG_GPIO_IRQ */
+#endif /* CONFIG_LPC17_GPIOIRQ */
/****************************************************************************
* Name: lpc17_setopendrain
@@ -412,7 +412,7 @@ static inline int lpc17_configinput(lpc17_pinset_t cfgset, unsigned int port, un
/* Forget about any falling/rising edge interrupt enabled */
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC17_GPIOIRQ
lpc17_setintedge(port, pin, 0);
#endif
}
@@ -453,7 +453,7 @@ static inline int lpc17_configinterrupt(lpc17_pinset_t cfgset, unsigned int port
/* Then just remember the rising/falling edge interrupt enabled */
DEBUGASSERT(port == 0 || port == 2);
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC17_GPIOIRQ
lpc17_setintedge(port, pin, (cfgset & GPIO_EDGE_MASK) >> GPIO_EDGE_SHIFT);
#endif
return OK;
diff --git a/arch/arm/src/lpc17xx/lpc178x_gpio.c b/arch/arm/src/lpc17xx/lpc178x_gpio.c
index a30b7d42558..a6892d597f6 100644
--- a/arch/arm/src/lpc17xx/lpc178x_gpio.c
+++ b/arch/arm/src/lpc17xx/lpc178x_gpio.c
@@ -79,7 +79,7 @@
* actually set up to interrupt until the interrupt is enabled.
*/
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC17_GPIOIRQ
uint64_t g_intedge0;
uint64_t g_intedge2;
#endif
@@ -526,7 +526,7 @@ static void lpc17_setpullup(lpc17_pinset_t cfgset, unsigned int port,
*
****************************************************************************/
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC17_GPIOIRQ
static void lpc17_setintedge(unsigned int port, unsigned int pin,
unsigned int value)
{
@@ -554,7 +554,7 @@ static void lpc17_setintedge(unsigned int port, unsigned int pin,
*intedge &= ~((uint64_t)3 << shift);
*intedge |= ((uint64_t)value << shift);
}
-#endif /* CONFIG_GPIO_IRQ */
+#endif /* CONFIG_LPC17_GPIOIRQ */
/****************************************************************************
* Name: lpc17_configinput
@@ -601,7 +601,7 @@ static inline int lpc17_configinput(lpc17_pinset_t cfgset, unsigned int port,
/* Forget about any falling/rising edge interrupt enabled */
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC17_GPIOIRQ
lpc17_setintedge(port, pin, 0);
#endif
}
@@ -656,7 +656,7 @@ static inline int lpc17_configinterrupt(lpc17_pinset_t cfgset, unsigned int port
/* Then just remember the rising/falling edge interrupt enabled */
DEBUGASSERT(port == 0 || port == 2);
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC17_GPIOIRQ
lpc17_setintedge(port, pin, (cfgset & GPIO_EDGE_MASK) >> GPIO_EDGE_SHIFT);
#endif
return OK;
diff --git a/arch/arm/src/lpc17xx/lpc17_can.c b/arch/arm/src/lpc17xx/lpc17_can.c
index f25de325b9f..f961bef5493 100644
--- a/arch/arm/src/lpc17xx/lpc17_can.c
+++ b/arch/arm/src/lpc17xx/lpc17_can.c
@@ -57,7 +57,7 @@
#include
#include
#include
-#include
+#include
#include "up_internal.h"
#include "up_arch.h"
diff --git a/arch/arm/src/lpc17xx/lpc17_gpio.h b/arch/arm/src/lpc17xx/lpc17_gpio.h
index 1129a26235d..6aab5b9f84c 100644
--- a/arch/arm/src/lpc17xx/lpc17_gpio.h
+++ b/arch/arm/src/lpc17xx/lpc17_gpio.h
@@ -89,7 +89,7 @@ extern "C"
* lpc17_gpioint.c, and lpc17_gpiodbg.c
*/
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC17_GPIOIRQ
EXTERN uint64_t g_intedge0;
EXTERN uint64_t g_intedge2;
#endif
@@ -109,7 +109,7 @@ EXTERN const uint32_t g_intbase[GPIO_NPORTS];
*
************************************************************************************/
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC17_GPIOIRQ
void lpc17_gpioirqinitialize(void);
#else
# define lpc17_gpioirqinitialize()
@@ -153,7 +153,7 @@ bool lpc17_gpioread(lpc17_pinset_t pinset);
*
************************************************************************************/
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC17_GPIOIRQ
void lpc17_gpioirqenable(int irq);
#else
# define lpc17_gpioirqenable(irq)
@@ -167,7 +167,7 @@ void lpc17_gpioirqenable(int irq);
*
************************************************************************************/
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC17_GPIOIRQ
void lpc17_gpioirqdisable(int irq);
#else
# define lpc17_gpioirqdisable(irq)
diff --git a/arch/arm/src/lpc17xx/lpc17_gpioint.c b/arch/arm/src/lpc17xx/lpc17_gpioint.c
index 46acb05e6fa..0c1ca613625 100644
--- a/arch/arm/src/lpc17xx/lpc17_gpioint.c
+++ b/arch/arm/src/lpc17xx/lpc17_gpioint.c
@@ -51,7 +51,7 @@
#include "chip.h"
#include "lpc17_gpio.h"
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC17_GPIOIRQ
/****************************************************************************
* Pre-processor Definitions
@@ -543,4 +543,4 @@ void lpc17_gpioirqdisable(int irq)
}
}
-#endif /* CONFIG_GPIO_IRQ */
+#endif /* CONFIG_LPC17_GPIOIRQ */
diff --git a/arch/arm/src/lpc17xx/lpc17_irq.c b/arch/arm/src/lpc17xx/lpc17_irq.c
index 44d149c7342..ac8fb8855cd 100644
--- a/arch/arm/src/lpc17xx/lpc17_irq.c
+++ b/arch/arm/src/lpc17xx/lpc17_irq.c
@@ -412,7 +412,7 @@ void up_irqinitialize(void)
* GPIO pins.
*/
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC17_GPIOIRQ
lpc17_gpioirqinitialize();
#endif
@@ -456,7 +456,7 @@ void up_disable_irq(int irq)
putreg32(regval, regaddr);
}
}
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC17_GPIOIRQ
else if (irq >= LPC17_VALID_FIRST0L)
{
/* Maybe it is a (derived) GPIO IRQ */
@@ -501,7 +501,7 @@ void up_enable_irq(int irq)
putreg32(regval, regaddr);
}
}
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC17_GPIOIRQ
else if (irq >= LPC17_VALID_FIRST0L)
{
/* Maybe it is a (derived) GPIO IRQ */
diff --git a/arch/arm/src/lpc17xx/lpc17_mcpwm.c b/arch/arm/src/lpc17xx/lpc17_mcpwm.c
index be526964c4a..db0d1a9d67d 100644
--- a/arch/arm/src/lpc17xx/lpc17_mcpwm.c
+++ b/arch/arm/src/lpc17xx/lpc17_mcpwm.c
@@ -47,7 +47,7 @@
#include
#include
-#include
+#include
#include
#include "up_internal.h"
diff --git a/arch/arm/src/lpc17xx/lpc17_pwm.c b/arch/arm/src/lpc17xx/lpc17_pwm.c
index dc073fc1a73..c284934570c 100644
--- a/arch/arm/src/lpc17xx/lpc17_pwm.c
+++ b/arch/arm/src/lpc17xx/lpc17_pwm.c
@@ -47,7 +47,7 @@
#include
#include
-#include
+#include
#include
#include "up_internal.h"
diff --git a/arch/arm/src/lpc17xx/lpc17_timer.c b/arch/arm/src/lpc17xx/lpc17_timer.c
index 9278578b678..434f416021f 100644
--- a/arch/arm/src/lpc17xx/lpc17_timer.c
+++ b/arch/arm/src/lpc17xx/lpc17_timer.c
@@ -47,7 +47,7 @@
#include
#include
-#include
+#include
#include
#include "up_internal.h"
diff --git a/arch/arm/src/lpc43xx/Kconfig b/arch/arm/src/lpc43xx/Kconfig
index e7f830ed2ba..80da35c00ca 100644
--- a/arch/arm/src/lpc43xx/Kconfig
+++ b/arch/arm/src/lpc43xx/Kconfig
@@ -81,36 +81,43 @@ config ARCH_FAMILY_LPC4320
bool
default y if ARCH_CHIP_LPC4320FBD144 || ARCH_CHIP_LPC4320FET100
select ARCH_HAVE_TICKLESS
+ select ARCH_HAVE_AHB_SRAM_BANK1
config ARCH_FAMILY_LPC4330
bool
default y if ARCH_CHIP_LPC4330FBD144 || ARCH_CHIP_LPC4330FET100 || ARCH_CHIP_LPC4330FET180 || ARCH_CHIP_LPC4330FET256 || ARCH_CHIP_LPC4337JET100
select ARCH_HAVE_TICKLESS
+ select ARCH_HAVE_AHB_SRAM_BANK1
config ARCH_FAMILY_LPC4337
bool
default y if ARCH_CHIP_LPC4337JBD144
select ARCH_HAVE_TICKLESS
+ select ARCH_HAVE_AHB_SRAM_BANK1
config ARCH_FAMILY_LPC4350
bool
default y if ARCH_CHIP_LPC4350FBD208 || ARCH_CHIP_LPC4350FET180 || ARCH_CHIP_LPC4350FET256
select ARCH_HAVE_TICKLESS
+ select ARCH_HAVE_AHB_SRAM_BANK1
config ARCH_FAMILY_LPC4353
bool
default y if ARCH_CHIP_LPC4353FBD208 || ARCH_CHIP_LPC4353FET180 || ARCH_CHIP_LPC4353FET256
select ARCH_HAVE_TICKLESS
+ select ARCH_HAVE_AHB_SRAM_BANK1
config ARCH_FAMILY_LPC4357
bool
default y if ARCH_CHIP_LPC4357FET180 || ARCH_CHIP_LPC4357FBD208 || ARCH_CHIP_LPC4357FET256
select ARCH_HAVE_TICKLESS
+ select ARCH_HAVE_AHB_SRAM_BANK1
config ARCH_FAMILY_LPC4370
bool
default y if ARCH_CHIP_LPC4370FET100
select ARCH_HAVE_TICKLESS
+ select ARCH_HAVE_AHB_SRAM_BANK1
choice
prompt "LPC43XX Boot Configuration"
@@ -177,9 +184,15 @@ config LPC43_DAC
config LPC43_EMC
bool "External Memory Controller (EMC)"
default n
+ select ARCH_HAVE_EXTSDRAM0
+ select ARCH_HAVE_EXTSDRAM1
+ select ARCH_HAVE_EXTSDRAM2
+ select ARCH_HAVE_EXTSDRAM3
config LPC43_ETHERNET
bool "Ethernet"
+ select NETDEVICES
+ select ARCH_HAVE_PHY
default n
config LPC43_EVNTMNTR
@@ -320,6 +333,158 @@ config LPC43_GPIO_IRQ
---help---
Enable support for GPIO interrupts
+menu "Internal Memory Configuration"
+
+config ARCH_HAVE_AHB_SRAM_BANK1
+ bool
+
+if !LPC43_BOOT_SRAM
+
+config LPC43_USE_LOCSRAM_BANK1
+ bool "Use local SRAM bank 1 memory region"
+ default n
+ ---help---
+ Add local SRAM bank 1 memory region.
+
+endif # LPC43_BOOT_SRAM
+
+config LPC43_USE_AHBSRAM_BANK0
+ bool "Use AHB SRAM bank 0 memory region"
+ default n
+ ---help---
+ Add local AHB SRAM bank 0 memory region.
+
+config LPC43_USE_AHBSRAM_BANK1
+ bool "Use AHB SRAM bank 1 memory region"
+ default n
+ depends on ARCH_HAVE_AHB_SRAM_BANK1
+ ---help---
+ Add local AHB SRAM bank 1 memory region.
+
+config LPC43_HEAP_AHBSRAM_BANK2
+ bool "Use AHB SRAM bank 2 (ETB SRAM) memory region"
+ default n
+ ---help---
+ Add local AHB SRAM bank 2 (ETB SRAM) memory region.
+
+endmenu # LPC43xx Internal Memory Configuration
+
+menu "External Memory Configuration"
+
+config ARCH_HAVE_EXTSDRAM0
+ bool
+
+config ARCH_HAVE_EXTSDRAM1
+ bool
+
+config ARCH_HAVE_EXTSDRAM2
+ bool
+
+config ARCH_HAVE_EXTSDRAM3
+ bool
+
+config LPC43_EXTSDRAM0
+ bool "Configure external SDRAM0 (on DYNCS0)"
+ default n
+ depends on ARCH_HAVE_EXTSDRAM0
+ select ARCH_HAVE_EXTSDRAM
+ ---help---
+ Configure external SDRAM memory and, if applicable, map then external
+ SDRAM into the memory map.
+
+if LPC43_EXTSDRAM0
+
+config LPC43_EXTSDRAM0_SIZE
+ int "External SDRAM0 size"
+ default 0
+ ---help---
+ Size of the external SDRAM on DYNCS0 in bytes.
+
+config LPC43_EXTSDRAM0_HEAP
+ bool "Add external SDRAM on DYNCS0 to the heap"
+ default y
+ ---help---
+ Add the external SDRAM on DYNCS0 into the heap.
+
+endif # LCP43_EXTSDRAM0
+
+config LPC43_EXTSDRAM1
+ bool "Configure external SDRAM1 (on DYNCS1)"
+ default n
+ depends on ARCH_HAVE_EXTSDRAM1
+ select ARCH_HAVE_EXTSDRAM
+ ---help---
+ Configure external SDRAM memoryand, if applicable, map then external
+ SDRAM into the memory map.
+
+if LPC43_EXTSDRAM1
+
+config LPC43_EXTSDRAM1_SIZE
+ int "External SDRAM1 size"
+ default 0
+ ---help---
+ Size of the external SDRAM on DYNCS1 in bytes.
+
+config LPC43_EXTSDRAM1_HEAP
+ bool "Add external SDRAM on DYNCS1 to the heap"
+ default y
+ ---help---
+ Add the external SDRAM on DYNCS1 into the heap.
+
+endif # LCP43_EXTSDRAM1
+
+config LPC43_EXTSDRAM2
+ bool "Configure external SDRAM2 (on DYNCS2)"
+ default n
+ depends on ARCH_HAVE_EXTSDRAM2
+ select ARCH_HAVE_EXTSDRAM
+ ---help---
+ Configure external SDRAM memoryand, if applicable, map then external
+ SDRAM into the memory map.
+
+if LPC43_EXTSDRAM2
+
+config LPC43_EXTSDRAM2_SIZE
+ int "External SDRAM2 size"
+ default 0
+ ---help---
+ Size of the external SDRAM on DYNCS2 in bytes.
+
+config LPC43_EXTSDRAM2_HEAP
+ bool "Add external SDRAM on DYNCS2 to the heap"
+ default y
+ ---help---
+ Add the external SDRAM on DYNCS2 into the heap.
+
+endif # LCP43_EXTSDRAM2
+
+config LPC43_EXTSDRAM3
+ bool "Configure external SDRAM3 (on DYNCS3)"
+ default n
+ depends on ARCH_HAVE_EXTSDRAM3
+ select ARCH_HAVE_EXTSDRAM
+ ---help---
+ Configure external SDRAM memoryand, if applicable, map then external
+ SDRAM into the memory map.
+
+if LPC43_EXTSDRAM3
+
+config LPC43_EXTSDRAM3_SIZE
+ int "External SDRAM3 size"
+ default 0
+ ---help---
+ Size of the external SDRAM in bytes.
+
+config LPC43_EXTSDRAM3_HEAP
+ bool "Add external SDRAM on DYNCS3 to the heap"
+ default y
+ ---help---
+ Add the external SDRAM on DYNCS3 into the heap.
+
+endif # LCP43_EXTSDRAM3
+
+endmenu # External Memory Configuration
+
if LPC43_ETHERNET
menu "Ethernet MAC configuration"
diff --git a/arch/arm/src/lpc43xx/Make.defs b/arch/arm/src/lpc43xx/Make.defs
index 6e5d7ef3a78..79ddaa4a022 100644
--- a/arch/arm/src/lpc43xx/Make.defs
+++ b/arch/arm/src/lpc43xx/Make.defs
@@ -126,6 +126,10 @@ ifeq ($(CONFIG_LPC43_ETHERNET),y)
CHIP_CSRCS += lpc43_ethernet.c
endif
+ifeq ($(CONFIG_LPC43_EMC),y)
+CHIP_CSRCS += lpc43_emc.c
+endif
+
ifeq ($(CONFIG_LPC43_SPI),y)
CHIP_CSRCS += lpc43_spi.c
else
diff --git a/arch/arm/src/lpc43xx/chip/lpc435357_memorymap.h b/arch/arm/src/lpc43xx/chip/lpc435357_memorymap.h
index 1b8312c965f..852bd2a862e 100644
--- a/arch/arm/src/lpc43xx/chip/lpc435357_memorymap.h
+++ b/arch/arm/src/lpc43xx/chip/lpc435357_memorymap.h
@@ -90,6 +90,8 @@
/* AHB SRAM */
#define LPC43_AHBSRAM_BANK0_BASE (LPC43_AHBSRAM_BASE)
+#define LPC43_AHBSRAM_BANK1_BASE (LPC43_AHBSRAM_BASE + 0x00008000)
+#define LPC43_AHBSRAM_BANK2_BASE (LPC43_AHBSRAM_BASE + 0x0000c000)
#define LPC43_EEPROM_BASE (LPC43_AHBSRAM_BASE + 0x00004000)
#define LPC43_AHBSRAM_BITBAND_BASE (LPC43_AHBSRAM_BASE + 0x02000000)
diff --git a/arch/arm/src/lpc43xx/chip/lpc4357fet256_pinconfig.h b/arch/arm/src/lpc43xx/chip/lpc4357fet256_pinconfig.h
index b29722479a3..41a5d939540 100644
--- a/arch/arm/src/lpc43xx/chip/lpc4357fet256_pinconfig.h
+++ b/arch/arm/src/lpc43xx/chip/lpc4357fet256_pinconfig.h
@@ -190,86 +190,86 @@
#define PINCONF_CTOUT15_2 (PINCONF_FUNC1|PINCONF_PINSD|PINCONF_PIN_0)
#define PINCONF_CTOUT15_3 (PINCONF_FUNC2|PINCONF_PINS1|PINCONF_PIN_11)
-#define PINCONF_EMC_A0 (PINCONF_FUNC3|PINCONF_PINS2|PINCONF_PIN_9)
-#define PINCONF_EMC_A1 (PINCONF_FUNC3|PINCONF_PINS2|PINCONF_PIN_10)
-#define PINCONF_EMC_A2 (PINCONF_FUNC3|PINCONF_PINS2|PINCONF_PIN_11)
-#define PINCONF_EMC_A3 (PINCONF_FUNC3|PINCONF_PINS2|PINCONF_PIN_12)
-#define PINCONF_EMC_A4 (PINCONF_FUNC3|PINCONF_PINS2|PINCONF_PIN_13)
-#define PINCONF_EMC_A5 (PINCONF_FUNC2|PINCONF_PINS1|PINCONF_PIN_0)
-#define PINCONF_EMC_A6 (PINCONF_FUNC2|PINCONF_PINS1|PINCONF_PIN_1)
-#define PINCONF_EMC_A7 (PINCONF_FUNC2|PINCONF_PINS1|PINCONF_PIN_2)
-#define PINCONF_EMC_A8 (PINCONF_FUNC3|PINCONF_PINS2|PINCONF_PIN_8)
-#define PINCONF_EMC_A9 (PINCONF_FUNC3|PINCONF_PINS2|PINCONF_PIN_7)
-#define PINCONF_EMC_A10 (PINCONF_FUNC2|PINCONF_PINS2|PINCONF_PIN_6)
-#define PINCONF_EMC_A11 (PINCONF_FUNC2|PINCONF_PINS2|PINCONF_PIN_2)
-#define PINCONF_EMC_A12 (PINCONF_FUNC2|PINCONF_PINS2|PINCONF_PIN_1)
-#define PINCONF_EMC_A13 (PINCONF_FUNC2|PINCONF_PINS2|PINCONF_PIN_0)
-#define PINCONF_EMC_A14 (PINCONF_FUNC1|PINCONF_PINS6|PINCONF_PIN_8)
-#define PINCONF_EMC_A15 (PINCONF_FUNC1|PINCONF_PINS6|PINCONF_PIN_7)
-#define PINCONF_EMC_A16 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_16)
-#define PINCONF_EMC_A17 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_15)
-#define PINCONF_EMC_A18 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_0)
-#define PINCONF_EMC_A19 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_1)
-#define PINCONF_EMC_A20 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_2)
-#define PINCONF_EMC_A21 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_3)
-#define PINCONF_EMC_A22 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_4)
-#define PINCONF_EMC_A23 (PINCONF_FUNC3|PINCONF_PINSA|PINCONF_PIN_4)
-#define PINCONF_EMC_BLS0 (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_4)
-#define PINCONF_EMC_BLS1 (PINCONF_FUNC1|PINCONF_PINS6|PINCONF_PIN_6)
-#define PINCONF_EMC_BLS2 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_13)
-#define PINCONF_EMC_BLS3 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_10)
-#define PINCONF_EMC_CAS (PINCONF_FUNC3|PINCONF_PINS6|PINCONF_PIN_4)
-#define PINCONF_EMC_CKEOUT0 (PINCONF_FUNC3|PINCONF_PINS6|PINCONF_PIN_11)
-#define PINCONF_EMC_CKEOUT1 (PINCONF_FUNC1|PINCONF_PINS6|PINCONF_PIN_2)
-#define PINCONF_EMC_CKEOUT2 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_1)
-#define PINCONF_EMC_CKEOUT3 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_15)
-#define PINCONF_EMC_CS0 (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_5)
-#define PINCONF_EMC_CS1 (PINCONF_FUNC3|PINCONF_PINS6|PINCONF_PIN_3)
-#define PINCONF_EMC_CS2 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_12)
-#define PINCONF_EMC_CS3 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_11)
-#define PINCONF_EMC_D0 (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_7)
-#define PINCONF_EMC_D1 (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_8)
-#define PINCONF_EMC_D2 (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_9)
-#define PINCONF_EMC_D3 (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_10)
-#define PINCONF_EMC_D4 (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_11)
-#define PINCONF_EMC_D5 (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_12)
-#define PINCONF_EMC_D6 (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_13)
-#define PINCONF_EMC_D7 (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_14)
-#define PINCONF_EMC_D8 (PINCONF_FUNC2|PINCONF_PINS5|PINCONF_PIN_4)
-#define PINCONF_EMC_D9 (PINCONF_FUNC2|PINCONF_PINS5|PINCONF_PIN_5)
-#define PINCONF_EMC_D10 (PINCONF_FUNC2|PINCONF_PINS5|PINCONF_PIN_6)
-#define PINCONF_EMC_D11 (PINCONF_FUNC2|PINCONF_PINS5|PINCONF_PIN_7)
-#define PINCONF_EMC_D12 (PINCONF_FUNC2|PINCONF_PINS5|PINCONF_PIN_0)
-#define PINCONF_EMC_D13 (PINCONF_FUNC2|PINCONF_PINS5|PINCONF_PIN_1)
-#define PINCONF_EMC_D14 (PINCONF_FUNC2|PINCONF_PINS5|PINCONF_PIN_2)
-#define PINCONF_EMC_D15 (PINCONF_FUNC2|PINCONF_PINS5|PINCONF_PIN_3)
-#define PINCONF_EMC_D16 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_2)
-#define PINCONF_EMC_D17 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_3)
-#define PINCONF_EMC_D18 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_4)
-#define PINCONF_EMC_D19 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_5)
-#define PINCONF_EMC_D20 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_6)
-#define PINCONF_EMC_D21 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_7)
-#define PINCONF_EMC_D22 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_8)
-#define PINCONF_EMC_D23 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_9)
-#define PINCONF_EMC_D24 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_5)
-#define PINCONF_EMC_D25 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_6)
-#define PINCONF_EMC_D26 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_7)
-#define PINCONF_EMC_D27 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_8)
-#define PINCONF_EMC_D28 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_9)
-#define PINCONF_EMC_D29 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_10)
-#define PINCONF_EMC_D30 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_11)
-#define PINCONF_EMC_D31 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_12)
-#define PINCONF_EMC_DQMOUT0 (PINCONF_FUNC3|PINCONF_PINS6|PINCONF_PIN_12)
-#define PINCONF_EMC_DQMOUT1 (PINCONF_FUNC3|PINCONF_PINS6|PINCONF_PIN_10)
-#define PINCONF_EMC_DQMOUT2 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_0)
-#define PINCONF_EMC_DQMOUT3 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_13)
-#define PINCONF_EMC_DYCS0 (PINCONF_FUNC3|PINCONF_PINS6|PINCONF_PIN_9)
-#define PINCONF_EMC_DYCS1 (PINCONF_FUNC1|PINCONF_PINS6|PINCONF_PIN_1)
-#define PINCONF_EMC_DYCS2 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_14)
-#define PINCONF_EMC_DYCS3 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_14)
-#define PINCONF_EMC_OE (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_3)
-#define PINCONF_EMC_RAS (PINCONF_FUNC3|PINCONF_PINS6|PINCONF_PIN_5)
-#define PINCONF_EMC_WE (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_6)
+#define PINCONF_EMC_A0 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS2|PINCONF_PIN_9)
+#define PINCONF_EMC_A1 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS2|PINCONF_PIN_10)
+#define PINCONF_EMC_A2 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS2|PINCONF_PIN_11)
+#define PINCONF_EMC_A3 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS2|PINCONF_PIN_12)
+#define PINCONF_EMC_A4 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS2|PINCONF_PIN_13)
+#define PINCONF_EMC_A5 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_0)
+#define PINCONF_EMC_A6 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_1)
+#define PINCONF_EMC_A7 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_2)
+#define PINCONF_EMC_A8 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS2|PINCONF_PIN_8)
+#define PINCONF_EMC_A9 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS2|PINCONF_PIN_7)
+#define PINCONF_EMC_A10 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS2|PINCONF_PIN_6)
+#define PINCONF_EMC_A11 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS2|PINCONF_PIN_2)
+#define PINCONF_EMC_A12 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS2|PINCONF_PIN_1)
+#define PINCONF_EMC_A13 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS2|PINCONF_PIN_0)
+#define PINCONF_EMC_A14 (PINCONF_FUNC1|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS6|PINCONF_PIN_8)
+#define PINCONF_EMC_A15 (PINCONF_FUNC1|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS6|PINCONF_PIN_7)
+#define PINCONF_EMC_A16 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_16)
+#define PINCONF_EMC_A17 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_15)
+#define PINCONF_EMC_A18 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_0)
+#define PINCONF_EMC_A19 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_1)
+#define PINCONF_EMC_A20 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_2)
+#define PINCONF_EMC_A21 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_3)
+#define PINCONF_EMC_A22 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_4)
+#define PINCONF_EMC_A23 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSA|PINCONF_PIN_4)
+#define PINCONF_EMC_BLS0 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_4)
+#define PINCONF_EMC_BLS1 (PINCONF_FUNC1|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS6|PINCONF_PIN_6)
+#define PINCONF_EMC_BLS2 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_13)
+#define PINCONF_EMC_BLS3 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_10)
+#define PINCONF_EMC_CAS (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS6|PINCONF_PIN_4)
+#define PINCONF_EMC_CKEOUT0 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS6|PINCONF_PIN_11)
+#define PINCONF_EMC_CKEOUT1 (PINCONF_FUNC1|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS6|PINCONF_PIN_2)
+#define PINCONF_EMC_CKEOUT2 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_1)
+#define PINCONF_EMC_CKEOUT3 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_15)
+#define PINCONF_EMC_CS0 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_5)
+#define PINCONF_EMC_CS1 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS6|PINCONF_PIN_3)
+#define PINCONF_EMC_CS2 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_12)
+#define PINCONF_EMC_CS3 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_11)
+#define PINCONF_EMC_D0 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_7)
+#define PINCONF_EMC_D1 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_8)
+#define PINCONF_EMC_D2 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_9)
+#define PINCONF_EMC_D3 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_10)
+#define PINCONF_EMC_D4 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_11)
+#define PINCONF_EMC_D5 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_12)
+#define PINCONF_EMC_D6 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_13)
+#define PINCONF_EMC_D7 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_14)
+#define PINCONF_EMC_D8 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS5|PINCONF_PIN_4)
+#define PINCONF_EMC_D9 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS5|PINCONF_PIN_5)
+#define PINCONF_EMC_D10 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS5|PINCONF_PIN_6)
+#define PINCONF_EMC_D11 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS5|PINCONF_PIN_7)
+#define PINCONF_EMC_D12 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS5|PINCONF_PIN_0)
+#define PINCONF_EMC_D13 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS5|PINCONF_PIN_1)
+#define PINCONF_EMC_D14 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS5|PINCONF_PIN_2)
+#define PINCONF_EMC_D15 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS5|PINCONF_PIN_3)
+#define PINCONF_EMC_D16 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_2)
+#define PINCONF_EMC_D17 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_3)
+#define PINCONF_EMC_D18 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_4)
+#define PINCONF_EMC_D19 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_5)
+#define PINCONF_EMC_D20 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_6)
+#define PINCONF_EMC_D21 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_7)
+#define PINCONF_EMC_D22 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_8)
+#define PINCONF_EMC_D23 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_9)
+#define PINCONF_EMC_D24 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_5)
+#define PINCONF_EMC_D25 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_6)
+#define PINCONF_EMC_D26 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_7)
+#define PINCONF_EMC_D27 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_8)
+#define PINCONF_EMC_D28 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_9)
+#define PINCONF_EMC_D29 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_10)
+#define PINCONF_EMC_D30 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_11)
+#define PINCONF_EMC_D31 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_12)
+#define PINCONF_EMC_DQMOUT0 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS6|PINCONF_PIN_12)
+#define PINCONF_EMC_DQMOUT1 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS6|PINCONF_PIN_10)
+#define PINCONF_EMC_DQMOUT2 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_0)
+#define PINCONF_EMC_DQMOUT3 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_13)
+#define PINCONF_EMC_DYCS0 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS6|PINCONF_PIN_9)
+#define PINCONF_EMC_DYCS1 (PINCONF_FUNC1|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS6|PINCONF_PIN_1)
+#define PINCONF_EMC_DYCS2 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_14)
+#define PINCONF_EMC_DYCS3 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_14)
+#define PINCONF_EMC_OE (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_3)
+#define PINCONF_EMC_RAS (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS6|PINCONF_PIN_5)
+#define PINCONF_EMC_WE (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_6)
#define PINCONF_ENET_COL_1 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_SLEW_FAST|PINCONF_PINS0|PINCONF_PIN_1)
#define PINCONF_ENET_COL_2 (PINCONF_FUNC5|PINCONF_INBUFFER|PINCONF_SLEW_FAST|PINCONF_PINS9|PINCONF_PIN_6)
diff --git a/arch/arm/src/lpc43xx/chip/lpc43_ccu.h b/arch/arm/src/lpc43xx/chip/lpc43_ccu.h
index a2cb20ca62f..51cdcdb9fc9 100644
--- a/arch/arm/src/lpc43xx/chip/lpc43_ccu.h
+++ b/arch/arm/src/lpc43xx/chip/lpc43_ccu.h
@@ -1,7 +1,7 @@
/****************************************************************************************************
* arch/arm/src/lpc43xx/chip/lpc43_ccu.h
*
- * Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2012, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -45,6 +45,7 @@
/****************************************************************************************************
* Pre-processor Definitions
****************************************************************************************************/
+
/* Register Offsets *********************************************************************************/
#define LPC43_CCU1_PM_OFFSET 0x0000 /* CCU1 power mode register */
@@ -343,6 +344,23 @@
#define CCU_CLK_STAT_WAKEUP (1 << 2) /* Bit 2: Wake-up mechanism enable status */
/* Bits 3-31: Reserved */
+/* CCU1 Branch Clock EMCDIV Configuration Registers */
+
+#define CCU_CLK_EMCDIV_CFG_RUN (1 << 0) /* Bit 0: Run enable */
+#define CCU_CLK_EMCDIV_CFG_AUTO (1 << 1) /* Bit 1: Auto (AHB disable mechanism) enable */
+#define CCU_CLK_EMCDIV_CFG_WAKEUP (1 << 2) /* Bit 2: Wake-up mechanism enable */
+ /* Bits 3-4: Reserved */
+#define CCU_CLK_EMCDIV_CLOCK_DIV_SHIFT (5) /* Bits 5-7: Clock divider */
+#define CCU_CLK_EMCDIV_CLOCK_DIV_MASK (7 << CCU_CLK_EMCDIV_CLOCK_DIV_SHIFT)
+# define CCU_CLK_EMCDIV_CFG_DIV_FUNC(n) ((n) << CCU_CLK_EMCDIV_CLOCK_DIV_SHIFT)
+# define CCU_CLK_EMCDIV_CFG_DIV_NODIV (0 << CCU_CLK_EMCDIV_CLOCK_DIV_SHIFT) /* Bit 5-7: No division */
+# define CCU_CLK_EMCDIV_CFG_DIV_BY2 (1 << CCU_CLK_EMCDIV_CLOCK_DIV_SHIFT) /* Bit 5-7: Division by 2 */
+ /* Bits 8-26: Reserved */
+#define CCU_CLK_EMCDIV_CLOCK_DIVSTAT_SHIFT (27) /* Bits 27-29: Clock divider status */
+#define CCU_CLK_EMCDIV_CLOCK_DIVSTAT_MASK (7 << CCU_CLK_EMCDIV_CLOCK_DIVSTAT_SHIFT)
+# define CCU_CLK_EMCDIV_CFG_DIVSTAT_NODIV (0 << CCU_CLK_EMCDIV_CLOCK_DIVSTAT_SHIFT) /* Bit 27-29: No division */
+# define CCU_CLK_EMCDIV_CFG_DIVSTAT_BY2 (1 << CCU_CLK_EMCDIV_CLOCK_DIVSTAT_MASK) /* Bit 26-29: Divistion by 2 */
+
/****************************************************************************************************
* Public Types
****************************************************************************************************/
diff --git a/arch/arm/src/lpc43xx/chip/lpc43_emc.h b/arch/arm/src/lpc43xx/chip/lpc43_emc.h
index 4fb3ae38be6..b61cbcbc585 100644
--- a/arch/arm/src/lpc43xx/chip/lpc43_emc.h
+++ b/arch/arm/src/lpc43xx/chip/lpc43_emc.h
@@ -1,7 +1,7 @@
/****************************************************************************************************
* arch/arm/src/lpc43xx/chip/lpc43_emc.h
*
- * Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2012, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -45,6 +45,7 @@
/****************************************************************************************************
* Pre-processor Definitions
****************************************************************************************************/
+
/* Register Offsets *********************************************************************************/
#define LPC43_EMC_CONTROL_OFFSET 0x0000 /* EMC Control register */
@@ -213,6 +214,7 @@
#define EMC_CONTROL_LOWPOWER (1 << 2) /* Bit 2: Low-power mode */
/* Bits 3-31: Reserved */
/* EMC Status register */
+
#define EMC__
#define EMC_STATUS_BUSY (1 << 0) /* Bit 0: Busy */
#define EMC_STATUS_WB (1 << 1) /* Bit 1: Write buffer status */
@@ -333,13 +335,64 @@
# define EMC_DYNCONFIG_MD_SDRAM (0 << EMC_DYNCONFIG_MD_SHIFT) /* SDRAM (POR reset value) */
/* Bits 5-6: Reserved */
#define EMC_DYNCONFIG_AM0_SHIFT (7) /* Bits 7-12: AM0 Address mapping (see user manual) */
-#define EMC_DYNCONFIG_AM0_MASK (0x3f << EMC_DYNCONFIG_AM0_SHIFT)
+#define EMC_DYNCONFIG_AM0_MASK (0x3F << EMC_DYNCONFIG_AM0_SHIFT)
/* Bit 13: Reserved */
#define EMC_DYNCONFIG_AM1 (1 << 14) /* Bit 14: AM1 Address mapping (see user manual) */
/* Bits 15-18: Reserved */
-#define EMC_DYNCONFIG_BENA (1 << 10) /* Bit 19: Buffer enable */
+#define EMC_DYNCONFIG_BENA (1 << 19) /* Bit 19: Buffer enable */
#define EMC_DYNCONFIG_WP (1 << 20) /* Bit 20: Write protect. */
/* Bits 21-31: Reserved */
+
+/* Dynamic Memory Configuration register Memory Configuration Values */
+/* TODO: complete configuration */
+
+/* Data Bus Width Value in LPC43_EMC_DYNCONFIG register (bit 14) */
+
+#define EMC_DYNCONFIG_DATA_BUS_16 (0 << 14) /* Data bus width 16 bit */
+#define EMC_DYNCONFIG_DATA_BUS_32 (1 << 14) /* Data bus width 32 bit */
+
+/* Low power SDRAM value in LPC43_EMC_DYNCONFIG register (bit 12) */
+
+#define EMC_DYNCONFIG_LPSDRAM (1 << 12) /* Low power SDRAM value (Bank, Row, Column)*/
+#define EMC_DYNCONFIG_HPSDRAM (0 << 12) /* High performance SDRAM value (Row, Bank, Column)*/
+
+/* Address mapping table for LPC43_EMC_DYNCONFIG register (bits 7-11) */
+
+/* Device size bits in LPC43_EMC_DYNCONFIG register (bits 9-11) */
+
+#define EMC_DYNCONFIG_DEV_SIZE_SHIFT (9)
+#define EMC_DYNCONFIG_DEV_SIZE_MASK (0x7)
+# define EMC_DYNCONFIG_DEV_SIZE_16Mb (0x00 << EMC_DYNCONFIG_DEV_SIZE_SHIFT)
+# define EMC_DYNCONFIG_DEV_SIZE_64Mb (0x01 << EMC_DYNCONFIG_DEV_SIZE_SHIFT)
+# define EMC_DYNCONFIG_DEV_SIZE_128Mb (0x02 << EMC_DYNCONFIG_DEV_SIZE_SHIFT)
+# define EMC_DYNCONFIG_DEV_SIZE_256Mb (0x03 << EMC_DYNCONFIG_DEV_SIZE_SHIFT)
+# define EMC_DYNCONFIG_DEV_SIZE_512Mb (0x04 << EMC_DYNCONFIG_DEV_SIZE_SHIFT)
+
+/* Bus width bits in LPC43_EMC_DYNCONFIG register (bits 7-8) */
+
+#define EMC_DYNCONFIG_DEV_BUS_SHIFT (7)
+#define EMC_DYNCONFIG_DEV_BUS_MASK (0x3)
+# define EMC_DYNCONFIG_DEV_BUS_8 (0x00 << EMC_DYNCONFIG_DEV_BUS_SHIFT)
+# define EMC_DYNCONFIG_DEV_BUS_16 (0x01 << EMC_DYNCONFIG_DEV_BUS_SHIFT)
+# define EMC_DYNCONFIG_DEV_BUS_32 (0x02 << EMC_DYNCONFIG_DEV_BUS_SHIFT)
+
+#define EMC_DYNCONFIG_2Mx8_2BANKS_11ROWS_9COLS ((0x0 << 9) | (0x0 << 7)) /* 16Mb (2Mx8), 2 banks, row length = 11, column length = 9 */
+#define EMC_DYNCONFIG_1Mx16_2BANKS_11ROWS_8COLS ((0x0 << 9) | (0x1 << 7)) /* 16Mb (1Mx16), 2 banks, row length = 11, column length = 8 */
+#define EMC_DYNCONFIG_8Mx8_4BANKS_12ROWS_9COLS ((0x1 << 9) | (0x0 << 7)) /* 64Mb (8Mx8), 4 banks, row length = 12, column length = 9 */
+#define EMC_DYNCONFIG_4Mx16_4BANKS_12ROWS_8COLS ((0x1 << 9) | (0x1 << 7)) /* 64Mb (4Mx16), 4 banks, row length = 12, column length = 8 */
+#define EMC_DYNCONFIG_2Mx32_4BANKS_11ROWS_8COLS ((0x1 << 9) | (0x2 << 7)) /* 64Mb (2Mx32), 4 banks, row length = 11, column length = 8, 32 bit bus only */
+#define EMC_DYNCONFIG_16Mx8_4BANKS_12ROWS_10COLS ((0x2 << 9) | (0x0 << 7)) /* 128Mb (16Mx8), 4 banks, row length = 12, column length = 10 */
+#define EMC_DYNCONFIG_8Mx16_4BANKS_12ROWS_9COLS ((0x2 << 9) | (0x1 << 7)) /* 128Mb (8Mx16), 4 banks, row length = 12, column length = 9 */
+#define EMC_DYNCONFIG_4Mx32_4BANKS_12ROWS_8COLS ((0x2 << 9) | (0x2 << 7)) /* 128Mb (4Mx32), 4 banks, row length = 12, column length = 8 */
+#define EMC_DYNCONFIG_32Mx8_4BANKS_13ROWS_10COLS ((0x3 << 9) | (0x0 << 7)) /* 256Mb (32Mx8), 4 banks, row length = 13, column length = 10, 32 bit bus only */
+#define EMC_DYNCONFIG_16Mx16_4BANKS_13ROWS_9COLS ((0x3 << 9) | (0x1 << 7)) /* 256Mb (16Mx16), 4 banks, row length = 13, column length = 9 */
+#define EMC_DYNCONFIG_8Mx32_4BANKS_13ROWS_8COLS ((0x3 << 9) | (0x2 << 7)) /* 256Mb (8Mx32), 4 banks, row length = 13, column length = 8, 32 bit bus only */
+#define EMC_DYNCONFIG_8Mx32_4BANKS_12ROWS_9COLS ((0x2 << 9) | (0x1 << 7)) /* 256Mb (8Mx32), 4 banks, row length = 12, column length = 9, 32 bit bus only */
+#define EMC_DYNCONFIG_64Mx8_4BANKS_13ROWS_10COLS ((0x4 << 9) | (0x0 << 7)) /* 512Mb (64Mx8), 4 banks, row length = 13, column length = 11 */
+#define EMC_DYNCONFIG_32Mx16_4BANKS_13ROWS_10COLS ((0x4 << 9) | (0x1 << 7)) /* 512Mb (32Mx16), 4 banks, row length = 13, column length = 10 */
+#define EMC_DYNCONFIG_16Mx32_4BANKS_13ROWS_9COLS ((0x3 << 9) | (0x1 << 7)) /* 512Mb (16Mx32), 4 banks, row length = 13, column length = 9, 32 bit bus only */
+#define EMC_DYNCONFIG_32Mx32_4BANKS_13ROWS_10COLS ((0x4 << 9) | (0x1 << 7)) /* 1Gb (32Mx32), 4 banks, row length = 13, column length = 10,32 bit bus only */
+
/* Dynamic Memory RAS & CAS Delay registers */
#define EMC_DYNRASCAS_RAS_SHIFT (0) /* Bits 0-1: RAS latency (active to read/write delay) */
@@ -354,6 +407,35 @@
# define EMC_DYNRASCAS_CAS_2CCLK (2 << EMC_DYNRASCAS_CAS_SHIFT) /* Two CCLK cycles */
# define EMC_DYNRASCAS_CAS_3CCLK (3 << EMC_DYNRASCAS_CAS_SHIFT) /* Three CCLK cycles (POR reset value) */
/* Bits 10-31: Reserved */
+
+/* Dynamic SDRAM mode register definitions */
+
+ /* Bits 0-2: Burst length. All other values are reserved. */
+#define EMC_DYNMODE_BURST_LENGTH_SHIFT (0)
+#define EMC_DYNMODE_BURST_LENGTH_MASK (0x7)
+# define EMC_DYNMODE_BURST_LENGTH_1 (0 << EMC_DYNMODE_BURST_LENGTH_SHIFT)
+# define EMC_DYNMODE_BURST_LENGTH_2 (1 << EMC_DYNMODE_BURST_LENGTH_SHIFT)
+# define EMC_DYNMODE_BURST_LENGTH_4 (2 << EMC_DYNMODE_BURST_LENGTH_SHIFT)
+# define EMC_DYNMODE_BURST_LENGTH_8 (3 << EMC_DYNMODE_BURST_LENGTH_SHIFT)
+ /* Bit 3: Burst mode type */
+#define EMC_DYNMODE_BURST_TYPE_SHIFT (3)
+# define EMC_DYNMODE_BURST_TYPE_SEQUENTIAL (0 << EMC_DYNMODE_BURST_TYPE_SHIFT) /* burst type sequential */
+# define EMC_DYNMODE_BURST_TYPE_INTERLEAVED (1 << EMC_DYNMODE_BURST_TYPE_INTERLEAVED) /* burst type interleaved */
+ /* Bits 4-6: Latency mode. All other values are reserved. */
+#define EMC_DYNMODE_CAS_SHIFT (4)
+#define EMC_DYNMODE_CAS_MASK (0x7)
+# define EMC_DYNMODE_CAS_2 (2 << EMC_DYNMODE_CAS_SHIFT) /* CAS latency of 2 cycles */
+# define EMC_DYNMODE_CAS_3 (3 << EMC_DYNMODE_CAS_SHIFT) /* CAS latency of 3 cycles */
+ /* Bits 7-8: Operating mode. All other values are reserved. */
+#define EMC_DYNMODE_OPMODE_SHIFT (7)
+#define EMC_DYNMODE_OPMODE_MASK (0x3)
+# define EMC_DYNMODE_OPMODE_STANDARD (0 << EMC_DYNMODE_OPMODE_SHIFT) /* dynamic standard operation mode */
+ /* Bit 9: Write burst mode */
+#define EMC_DYNMODE_WBMODE_SHIFT (9)
+# define EMC_DYNMODE_WBMODE_PROGRAMMED (0 << EMC_DYNMODE_WBMODE_SHIFT) /* write burst mode programmed */
+# define EMC_DYNMODE_WBMODE_SINGLE_LOC (1 << EMC_DYNMODE_WBMODE_SHIFT) /* write burst mode single loc */
+ /* Bits 10-11: Reserved */
+
/* Static Memory Configuration registers */
#define EMC_STATCONFIG_MW_SHIFT (0) /* Bits 0-1: Memory width */
diff --git a/arch/arm/src/lpc43xx/lpc43_allocateheap.c b/arch/arm/src/lpc43xx/lpc43_allocateheap.c
index 70a0bbe5873..b7a947b668f 100644
--- a/arch/arm/src/lpc43xx/lpc43_allocateheap.c
+++ b/arch/arm/src/lpc43xx/lpc43_allocateheap.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/lpc43xx/lpc43_allocateheap.c
*
- * Copyright (C) 2012-2013, 2015 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2012-2013, 2015-2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -61,6 +61,7 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
+
/* Get customizations for each supported chip.
*
* SRAM Resources
@@ -95,6 +96,25 @@
* NOTE 1: The 64Kb of AHB of SRAM on the LPC4350/30/20 span all AHB SRAM
* banks but are treated as two banks of 48 an 16Kb by the NuttX memory
* manager. This gives some symmetry to all of the members of the family.
+ *
+ * ----------------------------------------------------------------------
+ * EMC SDRAM
+ * ----------------------------------------------------------------------
+ * LPC43xx may have dynamic RAM connected on EMC bus. Up to 4 chips can be
+ * connected.
+ *
+ * DYCS0 (0x2800 0000) up to 128MB
+ * DYCS1 (0x3000 0000) up to 256MB
+ * DYCS2 (0x6000 0000) up to 256MB
+ * DYCS3 (0x7000 0000) up to 256MB
+ *
+ * LPC43xx may have static RAM connected on EMC bus.
+ *
+ * CS0 (0x1C00 0000) up to 16MB
+ * CS1 (0x1D00 0000) up to 16MB
+ * CS2 (0x1E00 0000) up to 16MB
+ * CS3 (0x1F00 0000) up to 16MB
+ *
*/
/* Configuration ************************************************************/
@@ -136,58 +156,89 @@
*
* CONFIG_RAM_START = The start of the data RAM region which may be
* either local SRAM bank 0 (Configuration A) or 1 (Configuration B).
- * CONFIG_RAM_START = The size of the data RAM region.
- * CONFIG_RAM_END = The sum of the above
+ * CONFIG_RAM_SIZE = The size of the data RAM region.
+ * CONFIG_RAM_END = The sum of the above.
+ */
+
+/* External Memory Configuration
+ *
+ * Dynamic memory configuration
+ * For dynamic memory configuration at least one of LPC43_EXTSDRAMx
+ * should by defined.
+ * Also, together with LPC43_EXTSDRAMx should be defined:
+ * LPC43_EXTSDRAMxSIZE = External RAM size in bytes.
+ * LPC43_EXTSDRAMxHEAP = Should this RAM be use as heap space?
*/
/* Check for Configuration A. */
+#undef MM_USE_LOCSRAM_BANK0
+#undef MM_USE_LOCSRAM_BANK1
+#undef MM_USE_AHBSRAM_BANK0
+#undef MM_USE_AHBSRAM_BANK1
+#undef MM_USE_AHBSRAM_BANK2
+#undef MM_USE_EXTSDRAM0
+#undef MM_USE_EXTSDRAM1
+#undef MM_USE_EXTSDRAM2
+#undef MM_USE_EXTSDRAM3
+#undef MM_HAVE_REGION
+
#ifndef CONFIG_LPC43_BOOT_SRAM
/* Configuration A */
-/* CONFIG_RAM_START should be set to the base of AHB SRAM, local 0. */
+/* CONFIG_RAM_START shoudl be set to the base of local SRAM, Bank 0. */
# if CONFIG_RAM_START != LPC43_LOCSRAM_BANK0_BASE
-# error "CONFIG_RAM_START must be set to the base address of RAM Bank 0"
+# error "CONFIG_RAM_START must be set to the base address of RAM bank 0"
# endif
-/* The configured RAM size should be equal to the size of local SRAM Bank 0 */
+/* The configured RAM size should be equal to the size of local SRAM Bank 0. */
# if CONFIG_RAM_SIZE != LPC43_LOCSRAM_BANK0_SIZE
-# error "CONFIG_RAM_SIZE must be set to size of AHB SRAM Bank 0"
+# error "CONFIG_RAM_SIZE must be set to size of local SRAM Bank 0"
# endif
-/* Now we can assign all of the memory regions for configuration A */
+/* Local SRAM Bank 0 will be used as main memory region */
-# define MM_REGION1_BASE LPC43_LOCSRAM_BANK0_BASE
-# define MM_REGION1_SIZE LPC43_LOCSRAM_BANK0_SIZE
-# define MM_REGION2_BASE LPC43_LOCSRAM_BANK1_BASE
-# define MM_REGION2_SIZE LPC43_LOCSRAM_BANK1_SIZE
-# define MM_REGION3_BASE LPC43_AHBSRAM_BANK0_BASE
-# define MM_REGION3_SIZE LPC43_AHBSRAM_BANK0_SIZE
-#else
+# define MM_USE_LOCSRAM_BANK0 0
+
+/* Use local SRAM Bank 1 if configured */
+
+# ifdef CONFIG_LPC43_USE_LOCSRAM_BANK1
+# define MM_USE_LOCSRAM_BANK1 1
+# endif
+
+#else /* CONFIG_LPC43_BOOT_SRAM */
/* Configuration B */
-/* CONFIG_RAM_START should be set to the base of local SRAM, bank 1. */
+/* CONFIG_RAM_START should be set to the base of local SRAM, Bank 1. */
# if CONFIG_RAM_START != LPC43_LOCSRAM_BANK1_BASE
-# error "CONFIG_RAM_START must be set to the base address of SRAM Bank 1"
+# error "CONFIG_RAM_START must be set to the base address of RAM bank 1"
# endif
-/* The configured RAM size should be equal to the size of local SRAM Bank 1 */
+/* The configured RAM size should be equal to the size of local SRAM Bank 1. */
# if CONFIG_RAM_SIZE != LPC43_LOCSRAM_BANK1_SIZE
-# error "CONFIG_RAM_SIZE must be set to size of AHB SRAM Bank 1"
+# error "CONFIG_RAM_SIZE must be set to size of local SRAM Bank 1"
# endif
-/* Now we can assign all of the memory regions for configuration B */
+/* Shouldn't use Local SRAM Bank 0 as system use it for code.
+ * Local SRAM Bank1 is used as main memory region.
+ */
-# define MM_REGION1_BASE LPC43_LOCSRAM_BANK1_BASE
-# define MM_REGION1_SIZE LPC43_LOCSRAM_BANK1_SIZE
-# define MM_REGION2_BASE LPC43_AHBSRAM_BANK0_BASE
-# define MM_REGION2_SIZE LPC43_AHBSRAM_BANK0_SIZE
-# undef MM_REGION3_BASE
-# undef MM_REGION3_SIZE
+# define MM_USE_LOCSRAM_BANK1 0
+
+#endif /* CONFIG_LPC43_BOOT_SRAM */
+
+/* Configure other memory banks */
+
+#ifdef CONFIG_LPC43_AHBSRAM_BANK0
+# define MM_USE_AHBSRAM_BANK0 1
+#endif
+
+#ifdef CONFIG_LPC43_AHBSRAM_BANK1
+# define MM_USE_AHBSRAM_BANK1 1
#endif
#define MM_DMAREGION_BASE LPC43_AHBSRAM_BANK2_BASE
@@ -199,8 +250,69 @@
#warning "Missing Logic"
-#define MM_DMAHEAP_BASE MM_DMAREGION_BASE /* For now... use it all */
-#define MM_DMAHEAP_SIZE MM_DMAREGION_SIZE
+#ifdef CONFIG_LPC43_AHBSRAM_BANK2
+# define MM_USE_AHBSRAM_BANK2 1
+# define MM_DMAHEAP_BASE MM_DMAREGION_BASE /* For now... use it all */
+# define MM_DMAHEAP_SIZE MM_DMAREGION_SIZE
+#endif
+
+/* External RAM configuration */
+
+/* Check if external SDRAM is supported and, if so, it is intended to be used
+ * used as heap.
+ */
+
+#if !defined(CONFIG_LPC43_EXTSDRAM0) || !defined(CONFIG_LPC43_EXTSDRAM0_HEAP)
+# undef CONFIG_LPC43_EXTSDRAM0_SIZE
+# define CONFIG_LPC43_EXTSDRAM0_SIZE 0
+#endif
+
+#if !defined(CONFIG_LPC43_EXTSDRAM1) || !defined(CONFIG_LPC43_EXTSDRAM1_HEAP)
+# undef CONFIG_LPC43_EXTSDRAM1_SIZE
+# define CONFIG_LPC43_EXTSDRAM1_SIZE 0
+#endif
+
+#if !defined(CONFIG_LPC43_EXTSDRAM2) || !defined(CONFIG_LPC43_EXTSDRAM2_HEAP)
+# undef CONFIG_LPC43_EXTSDRAM2_SIZE
+# define CONFIG_LPC43_EXTSDRAM2_SIZE 0
+#endif
+
+#if !defined(CONFIG_LPC43_EXTSDRAM3) || !defined(CONFIG_LPC43_EXTSDRAM3_HEAP)
+# undef CONFIG_LPC43_EXTSDRAM3_SIZE
+# define CONFIG_LPC43_EXTSDRAM3_SIZE 0
+#endif
+
+#if CONFIG_LPC43_EXTSDRAM0_SIZE > 0
+# define MM_USE_EXTSDRAM0 1
+# define MM_EXTSDRAM0_REGION LPC43_DYCS0_BASE
+# define MM_EXTSDRAM0_SIZE CONFIG_LPC43_EXTSDRAM0_SIZE
+#endif /* CONFIG_LPC43_EXTSDRAM0_SIZE */
+
+#if CONFIG_LPC43_EXTSDRAM1_SIZE > 0
+# define MM_USE_EXTSDRAM1 1
+# define MM_EXTSDRAM1_REGION LPC43_DYCS1_BASE
+# define MM_EXTSDRAM1_SIZE CONFIG_LPC43_EXTSDRAM1_SIZE
+#endif /* CONFIG_LPC43_EXTSDRAM1_SIZE */
+
+#if CONFIG_LPC43_EXTSDRAM2_SIZE > 0
+# define MM_USE_EXTSDRAM2 1
+# define MM_EXTSDRAM2_REGION LPC43_DYCS2_BASE
+# define MM_EXTSDRAM2_SIZE CONFIG_LPC43_EXTSDRAM2_SIZE
+#endif /* CONFIG_LPC43_EXTSDRAM1_SIZE */
+
+#if CONFIG_LPC43_EXTSDRAM3_SIZE > 0
+# define HAVE_EXTSDRAM3_REGION 1
+# define MM_EXTSDRAM3_REGION LPC43_DYCS3_BASE
+# define MM_EXTSDRAM3_SIZE CONFIG_LPC43_EXTSDRAM3_SIZE
+#endif /* CONFIG_LPC43_EXTSDRAM3_SIZE */
+
+#if CONFIG_MM_REGIONS > 1 && \
+ (defined(MM_USE_LOCSRAM_BANK1) || defined(MM_USE_AHBSRAM_BANK0) || \
+ defined(MM_USE_AHBSRAM_BANK1) || defined(MM_USE_AHBSRAM_BANK2) || \
+ defined(MM_USE_EXTSDRAM0) || defined(MM_USE_EXTSDRAM1) || \
+ defined(MM_USE_EXTSDRAM2) || defined(MM_USE_EXTSDRAM3))
+# define MM_HAVE_REGION 1
+#endif
/****************************************************************************
* Private Data
@@ -216,15 +328,31 @@
* thread is the thread that the system boots on and, eventually, becomes the
* idle, do nothing task that runs only when there is nothing else to run.
* The heap continues from there until the configured end of memory.
- * g_idle_topstack is the beginning of this heap region (not necessarily aligned).
+ * g_idle_topstack is the beginning of this heap region (not necessarily
+ * aligned).
*/
const uint32_t g_idle_topstack = (uint32_t)&_ebss + CONFIG_IDLETHREAD_STACKSIZE;
+#ifdef MM_HAVE_REGION
+static uint8_t g_mem_region_next = 0;
+#endif
+
/****************************************************************************
* Private Functions
****************************************************************************/
+#ifdef MM_HAVE_REGION
+static void mem_addregion(FAR void *region_start, size_t region_size)
+{
+ if (g_mem_region_next <= CONFIG_MM_REGIONS)
+ {
+ kmm_addregion(region_start, region_size);
+ g_mem_region_next++;
+ }
+}
+#endif
+
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -265,35 +393,42 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
#if CONFIG_MM_REGIONS > 1
void up_addregion(void)
{
-#if CONFIG_MM_REGIONS > 1
- /* Add the next SRAM region (which should exist) */
+#ifdef MM_HAVE_REGION
+ /* start from second region */
- kmm_addregion((FAR void *)MM_REGION2_BASE, MM_REGION2_SIZE);
+ g_mem_region_next = 2;
-#ifdef MM_REGION3_BASE
- /* Add the third SRAM region (which will not exist in configuration B) */
+# ifdef MM_USE_LOCSRAM_BANK1
+ mem_addregion((FAR void *)LPC43_LOCSRAM_BANK1_BASE, LPC43_LOCSRAM_BANK1_SIZE);
+# endif
-#if CONFIG_MM_REGIONS > 2
- /* Add the third SRAM region (which may not exist) */
+# ifdef MM_USE_AHBSRAM_BANK0
+ mem_addregion((FAR void *)LPC43_AHBSRAM_BANK0_BASE, LPC43_AHBSRAM_BANK0_SIZE);
+# endif
- kmm_addregion((FAR void *)MM_REGION3_BASE, MM_REGION3_SIZE);
+# ifdef MM_USE_AHBSRAM_BANK1
+ mem_addregion((FAR void *)LPC43_AHBSRAM_BANK1_BASE, LPC43_AHBSRAM_BANK1_SIZE);
+# endif
-#if CONFIG_MM_REGIONS > 3 && defined(MM_DMAHEAP_BASE)
- /* Add the DMA region (which may not be available) */
+# ifdef MM_USE_AHBSRAM_BANK2
+ mem_addregion((FAR void *)MM_DMAREGION_BASE, MM_DMAREGION_SIZE);
+# endif
- kmm_addregion((FAR void *)MM_DMAHEAP_BASE, MM_DMAHEAP_SIZE);
+# ifdef MM_USE_EXTSDRAM0
+ mem_addregion((FAR void *)MM_EXTSDRAM0_REGION, MM_EXTSDRAM0_SIZE);
+# endif
-#endif /* CONFIG_MM_REGIONS > 3 && defined(MM_DMAHEAP_BASE) */
-#endif /* CONFIG_MM_REGIONS > 2 */
-#else /* MM_REGION3_BASE */
+# ifdef MM_USE_EXTSDRAM1
+ mem_addregion((FAR void *)MM_EXTSDRAM1_REGION, MM_EXTSDRAM1_SIZE);
+# endif
-#if CONFIG_MM_REGIONS > 2 && defined(MM_DMAHEAP_BASE)
- /* Add the DMA region (which may not be available) */
+# ifdef MM_USE_EXTSDRAM2
+ mem_addregion((FAR void *)MM_EXTSDRAM2_REGION, MM_EXTSDRAM2_SIZE);
+# endif
- kmm_addregion((FAR void *)MM_DMAHEAP_BASE, MM_DMAHEAP_SIZE);
-
-#endif /* CONFIG_MM_REGIONS > 3 && defined(MM_DMAHEAP_BASE) */
-#endif /* MM_REGION3_BASE */
-#endif /* CONFIG_MM_REGIONS > 1 */
+# ifdef MM_USE_EXTSDRAM3
+ mem_addregion((FAR void *)MM_EXTSDRAM3_REGION, MM_EXTSDRAM3_SIZE);
+# endif
+#endif
}
#endif
diff --git a/arch/arm/src/lpc43xx/lpc43_emc.c b/arch/arm/src/lpc43xx/lpc43_emc.c
new file mode 100644
index 00000000000..a15ecb5610d
--- /dev/null
+++ b/arch/arm/src/lpc43xx/lpc43_emc.c
@@ -0,0 +1,141 @@
+/****************************************************************************
+ * arch/arm/src/lpc43xx/lpc43_emc.c
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+
+/* TODO: add #if defined(CONFIG_LPC43_EMC) */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+
+#include
+#include
+#include
+
+#include "up_internal.h"
+
+#include "chip.h"
+#include "lpc43_pinconfig.h"
+#include "lpc43_emc.h"
+#include "chip/lpc43_creg.h"
+#include "chip/lpc43_cgu.h"
+#include "chip/lpc43_ccu.h"
+#include "lpc43_rgu.h"
+#include "lpc43_gpio.h"
+#include "up_arch.h"
+#include
+
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: lpc43_emcinit
+ *
+ * Description:
+ * Initialize EMC controller. Start in full power
+ * mode.
+ *
+ ****************************************************************************/
+void lpc43_emcinit(uint32_t enable, uint32_t clock_ratio, uint32_t endian_mode)
+{
+ uint32_t regval;
+
+ /* Enable clock for EMC controller. */
+
+ regval = getreg32(LPC43_CCU1_M4_EMC_CFG);
+ regval |= CCU_CLK_CFG_RUN;
+ putreg32(regval, LPC43_CCU1_M4_EMC_CFG);
+
+ /* Configure endian mode and clock ratio. */
+
+ regval = 0;
+ if (endian_mode)
+ regval |= EMC_CONFIG_EM;
+ if (clock_ratio)
+ regval |= EMC_CONFIG_CR;
+
+ putreg32(regval, LPC43_EMC_CONFIG);
+
+ /* Enable EMC 001 normal memory map, no low power mode. */
+
+ putreg32(EMC_CONTROL_ENA, LPC43_EMC_CONTROL);
+}
+
+/****************************************************************************
+ * Name: lpc43_lowpowermode
+ *
+ * Description:
+ * Set EMC lowpower mode.
+ *
+ ****************************************************************************/
+void lpc43_lowpowermode(uint8_t enable)
+{
+ uint32_t regval;
+
+ regval = getreg32(LPC43_EMC_CONTROL);
+ if (enable)
+ {
+ regval |= EMC_CONTROL_LOWPOWER;
+ putreg32(regval, LPC43_EMC_CONTROL);
+ }
+ else
+ {
+ regval &= ~EMC_CONTROL_LOWPOWER;
+ putreg32(regval, LPC43_EMC_CONTROL);
+ }
+}
+
+/****************************************************************************
+ * Name: lpc43_emcenable
+ *
+ * Description:
+ * Enable or disable EMC controller.
+ *
+ ****************************************************************************/
+void lpc43_emcenable(uint8_t enable)
+{
+ uint32_t regval;
+
+ regval = getreg32(LPC43_EMC_CONTROL);
+ if (enable)
+ {
+ regval |= EMC_CONTROL_ENA;
+ putreg32(regval, LPC43_EMC_CONTROL);
+ }
+ else
+ {
+ regval &= ~EMC_CONTROL_ENA;
+ putreg32(regval, LPC43_EMC_CONTROL);
+ }
+}
diff --git a/arch/arm/src/lpc43xx/lpc43_emc.h b/arch/arm/src/lpc43xx/lpc43_emc.h
index 3c2bd2496fe..77b71d86120 100644
--- a/arch/arm/src/lpc43xx/lpc43_emc.h
+++ b/arch/arm/src/lpc43xx/lpc43_emc.h
@@ -1,7 +1,7 @@
/************************************************************************************
* arch/arm/src/lpc43xx/lpc43_emc.h
*
- * Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2012, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -48,16 +48,22 @@
* Pre-processor Definitions
************************************************************************************/
-/************************************************************************************
- * Public Types
- ************************************************************************************/
+/* Chip select Definitions **********************************************************/
+
+#define EMC_CS0 0
+#define EMC_CS1 1
+#define EMC_CS2 2
+#define EMC_CS3 3
+
+#define EMC_DYNCS0 0
+#define EMC_DYNCS1 1
+#define EMC_DYNCS2 2
+#define EMC_DYNCS3 3
/************************************************************************************
- * Public Data
+ * Public Function Prototypes
************************************************************************************/
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
+void lpc43_emcinit(uint32_t enable, uint32_t clock_ratio, uint32_t endian_mode);
#endif /* __ARCH_ARM_SRC_LPC43XX_LPC43_EMC_H */
diff --git a/arch/arm/src/lpc43xx/lpc43_irq.c b/arch/arm/src/lpc43xx/lpc43_irq.c
index 26881472c8d..09680bd9e91 100644
--- a/arch/arm/src/lpc43xx/lpc43_irq.c
+++ b/arch/arm/src/lpc43xx/lpc43_irq.c
@@ -91,10 +91,6 @@ volatile uint32_t *g_current_regs[1];
extern uint32_t _vectors[];
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
/****************************************************************************
* Private Functions
****************************************************************************/
@@ -250,15 +246,9 @@ static int lpc43_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
if (irq >= LPC43_IRQ_EXTINT)
{
- n = irq - LPC43_IRQ_EXTINT;
+ n = irq - LPC43_IRQ_EXTINT;
*regaddr = NVIC_IRQ_ENABLE(n) + offset;
-
- while (n >= 32)
- {
- n -= 32;
- }
-
- *bit = 1 << n;
+ *bit = (uint32_t)1 << (n & 0x1f);
}
/* Handle processor exceptions. Only a few can be disabled */
diff --git a/arch/arm/src/lpc43xx/lpc43_spifi.c b/arch/arm/src/lpc43xx/lpc43_spifi.c
index 71920dc4775..57349370c02 100644
--- a/arch/arm/src/lpc43xx/lpc43_spifi.c
+++ b/arch/arm/src/lpc43xx/lpc43_spifi.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/lpc43/lpc43_spifi.c
*
- * Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2012, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -779,12 +779,13 @@ static ssize_t lpc43_bwrite(FAR struct mtd_dev_s *dev, off_t startblock, size_t
lpc43_cachewrite(priv, buffer, startblock, nblocks);
lpc43_dumpbuffer(__func__, buffer, nblocks << SPIFI_512SHIFT)
- return nblocks;
+ return (ssize_t)nblocks;
#else
FAR struct lpc43_dev_s *priv = (FAR struct lpc43_dev_s *)dev;
FAR uint8_t *dest;
+ int ret;
finfo("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks);
@@ -792,19 +793,17 @@ static ssize_t lpc43_bwrite(FAR struct mtd_dev_s *dev, off_t startblock, size_t
dest = SPIFI_BASE + (startblock << SPIFI_BLKSHIFT);
-#if defined(CONFIG_SPIFI_SECTOR512)
/* Write all of the erase blocks to FLASH */
- ret = lpc43_pagewrite(priv, dest, buffer, nblocks << SPIFI_512SHIFT);
+ ret = lpc43_pagewrite(priv, dest, buffer, nblocks << SPIFI_BLKSHIFT);
if (ret < 0)
{
ferr("ERROR: lpc43_pagewrite failed: %d\n", ret);
return ret;
}
-#endif
- lpc43_dumpbuffer(__func__, buffer, nblocks << SPIFI_BLKSHIFT)
- return nblocks;
+ lpc43_dumpbuffer(__func__, buffer, nblocks << SPIFI_BLKSHIFT);
+ return (ssize_t)nblocks;
#endif
}
diff --git a/arch/arm/src/sam34/chip/sam3x_memorymap.h b/arch/arm/src/sam34/chip/sam3x_memorymap.h
index e32e6ec226e..ba053d3c353 100644
--- a/arch/arm/src/sam34/chip/sam3x_memorymap.h
+++ b/arch/arm/src/sam34/chip/sam3x_memorymap.h
@@ -91,6 +91,7 @@
# define SAM_TC8_BASE 0x40088080 /* 0x40088080-0x400880bf: Timer Counter 5 */
/* 0x400880c0-0x4008ffff Reserved */
#define SAM_TWI_BASE 0x4008c000 /* 0x4008c000-0x4001ffff: Two-Wire Interface */
+# define SAM_TWIN_BASE(n) (SAM_TWI_BASE + ((n) << 14))
# define SAM_TWI0_BASE 0x4008c000 /* 0x4008c000-0x4008ffff: Two-Wire Interface 0 */
# define SAM_TWI1_BASE 0x40090000 /* 0x40090000-0x40093fff: Two-Wire Interface 1 */
#define SAM_PWM_BASE 0x40094000 /* 0x40020000-0x4003ffff: Pulse Width Modulation */
diff --git a/arch/arm/src/sam34/chip/sam4cm_memorymap.h b/arch/arm/src/sam34/chip/sam4cm_memorymap.h
index 15505238845..c0b2de041b8 100644
--- a/arch/arm/src/sam34/chip/sam4cm_memorymap.h
+++ b/arch/arm/src/sam34/chip/sam4cm_memorymap.h
@@ -77,8 +77,12 @@
#define SAM_TC3_BASE 0x40014000
#define SAM_TC4_BASE 0x40014040
#define SAM_TC5_BASE 0x40014080
+
+#define SAM_TWI_BASE 0x40018000
+#define SAM_TWIN_BASE(n) (SAM_TWI_BASE + ((n) << 14))
#define SAM_TWI0_BASE 0x40018000
#define SAM_TWI1_BASE 0x4001C000
+
#define SAM_USART0_BASE 0x40024000
#define SAM_USART1_BASE 0x40028000
#define SAM_USART2_BASE 0x4002C000
diff --git a/arch/arm/src/sam34/chip/sam4e_memorymap.h b/arch/arm/src/sam34/chip/sam4e_memorymap.h
index 95bfdef2eb7..1cf95993996 100644
--- a/arch/arm/src/sam34/chip/sam4e_memorymap.h
+++ b/arch/arm/src/sam34/chip/sam4e_memorymap.h
@@ -108,6 +108,7 @@
# define SAM_USART0_BASE 0x400a0000 /* 0x400a0000-0x400a3fff: USART0 */
# define SAM_USART1_BASE 0x400a4000 /* 0x400a4000-0x400abfff: USART1 */
#define SAM_TWI_BASE 0x400a8000 /* 0x400a8000-0x400affff: Two-Wire Interface */
+# define SAM_TWIN_BASE(n) (SAM_TWI_BASE + ((n) << 14))
# define SAM_TWI0_BASE 0x400a8000 /* 0x400a8000-0x400abfff: Two-Wire Interface 0 */
# define SAM_TWI1_BASE 0x400ac000 /* 0x400ac000-0x400affff: Two-Wire Interface 1 */
#define SAM_AFEC_BASE 0x400b0000 /* 0x400b0000-0x400b7fff: Analog Front End */
diff --git a/arch/arm/src/sam34/chip/sam4l_memorymap.h b/arch/arm/src/sam34/chip/sam4l_memorymap.h
index 56810fe442c..62a8c6a0c5c 100644
--- a/arch/arm/src/sam34/chip/sam4l_memorymap.h
+++ b/arch/arm/src/sam34/chip/sam4l_memorymap.h
@@ -82,6 +82,9 @@
/* 0x4000c000-0x4000ffff: Reserved */
#define SAM_TC0_BASE 0x40100000 /* 0x40100000-0x4013ffff: Timer Counter 0 */
#define SAM_TC1_BASE 0x40140000 /* 0x40180000-0x4017ffff: Timer Counter 1 */
+
+#define SAM_TWIMS_BASE 0x40180000 /* 0x40180000-0x401fffff: Two-wire Master/Slave */
+#define SAM_TWIN_BASE(n) (SAM_TWIMS_BASE + ((n) << 14))
#define SAM_TWIMS0_BASE 0x40180000 /* 0x40180000-0x401bffff: Two-wire Master/Slave Interface 0 */
#define SAM_TWIMS1_BASE 0x401c0000 /* 0x401c0000-0x401fffff: Two-wire Master/Slave Interface 1 */
/* 0x40020000-0x40023fff: Reserved */
diff --git a/arch/arm/src/sam34/chip/sam4s_memorymap.h b/arch/arm/src/sam34/chip/sam4s_memorymap.h
index 0ebf658866c..45e8a97a3f6 100644
--- a/arch/arm/src/sam34/chip/sam4s_memorymap.h
+++ b/arch/arm/src/sam34/chip/sam4s_memorymap.h
@@ -84,6 +84,7 @@
# define SAM_TC5_BASE 0x40014080 /* 0x40014080-0x400140bf: Timer Counter 5 */
#define SAM_TWI_BASE 0x40018000 /* 0x40018000-0x4001ffff: Two-Wire Interface */
+# define SAM_TWIN_BASE(n) (SAM_TWI_BASE + ((n) << 14))
# define SAM_TWI0_BASE 0x40018000 /* 0x40018000-0x4001bfff: Two-Wire Interface 0 */
# define SAM_TWI1_BASE 0x4001c000 /* 0x4001c000-0x4001ffff: Two-Wire Interface 1 */
#define SAM_PWM_BASE 0x40020000 /* 0x40020000-0x4003ffff: Pulse Width Modulation */
diff --git a/arch/arm/src/sam34/chip/sam_tc.h b/arch/arm/src/sam34/chip/sam_tc.h
index bb1bd15f0c1..e5951fcdc9a 100644
--- a/arch/arm/src/sam34/chip/sam_tc.h
+++ b/arch/arm/src/sam34/chip/sam_tc.h
@@ -2,7 +2,7 @@
* arch/arm/src/sam34/chip/sam_tc.h
* Timer Counter (TC) definitions for the SAM3U, SAM4E, and SAM4S
*
- * Copyright (C) 2009, 2013-2014 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2009, 2013-2014, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -537,16 +537,10 @@
# define TC_BMR_TC1XC1S_TIOA2 (3 << TC_BMR_TC1XC1S_SHIFT)
#define TC_BMR_TC2XC2S_SHIFT (4) /* Bits 4-5: External Clock Signal 2 Selection */
#define TC_BMR_TC2XC2S_MASK (3 << TC_BMR_TC2XC2S_SHIFT)
-#if defined(CONFIG_ARCH_CHIP_SAM4s) || defined(CONFIG_ARCH_CHIP_SAM4E)
-# define TC_BMR_TC2XC2S_TCLK2 (0 << TC_BMR_TC2XC2S_SHIFT)
-# define TC_BMR_TC2XC2S_TIOA1 (2 << TC_BMR_TC2XC2S_SHIFT)
-# define TC_BMR_TC2XC2S_TIOA2 (3 << TC_BMR_TC2XC2S_SHIFT)
-#else
# define TC_BMR_TC2XC2S_TCLK2 (0 << TC_BMR_TC2XC2S_SHIFT)
# define TC_BMR_TC2XC2S_NONE (1 << TC_BMR_TC2XC2S_SHIFT)
# define TC_BMR_TC2XC2S_TIOA0 (2 << TC_BMR_TC2XC2S_SHIFT)
# define TC_BMR_TC2XC2S_TIOA1 (3 << TC_BMR_TC2XC2S_SHIFT)
-#endif
#define TC_BMR_QDEN (1 << 8) /* Bit 8: Quadrature Decoder Enabled */
#define TC_BMR_POSEN (1 << 9) /* Bit 9: Position Enabled */
#define TC_BMR_SPEEDEN (1 << 10) /* Bit 10: Speed Enabled */
diff --git a/arch/arm/src/sam34/chip/sam_twi.h b/arch/arm/src/sam34/chip/sam_twi.h
index 8ad5a0f8aeb..2f843dd07c3 100644
--- a/arch/arm/src/sam34/chip/sam_twi.h
+++ b/arch/arm/src/sam34/chip/sam_twi.h
@@ -143,6 +143,7 @@
#define TWI_MMR_MREAD (1 << 12) /* Bit 12: Master Read Direction */
#define TWI_MMR_DADR_SHIFT (16) /* Bits 16-22: Device Address */
#define TWI_MMR_DADR_MASK (0x7f << TWI_MMR_DADR_SHIFT)
+# define TWI_MMR_DADR(n) ((uint32_t)(n) << TWI_MMR_DADR_SHIFT)
/* TWI Slave Mode Register */
@@ -186,6 +187,9 @@
#define TWI_INT_RXBUFF (1 << 14) /* Bit 14: RX Buffer */
#define TWI_INT_TXBUFE (1 << 15) /* Bit 15: TX Buffer Empty */
+#define TWI_INT_ERRORS (0x00000340)
+#define TWI_INT_ALL (0x0000ffff)
+
/* TWI Receive Holding Register */
#define TWI_RHR_RXDATA_SHIFT (0) /* Bits 0-7: Master or Slave Receive Holding Data */
diff --git a/arch/arm/src/sam34/sam_serial.c b/arch/arm/src/sam34/sam_serial.c
index 46df27954a1..36043e9deb8 100644
--- a/arch/arm/src/sam34/sam_serial.c
+++ b/arch/arm/src/sam34/sam_serial.c
@@ -692,8 +692,8 @@ static void up_disableallints(struct up_dev_s *priv, uint32_t *imr)
static int up_setup(struct uart_dev_s *dev)
{
- struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
#ifndef CONFIG_SUPPRESS_UART_CONFIG
+ struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
uint32_t regval;
uint32_t imr;
diff --git a/arch/arm/src/sam34/sam_udp.c b/arch/arm/src/sam34/sam_udp.c
index 6fe76f4f57b..96a521d0ba5 100644
--- a/arch/arm/src/sam34/sam_udp.c
+++ b/arch/arm/src/sam34/sam_udp.c
@@ -305,6 +305,7 @@ struct sam_ep_s
uint8_t zlpneeded:1; /* Zero length packet needed at end of transfer */
uint8_t zlpsent:1; /* Zero length packet has been sent */
uint8_t txbusy:1; /* Write request queue is busy (recursion avoidance kludge) */
+ uint8_t lastbank:1; /* Last bank we read data from */
};
struct sam_usbdev_s
@@ -1188,9 +1189,14 @@ static int sam_req_read(struct sam_usbdev_s *priv, struct sam_ep_s *privep,
/* We get here when an RXDATABK0/1 interrupt occurs. That interrupt
* cannot be cleared until all of the data has been taken from the RX
- * FIFO. But we can
+ * FIFO.
+ *
+ * Also, we need to remember which bank we read last so the interrupt handler
+ * can determine the correct bank read sequence for future reads.
*/
+ privep->lastbank = bank;
+
sam_csr_clrbits(epno, bank ? UDPEP_CSR_RXDATABK1 : UDPEP_CSR_RXDATABK0);
/* Complete the transfer immediately and give the data to the class
@@ -1873,7 +1879,6 @@ static void sam_ep_bankinterrupt(struct sam_usbdev_s *priv,
* transferred from the FIFO.
*/
- privep->epstate = UDP_EPSTATE_IDLE;
(void)sam_req_read(priv, privep, pktsize, bank);
}
@@ -1959,6 +1964,8 @@ static void sam_ep_interrupt(struct sam_usbdev_s *priv, int epno)
struct sam_ep_s *privep;
uintptr_t regaddr;
uint32_t csr;
+ bool bk0;
+ bool bk1;
DEBUGASSERT((unsigned)epno < SAM_UDP_NENDPOINTS);
@@ -2020,34 +2027,82 @@ static void sam_ep_interrupt(struct sam_usbdev_s *priv, int epno)
}
}
- /* OUT packet received in data bank 0 */
- if ((csr & UDPEP_CSR_RXDATABK0) != 0)
+ /* OUT packet received.
+ *
+ * OUT packets are received in two banks. The hardware does not provide
+ * information about which bank has been filled last. Therefore we need to
+ * keep track about which bank we read last to figure out which bank(s) we
+ * need to read next.
+ *
+ * When we get here either none, one or both banks can be filled with data.
+ * Depending on which bank we read last and which bank(s) contain data we
+ * need to correctly sequence the FIFO reads:
+ *
+ * case lastbank bk0 bk1 read sequence
+ * 1. 0 0 0 No data to read
+ * 2. 0 1 0 Only read bank 0
+ * 3. 0 0 1 Only read bank 1
+ * 4. 0 1 1 Read bank 1, then read bank 0
+ *
+ * 5. 1 0 0 No data to read
+ * 6. 1 1 0 Only read bank 0
+ * 7. 1 0 1 Only read bank 1 (should not happen)
+ * 8. 1 1 1 Read bank 0, then read bank 1
+ *
+ * lastbank will be updated in sam_req_read() after the FIFO has been read
+ * and clear RXDATABKx.
+ */
+
+ bk0 = (csr & UDPEP_CSR_RXDATABK0) != 0;
+ bk1 = (csr & UDPEP_CSR_RXDATABK1) != 0;
+
+ /* 2. and 6. - Only read bank 0 */
+
+ if (bk0 && !bk1)
{
usbtrace(TRACE_INTDECODE(SAM_TRACEINTID_RXDATABK0), (uint16_t)csr);
-
- /* Handle data received on Bank 0. sam_ep_bankinterrupt will
- * clear the RXDATABK0 interrupt once that data has been
- * transferred from the FIFO.
- */
-
sam_ep_bankinterrupt(priv, privep, csr, 0);
}
- /* OUT packet received in data bank 1 */
+ /* 3. and 7. - Only read bank 1*/
- else if ((csr & UDPEP_CSR_RXDATABK1) != 0)
+ else if (!bk0 && bk1)
{
+#ifdef CONFIG_DEBUG_USB_WARN
+ if (privep->lastbank == 1)
+ {
+ uwarn("WARNING: Unexpected USB RX case.\n");
+ }
+#endif
+
usbtrace(TRACE_INTDECODE(SAM_TRACEINTID_RXDATABK1), (uint16_t)csr);
- DEBUGASSERT(SAM_UDP_NBANKS(epno) > 1);
-
- /* Handle data received on Bank 1. sam_ep_bankinterrupt will
- * clear the RXDATABK1 interrupt once that data has been
- * transferred from the FIFO.
- */
-
sam_ep_bankinterrupt(priv, privep, csr, 1);
}
+ else if (bk0 && bk1)
+ {
+ /* 4. - Read bank 1, then read bank 0 */
+
+ if (privep->lastbank == 0)
+ {
+ usbtrace(TRACE_INTDECODE(SAM_TRACEINTID_RXDATABK1), (uint16_t)csr);
+ sam_ep_bankinterrupt(priv, privep, csr, 1);
+
+ usbtrace(TRACE_INTDECODE(SAM_TRACEINTID_RXDATABK0), (uint16_t)csr);
+ sam_ep_bankinterrupt(priv, privep, csr, 0);
+ }
+
+ /* 8. - Read bank 0, then read bank 1 */
+
+ else
+ {
+ usbtrace(TRACE_INTDECODE(SAM_TRACEINTID_RXDATABK0), (uint16_t)csr);
+ sam_ep_bankinterrupt(priv, privep, csr, 0);
+
+ usbtrace(TRACE_INTDECODE(SAM_TRACEINTID_RXDATABK1), (uint16_t)csr);
+ sam_ep_bankinterrupt(priv, privep, csr, 1);
+ }
+ }
/* STALL sent */
@@ -2510,6 +2565,7 @@ static void sam_ep_reset(struct sam_usbdev_s *priv, uint8_t epno)
privep->zlpneeded = false;
privep->zlpsent = false;
privep->txbusy = false;
+ privep->lastbank = 1;
}
/****************************************************************************
diff --git a/arch/arm/src/sama5/sam_can.c b/arch/arm/src/sama5/sam_can.c
index 3e1b3d116a1..f801e6e8341 100644
--- a/arch/arm/src/sama5/sam_can.c
+++ b/arch/arm/src/sama5/sam_can.c
@@ -60,7 +60,7 @@
#include
#include
-#include
+#include
#include "up_internal.h"
#include "up_arch.h"
diff --git a/arch/arm/src/sama5/sam_can.h b/arch/arm/src/sama5/sam_can.h
index c18361533f2..5a26fe83143 100644
--- a/arch/arm/src/sama5/sam_can.h
+++ b/arch/arm/src/sama5/sam_can.h
@@ -45,7 +45,7 @@
#include "chip.h"
#include "chip/sam_can.h"
-#include
+#include
#if defined(CONFIG_CAN) && (defined(CONFIG_SAMA5_CAN0) || defined(CONFIG_SAMA5_CAN1))
diff --git a/arch/arm/src/sama5/sam_pwm.c b/arch/arm/src/sama5/sam_pwm.c
index 0de1d91dea0..d523da24a1c 100644
--- a/arch/arm/src/sama5/sam_pwm.c
+++ b/arch/arm/src/sama5/sam_pwm.c
@@ -47,7 +47,7 @@
#include
#include
-#include
+#include
#include "chip/sam_pinmap.h"
#include
diff --git a/arch/arm/src/sama5/sam_trng.c b/arch/arm/src/sama5/sam_trng.c
index a3eb102640e..4c0f5ab1bcc 100644
--- a/arch/arm/src/sama5/sam_trng.c
+++ b/arch/arm/src/sama5/sam_trng.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/sama5/sam_trng.c
*
- * Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2013, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Derives, in part, from Max Holtzberg's STM32 RNG Nuttx driver:
@@ -52,6 +52,8 @@
#include
#include
+#include
+#include
#include "up_arch.h"
#include "up_internal.h"
@@ -59,6 +61,9 @@
#include "sam_periphclks.h"
#include "sam_trng.h"
+#if defined(CONFIG_SAMA5_TRNG)
+#if defined(CONFIG_DEV_RANDOM) || defined(CONFIG_DEV_URANDOM_ARCH)
+
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
@@ -325,14 +330,10 @@ errout:
}
/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Name: up_rnginitialize
+ * Name: sam_rng_initialize
*
* Description:
- * Initialize the TRNG hardware and register the /dev/randome driver.
+ * Initialize the TRNG hardware.
*
* Input Parameters:
* None
@@ -342,7 +343,7 @@ errout:
*
****************************************************************************/
-void up_rnginitialize(void)
+static int sam_rng_initialize(void)
{
int ret;
@@ -360,10 +361,11 @@ void up_rnginitialize(void)
/* Initialize the TRNG interrupt */
- if (irq_attach(SAM_IRQ_TRNG, sam_interrupt))
+ ret = irq_attach(SAM_IRQ_TRNG, sam_interrupt);
+ if (ret < 0)
{
ferr("ERROR: Failed to attach to IRQ%d\n", SAM_IRQ_TRNG);
- return;
+ return ret;
}
/* Disable the interrupts at the TRNG */
@@ -374,16 +376,80 @@ void up_rnginitialize(void)
putreg32(TRNG_CR_DISABLE | TRNG_CR_KEY, SAM_TRNG_CR);
- /* Register the character driver */
-
- ret = register_driver("/dev/random", &g_trngops, 0644, NULL);
- if (ret < 0)
- {
- ferr("ERROR: Failed to register /dev/random\n");
- return;
- }
-
/* Enable the TRNG interrupt at the AIC */
up_enable_irq(SAM_IRQ_TRNG);
+ return OK;
}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: devrandom_register
+ *
+ * Description:
+ * Initialize the TRNG hardware and register the /dev/random driver.
+ * Must be called BEFORE devurandom_register.
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_DEV_RANDOM
+void devrandom_register(void)
+{
+ int ret;
+
+ ret = sam_rng_initialize();
+ if (ret >= 0)
+ {
+ ret = register_driver("/dev/random", &g_trngops, 0644, NULL);
+ if (ret < 0)
+ {
+ ferr("ERROR: Failed to register /dev/random\n");
+ }
+ }
+}
+#endif
+
+/****************************************************************************
+ * Name: devurandom_register
+ *
+ * Description:
+ * Register /dev/urandom
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_DEV_URANDOM_ARCH
+void devurandom_register(void)
+{
+ int ret;
+
+#ifndef CONFIG_DEV_RANDOM
+ ret = sam_rng_initialize();
+ if (ret >= 0)
+#endif
+ {
+ ret = register_driver("/dev/urandom", &g_trngops, 0644, NULL);
+ if (ret < 0)
+ {
+ ferr("ERROR: Failed to register /dev/urandom\n");
+ }
+ }
+}
+#endif
+
+#endif /* CONFIG_DEV_RANDOM || CONFIG_DEV_URANDOM_ARCH */
+#endif /* CONFIG_SAMA5_TRNG */
diff --git a/arch/arm/src/samv7/sam_mcan.c b/arch/arm/src/samv7/sam_mcan.c
index 748b01b10b3..49e05f306b9 100644
--- a/arch/arm/src/samv7/sam_mcan.c
+++ b/arch/arm/src/samv7/sam_mcan.c
@@ -56,7 +56,7 @@
#include
#include
#include
-#include
+#include
#include "cache.h"
#include "up_internal.h"
diff --git a/arch/arm/src/samv7/sam_mcan.h b/arch/arm/src/samv7/sam_mcan.h
index 540800b37d3..07ecdd71ad3 100644
--- a/arch/arm/src/samv7/sam_mcan.h
+++ b/arch/arm/src/samv7/sam_mcan.h
@@ -45,7 +45,7 @@
#include "chip.h"
#include "chip/sam_mcan.h"
-#include
+#include
#if defined(CONFIG_CAN) && (defined(CONFIG_SAMV7_MCAN0) || \
defined(CONFIG_SAMV7_MCAN1))
diff --git a/arch/arm/src/samv7/sam_trng.c b/arch/arm/src/samv7/sam_trng.c
index 7dc29a77d83..098cf0ae68b 100644
--- a/arch/arm/src/samv7/sam_trng.c
+++ b/arch/arm/src/samv7/sam_trng.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/samv7/sam_trng.c
*
- * Copyright (C) 2015 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2015-2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Derives from the SAMA5D3 TRNG Nuttx driver which, in turn, derives, in
@@ -53,6 +53,8 @@
#include
#include
+#include
+#include
#include "up_arch.h"
#include "up_internal.h"
@@ -60,6 +62,9 @@
#include "sam_periphclks.h"
#include "sam_trng.h"
+#if defined(CONFIG_SAMV7_TRNG)
+#if defined(CONFIG_DEV_RANDOM) || defined(CONFIG_DEV_URANDOM_ARCH)
+
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
@@ -326,14 +331,10 @@ errout:
}
/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Name: up_rnginitialize
+ * Name: sam_rng_initialize
*
* Description:
- * Initialize the TRNG hardware and register the /dev/randome driver.
+ * Initialize the TRNG hardware.
*
* Input Parameters:
* None
@@ -343,7 +344,7 @@ errout:
*
****************************************************************************/
-void up_rnginitialize(void)
+static int sam_rng_initialize(void)
{
int ret;
@@ -361,10 +362,11 @@ void up_rnginitialize(void)
/* Initialize the TRNG interrupt */
- if (irq_attach(SAM_IRQ_TRNG, sam_interrupt))
+ ret = irq_attach(SAM_IRQ_TRNG, sam_interrupt);
+ if (ret < 0)
{
ferr("ERROR: Failed to attach to IRQ%d\n", SAM_IRQ_TRNG);
- return;
+ return ret;
}
/* Disable the interrupts at the TRNG */
@@ -375,16 +377,79 @@ void up_rnginitialize(void)
putreg32(TRNG_CR_DISABLE | TRNG_CR_KEY, SAM_TRNG_CR);
- /* Register the character driver */
-
- ret = register_driver("/dev/random", &g_trngops, 0644, NULL);
- if (ret < 0)
- {
- ferr("ERROR: Failed to register /dev/random\n");
- return;
- }
-
/* Enable the TRNG interrupt at the AIC */
up_enable_irq(SAM_IRQ_TRNG);
+ return OK;
}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: devrandom_register
+ *
+ * Description:
+ * Initialize the TRNG hardware and register the /dev/random driver.
+ * Must be called BEFORE devurandom_register.
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_DEV_RANDOM
+void devrandom_register(void)
+{
+ int ret;
+
+ ret = sam_rng_initialize();
+ if (ret >= 0)
+ {
+ ret = register_driver("/dev/random", &g_trngops, 0644, NULL);
+ if (ret < 0)
+ {
+ ferr("ERROR: Failed to register /dev/random\n");
+ }
+ }
+}
+#endif
+
+/****************************************************************************
+ * Name: devurandom_register
+ *
+ * Description:
+ * Register /dev/urandom
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_DEV_URANDOM_ARCH
+void devurandom_register(void)
+{
+ int ret;
+
+#ifndef CONFIG_DEV_RANDOM
+ ret = sam_rng_initialize();
+ if (ret >= 0)
+#endif
+ {
+ ret = register_driver("/dev/urandom", &g_trngops, 0644, NULL);
+ if (ret < 0)
+ {
+ ferr("ERROR: Failed to register /dev/urandom\n");
+ }
+ }
+}
+#endif
+
+#endif /* CONFIG_DEV_RANDOM || CONFIG_DEV_URANDOM_ARCH */
diff --git a/arch/arm/src/samv7/sam_usbdevhs.c b/arch/arm/src/samv7/sam_usbdevhs.c
index 07bfe1d2d4b..087db9c0e1a 100644
--- a/arch/arm/src/samv7/sam_usbdevhs.c
+++ b/arch/arm/src/samv7/sam_usbdevhs.c
@@ -301,6 +301,7 @@ enum sam_epstate_e
USBHS_EPSTATE_STALLED, /* Endpoint is stalled */
USBHS_EPSTATE_IDLE, /* Endpoint is idle (i.e. ready for transmission) */
USBHS_EPSTATE_SENDING, /* Endpoint is sending data */
+ USBHS_EPSTATE_SENDING_DMA, /* Endpoint is sending data via DMA */
USBHS_EPSTATE_NBUSYBK, /* Endpoint DMA complete, waiting for NBUSYBK==0 */
USBHS_EPSTATE_RECEIVING, /* Endpoint is receiving data */
/* --- Endpoint 0 Only --- */
@@ -1006,7 +1007,7 @@ static void sam_dma_wrsetup(struct sam_usbdev_s *priv, struct sam_ep_s *privep,
/* Switch to the sending state */
- privep->epstate = USBHS_EPSTATE_SENDING;
+ privep->epstate = USBHS_EPSTATE_SENDING_DMA;
privreq->inflight = 0;
/* Get the endpoint number */
@@ -1211,16 +1212,23 @@ static void sam_req_complete(struct sam_ep_s *privep, int16_t result)
privreq->req.result = result;
- /* Callback to the request completion handler */
-
- privreq->flink = NULL;
- privreq->req.callback(&privep->ep, &privreq->req);
-
- /* Reset the endpoint state and restore the stalled indication */
+ /* Reset the endpoint state and restore the stalled indication.
+ *
+ * At least the USB class CDC/ACM calls the function sam_ep_submit within
+ * the callback. This function uses sam_req_write or sam_req_read to process
+ * the request, both functions can change the state. Therefore it is verry
+ * important to set the state to USBHS_EPSTATE_IDLE before the callback is
+ * called.
+ */
privep->epstate = USBHS_EPSTATE_IDLE;
privep->zlpneeded = false;
privep->zlpsent = false;
+
+ /* Callback to the request completion handler */
+
+ privreq->flink = NULL;
+ privreq->req.callback(&privep->ep, &privreq->req);
}
}
@@ -2497,7 +2505,8 @@ static void sam_dma_interrupt(struct sam_usbdev_s *priv, int epno)
/* Were we sending? Or receiving? */
- if (privep->epstate == USBHS_EPSTATE_SENDING)
+ if (privep->epstate == USBHS_EPSTATE_SENDING ||
+ privep->epstate == USBHS_EPSTATE_SENDING_DMA)
{
uint32_t nbusybk;
uint32_t byct;
@@ -2923,7 +2932,8 @@ static void sam_ep_interrupt(struct sam_usbdev_s *priv, int epno)
*/
if (privep->epstate == USBHS_EPSTATE_RECEIVING ||
- privep->epstate == USBHS_EPSTATE_SENDING)
+ privep->epstate == USBHS_EPSTATE_SENDING ||
+ privep->epstate == USBHS_EPSTATE_SENDING_DMA)
{
sam_req_complete(privep, -EPROTO);
}
diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig
index 932e74c81b5..3b7a1cf8cc8 100644
--- a/arch/arm/src/stm32/Kconfig
+++ b/arch/arm/src/stm32/Kconfig
@@ -1206,7 +1206,6 @@ config STM32_CONNECTIVITYLINE
select STM32_HAVE_TIM5
select STM32_HAVE_TIM6
select STM32_HAVE_TIM7
- select STM32_HAVE_TIM8
select STM32_HAVE_ADC2
select STM32_HAVE_CAN1
select STM32_HAVE_CAN2
diff --git a/arch/arm/src/stm32/stm32_1wire.c b/arch/arm/src/stm32/stm32_1wire.c
index 4c0fa6c0f77..d0afa9d8bba 100644
--- a/arch/arm/src/stm32/stm32_1wire.c
+++ b/arch/arm/src/stm32/stm32_1wire.c
@@ -54,9 +54,9 @@
#include
#include
-#include
#include
#include
+#include
#include
diff --git a/arch/arm/src/stm32/stm32_can.c b/arch/arm/src/stm32/stm32_can.c
index 334c7337d62..ed973d57bd0 100644
--- a/arch/arm/src/stm32/stm32_can.c
+++ b/arch/arm/src/stm32/stm32_can.c
@@ -53,7 +53,7 @@
#include
#include
#include
-#include
+#include
#include "up_internal.h"
#include "up_arch.h"
diff --git a/arch/arm/src/stm32/stm32_can.h b/arch/arm/src/stm32/stm32_can.h
index e78b3af34f7..765dc95c0ca 100644
--- a/arch/arm/src/stm32/stm32_can.h
+++ b/arch/arm/src/stm32/stm32_can.h
@@ -45,7 +45,7 @@
#include "chip.h"
#include "chip/stm32_can.h"
-#include
+#include
/************************************************************************************
* Pre-processor Definitions
diff --git a/arch/arm/src/stm32/stm32_exti_alarm.c b/arch/arm/src/stm32/stm32_exti_alarm.c
index f38574f2523..2e6d582a4aa 100644
--- a/arch/arm/src/stm32/stm32_exti_alarm.c
+++ b/arch/arm/src/stm32/stm32_exti_alarm.c
@@ -53,10 +53,6 @@
#include "stm32_gpio.h"
#include "stm32_exti.h"
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
/****************************************************************************
* Private Data
****************************************************************************/
@@ -65,10 +61,6 @@
static xcpt_t stm32_exti_callback;
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
/****************************************************************************
* Private Functions
****************************************************************************/
diff --git a/arch/arm/src/stm32/stm32_irq.c b/arch/arm/src/stm32/stm32_irq.c
index ea7c4ddfcbe..ff40bf8d033 100644
--- a/arch/arm/src/stm32/stm32_irq.c
+++ b/arch/arm/src/stm32/stm32_irq.c
@@ -253,15 +253,9 @@ static int stm32_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
if (irq >= STM32_IRQ_FIRST)
{
- n = irq - STM32_IRQ_FIRST;
+ n = irq - STM32_IRQ_FIRST;
*regaddr = NVIC_IRQ_ENABLE(n) + offset;
-
- while (n >= 32)
- {
- n -= 32;
- }
-
- *bit = 1 << n;
+ *bit = (uint32_t)1 << (n & 0x1f);
}
/* Handle processor exceptions. Only a few can be disabled */
diff --git a/arch/arm/src/stm32/stm32_oneshot.c b/arch/arm/src/stm32/stm32_oneshot.c
index 8f5e89df622..a47307e7212 100644
--- a/arch/arm/src/stm32/stm32_oneshot.c
+++ b/arch/arm/src/stm32/stm32_oneshot.c
@@ -95,9 +95,10 @@ static int stm32_oneshot_handler(int irq, void *context)
* Disable the TC now and disable any further interrupts.
*/
+ STM32_TIM_SETISR(oneshot->tch, NULL, 0);
+ STM32_TIM_DISABLEINT(oneshot->tch, 0);
STM32_TIM_SETMODE(oneshot->tch, STM32_TIM_MODE_DISABLED);
STM32_TIM_ACKINT(oneshot->tch, 0);
- STM32_TIM_DISABLEINT(oneshot->tch, 0);
/* The timer is no longer running */
@@ -351,6 +352,7 @@ int stm32_oneshot_cancel(struct stm32_oneshot_s *oneshot,
/* Now we can disable the interrupt and stop the timer. */
STM32_TIM_DISABLEINT(oneshot->tch, 0);
+ STM32_TIM_SETISR(oneshot->tch, NULL, 0);
STM32_TIM_SETMODE(oneshot->tch, STM32_TIM_MODE_DISABLED);
oneshot->running = false;
diff --git a/arch/arm/src/stm32/stm32_pwm.c b/arch/arm/src/stm32/stm32_pwm.c
index 7b8f4224e08..425f256ba05 100644
--- a/arch/arm/src/stm32/stm32_pwm.c
+++ b/arch/arm/src/stm32/stm32_pwm.c
@@ -48,7 +48,7 @@
#include
#include
-#include
+#include
#include
#include "up_internal.h"
diff --git a/arch/arm/src/stm32/stm32_pwm.h b/arch/arm/src/stm32/stm32_pwm.h
index e636ead3a37..1321389046e 100644
--- a/arch/arm/src/stm32/stm32_pwm.h
+++ b/arch/arm/src/stm32/stm32_pwm.h
@@ -41,7 +41,7 @@
/* The STM32 does not have dedicated PWM hardware. Rather, pulsed output control
* is a capabilitiy of the STM32 timers. The logic in this file implements the
* lower half of the standard, NuttX PWM interface using the STM32 timers. That
- * interface is described in include/nuttx/pwm.h.
+ * interface is described in include/nuttx/drivers/pwm.h.
*/
/************************************************************************************
diff --git a/arch/arm/src/stm32/stm32_rng.c b/arch/arm/src/stm32/stm32_rng.c
index fce55ebf0a3..8dde6a6c35c 100644
--- a/arch/arm/src/stm32/stm32_rng.c
+++ b/arch/arm/src/stm32/stm32_rng.c
@@ -46,16 +46,21 @@
#include
#include
+#include
+#include
#include "up_arch.h"
#include "chip/stm32_rng.h"
#include "up_internal.h"
+#if defined(CONFIG_STM32_RNG)
+#if defined(CONFIG_DEV_RANDOM) || defined(CONFIG_DEV_URANDOM_ARCH)
+
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
-static int stm32_rnginitialize(void);
+static int stm32_rng_initialize(void);
static int stm32_interrupt(int irq, void *context);
static void stm32_enable(void);
static void stm32_disable(void);
@@ -98,7 +103,7 @@ static const struct file_operations g_rngops =
* Private functions
****************************************************************************/
-static int stm32_rnginitialize()
+static int stm32_rng_initialize()
{
uint32_t regval;
@@ -258,8 +263,52 @@ static ssize_t stm32_read(struct file *filep, char *buffer, size_t buflen)
* Public Functions
****************************************************************************/
-void up_rnginitialize()
+/****************************************************************************
+ * Name: devrandom_register
+ *
+ * Description:
+ * Initialize the RNG hardware and register the /dev/random driver.
+ * Must be called BEFORE devurandom_register.
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_DEV_RANDOM
+void devrandom_register(void)
{
- stm32_rnginitialize();
- register_driver("/dev/random", &g_rngops, 0444, NULL);
+ stm32_rng_initialize();
+ (void)register_driver("/dev/random", &g_rngops, 0444, NULL);
}
+#endif
+
+/****************************************************************************
+ * Name: devurandom_register
+ *
+ * Description:
+ * Register /dev/urandom
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_DEV_URANDOM_ARCH
+void devurandom_register(void)
+{
+#ifndef CONFIG_DEV_RANDOM
+ stm32_rng_initialize();
+#endif
+ (void)register_driver("/dev/urandom", &g_rngops, 0444, NULL);
+}
+#endif
+
+#endif /* CONFIG_DEV_RANDOM || CONFIG_DEV_URANDOM_ARCH */
+#endif /* CONFIG_STM32_RNG */
diff --git a/arch/arm/src/stm32/stm32_start.c b/arch/arm/src/stm32/stm32_start.c
index 480d5f58b46..ac16478b337 100644
--- a/arch/arm/src/stm32/stm32_start.c
+++ b/arch/arm/src/stm32/stm32_start.c
@@ -282,6 +282,12 @@ void __start(void)
showprogress('C');
+#ifdef CONFIG_ARMV7M_ITMSYSLOG
+ /* Perform ARMv7-M ITM SYSLOG initialization */
+
+ itm_syslog_initialize();
+#endif
+
/* Perform early serial initialization */
#ifdef USE_EARLYSERIALINIT
diff --git a/arch/arm/src/stm32/stm32f40xxx_rcc.c b/arch/arm/src/stm32/stm32f40xxx_rcc.c
index 3d259ec5c39..347d8a3d62b 100644
--- a/arch/arm/src/stm32/stm32f40xxx_rcc.c
+++ b/arch/arm/src/stm32/stm32f40xxx_rcc.c
@@ -919,7 +919,6 @@ static inline void rcc_itm_syslog(void)
modifyreg32(STM32_DBGMCU_CR, DBGMCU_CR_TRACEMODE_MASK, DBGMCU_CR_ASYNCH |
DBGMCU_CR_TRACEIOEN);
- itm_syslog_initialize();
}
#else
# define rcc_itm_syslog()
diff --git a/arch/arm/src/stm32/stm32f40xxx_rtcc.c b/arch/arm/src/stm32/stm32f40xxx_rtcc.c
index c20024d8b1a..7145243b894 100644
--- a/arch/arm/src/stm32/stm32f40xxx_rtcc.c
+++ b/arch/arm/src/stm32/stm32f40xxx_rtcc.c
@@ -136,6 +136,7 @@ struct alm_cbinfo_s
/* Callback to use when an EXTI is activated */
static struct alm_cbinfo_s g_alarmcb[RTC_ALARM_LAST];
+static bool g_alarm_enabled; /* True: Alarm interrupts are enabled */
#endif
/****************************************************************************
@@ -157,6 +158,7 @@ static int rtchw_set_alrmar(rtc_alarmreg_t alarmreg);
static int rtchw_check_alrbwf(void);
static int rtchw_set_alrmbr(rtc_alarmreg_t alarmreg);
#endif
+static inline void rtc_enable_alarm(void);
#endif
/****************************************************************************
@@ -811,6 +813,46 @@ rtchw_set_alrmbr_exit:
}
#endif
+/****************************************************************************
+ * Name: rtc_enable_alarm
+ *
+ * Description:
+ * Enable ALARM interrupts
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_RTC_ALARM
+static inline void rtc_enable_alarm(void)
+{
+ /* Is the alarm already enabled? */
+
+ if (!g_alarm_enabled)
+ {
+ /* Configure RTC interrupt to catch alarm interrupts. All RTC
+ * interrupts are connected to the EXTI controller. To enable the
+ * RTC Alarm interrupt, the following sequence is required:
+ *
+ * 1. Configure and enable the EXTI Line 17 RTC ALARM in interrupt
+ * mode and select the rising edge sensitivity.
+ * For STM32F4xx
+ * EXTI line 21 RTC Tamper & Timestamp
+ * EXTI line 22 RTC Wakeup
+ * 2. Configure and enable the RTC_Alarm IRQ channel in the NVIC.
+ * 3. Configure the RTC to generate RTC alarms (Alarm A or Alarm B).
+ */
+
+ stm32_exti_alarm(true, false, true, stm32_rtc_alarm_handler);
+ g_alarm_enabled = true;
+ }
+}
+#endif
+
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -1010,25 +1052,7 @@ int up_rtc_initialize(void)
return -ETIMEDOUT;
}
-#ifdef CONFIG_RTC_ALARM
- /* Configure RTC interrupt to catch alarm interrupts. All RTC interrupts
- * are connected to the EXTI controller. To enable the RTC Alarm
- * interrupt, the following sequence is required:
- *
- * 1. Configure and enable the EXTI Line 17 RTC ALARM in interrupt mode
- * and select the rising edge sensitivity.
- * For STM32F4xx
- * EXTI line 21 RTC Tamper & Timestamp
- * EXTI line 22 RTC Wakeup
- * 2. Configure and enable the RTC_Alarm IRQ channel in the NVIC.
- * 3. Configure the RTC to generate RTC alarms (Alarm A or Alarm B).
- */
-
- stm32_exti_alarm(true, false, true, stm32_rtc_alarm_handler);
- rtc_dumpregs("After InitExtiAlarm");
-#else
rtc_dumpregs("After Initialization");
-#endif
g_rtc_enabled = true;
return OK;
@@ -1321,6 +1345,10 @@ int stm32_rtc_setalarm(FAR struct alm_setalarm_s *alminfo)
ASSERT(alminfo != NULL);
DEBUGASSERT(RTC_ALARM_LAST > alminfo->as_id);
+ /* Make sure the the alarm interrupt is enabled at the NVIC */
+
+ rtc_enable_alarm();
+
/* REVISIT: Should test that the time is in the future */
rtc_dumptime(&alminfo->as_time, "New alarm time");
@@ -1335,7 +1363,7 @@ int stm32_rtc_setalarm(FAR struct alm_setalarm_s *alminfo)
(rtc_bin2bcd(alminfo->as_time.tm_hour) << RTC_ALRMR_HU_SHIFT) |
(rtc_bin2bcd(alminfo->as_time.tm_mday) << RTC_ALRMR_DU_SHIFT);
- /* Set the alarm in hardware and enable interrupts */
+ /* Set the alarm in hardware and enable interrupts from the RTC */
switch (alminfo->as_id)
{
diff --git a/arch/arm/src/stm32l4/stm32l4_can.c b/arch/arm/src/stm32l4/stm32l4_can.c
index 7891319e8f1..18b49a86e74 100644
--- a/arch/arm/src/stm32l4/stm32l4_can.c
+++ b/arch/arm/src/stm32l4/stm32l4_can.c
@@ -57,7 +57,7 @@
#include
#include
#include
-#include
+#include
#include "up_internal.h"
#include "up_arch.h"
diff --git a/arch/arm/src/stm32l4/stm32l4_can.h b/arch/arm/src/stm32l4/stm32l4_can.h
index 453b031bda2..86eb26fb659 100644
--- a/arch/arm/src/stm32l4/stm32l4_can.h
+++ b/arch/arm/src/stm32l4/stm32l4_can.h
@@ -49,7 +49,7 @@
#include "chip.h"
#include "chip/stm32l4_can.h"
-#include
+#include
/************************************************************************************
* Pre-processor Definitions
diff --git a/arch/arm/src/stm32l4/stm32l4_irq.c b/arch/arm/src/stm32l4/stm32l4_irq.c
index 8e90bf0fa8a..720c05ecc69 100644
--- a/arch/arm/src/stm32l4/stm32l4_irq.c
+++ b/arch/arm/src/stm32l4/stm32l4_irq.c
@@ -1,8 +1,7 @@
/****************************************************************************
* arch/arm/src/stm32l4/stm32l4_irq.c
- * arch/arm/src/chip/stm32l4_irq.c
*
- * Copyright (C) 2009-2015 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2009-2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -90,10 +89,6 @@ volatile uint32_t *g_current_regs[1];
extern uint32_t _vectors[];
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
/****************************************************************************
* Private Functions
****************************************************************************/
@@ -252,15 +247,9 @@ static int stm32l4_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
if (irq >= STM32L4_IRQ_FIRST)
{
- n = irq - STM32L4_IRQ_FIRST;
+ n = irq - STM32L4_IRQ_FIRST;
*regaddr = NVIC_IRQ_ENABLE(n) + offset;
-
- while (n >= 32)
- {
- n -= 32;
- }
-
- *bit = 1 << n;
+ *bit = (uint32_t)1 << (n & 0x1f);
}
/* Handle processor exceptions. Only a few can be disabled */
diff --git a/arch/arm/src/stm32l4/stm32l4_oneshot.c b/arch/arm/src/stm32l4/stm32l4_oneshot.c
index 6c8027e15cb..073ca62d423 100644
--- a/arch/arm/src/stm32l4/stm32l4_oneshot.c
+++ b/arch/arm/src/stm32l4/stm32l4_oneshot.c
@@ -96,9 +96,10 @@ static int stm32l4_oneshot_handler(int irq, FAR void *context)
* Disable the TC now and disable any further interrupts.
*/
+ STM32L4_TIM_SETISR(oneshot->tch, NULL, 0);
+ STM32L4_TIM_DISABLEINT(oneshot->tch, 0);
STM32L4_TIM_SETMODE(oneshot->tch, STM32L4_TIM_MODE_DISABLED);
STM32L4_TIM_ACKINT(oneshot->tch, 0);
- STM32L4_TIM_DISABLEINT(oneshot->tch, 0);
/* The timer is no longer running */
@@ -353,6 +354,7 @@ int stm32l4_oneshot_cancel(FAR struct stm32l4_oneshot_s *oneshot,
/* Now we can disable the interrupt and stop the timer. */
STM32L4_TIM_DISABLEINT(oneshot->tch, 0);
+ STM32L4_TIM_SETISR(oneshot->tch, NULL, 0);
STM32L4_TIM_SETMODE(oneshot->tch, STM32L4_TIM_MODE_DISABLED);
oneshot->running = false;
diff --git a/arch/arm/src/stm32l4/stm32l4_pwm.c b/arch/arm/src/stm32l4/stm32l4_pwm.c
index b5cd35fb29d..d3478ea0df2 100644
--- a/arch/arm/src/stm32l4/stm32l4_pwm.c
+++ b/arch/arm/src/stm32l4/stm32l4_pwm.c
@@ -48,7 +48,7 @@
#include
#include
-#include
+#include
#include
#include "up_internal.h"
diff --git a/arch/arm/src/stm32l4/stm32l4_pwm.h b/arch/arm/src/stm32l4/stm32l4_pwm.h
index fff04e9e476..942aef0cfa5 100644
--- a/arch/arm/src/stm32l4/stm32l4_pwm.h
+++ b/arch/arm/src/stm32l4/stm32l4_pwm.h
@@ -41,7 +41,7 @@
/* The STM32L4 does not have dedicated PWM hardware. Rather, pulsed output control
* is a capability of the STM32L4 timers. The logic in this file implements the
* lower half of the standard, NuttX PWM interface using the STM32L4 timers. That
- * interface is described in include/nuttx/pwm.h.
+ * interface is described in include/nuttx/drivers/pwm.h.
*/
/************************************************************************************
diff --git a/arch/arm/src/stm32l4/stm32l4_rng.c b/arch/arm/src/stm32l4/stm32l4_rng.c
index f9324fb6f1e..a544847061b 100644
--- a/arch/arm/src/stm32l4/stm32l4_rng.c
+++ b/arch/arm/src/stm32l4/stm32l4_rng.c
@@ -47,18 +47,21 @@
#include
#include
+#include
+#include
#include "up_arch.h"
#include "chip/stm32l4_rng.h"
#include "up_internal.h"
-#ifdef CONFIG_STM32L4_RNG
+#if defined(CONFIG_STM32L4_RNG)
+#if defined(CONFIG_DEV_RANDOM) || defined(CONFIG_DEV_URANDOM_ARCH)
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
-static int stm32l4_rnginitialize(void);
+static int stm32l4_rng_initialize(void);
static int stm32l4_rnginterrupt(int irq, void *context);
static void stm32l4_rngenable(void);
static void stm32l4_rngdisable(void);
@@ -105,7 +108,7 @@ static const struct file_operations g_rngops =
* Private functions
****************************************************************************/
-static int stm32l4_rnginitialize(void)
+static int stm32l4_rng_initialize(void)
{
_info("Initializing RNG\n");
@@ -289,10 +292,52 @@ static ssize_t stm32l4_rngread(struct file *filep, char *buffer, size_t buflen)
* Public Functions
****************************************************************************/
-void up_rnginitialize(void)
-{
- stm32l4_rnginitialize();
- register_driver("/dev/random", &g_rngops, 0444, NULL);
-}
+/****************************************************************************
+ * Name: devrandom_register
+ *
+ * Description:
+ * Initialize the RNG hardware and register the /dev/random driver.
+ * Must be called BEFORE devurandom_register.
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+#ifdef CONFIG_DEV_RANDOM
+void devrandom_register(void)
+{
+ stm32l4_rng_initialize();
+ (void)register_driver("/dev/random", &g_rngops, 0444, NULL);
+}
+#endif
+
+/****************************************************************************
+ * Name: devurandom_register
+ *
+ * Description:
+ * Register /dev/urandom
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_DEV_URANDOM_ARCH
+void devurandom_register(void)
+{
+#ifndef CONFIG_DEV_RANDOM
+ stm32l4_rng_initialize();
+#endif
+ (void)register_driver("/dev/urandom", &g_rngops, 0444, NULL);
+}
+#endif
+
+#endif /* CONFIG_DEV_RANDOM || CONFIG_DEV_URANDOM_ARCH */
#endif /* CONFIG_STM32L4_RNG */
diff --git a/arch/arm/src/stm32l4/stm32l4_rtcc.c b/arch/arm/src/stm32l4/stm32l4_rtcc.c
index 338d9a54076..1ee4306080f 100644
--- a/arch/arm/src/stm32l4/stm32l4_rtcc.c
+++ b/arch/arm/src/stm32l4/stm32l4_rtcc.c
@@ -1,7 +1,7 @@
/************************************************************************************
* arch/arm/src/stm32l4/stm32l4_rtcc.c
*
- * Copyright (C) 2012-2015 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2012-2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
* dev@ziggurat29.com (adaptations to stm32l4)
*
@@ -134,6 +134,7 @@ struct alm_cbinfo_s
/* Callback to use when an EXTI is activated */
static struct alm_cbinfo_s g_alarmcb[RTC_ALARM_LAST];
+static bool g_alarm_enabled; /* True: Alarm interrupts are enabled */
#endif
/************************************************************************************
@@ -153,6 +154,7 @@ static int rtchw_check_alrawf(void);
static int rtchw_check_alrbwf(void);
static int rtchw_set_alrmar(rtc_alarmreg_t alarmreg);
static int rtchw_set_alrmbr(rtc_alarmreg_t alarmreg);
+static inline void rtc_enable_alarm(void);
#endif
/************************************************************************************
@@ -234,31 +236,6 @@ static void rtc_dumptime(FAR const struct tm *tp, FAR const char *msg)
# define rtc_dumptime(tp, msg)
#endif
-/************************************************************************************
- * Name: rtc_is_inits
- *
- * Description:
- * Returns 'true' if the RTC has been initialized (according to the RTC itself).
- * It will be 'false' if the RTC has never been initialized since first time power
- * up, and the counters are stopped until it is first initialized.
- *
- * Input Parameters:
- * None
- *
- * Returned Value:
- * bool -- true if the INITS flag is set in the ISR.
- *
- ************************************************************************************/
-
-bool rtc_is_inits(void)
-{
- uint32_t regval;
-
- regval = getreg32(STM32L4_RTC_ISR);
-
- return (regval & RTC_ISR_INITS) ? true : false;
-}
-
/************************************************************************************
* Name: rtc_wprunlock
*
@@ -791,10 +768,74 @@ rtchw_set_alrmbr_exit:
}
#endif
+/****************************************************************************
+ * Name: rtc_enable_alarm
+ *
+ * Description:
+ * Enable ALARM interrupts
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_RTC_ALARM
+static inline void rtc_enable_alarm(void)
+{
+ /* Is the alarm already enabled? */
+
+ if (!g_alarm_enabled)
+ {
+ /* Configure RTC interrupt to catch alarm interrupts. All RTC
+ * interrupts are connected to the EXTI controller. To enable the
+ * RTC Alarm interrupt, the following sequence is required:
+ *
+ * 1. Configure and enable the EXTI Line 18 in interrupt mode and
+ * select the rising edge sensitivity.
+ * EXTI line 19 RTC Tamper or Timestamp or CSS_LSE
+ * EXTI line 20 RTC Wakeup
+ * 2. Configure and enable the RTC_Alarm IRQ channel in the NVIC.
+ * 3. Configure the RTC to generate RTC alarms (Alarm A or Alarm B).
+ */
+
+ stm32l4_exti_alarm(true, false, true, stm32l4_rtc_alarm_handler);
+ g_alarm_enabled = true;
+ }
+}
+#endif
+
/************************************************************************************
* Public Functions
************************************************************************************/
+/************************************************************************************
+ * Name: rtc_is_inits
+ *
+ * Description:
+ * Returns 'true' if the RTC has been initialized (according to the RTC itself).
+ * It will be 'false' if the RTC has never been initialized since first time power
+ * up, and the counters are stopped until it is first initialized.
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * bool -- true if the INITS flag is set in the ISR.
+ *
+ ************************************************************************************/
+
+bool rtc_is_inits(void)
+{
+ uint32_t regval;
+
+ regval = getreg32(STM32L4_RTC_ISR);
+
+ return (regval & RTC_ISR_INITS) ? true : false;
+}
+
/************************************************************************************
* Name: up_rtc_initialize
*
@@ -949,22 +990,6 @@ int up_rtc_initialize(void)
(void)stm32l4_pwr_enablebkp(false);
}
-#ifdef CONFIG_RTC_ALARM
- /* Configure RTC interrupt to catch alarm interrupts. All RTC interrupts are
- * connected to the EXTI controller. To enable the RTC Alarm interrupt, the
- * following sequence is required:
- *
- * 1. Configure and enable the EXTI Line 18 in interrupt mode and select the
- * rising edge sensitivity.
- * EXTI line 19 RTC Tamper or Timestamp or CSS_LSE
- * EXTI line 20 RTC Wakeup
- * 2. Configure and enable the RTC_Alarm IRQ channel in the NVIC.
- * 3. Configure the RTC to generate RTC alarms (Alarm A or Alarm B).
- */
-
- stm32l4_exti_alarm(true, false, true, stm32l4_rtc_alarm_handler);
-#endif
-
g_rtc_enabled = true;
rtc_dumpregs("After Initialization");
@@ -1241,6 +1266,10 @@ int stm32l4_rtc_setalarm(FAR struct alm_setalarm_s *alminfo)
ASSERT(alminfo != NULL);
DEBUGASSERT(RTC_ALARM_LAST > alminfo->as_id);
+ /* Make sure the the alarm interrupt is enabled at the NVIC */
+
+ rtc_enable_alarm();
+
/* REVISIT: Should test that the time is in the future */
rtc_dumptime(&alminfo->as_time, "New alarm time");
@@ -1249,7 +1278,7 @@ int stm32l4_rtc_setalarm(FAR struct alm_setalarm_s *alminfo)
alarmreg = rtc_reg_alrmr_bin2bcd(&alminfo->as_time);
- /* Set the alarm in hardware and enable interrupts */
+ /* Set the alarm in hardware and enable interrupts from the RTC */
switch (alminfo->as_id)
{
diff --git a/arch/arm/src/stm32l4/stm32l4_serial.c b/arch/arm/src/stm32l4/stm32l4_serial.c
index 548d1e19571..e85e73a3e35 100644
--- a/arch/arm/src/stm32l4/stm32l4_serial.c
+++ b/arch/arm/src/stm32l4/stm32l4_serial.c
@@ -139,65 +139,27 @@
/* DMA priority */
# ifndef CONFIG_USART_DMAPRIO
-# if defined(CONFIG_STM32L4_STM32L15XX) || defined(CONFIG_STM32L4_STM32F10XX) || \
- defined(CONFIG_STM32L4_STM32F30XX) || defined(CONFIG_STM32L4_STM32F37XX)
-# define CONFIG_USART_DMAPRIO DMA_CCR_PRIMED
-# elif defined(CONFIG_STM32L4_STM32F20XX) || defined(CONFIG_STM32L4_STM32F40XX)
-# define CONFIG_USART_DMAPRIO DMA_SCR_PRIMED
-# else
-# error "Unknown STM32 DMA"
-# endif
+# define CONFIG_USART_DMAPRIO DMA_CCR_PRIMED
# endif
-# if defined(CONFIG_STM32L4_STM32L15XX) || defined(CONFIG_STM32L4_STM32F10XX) || \
- defined(CONFIG_STM32L4_STM32F30XX) || defined(CONFIG_STM32L4_STM32F37XX)
-# if (CONFIG_USART_DMAPRIO & ~DMA_CCR_PL_MASK) != 0
-# error "Illegal value for CONFIG_USART_DMAPRIO"
-# endif
-# elif defined(CONFIG_STM32L4_STM32F20XX) || defined(CONFIG_STM32L4_STM32F40XX)
-# if (CONFIG_USART_DMAPRIO & ~DMA_SCR_PL_MASK) != 0
-# error "Illegal value for CONFIG_USART_DMAPRIO"
-# endif
-# else
-# error "Unknown STM32 DMA"
+# if (CONFIG_USART_DMAPRIO & ~DMA_CCR_PL_MASK) != 0
+# error "Illegal value for CONFIG_USART_DMAPRIO"
# endif
/* DMA control words */
-# if defined(CONFIG_STM32L4_STM32F20XX) || defined(CONFIG_STM32L4_STM32F40XX)
-# define SERIAL_DMA_CONTROL_WORD \
- (DMA_SCR_DIR_P2M | \
- DMA_SCR_CIRC | \
- DMA_SCR_MINC | \
- DMA_SCR_PSIZE_8BITS | \
- DMA_SCR_MSIZE_8BITS | \
- CONFIG_USART_DMAPRIO | \
- DMA_SCR_PBURST_SINGLE | \
- DMA_SCR_MBURST_SINGLE)
-# ifdef CONFIG_SERIAL_IFLOWCONTROL
-# define SERIAL_DMA_IFLOW_CONTROL_WORD \
- (DMA_SCR_DIR_P2M | \
- DMA_SCR_MINC | \
- DMA_SCR_PSIZE_8BITS | \
- DMA_SCR_MSIZE_8BITS | \
- CONFIG_USART_DMAPRIO | \
- DMA_SCR_PBURST_SINGLE | \
- DMA_SCR_MBURST_SINGLE)
-# endif
-# else
-# define SERIAL_DMA_CONTROL_WORD \
- (DMA_CCR_CIRC | \
- DMA_CCR_MINC | \
- DMA_CCR_PSIZE_8BITS | \
- DMA_CCR_MSIZE_8BITS | \
- CONFIG_USART_DMAPRIO)
-# ifdef CONFIG_SERIAL_IFLOWCONTROL
-# define SERIAL_DMA_IFLOW_CONTROL_WORD \
- (DMA_CCR_MINC | \
- DMA_CCR_PSIZE_8BITS | \
- DMA_CCR_MSIZE_8BITS | \
- CONFIG_USART_DMAPRIO)
-# endif
-# endif
+# define SERIAL_DMA_CONTROL_WORD \
+ (DMA_CCR_CIRC | \
+ DMA_CCR_MINC | \
+ DMA_CCR_PSIZE_8BITS | \
+ DMA_CCR_MSIZE_8BITS | \
+ CONFIG_USART_DMAPRIO)
+# ifdef CONFIG_SERIAL_IFLOWCONTROL
+# define SERIAL_DMA_IFLOW_CONTROL_WORD \
+ (DMA_CCR_MINC | \
+ DMA_CCR_PSIZE_8BITS | \
+ DMA_CCR_MSIZE_8BITS | \
+ CONFIG_USART_DMAPRIO)
+# endif
#endif
@@ -1590,12 +1552,11 @@ static int up_interrupt_common(FAR struct stm32l4_serial_s *priv)
static int stm32l4serial_ioctl(FAR struct file *filep, int cmd,
unsigned long arg)
{
-#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT) \
- || defined(CONFIG_STM32F7_SERIALBRK_BSDCOMPAT)
+#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT)
FAR struct inode *inode = filep->f_inode;
FAR struct uart_dev_s *dev = inode->i_private;
#endif
-#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_STM32F7_SERIALBRK_BSDCOMPAT)
+#if defined(CONFIG_SERIAL_TERMIOS)
FAR struct stm32l4_serial_s *priv = (FAR struct stm32l4_serial_s *)dev->priv;
#endif
int ret = OK;
@@ -1619,6 +1580,7 @@ static int stm32l4serial_ioctl(FAR struct file *filep, int cmd,
#endif
#ifdef CONFIG_STM32L4_USART_SINGLEWIRE
+#warning please review the potential use of ALTERNATE_FUNCTION_OPENDRAIN
case TIOCSSINGLEWIRE:
{
/* Change the TX port to be open-drain/push-pull and enable/disable
@@ -1627,18 +1589,6 @@ static int stm32l4serial_ioctl(FAR struct file *filep, int cmd,
uint32_t cr = stm32l4serial_getreg(priv, STM32L4_USART_CR3_OFFSET);
-#if defined(CONFIG_STM32L4_STM32F10XX)
- if (arg == SER_SINGLEWIRE_ENABLED)
- {
- stm32l4_configgpio((priv->tx_gpio & ~(GPIO_CNF_MASK)) | GPIO_CNF_AFOD);
- cr |= USART_CR3_HDSEL;
- }
- else
- {
- stm32l4_configgpio((priv->tx_gpio & ~(GPIO_CNF_MASK)) | GPIO_CNF_AFPP);
- cr &= ~USART_CR3_HDSEL;
- }
-#else
if (arg == SER_SINGLEWIRE_ENABLED)
{
stm32l4_configgpio(priv->tx_gpio | GPIO_OPENDRAIN);
@@ -1649,7 +1599,6 @@ static int stm32l4serial_ioctl(FAR struct file *filep, int cmd,
stm32l4_configgpio(priv->tx_gpio | GPIO_PUSHPULL);
cr &= ~USART_CR3_HDSEL;
}
-#endif
stm32l4serial_putreg(priv, STM32L4_USART_CR3_OFFSET, cr);
}
@@ -2484,7 +2433,7 @@ void up_earlyserialinit(void)
*
****************************************************************************/
-void stm32l4serial_getregit(void)
+void up_serialinit(void)
{
#ifdef HAVE_UART
char devname[16];
diff --git a/arch/arm/src/tiva/chip/tm4c_pinmap.h b/arch/arm/src/tiva/chip/tm4c_pinmap.h
index ec9bceca5de..5d32959f062 100644
--- a/arch/arm/src/tiva/chip/tm4c_pinmap.h
+++ b/arch/arm/src/tiva/chip/tm4c_pinmap.h
@@ -1186,34 +1186,34 @@
# define GPIO_HIB_RTCCLK_2 (GPIO_FUNC_PFOUTPUT | GPIO_ALT_5 | GPIO_PORTK | GPIO_PIN_7)
# define GPIO_HIB_RTCCLK_3 (GPIO_FUNC_PFOUTPUT | GPIO_ALT_7 | GPIO_PORTP | GPIO_PIN_3)
-# define GPIO_I2C0_SCL (GPIO_FUNC_PFODIO | GPIO_ALT_2 | GPIO_PORTB | GPIO_PIN_2 | GPIO_PADTYPE_ODWPU)
+# define GPIO_I2C0_SCL (GPIO_FUNC_PFOUTPUT | GPIO_ALT_2 | GPIO_PORTB | GPIO_PIN_2)
# define GPIO_I2C0_SDA (GPIO_FUNC_PFODIO | GPIO_ALT_2 | GPIO_PORTB | GPIO_PIN_3 | GPIO_PADTYPE_ODWPU)
-# define GPIO_I2C1_SCL (GPIO_FUNC_PFODIO | GPIO_ALT_2 | GPIO_PORTG | GPIO_PIN_0 | GPIO_PADTYPE_ODWPU)
+# define GPIO_I2C1_SCL (GPIO_FUNC_PFOUTPUT | GPIO_ALT_2 | GPIO_PORTG | GPIO_PIN_0)
# define GPIO_I2C1_SDA (GPIO_FUNC_PFODIO | GPIO_ALT_2 | GPIO_PORTG | GPIO_PIN_1 | GPIO_PADTYPE_ODWPU)
-# define GPIO_I2C2_SCL_1 (GPIO_FUNC_PFODIO | GPIO_ALT_2 | GPIO_PORTL | GPIO_PIN_1 | GPIO_PADTYPE_ODWPU)
-# define GPIO_I2C2_SCL_2 (GPIO_FUNC_PFODIO | GPIO_ALT_3 | GPIO_PORTN | GPIO_PIN_5 | GPIO_PADTYPE_ODWPU)
-# define GPIO_I2C2_SCL_3 (GPIO_FUNC_PFODIO | GPIO_ALT_2 | GPIO_PORTP | GPIO_PIN_5 | GPIO_PADTYPE_ODWPU)
+# define GPIO_I2C2_SCL_1 (GPIO_FUNC_PFOUTPUT | GPIO_ALT_2 | GPIO_PORTL | GPIO_PIN_1)
+# define GPIO_I2C2_SCL_2 (GPIO_FUNC_PFOUTPUT | GPIO_ALT_2 | GPIO_PORTP | GPIO_PIN_5)
+# define GPIO_I2C2_SCL_3 (GPIO_FUNC_PFOUTPUT | GPIO_ALT_3 | GPIO_PORTN | GPIO_PIN_5)
# define GPIO_I2C2_SDA_1 (GPIO_FUNC_PFODIO | GPIO_ALT_2 | GPIO_PORTL | GPIO_PIN_0 | GPIO_PADTYPE_ODWPU)
# define GPIO_I2C2_SDA_2 (GPIO_FUNC_PFODIO | GPIO_ALT_3 | GPIO_PORTN | GPIO_PIN_4 | GPIO_PADTYPE_ODWPU)
-# define GPIO_I2C3_SCL (GPIO_FUNC_PFODIO | GPIO_ALT_2 | GPIO_PORTK | GPIO_PIN_4 | GPIO_PADTYPE_ODWPU)
+# define GPIO_I2C3_SCL (GPIO_FUNC_PFOUTPUT | GPIO_ALT_2 | GPIO_PORTK | GPIO_PIN_4)
# define GPIO_I2C3_SDA (GPIO_FUNC_PFODIO | GPIO_ALT_2 | GPIO_PORTK | GPIO_PIN_5 | GPIO_PADTYPE_ODWPU)
-# define GPIO_I2C4_SCL (GPIO_FUNC_PFODIO | GPIO_ALT_2 | GPIO_PORTK | GPIO_PIN_6 | GPIO_PADTYPE_ODWPU)
+# define GPIO_I2C4_SCL (GPIO_FUNC_PFOUTPUT | GPIO_ALT_2 | GPIO_PORTK | GPIO_PIN_6)
# define GPIO_I2C4_SDA (GPIO_FUNC_PFODIO | GPIO_ALT_2 | GPIO_PORTK | GPIO_PIN_7 | GPIO_PADTYPE_ODWPU)
-# define GPIO_I2C5_SCL_1 (GPIO_FUNC_PFODIO | GPIO_ALT_2 | GPIO_PORTB | GPIO_PIN_0 | GPIO_PADTYPE_ODWPU)
-# define GPIO_I2C5_SCL_2 (GPIO_FUNC_PFODIO | GPIO_ALT_2 | GPIO_PORTB | GPIO_PIN_4 | GPIO_PADTYPE_ODWPU)
+# define GPIO_I2C5_SCL_1 (GPIO_FUNC_PFOUTPUT | GPIO_ALT_2 | GPIO_PORTB | GPIO_PIN_0)
+# define GPIO_I2C5_SCL_2 (GPIO_FUNC_PFOUTPUT | GPIO_ALT_2 | GPIO_PORTB | GPIO_PIN_4)
# define GPIO_I2C5_SDA_1 (GPIO_FUNC_PFODIO | GPIO_ALT_2 | GPIO_PORTB | GPIO_PIN_1 | GPIO_PADTYPE_ODWPU)
# define GPIO_I2C5_SDA_2 (GPIO_FUNC_PFODIO | GPIO_ALT_2 | GPIO_PORTB | GPIO_PIN_5 | GPIO_PADTYPE_ODWPU)
-# define GPIO_I2C6_SCL (GPIO_FUNC_PFODIO | GPIO_ALT_2 | GPIO_PORTA | GPIO_PIN_6 | GPIO_PADTYPE_ODWPU)
+# define GPIO_I2C6_SCL (GPIO_FUNC_PFOUTPUT | GPIO_ALT_2 | GPIO_PORTA | GPIO_PIN_6)
# define GPIO_I2C6_SDA (GPIO_FUNC_PFODIO | GPIO_ALT_2 | GPIO_PORTA | GPIO_PIN_7 | GPIO_PADTYPE_ODWPU)
-# define GPIO_I2C7_SCL_1 (GPIO_FUNC_PFODIO | GPIO_ALT_2 | GPIO_PORTA | GPIO_PIN_4 | GPIO_PADTYPE_ODWPU)
-# define GPIO_I2C7_SCL_2 (GPIO_FUNC_PFODIO | GPIO_ALT_2 | GPIO_PORTD | GPIO_PIN_0 | GPIO_PADTYPE_ODWPU)
-# define GPIO_I2C7_SDA_1 (GPIO_FUNC_PFODIO | GPIO_ALT_2 | GPIO_PORTA | GPIO_PIN_5 | GPIO_PADTYPE_ODWPU)
-# define GPIO_I2C7_SDA_2 (GPIO_FUNC_PFODIO | GPIO_ALT_2 | GPIO_PORTD | GPIO_PIN_1 | GPIO_PADTYPE_ODWPU)
-# define GPIO_I2C8_SCL_1 (GPIO_FUNC_PFODIO | GPIO_ALT_2 | GPIO_PORTA | GPIO_PIN_2 | GPIO_PADTYPE_ODWPU)
-# define GPIO_I2C8_SCL_2 (GPIO_FUNC_PFODIO | GPIO_ALT_2 | GPIO_PORTD | GPIO_PIN_2 | GPIO_PADTYPE_ODWPU)
-# define GPIO_I2C8_SDA_1 (GPIO_FUNC_PFODIO | GPIO_ALT_2 | GPIO_PORTA | GPIO_PIN_3 | GPIO_PADTYPE_ODWPU)
-# define GPIO_I2C8_SDA_2 (GPIO_FUNC_PFODIO | GPIO_ALT_2 | GPIO_PORTD | GPIO_PIN_3 | GPIO_PADTYPE_ODWPU)
-# define GPIO_I2C9_SCL (GPIO_FUNC_PFODIO | GPIO_ALT_2 | GPIO_PORTA | GPIO_PIN_0 | GPIO_PADTYPE_ODWPU)
+# define GPIO_I2C7_SCL_1 (GPIO_FUNC_PFOUTPUT | GPIO_ALT_2 | GPIO_PORTD | GPIO_PIN_0)
+# define GPIO_I2C7_SCL_2 (GPIO_FUNC_PFOUTPUT | GPIO_ALT_2 | GPIO_PORTA | GPIO_PIN_4)
+# define GPIO_I2C7_SDA_1 (GPIO_FUNC_PFODIO | GPIO_ALT_2 | GPIO_PORTD | GPIO_PIN_1 | GPIO_PADTYPE_ODWPU)
+# define GPIO_I2C7_SDA_2 (GPIO_FUNC_PFODIO | GPIO_ALT_2 | GPIO_PORTA | GPIO_PIN_5 | GPIO_PADTYPE_ODWPU)
+# define GPIO_I2C8_SCL_1 (GPIO_FUNC_PFOUTPUT | GPIO_ALT_2 | GPIO_PORTD | GPIO_PIN_2)
+# define GPIO_I2C8_SCL_2 (GPIO_FUNC_PFOUTPUT | GPIO_ALT_2 | GPIO_PORTA | GPIO_PIN_2)
+# define GPIO_I2C8_SDA_1 (GPIO_FUNC_PFODIO | GPIO_ALT_2 | GPIO_PORTD | GPIO_PIN_3 | GPIO_PADTYPE_ODWPU)
+# define GPIO_I2C8_SDA_2 (GPIO_FUNC_PFODIO | GPIO_ALT_2 | GPIO_PORTA | GPIO_PIN_3 | GPIO_PADTYPE_ODWPU)
+# define GPIO_I2C9_SCL (GPIO_FUNC_PFOUTPUT | GPIO_ALT_2 | GPIO_PORTA | GPIO_PIN_0)
# define GPIO_I2C9_SDA (GPIO_FUNC_PFODIO | GPIO_ALT_2 | GPIO_PORTA | GPIO_PIN_1 | GPIO_PADTYPE_ODWPU)
# define GPIO_JTAG_SWCLK (GPIO_FUNC_PFINPUT | GPIO_ALT_1 | GPIO_PORTC | GPIO_PIN_0)
diff --git a/arch/avr/src/common/up_initialize.c b/arch/avr/src/common/up_initialize.c
index 669821631c0..55a9b167530 100644
--- a/arch/avr/src/common/up_initialize.c
+++ b/arch/avr/src/common/up_initialize.c
@@ -43,13 +43,16 @@
#include
#include
-#include
+#include
#include
#include
#include
#include
#include
#include
+#include
+#include
+#include
#include
@@ -199,11 +202,21 @@ void up_initialize(void)
up_irqinitialize();
- /* Initialize the DMA subsystem if the weak function stm32_dmainitialize has been
+#ifdef CONFIG_PM
+ /* Initialize the power management subsystem. This MCU-specific function
+ * must be called *very* early in the initialization sequence *before* any
+ * other device drivers are initialized (since they may attempt to register
+ * with the power management subsystem).
+ */
+
+ up_pminitialize();
+#endif
+
+#ifdef CONFIG_ARCH_DMA
+ /* Initialize the DMA subsystem if the weak function up_dmainitialize has been
* brought into the build
*/
-#ifdef CONFIG_ARCH_DMA
#ifdef CONFIG_HAVE_WEAKFUNCTIONS
if (up_dmainitialize)
#endif
@@ -226,6 +239,14 @@ void up_initialize(void)
devnull_register(); /* Standard /dev/null */
#endif
+#if defined(CONFIG_DEV_RANDOM)
+ devrandom_register(); /* Standard /dev/random */
+#endif
+
+#if defined(CONFIG_DEV_URANDOM)
+ devurandom_register(); /* Standard /dev/urandom */
+#endif
+
#if defined(CONFIG_DEV_ZERO)
devzero_register(); /* Standard /dev/zero */
#endif
@@ -258,6 +279,12 @@ void up_initialize(void)
ramlog_consoleinit();
#endif
+#if CONFIG_NFILE_DESCRIPTORS > 0 && defined(CONFIG_PSEUDOTERM_SUSV1)
+ /* Register the master pseudo-terminal multiplexor device */
+
+ (void)ptmx_register();
+#endif
+
/* Early initialization of the system logging device. Some SYSLOG channel
* can be initialized early in the initialization sequence because they
* depend on only minimal OS initialization.
@@ -265,6 +292,16 @@ void up_initialize(void)
syslog_initialize(SYSLOG_INIT_EARLY);
+#if defined(CONFIG_CRYPTO)
+ /* Initialize the HW crypto and /dev/crypto */
+
+ up_cryptoinitialize();
+#endif
+
+#if CONFIG_NFILE_DESCRIPTORS > 0 && defined(CONFIG_CRYPTO_CRYPTODEV)
+ devcrypto_register();
+#endif
+
#ifndef CONFIG_NETDEV_LATEINIT
/* Initialize the network */
diff --git a/arch/hc/include/m9s12/irq.h b/arch/hc/include/m9s12/irq.h
index 63ab556b8e4..d70e40de349 100644
--- a/arch/hc/include/m9s12/irq.h
+++ b/arch/hc/include/m9s12/irq.h
@@ -108,7 +108,7 @@
* Port J: Pins 0-3 and 6-7
*/
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_HCS12_GPIOIRQ
/* To conserve space, interrupts must also be configured, port by port */
@@ -156,7 +156,7 @@
# endif
#else
# define HCS12_IRQ_NIRQS HCS12_IRQ_NVECTORS
-#endif /* CONFIG_GPIO_IRQ */
+#endif /* CONFIG_HCS12_GPIOIRQ */
#define HCS12_IRQ_VILLEGAL HCS12_IRQ_NIRQS /* Any reserved vector */
#define NR_IRQS (HCS12_IRQ_NIRQS+1)
diff --git a/arch/hc/src/common/up_initialize.c b/arch/hc/src/common/up_initialize.c
index c5b1149d04a..1d75e24baf9 100644
--- a/arch/hc/src/common/up_initialize.c
+++ b/arch/hc/src/common/up_initialize.c
@@ -44,13 +44,16 @@
#include
#include
#include
-#include
+#include
#include
#include
#include
#include
#include
#include
+#include
+#include
+#include
#include "up_arch.h"
#include "up_internal.h"
@@ -125,11 +128,21 @@ void up_initialize(void)
up_irqinitialize();
- /* Initialize the DMA subsystem if the weak function stm32_dmainitialize has been
+#ifdef CONFIG_PM
+ /* Initialize the power management subsystem. This MCU-specific function
+ * must be called *very* early in the initialization sequence *before* any
+ * other device drivers are initialized (since they may attempt to register
+ * with the power management subsystem).
+ */
+
+ up_pminitialize();
+#endif
+
+#ifdef CONFIG_ARCH_DMA
+ /* Initialize the DMA subsystem if the weak function up_dmainitialize has been
* brought into the build
*/
-#ifdef CONFIG_ARCH_DMA
#ifdef CONFIG_HAVE_WEAKFUNCTIONS
if (up_dmainitialize)
#endif
@@ -152,6 +165,14 @@ void up_initialize(void)
devnull_register(); /* Standard /dev/null */
#endif
+#if defined(CONFIG_DEV_RANDOM)
+ devrandom_register(); /* Standard /dev/random */
+#endif
+
+#if defined(CONFIG_DEV_URANDOM)
+ devurandom_register(); /* Standard /dev/urandom */
+#endif
+
#if defined(CONFIG_DEV_ZERO)
devzero_register(); /* Standard /dev/zero */
#endif
@@ -184,6 +205,12 @@ void up_initialize(void)
ramlog_consoleinit();
#endif
+#if CONFIG_NFILE_DESCRIPTORS > 0 && defined(CONFIG_PSEUDOTERM_SUSV1)
+ /* Register the master pseudo-terminal multiplexor device */
+
+ (void)ptmx_register();
+#endif
+
/* Early initialization of the system logging device. Some SYSLOG channel
* can be initialized early in the initialization sequence because they
* depend on only minimal OS initialization.
@@ -191,6 +218,16 @@ void up_initialize(void)
syslog_initialize(SYSLOG_INIT_EARLY);
+#if defined(CONFIG_CRYPTO)
+ /* Initialize the HW crypto and /dev/crypto */
+
+ up_cryptoinitialize();
+#endif
+
+#if CONFIG_NFILE_DESCRIPTORS > 0 && defined(CONFIG_CRYPTO_CRYPTODEV)
+ devcrypto_register();
+#endif
+
#ifndef CONFIG_NETDEV_LATEINIT
/* Initialize the network */
diff --git a/arch/hc/src/m9s12/Kconfig b/arch/hc/src/m9s12/Kconfig
index 9e05745e49c..37c357c79d7 100644
--- a/arch/hc/src/m9s12/Kconfig
+++ b/arch/hc/src/m9s12/Kconfig
@@ -40,4 +40,12 @@ config HCS12_NONBANKED
in memory.
endmenu # HSC12 Build Options
+
+config HCS12_GPIOIRQ
+ bool "GPIO interrupt support"
+ default n
+ depends on EXPERIMENTAL
+ ---help---
+ Enable support for GPIO interrupts (not implemented)
+
endif # ARCH_HSC12
diff --git a/arch/hc/src/m9s12/m9s12.h b/arch/hc/src/m9s12/m9s12.h
index 9a1c9711599..50e3a14abe7 100644
--- a/arch/hc/src/m9s12/m9s12.h
+++ b/arch/hc/src/m9s12/m9s12.h
@@ -266,7 +266,7 @@ bool hcs12_gpioread(uint16_t pinset);
*
************************************************************************************/
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_HCS12_GPIOIRQ
void hcs12_gpioirqenable(int irq);
#else
# define hcs12_gpioirqenable(irq)
@@ -280,7 +280,7 @@ void hcs12_gpioirqenable(int irq);
*
************************************************************************************/
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_HCS12_GPIOIRQ
void hcs12_gpioirqdisable(int irq);
#else
# define hcs12_gpioirqdisable(irq)
diff --git a/arch/hc/src/m9s12/m9s12_gpioirq.c b/arch/hc/src/m9s12/m9s12_gpioirq.c
index 4dae0551244..d16c208f4cb 100644
--- a/arch/hc/src/m9s12/m9s12_gpioirq.c
+++ b/arch/hc/src/m9s12/m9s12_gpioirq.c
@@ -75,7 +75,7 @@
*
****************************************************************************/
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_HCS12_GPIOIRQ
static int hcs12_mapirq(int irq, uint16_t *regaddr, uint8_t *pin)
{
if (irq >= HCC12_IRQ_PGFIRST)
@@ -121,7 +121,7 @@ static int hcs12_mapirq(int irq, uint16_t *regaddr, uint8_t *pin)
}
return -EINVAL;
}
-#endif /* CONFIG_GPIO_IRQ */
+#endif /* CONFIG_HCS12_GPIOIRQ */
/****************************************************************************
* Name: up_gpioa/b/cinterrupt
@@ -131,7 +131,7 @@ static int hcs12_mapirq(int irq, uint16_t *regaddr, uint8_t *pin)
*
****************************************************************************/
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_HCS12_GPIOIRQ
static int hcs12_interrupt(uint16_t base, int irq0, uint8_t valid, void *context)
{
uint8_t pending;
@@ -204,7 +204,7 @@ static int hcs12_pjinterrupt(int irq, void *context)
HCS12_IRQ_PJSET, context);
}
#endif
-#endif /* CONFIG_GPIO_IRQ */
+#endif /* CONFIG_HCS12_GPIOIRQ */
/****************************************************************************
* Public Functions
@@ -229,7 +229,7 @@ void hcs12_gpioirqinitialize(void)
/* Attach GPIO IRQ interrupt handlers */
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_HCS12_GPIOIRQ
# ifdef CONFIG_HCS12_PORTG_INTS
irq_attach(HCS12_IRQ_VPORTG, hcs12_pginterrupt);
# endif
@@ -239,7 +239,7 @@ void hcs12_gpioirqinitialize(void)
# ifdef CONFIG_HCS12_PORTJ_INTS
irq_attach(HCS12_IRQ_VPORTJ, hcs12_pjinterrupt);
# endif
-#endif /* CONFIG_GPIO_IRQ */
+#endif /* CONFIG_HCS12_GPIOIRQ */
}
/****************************************************************************
@@ -250,7 +250,7 @@ void hcs12_gpioirqinitialize(void)
*
****************************************************************************/
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_HCS12_GPIOIRQ
void hcs12_gpioirqenable(int irq)
{
uint16_t regaddr;
@@ -265,7 +265,7 @@ void hcs12_gpioirqenable(int irq)
leave_critical_section(flags);
}
}
-#endif /* CONFIG_GPIO_IRQ */
+#endif /* CONFIG_HCS12_GPIOIRQ */
/****************************************************************************
* Name: hcs12_gpioirqdisable
@@ -275,7 +275,7 @@ void hcs12_gpioirqenable(int irq)
*
****************************************************************************/
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_HCS12_GPIOIRQ
void hcs12_gpioirqdisable(int irq)
{
uint16_t regaddr;
@@ -290,5 +290,5 @@ void hcs12_gpioirqdisable(int irq)
leave_critical_section(flags);
}
}
-#endif /* CONFIG_GPIO_IRQ */
+#endif /* CONFIG_HCS12_GPIOIRQ */
diff --git a/arch/hc/src/m9s12/m9s12_irq.c b/arch/hc/src/m9s12/m9s12_irq.c
index a91c270f099..4ce19d70e90 100644
--- a/arch/hc/src/m9s12/m9s12_irq.c
+++ b/arch/hc/src/m9s12/m9s12_irq.c
@@ -75,7 +75,7 @@ void up_irqinitialize(void)
* GPIO pins.
*/
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_HCS12_GPIOIRQ
hcs12_gpioirqinitialize();
#endif
diff --git a/arch/mips/src/common/up_initialize.c b/arch/mips/src/common/up_initialize.c
index d6d634c9bc7..609ce62f826 100644
--- a/arch/mips/src/common/up_initialize.c
+++ b/arch/mips/src/common/up_initialize.c
@@ -44,13 +44,16 @@
#include
#include
#include
-#include
+#include
#include
#include
#include
#include
#include
#include
+#include
+#include
+#include
#include
@@ -127,11 +130,21 @@ void up_initialize(void)
up_irqinitialize();
- /* Initialize the DMA subsystem if the weak function stm32_dmainitialize has been
+#ifdef CONFIG_PM
+ /* Initialize the power management subsystem. This MCU-specific function
+ * must be called *very* early in the initialization sequence *before* any
+ * other device drivers are initialized (since they may attempt to register
+ * with the power management subsystem).
+ */
+
+ up_pminitialize();
+#endif
+
+#ifdef CONFIG_ARCH_DMA
+ /* Initialize the DMA subsystem if the weak function up_dmainitialize has been
* brought into the build
*/
-#ifdef CONFIG_ARCH_DMA
#ifdef CONFIG_HAVE_WEAKFUNCTIONS
if (up_dmainitialize)
#endif
@@ -154,6 +167,14 @@ void up_initialize(void)
devnull_register(); /* Standard /dev/null */
#endif
+#if defined(CONFIG_DEV_RANDOM)
+ devrandom_register(); /* Standard /dev/random */
+#endif
+
+#if defined(CONFIG_DEV_URANDOM)
+ devurandom_register(); /* Standard /dev/urandom */
+#endif
+
#if defined(CONFIG_DEV_ZERO)
devzero_register(); /* Standard /dev/zero */
#endif
@@ -186,6 +207,12 @@ void up_initialize(void)
ramlog_consoleinit();
#endif
+#if CONFIG_NFILE_DESCRIPTORS > 0 && defined(CONFIG_PSEUDOTERM_SUSV1)
+ /* Register the master pseudo-terminal multiplexor device */
+
+ (void)ptmx_register();
+#endif
+
/* Early initialization of the system logging device. Some SYSLOG channel
* can be initialized early in the initialization sequence because they
* depend on only minimal OS initialization.
@@ -193,6 +220,16 @@ void up_initialize(void)
syslog_initialize(SYSLOG_INIT_EARLY);
+#if defined(CONFIG_CRYPTO)
+ /* Initialize the HW crypto and /dev/crypto */
+
+ up_cryptoinitialize();
+#endif
+
+#if CONFIG_NFILE_DESCRIPTORS > 0 && defined(CONFIG_CRYPTO_CRYPTODEV)
+ devcrypto_register();
+#endif
+
#ifndef CONFIG_NETDEV_LATEINIT
/* Initialize the network */
diff --git a/arch/rgmp/src/nuttx.c b/arch/rgmp/src/nuttx.c
index 4a274264d7f..07faf590fd7 100644
--- a/arch/rgmp/src/nuttx.c
+++ b/arch/rgmp/src/nuttx.c
@@ -45,14 +45,21 @@
#include
#include
-#include
-#include
-#include
#include
#include
#include
#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
#include "task/task.h"
#include "sched/sched.h"
#include "group/group.h"
@@ -85,23 +92,90 @@ static inline void up_switchcontext(struct tcb_s *ctcb, struct tcb_s *ntcb)
void up_initialize(void)
{
- extern pidhash_t g_pidhash[];
- extern void vdev_init(void);
- extern void nuttx_arch_init(void);
+ extern pidhash_t g_pidhash[];
+ extern void vdev_init(void);
+ extern void nuttx_arch_init(void);
- // initialize the current_task to g_idletcb
- current_task = g_pidhash[PIDHASH(0)].tcb;
+ /* Initialize the current_task to g_idletcb */
- // OS memory alloc system is ready
- use_os_kmalloc = 1;
+ current_task = g_pidhash[PIDHASH(0)].tcb;
- // rgmp vdev init
- vdev_init();
+ /* OS memory alloc system is ready */
- nuttx_arch_init();
+ use_os_kmalloc = 1;
- // enable interrupt
- local_irq_enable();
+ /* rgmp vdev init */
+
+ vdev_init();
+
+ nuttx_arch_init();
+
+#ifdef CONFIG_PM
+ /* Initialize the power management subsystem. This MCU-specific function
+ * must be called *very* early in the initialization sequence *before* any
+ * other device drivers are initialized (since they may attempt to register
+ * with the power management subsystem).
+ */
+
+ up_pminitialize();
+#endif
+
+#if CONFIG_NFILE_DESCRIPTORS > 0 && defined(CONFIG_PSEUDOTERM_SUSV1)
+ /* Register the master pseudo-terminal multiplexor device */
+
+ (void)ptmx_register();
+#endif
+
+ /* Early initialization of the system logging device. Some SYSLOG channel
+ * can be initialized early in the initialization sequence because they
+ * depend on only minimal OS initialization.
+ */
+
+ syslog_initialize(SYSLOG_INIT_EARLY);
+
+ /* Register devices */
+
+#if CONFIG_NFILE_DESCRIPTORS > 0
+
+#if defined(CONFIG_DEV_NULL)
+ devnull_register(); /* Standard /dev/null */
+#endif
+
+#if defined(CONFIG_DEV_RANDOM)
+ devrandom_register(); /* Standard /dev/random */
+#endif
+
+#if defined(CONFIG_DEV_URANDOM)
+ devurandom_register(); /* Standard /dev/urandom */
+#endif
+
+#if defined(CONFIG_DEV_ZERO)
+ devzero_register(); /* Standard /dev/zero */
+#endif
+
+#if defined(CONFIG_DEV_LOOP)
+ loop_register(); /* Standard /dev/loop */
+#endif
+#endif /* CONFIG_NFILE_DESCRIPTORS */
+
+#if defined(CONFIG_SCHED_INSTRUMENTATION_BUFFER) && \
+ defined(CONFIG_DRIVER_NOTE)
+ note_register(); /* Non-standard /dev/note */
+#endif
+
+#if defined(CONFIG_CRYPTO)
+ /* Initialize the HW crypto and /dev/crypto */
+
+ up_cryptoinitialize();
+#endif
+
+#if CONFIG_NFILE_DESCRIPTORS > 0 && defined(CONFIG_CRYPTO_CRYPTODEV)
+ devcrypto_register();
+#endif
+
+ /* Enable interrupt */
+
+ local_irq_enable();
}
void up_idle(void)
@@ -251,6 +325,7 @@ void up_release_stack(struct tcb_s *dtcb, uint8_t ttype)
* hold the blocked task TCB.
*
****************************************************************************/
+
void up_block_task(struct tcb_s *tcb, tstate_t task_state)
{
/* Verify that the context switch can be performed */
diff --git a/arch/rgmp/src/x86/arch_nuttx.c b/arch/rgmp/src/x86/arch_nuttx.c
index d5ae6916862..32f919cd784 100644
--- a/arch/rgmp/src/x86/arch_nuttx.c
+++ b/arch/rgmp/src/x86/arch_nuttx.c
@@ -44,7 +44,6 @@
#include
#include
-
void nuttx_arch_init(void)
{
extern void e1000_mod_init(void);
@@ -57,7 +56,6 @@ void nuttx_arch_init(void)
// setup e1000
e1000_mod_init();
#endif
-
}
void nuttx_arch_exit(void)
diff --git a/arch/sh/src/common/up_initialize.c b/arch/sh/src/common/up_initialize.c
index c333f4b9939..2cd40a07188 100644
--- a/arch/sh/src/common/up_initialize.c
+++ b/arch/sh/src/common/up_initialize.c
@@ -44,13 +44,16 @@
#include
#include
#include
-#include
+#include
#include
#include
#include
#include
#include
#include
+#include
+#include
+#include
#include "up_arch.h"
#include "up_internal.h"
@@ -129,9 +132,19 @@ void up_initialize(void)
up_irqinitialize();
- /* Initialize the system timer interrupt */
+#ifdef CONFIG_PM
+ /* Initialize the power management subsystem. This MCU-specific function
+ * must be called *very* early in the initialization sequence *before* any
+ * other device drivers are initialized (since they may attempt to register
+ * with the power management subsystem).
+ */
+
+ up_pminitialize();
+#endif
#if !defined(CONFIG_SUPPRESS_INTERRUPTS) && !defined(CONFIG_SUPPRESS_TIMER_INTS)
+ /* Initialize the system timer interrupt */
+
up_timer_initialize();
#endif
@@ -143,6 +156,14 @@ void up_initialize(void)
devnull_register(); /* Standard /dev/null */
#endif
+#if defined(CONFIG_DEV_RANDOM)
+ devrandom_register(); /* Standard /dev/random */
+#endif
+
+#if defined(CONFIG_DEV_URANDOM)
+ devurandom_register(); /* Standard /dev/urandom */
+#endif
+
#if defined(CONFIG_DEV_ZERO)
devzero_register(); /* Standard /dev/zero */
#endif
@@ -178,6 +199,12 @@ void up_initialize(void)
ramlog_consoleinit();
#endif
+#if CONFIG_NFILE_DESCRIPTORS > 0 && defined(CONFIG_PSEUDOTERM_SUSV1)
+ /* Register the master pseudo-terminal multiplexor device */
+
+ (void)ptmx_register();
+#endif
+
/* Early initialization of the system logging device. Some SYSLOG channel
* can be initialized early in the initialization sequence because they
* depend on only minimal OS initialization.
@@ -185,6 +212,16 @@ void up_initialize(void)
syslog_initialize(SYSLOG_INIT_EARLY);
+#if defined(CONFIG_CRYPTO)
+ /* Initialize the HW crypto and /dev/crypto */
+
+ up_cryptoinitialize();
+#endif
+
+#if CONFIG_NFILE_DESCRIPTORS > 0 && defined(CONFIG_CRYPTO_CRYPTODEV)
+ devcrypto_register();
+#endif
+
#ifndef CONFIG_NETDEV_LATEINIT
/* Initialize the network */
diff --git a/arch/sim/Kconfig b/arch/sim/Kconfig
index 7384d3d7230..614b8e7ef7e 100644
--- a/arch/sim/Kconfig
+++ b/arch/sim/Kconfig
@@ -245,20 +245,6 @@ config SIM_SPIFLASH_128M
endchoice
-config SIM_SPIFLASH_MANUFACTURER
- hex "Hex ID of the FLASH manufacturer code"
- default 0x20
- depends on SIM_SPIFLASH
- ---help---
- Allows the simulated FLASH Manufacturer ID to be set.
-
-config SIM_SPIFLASH_MEMORY_TYPE
- hex "Hex ID of the FLASH Memory Type code"
- default 0x20
- depends on SIM_SPIFLASH
- ---help---
- Allows the simulated FLASH Memory Type code to be set.
-
config SIM_SPIFLASH_SECTORSIZE
int "FLASH Sector Erase Size"
default 65536
@@ -277,6 +263,51 @@ config SIM_SPIFLASH_SUBSECTORSIZE
Sets the smaller sub-sector erase size supported by the
FLASH emulation
+config SIM_SPIFLASH_M25P
+ bool "Enable M25Pxx FLASH"
+ depends on MTD_M25P
+ ---help---
+ Enables simulation of an M25P type FLASH
+
+config SIM_SPIFLASH_SST26
+ bool "Enable SST26 FLASH"
+ depends on MTD_SST26
+ ---help---
+ Enables simulation of an SST26 type FLASH
+
+config SIM_SPIFLASH_W25
+ bool "Enable W25 FLASH"
+ depends on MTD_W25
+ ---help---
+ Enables simulation of a W25 type FLASH
+
+config SIM_SPIFLASH_CUSTOM
+ bool "Enable Emulation of a Custom Manufacturer / ID FLASH"
+ depends on SIM_SPIFLASH
+ ---help---
+ Enables simulation of FLASH with a custom Manufacturer, ID and Capacity
+
+config SIM_SPIFLASH_MANUFACTURER
+ hex "Hex ID of the FLASH manufacturer code"
+ default 0x20
+ depends on SIM_SPIFLASH_CUSTOM
+ ---help---
+ Allows the simulated FLASH Manufacturer ID to be set.
+
+config SIM_SPIFLASH_MEMORY_TYPE
+ hex "Hex ID of the FLASH Memory Type code"
+ default 0x20
+ depends on SIM_SPIFLASH_CUSTOM
+ ---help---
+ Allows the simulated FLASH Memory Type code to be set.
+
+config SIM_SPIFLASH_CAPACITY
+ hex "Hex ID of the FLASH capacity code"
+ default 0x14
+ depends on SIM_SPIFLASH_CUSTOM
+ ---help---
+ Allows the simulated FLASH Memory Capacity code to be set.
+
config SIM_SPIFLASH_PAGESIZE
int "FLASH Write / Program Page Size"
default 256
@@ -289,4 +320,79 @@ config SIM_SPIFLASH_PAGESIZE
"wrap" causing the initial data sent to be overwritten.
This is consistent with standard SPI FLASH operation.
+config SIM_QSPIFLASH
+ bool "Simulated QSPI FLASH with SMARTFS"
+ default n
+ select FS_SMARTFS
+ select MTD_SMART
+ ---help---
+ Adds a simulated QSPI FLASH that responds to N25QXXX style
+ commands on the QSPI bus.
+
+choice
+ prompt "Simulated QSPI FLASH Size"
+ default SIM_QSPIFLASH_1M
+ depends on SIM_QSPIFLASH
+
+config SIM_QSPIFLASH_1M
+ bool "1 MBit (128K Byte)"
+
+config SIM_QSPIFLASH_8M
+ bool "8 MBit (1M Byte)"
+
+config SIM_QSPIFLASH_32M
+ bool "32 MBit (4M Byte)"
+
+config SIM_QSPIFLASH_64M
+ bool "64 MBit (8M Byte)"
+
+config SIM_QSPIFLASH_128M
+ bool "128 MBit (16M Byte)"
+
+endchoice
+
+config SIM_QSPIFLASH_MANUFACTURER
+ hex "Hex ID of the FLASH manufacturer code"
+ default 0x20
+ depends on SIM_QSPIFLASH
+ ---help---
+ Allows the simulated FLASH Manufacturer ID to be set.
+
+config SIM_QSPIFLASH_MEMORY_TYPE
+ hex "Hex ID of the FLASH Memory Type code"
+ default 0xba
+ depends on SIM_QSPIFLASH
+ ---help---
+ Allows the simulated FLASH Memory Type code to be set.
+
+config SIM_QSPIFLASH_SECTORSIZE
+ int "FLASH Sector Erase Size"
+ default 65536
+ depends on SIM_QSPIFLASH
+ ---help---
+ Sets the large sector erase size that the part simulates.
+ This driver simulates QSPI devices that have both a large
+ sector erase as well as a "sub-sector" (per the datasheet)
+ erase size (typically 4K bytes).
+
+config SIM_QSPIFLASH_SUBSECTORSIZE
+ int "FLASH Sub-Sector Erase Size"
+ default 4096
+ depends on SIM_QSPIFLASH
+ ---help---
+ Sets the smaller sub-sector erase size supported by the
+ FLASH emulation
+
+config SIM_QSPIFLASH_PAGESIZE
+ int "FLASH Write / Program Page Size"
+ default 256
+ depends on SIM_QSPIFLASH
+ ---help---
+ Sets the size of a page program operation. The page size
+ represents the maximum number of bytes that can be sent
+ for a program operation. If more bytes than this are
+ sent on a single Page Program, then the address will
+ "wrap" causing the initial data sent to be overwritten.
+ This is consistent with standard SPI FLASH operation.
+
endif
diff --git a/arch/sim/src/Makefile b/arch/sim/src/Makefile
index 72401d6c773..fdac7796be5 100644
--- a/arch/sim/src/Makefile
+++ b/arch/sim/src/Makefile
@@ -57,7 +57,7 @@ CSRCS = up_initialize.c up_idle.c up_interruptcontext.c up_initialstate.c
CSRCS += up_createstack.c up_usestack.c up_releasestack.c up_stackframe.c
CSRCS += up_unblocktask.c up_blocktask.c up_releasepending.c
CSRCS += up_reprioritizertr.c up_exit.c up_schedulesigaction.c up_spiflash.c
-CSRCS += up_allocateheap.c up_devconsole.c
+CSRCS += up_allocateheap.c up_devconsole.c up_qspiflash.c
HOSTSRCS = up_hostusleep.c
diff --git a/arch/sim/src/nuttx-names.dat b/arch/sim/src/nuttx-names.dat
index 698df015764..13c064b1778 100644
--- a/arch/sim/src/nuttx-names.dat
+++ b/arch/sim/src/nuttx-names.dat
@@ -1,34 +1,58 @@
+_exit NX_exit
accept NXaccept
+asprintf NXasprintf
+basename NXbasename
calloc NXcalloc
+chdir NXchdir
+clearenv NXclearenv
clock_gettime NXclock_gettime
close NXclose
closedir NXclosedir
dup NXdup
+dup2 NXdup2
+exit NXexit
free NXfree
fclose NXfclose
+fdopen NXfdopen
+fgetc NXfgetc
fopen NXfopen
+fprintf NXfprintf
fputc NXfputc
fcntl NXfcntl
fputs NXfputs
fread NXfread
+fseek NXfseek
fwrite NXfwrite
fsync NXfsync
+ftell NXftell
getenv NXgetenv
+getopt NXgetopt
+getpid NXgetpid
gettimeofday NXgettimeofday
ioctl NXioctl
isatty NXisatty
+kill NXkill
listen NXlisten
lseek NXlseek
+mallinfo NXmallinfo
malloc NXmalloc
malloc_init NXmalloc_init
+memcmp NXmemcmp
+memcpy NXmemcpy
+memset NXmemset
+mkfifo NXmkfifo
+mktime NXmktime
+mq_close NXmq_close
mkdir NXmkdir
mount NXmount
open NXopen
opendir NXopendir
nanosleep NXnanosleep
+pipe NXpipe
poll NXpoll
printf NXprintf
pthread_create NXpthread_create
+pthread_exit NXpthread_exit
pthread_getspecific NXpthread_getspecific
pthread_key_create NXpthread_key_create
pthread_kill NXpthread_kill
@@ -40,38 +64,71 @@ pthread_mutex_unlock NXpthread_mutex_unlock
pthread_setspecific NXpthread_setspecific
pthread_sigmask NXpthread_sigmask
pthread_yield NXpthread_yield
+ptsname NXptsname
+ptsname_r NXptsname_r
puts NXputs
read NXread
readdir NXreaddir
realloc NXrealloc
recv NXrecv
recvfrom NXrecvfrom
+rename NXrename
rewinddir NXrewinddir
rmdir NXrmdir
sched_yield NXsched_yield
seekdir NXseekdir
select NXselect
+sem_getvalue NXsem_getvalue
sem_init NXsem_init
sem_post NXsem_post
sem_wait NXsem_wait
send NXsend
sendto NXsendto
+setenv NXsetenv
+setlogmask NXsetlogmask
setsockopt NXsetsockopt
sigaction NXsigaction
+sigdelset NXsigdelset
+sigemptyset NXsigemptyset
+sigfillset NXsigfillset
sighold NXsighold
+sigismember NXsigismember
sigprocmask NXsigprocmask
sigtimedwait NXsigtimedwait
sigrelse NXsigrelse
sleep NXsleep
+snprintf NXsnprintf
socket NXsocket
+sprintf NXsprintf
stat NXstat
statfs NXstatfs
+strcat NXstrcat
+strchr NXstrchr
+strcmp NXstrcmp
+strcpy NXstrcpy
+strcspn NXstrcspn
+strdup NXstrdup
+strftime NXstrftime
+strlen NXstrlen
+strncasecmp NXstrncasecmp
+strncmp NXstrncmp
+strncpy NXstrncpy
+strrchr NXstrrchr
+strtok_r NXstrtok_r
+strtol NXstrtol
+strtoul NXstrtoul
+syslog NXsyslog
system NXsystem
tcgetattr NXtcgetattr
tcsetattr NXtcsetattr
umount2 NXumount2
unlink NXunlink
+unlockpt NXunlockpt
+uname NXuname
+unsetenv NXunsetenv
usleep NXusleep
+vasprintf NXvasprintf
vfork NXvfork
+vfprintf NXvfprintf
write NXwrite
zmalloc NXzmalloc
diff --git a/arch/sim/src/up_blockdevice.c b/arch/sim/src/up_blockdevice.c
index 066df0a1dfe..b74480ecc06 100644
--- a/arch/sim/src/up_blockdevice.c
+++ b/arch/sim/src/up_blockdevice.c
@@ -44,7 +44,7 @@
#include
#include
-#include
+#include
#include "up_internal.h"
diff --git a/arch/sim/src/up_hostfs.c b/arch/sim/src/up_hostfs.c
index f0928ed0dac..5e1e1f79cb4 100644
--- a/arch/sim/src/up_hostfs.c
+++ b/arch/sim/src/up_hostfs.c
@@ -36,6 +36,7 @@
/****************************************************************************
* Included Files
****************************************************************************/
+
#define _BSD_SOURCE
#include
@@ -50,6 +51,7 @@
#include
#include
+#define __SIM__ 1
#include "hostfs.h"
/****************************************************************************
@@ -62,40 +64,44 @@ int host_open(const char *pathname, int flags, int mode)
/* Perform flag mapping */
- if ((flags & (HOSTFS_FLAG_RDOK | HOSTFS_FLAG_WROK)) ==
- (HOSTFS_FLAG_RDOK | HOSTFS_FLAG_WROK))
+ if ((flags & NUTTX_O_RDWR) == NUTTX_O_RDWR)
{
mapflags = O_RDWR;
}
- else if (flags & HOSTFS_FLAG_RDOK)
+ else if (flags & NUTTX_O_RDONLY)
{
mapflags = O_RDONLY;
}
- else if (flags & HOSTFS_FLAG_WROK)
+ else if (flags & NUTTX_O_WRONLY)
{
mapflags = O_WRONLY;
}
- if (flags & HOSTFS_FLAG_APPEND)
+ if (flags & NUTTX_O_APPEND)
{
mapflags |= O_APPEND;
}
- if (flags & HOSTFS_FLAG_CREAT)
+ if (flags & NUTTX_O_CREAT)
{
mapflags |= O_CREAT;
}
- if (flags & HOSTFS_FLAG_EXCL)
+ if (flags & NUTTX_O_EXCL)
{
mapflags |= O_EXCL;
}
- if (flags & HOSTFS_FLAG_TRUNC)
+ if (flags & NUTTX_O_TRUNC)
{
mapflags |= O_TRUNC;
}
+ if (flags & NUTTX_O_NONBLOCK)
+ {
+ mapflags |= O_NONBLOCK;
+ }
+
return open(pathname, mapflags, mode);
}
@@ -180,21 +186,22 @@ int host_dup(int fd)
void *host_opendir(const char *name)
{
- return (void *) opendir(name);
+ /* Return the host DIR pointer */
+
+ return (void *)opendir(name);
}
/****************************************************************************
* Public Functions
****************************************************************************/
-int host_readdir(void* dirp, struct host_dirent_s* entry)
+int host_readdir(void* dirp, struct nuttx_dirent_s* entry)
{
- struct dirent *ent;
+ struct dirent *ent;
/* Call the host's readdir routine */
ent = readdir(dirp);
-
if (ent != NULL)
{
/* Copy the entry name */
@@ -206,24 +213,21 @@ int host_readdir(void* dirp, struct host_dirent_s* entry)
entry->d_type = 0;
if (ent->d_type == DT_REG)
{
- entry->d_type = HOSTFS_DTYPE_FILE;
+ entry->d_type = NUTTX_DTYPE_FILE;
}
else if (ent->d_type == DT_CHR)
{
- entry->d_type = HOSTFS_DTYPE_CHR;
+ entry->d_type = NUTTX_DTYPE_CHR;
}
else if (ent->d_type == DT_BLK)
{
- entry->d_type = HOSTFS_DTYPE_BLK;
+ entry->d_type = NUTTX_DTYPE_BLK;
}
else if (ent->d_type == DT_DIR)
{
- entry->d_type = HOSTFS_DTYPE_DIRECTORY;
+ entry->d_type = NUTTX_DTYPE_DIRECTORY;
}
- }
- if (ent)
- {
return 0;
}
@@ -234,7 +238,7 @@ int host_readdir(void* dirp, struct host_dirent_s* entry)
* Public Functions
****************************************************************************/
-void host_rewinddir(void* dirp)
+void host_rewinddir(void *dirp)
{
/* Just call the rewinddir routine */
@@ -245,7 +249,7 @@ void host_rewinddir(void* dirp)
* Public Functions
****************************************************************************/
-int host_closedir(void* dirp)
+int host_closedir(void *dirp)
{
return closedir(dirp);
}
@@ -254,7 +258,7 @@ int host_closedir(void* dirp)
* Public Functions
****************************************************************************/
-int host_statfs(const char *path, struct host_statfs_s *buf)
+int host_statfs(const char *path, struct nuttx_statfs_s *buf)
{
int ret;
struct statfs host_buf;
@@ -263,18 +267,16 @@ int host_statfs(const char *path, struct host_statfs_s *buf)
ret = statfs(path, &host_buf);
- /* Map the return values */
+ /* Map the struct statfs value */
buf->f_type = host_buf.f_type;
+ buf->f_namelen = host_buf.f_namelen;
buf->f_bsize = host_buf.f_bsize;
buf->f_blocks = host_buf.f_blocks;
buf->f_bfree = host_buf.f_bfree;
buf->f_bavail = host_buf.f_bavail;
buf->f_files = host_buf.f_files;
buf->f_ffree = host_buf.f_ffree;
- buf->f_fsid = 0;
- buf->f_namelen = host_buf.f_namelen;
- buf->f_frsize = host_buf.f_frsize;
return ret;
}
@@ -321,62 +323,50 @@ int host_rename(const char *oldpath, const char *newpath)
* Public Functions
****************************************************************************/
-int host_stat(const char *path, struct host_stat_s *buf)
+int host_stat(const char *path, struct nuttx_stat_s *buf)
{
- struct stat host_buf;
- int ret;
+ struct stat host_buf;
+ int ret;
/* Call the host's stat routine */
ret = stat(path, &host_buf);
- /* Now map the return values to the common struct */
+ /* Map the return values */
- buf->st_dev = host_buf.st_dev; /* ID of the device containing file */
- buf->st_ino = host_buf.st_ino;; /* inode number */
- buf->st_nlink = host_buf.st_nlink; /* number of hard links */
- buf->st_uid = host_buf.st_uid; /* user ID of owner */
- buf->st_gid = host_buf.st_gid; /* group ID of owner */
- buf->st_rdev = host_buf.st_rdev; /* device ID */
- buf->st_size = host_buf.st_size; /* total size, in bytes */
- buf->st_blksize = host_buf.st_blksize; /* blocksize for file system I/O */
- buf->st_blocks = host_buf.st_blocks; /* number of 512B blocks allocated */
- buf->st_atim = host_buf.st_atime; /* time of last access */
- buf->st_mtim = host_buf.st_mtime; /* time of last modification */
- buf->st_ctim = host_buf.st_ctime; /* time of last status change */
+ buf->st_mode = host_buf.st_mode & 0777;
- /* Map the mode bits */
-
- buf->st_mode = host_buf.st_mode & 0xFFF;
- if (S_ISREG(host_buf.st_mode))
+ if (host_buf.st_mode & S_IFDIR)
{
- buf->st_mode |= HOST_ST_MODE_REG;
+ buf->st_mode |= NUTTX_S_IFDIR;
+ }
+ else if (host_buf.st_mode & S_IFREG)
+ {
+ buf->st_mode |= NUTTX_S_IFREG;
+ }
+ else if (host_buf.st_mode & S_IFCHR)
+ {
+ buf->st_mode |= NUTTX_S_IFCHR;
+ }
+ else if (host_buf.st_mode & S_IFBLK)
+ {
+ buf->st_mode |= NUTTX_S_IFBLK;
+ }
+ else if (host_buf.st_mode & S_IFLNK)
+ {
+ buf->st_mode |= NUTTX_S_IFLNK;
+ }
+ else /* if (host_buf.st_mode & S_IFIFO) */
+ {
+ buf->st_mode |= NUTTX_S_IFIFO;
}
- if (S_ISDIR(host_buf.st_mode))
- {
- buf->st_mode |= HOST_ST_MODE_DIR;
- }
-
- if (S_ISCHR(host_buf.st_mode))
- {
- buf->st_mode |= HOST_ST_MODE_CHR;
- }
-
- if (S_ISBLK(host_buf.st_mode))
- {
- buf->st_mode |= HOST_ST_MODE_BLK;
- }
-
- if (S_ISFIFO(host_buf.st_mode))
- {
- buf->st_mode |= HOST_ST_MODE_PIPE;
- }
-
- if (S_ISLNK(host_buf.st_mode))
- {
- buf->st_mode |= HOST_ST_MODE_LINK;
- }
+ buf->st_size = host_buf.st_size;
+ buf->st_blksize = host_buf.st_blksize;
+ buf->st_blocks = host_buf.st_blocks;
+ buf->st_atim = host_buf.st_atim.tv_sec;
+ buf->st_mtim = host_buf.st_mtim.tv_sec;
+ buf->st_ctim = host_buf.st_ctim.tv_sec;
return ret;
}
diff --git a/arch/sim/src/up_initialize.c b/arch/sim/src/up_initialize.c
index cb07619eabd..ada5bb33ba0 100644
--- a/arch/sim/src/up_initialize.c
+++ b/arch/sim/src/up_initialize.c
@@ -43,7 +43,7 @@
#include
#include
-#include
+#include
#include
#include
#include
@@ -52,6 +52,9 @@
#include
#include
#include
+#include
+#include
+#include
#include "up_internal.h"
@@ -68,32 +71,86 @@
*
****************************************************************************/
-#if defined(CONFIG_FS_SMARTFS) && defined(CONFIG_SIM_SPIFLASH)
+#if defined(CONFIG_FS_SMARTFS) && (defined(CONFIG_SIM_SPIFLASH) || defined(CONFIG_SIM_QSPIFLASH))
static void up_init_smartfs(void)
{
FAR struct mtd_dev_s *mtd;
+ int minor = 0;
+#if defined(CONFIG_MTD_M25P) || defined(CONFIG_MTD_W25) || defined(CONFIG_MTD_SST26)
FAR struct spi_dev_s *spi;
+#endif
+#ifdef CONFIG_MTD_N25QXXX
+ FAR struct qspi_dev_s *qspi;
+#endif
+#ifdef CONFIG_SIM_SPIFLASH
#ifdef CONFIG_MTD_M25P
/* Initialize a simulated SPI FLASH block device m25p MTD driver */
- spi = up_spiflashinitialize();
- mtd = m25p_initialize(spi);
+ spi = up_spiflashinitialize("m25p");
+ if (spi != NULL)
+ {
+ mtd = m25p_initialize(spi);
- /* Now initialize a SMART Flash block device and bind it to the MTD device */
+ /* Now initialize a SMART Flash block device and bind it to the MTD device */
- smart_initialize(0, mtd, NULL);
+ if (mtd != NULL)
+ {
+ smart_initialize(minor++, mtd, "_m25p");
+ }
+ }
+#endif
+
+#ifdef CONFIG_MTD_SST26
+ /* Initialize a simulated SPI FLASH block device sst26 MTD driver */
+
+ spi = up_spiflashinitialize("sst26");
+ if (spi != NULL)
+ {
+ mtd = sst26_initialize_spi(spi);
+
+ /* Now initialize a SMART Flash block device and bind it to the MTD device */
+
+ if (mtd != NULL)
+ {
+ smart_initialize(minor++, mtd, "_sst26");
+ }
+ }
#endif
#ifdef CONFIG_MTD_W25
- /* Initialize a simulated SPI FLASH block device m25p MTD driver */
+ /* Initialize a simulated SPI FLASH block device w25 MTD driver */
- spi = up_spiflashinitialize();
- mtd = w25_initialize(spi);
+ spi = up_spiflashinitialize("w25");
+ if (spi != NULL)
+ {
+ mtd = w25_initialize(spi);
- /* Now initialize a SMART Flash block device and bind it to the MTD device */
+ /* Now initialize a SMART Flash block device and bind it to the MTD device */
- smart_initialize(0, mtd, NULL);
+ if (mtd != NULL)
+ {
+ smart_initialize(minor++, mtd, "_w25");
+ }
+ }
+#endif
+#endif /* CONFIG_SIM_SPIFLASH */
+
+#if defined(CONFIG_MTD_N25QXXX) && defined(CONFIG_SIM_QSPIFLASH)
+ /* Initialize a simulated SPI FLASH block device n25qxxx MTD driver */
+
+ qspi = up_qspiflashinitialize();
+ if (qspi != NULL)
+ {
+ mtd = n25qxxx_initialize(qspi, 0);
+
+ /* Now initialize a SMART Flash block device and bind it to the MTD device */
+
+ if (mtd != NULL)
+ {
+ smart_initialize(minor++, mtd, "_n25q");
+ }
+ }
#endif
}
#endif
@@ -124,15 +181,25 @@ static void up_init_smartfs(void)
void up_initialize(void)
{
+#ifdef CONFIG_NET
/* The real purpose of the following is to make sure that syslog
* is drawn into the link. It is needed by up_tapdev which is linked
* separately.
*/
-#ifdef CONFIG_NET
syslog(LOG_INFO, "SIM: Initializing");
#endif
+#ifdef CONFIG_PM
+ /* Initialize the power management subsystem. This MCU-specific function
+ * must be called *very* early in the initialization sequence *before* any
+ * other device drivers are initialized (since they may attempt to register
+ * with the power management subsystem).
+ */
+
+ up_pminitialize();
+#endif
+
#if CONFIG_NFILE_DESCRIPTORS > 0
/* Register devices */
@@ -140,6 +207,14 @@ void up_initialize(void)
devnull_register(); /* Standard /dev/null */
#endif
+#if defined(CONFIG_DEV_RANDOM)
+ devrandom_register(); /* Standard /dev/random */
+#endif
+
+#if defined(CONFIG_DEV_URANDOM)
+ devurandom_register(); /* Standard /dev/urandom */
+#endif
+
#if defined(CONFIG_DEV_ZERO)
devzero_register(); /* Standard /dev/zero */
#endif
@@ -168,6 +243,12 @@ void up_initialize(void)
ramlog_consoleinit();
#endif
+#if CONFIG_NFILE_DESCRIPTORS > 0 && defined(CONFIG_PSEUDOTERM_SUSV1)
+ /* Register the master pseudo-terminal multiplexor device */
+
+ (void)ptmx_register();
+#endif
+
/* Early initialization of the system logging device. Some SYSLOG channel
* can be initialized early in the initialization sequence because they
* depend on only minimal OS initialization.
@@ -175,6 +256,16 @@ void up_initialize(void)
syslog_initialize(SYSLOG_INIT_EARLY);
+#if defined(CONFIG_CRYPTO)
+ /* Initialize the HW crypto and /dev/crypto */
+
+ up_cryptoinitialize();
+#endif
+
+#if CONFIG_NFILE_DESCRIPTORS > 0 && defined(CONFIG_CRYPTO_CRYPTODEV)
+ devcrypto_register();
+#endif
+
#if defined(CONFIG_FS_FAT) && !defined(CONFIG_DISABLE_MOUNTPOINT)
up_registerblockdevice(); /* Our FAT ramdisk at /dev/ram0 */
#endif
@@ -201,7 +292,7 @@ void up_initialize(void)
(void)telnet_initialize();
#endif
-#if defined(CONFIG_FS_SMARTFS) && defined(CONFIG_SIM_SPIFLASH)
+#if defined(CONFIG_FS_SMARTFS) && (defined(CONFIG_SIM_SPIFLASH) || defined(CONFIG_SIM_QSPIFLASH))
up_init_smartfs();
#endif
}
diff --git a/arch/sim/src/up_internal.h b/arch/sim/src/up_internal.h
index f163e67a254..1304419af34 100644
--- a/arch/sim/src/up_internal.h
+++ b/arch/sim/src/up_internal.h
@@ -336,7 +336,12 @@ void netdriver_loop(void);
#ifdef CONFIG_SIM_SPIFLASH
struct spi_dev_s;
-struct spi_dev_s *up_spiflashinitialize(void);
+struct spi_dev_s *up_spiflashinitialize(FAR const char *name);
+#endif
+
+#ifdef CONFIG_SIM_QSPIFLASH
+struct qspi_dev_s;
+struct qspi_dev_s *up_qspiflashinitialize(void);
#endif
#endif /* __ASSEMBLY__ */
diff --git a/arch/sim/src/up_qspiflash.c b/arch/sim/src/up_qspiflash.c
new file mode 100644
index 00000000000..f2cafe608bb
--- /dev/null
+++ b/arch/sim/src/up_qspiflash.c
@@ -0,0 +1,607 @@
+/************************************************************************************
+ * arch/sim/src/up_qspiflash.c
+ *
+ * Copyright (C) 2014, 2016 Ken Pettit. All rights reserved.
+ * Author: Ken Pettit
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include
+#include
+
+#include
+#include
+#include