From fe94318bb413d39f07869210b219332da52afc66 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 5 Jan 2016 10:04:12 -0600 Subject: [PATCH 1/3] PIC32MX/MZ: Fix error in assember macro. Noted by Tilak Tangudu --- arch/mips/src/pic32mx/excptmacros.h | 12 ++++++------ arch/mips/src/pic32mx/pic32mx-head.S | 8 ++++---- arch/mips/src/pic32mz/pic32mz-excptmacros.h | 12 ++++++------ arch/mips/src/pic32mz/pic32mz-head.S | 8 ++++---- 4 files changed, 20 insertions(+), 20 deletions(-) diff --git a/arch/mips/src/pic32mx/excptmacros.h b/arch/mips/src/pic32mx/excptmacros.h index f759e4e9e1f..4fdc8afaf55 100644 --- a/arch/mips/src/pic32mx/excptmacros.h +++ b/arch/mips/src/pic32mx/excptmacros.h @@ -72,7 +72,7 @@ * my_exception: * EXCPT_PROLOGUE t0 - Save registers on stack, enable nested interrupts * move a0, sp - Pass register save structure as the parameter 1 - * USE_INTSTACK t0, t1, t2 - Switch to the interrupt stack + * USE_INTSTACK t0, t1, t2, t3 - Switch to the interrupt stack * jal handler - Handle the exception IN=old regs OUT=new regs * di - Disable interrupts * RESTORE_STACK t0, t1 - Undo the operations of USE_STACK @@ -368,7 +368,7 @@ * * On Entry: * sp - Current value of the user stack pointer - * tmp1, tmp2, and tmp3 are registers that can be used temporarily. + * tmp1, tmp2, tmp3, and tmp4 are registers that can be used temporarily. * All interrupts should still be disabled. * * At completion: @@ -378,7 +378,7 @@ * ********************************************************************************************/ - .macro USE_INTSTACK, tmp1, tmp2, tmp3 + .macro USE_INTSTACK, tmp1, tmp2, tmp3, tmp4 #if CONFIG_ARCH_INTERRUPTSTACK > 3 #ifdef CONFIG_PIC32MX_NESTED_INTERRUPTS @@ -398,9 +398,9 @@ */ la \tmp3, g_intstackbase - lw \tmp, (\tmp3) - sw sp, (\tmp3) - move sp, \tmp3 + lw \tmp4, (\tmp3) + sw sp, (\tmp4) + move sp, \tmp4 #ifdef CONFIG_PIC32MX_NESTED_INTERRUPTS 1: diff --git a/arch/mips/src/pic32mx/pic32mx-head.S b/arch/mips/src/pic32mx/pic32mx-head.S index 2a6f43230a6..b5e19f39d80 100644 --- a/arch/mips/src/pic32mx/pic32mx-head.S +++ b/arch/mips/src/pic32mx/pic32mx-head.S @@ -490,8 +490,8 @@ __start: _exception_handler: EXCPT_PROLOGUE t0 /* Save registers on stack, enable nested interrupts */ move a0, sp /* Pass register save structure as the parameter 1 */ - USE_INTSTACK t0, t1, t2 /* Switch to the interrupt stack */ - la t0, pic32mx_exception /* Call pic32mx_exception(regs) */ + USE_INTSTACK t0, t1, t2, t3 /* Switch to the interrupt stack */ + la t0, pic32mx_exception /* Call pic32mx_exception(regs) */ jalr ra, t0 nop #ifdef CONFIG_PIC32MX_NESTED_INTERRUPTS @@ -515,7 +515,7 @@ _exception_handler: _int_handler: EXCPT_PROLOGUE t0 /* Save registers on stack, enable nested interrupts */ move a0, sp /* Pass register save structure as the parameter 1 */ - USE_INTSTACK t0, t1, t2 /* Switch to the interrupt stack */ + USE_INTSTACK t0, t1, t2, t3 /* Switch to the interrupt stack */ la t0, pic32mx_decodeirq /* Call pic32mx_decodeirq(regs) */ jalr ra, t0 nop @@ -541,7 +541,7 @@ _int_handler: _nmi_handler: EXCPT_PROLOGUE t0 /* Save registers on stack, enable nested interrupts */ move a0, sp /* Pass register save structure as the parameter 1 */ - USE_INTSTACK t0, t1, t2 /* Switch to the interrupt stack */ + USE_INTSTACK t0, t1, t2, t3 /* Switch to the interrupt stack */ la t0, pic32mx_donmi /* Call up_donmi(regs) */ jalr ra, t0 nop diff --git a/arch/mips/src/pic32mz/pic32mz-excptmacros.h b/arch/mips/src/pic32mz/pic32mz-excptmacros.h index d52b1be162a..2ddb5b464f9 100644 --- a/arch/mips/src/pic32mz/pic32mz-excptmacros.h +++ b/arch/mips/src/pic32mz/pic32mz-excptmacros.h @@ -72,7 +72,7 @@ * my_exception: * EXCPT_PROLOGUE t0 - Save registers on stack, enable nested interrupts * move a0, sp - Pass register save structure as the parameter 1 - * USE_INTSTACK t0, t1, t2 - Switch to the interrupt stack + * USE_INTSTACK t0, t1, t2, t3 - Switch to the interrupt stack * jal handler - Handle the exception IN=old regs OUT=new regs * di - Disable interrupts * RESTORE_STACK t0, t1 - Undo the operations of USE_STACK @@ -368,7 +368,7 @@ * * On Entry: * sp - Current value of the user stack pointer - * tmp1, tmp2, and tmp3 are registers that can be used temporarily. + * tmp1, tmp2, tmp3, and tmp4 are registers that can be used temporarily. * All interrupts should still be disabled. * * At completion: @@ -378,7 +378,7 @@ * ********************************************************************************************/ - .macro USE_INTSTACK, tmp1, tmp2, tmp3 + .macro USE_INTSTACK, tmp1, tmp2, tmp3, tmp4 #if CONFIG_ARCH_INTERRUPTSTACK > 3 #ifdef CONFIG_PIC32MZ_NESTED_INTERRUPTS @@ -398,9 +398,9 @@ */ la \tmp3, g_intstackbase - lw \tmp, (\tmp3) - sw sp, (\tmp3) - move sp, \tmp3 + lw \tmp4, (\tmp3) + sw sp, (\tmp4) + move sp, \tmp4 #ifdef CONFIG_PIC32MZ_NESTED_INTERRUPTS 1: diff --git a/arch/mips/src/pic32mz/pic32mz-head.S b/arch/mips/src/pic32mz/pic32mz-head.S index fae8eb73e6c..b04ab231f13 100644 --- a/arch/mips/src/pic32mz/pic32mz-head.S +++ b/arch/mips/src/pic32mz/pic32mz-head.S @@ -561,8 +561,8 @@ __start: _exception_handler: EXCPT_PROLOGUE t0 /* Save registers on stack, enable nested interrupts */ move a0, sp /* Pass register save structure as the parameter 1 */ - USE_INTSTACK t0, t1, t2 /* Switch to the interrupt stack */ - la t0, pic32mz_exception /* Call pic32mz_exception(regs) */ + USE_INTSTACK t0, t1, t2, t3 /* Switch to the interrupt stack */ + la t0, pic32mz_exception /* Call pic32mz_exception(regs) */ jalr ra, t0 nop #ifdef CONFIG_PIC32MZ_NESTED_INTERRUPTS @@ -590,7 +590,7 @@ _exception_handler: _int_handler: EXCPT_PROLOGUE t0 /* Save registers on stack, enable nested interrupts */ move a0, sp /* Pass register save structure as the parameter 1 */ - USE_INTSTACK t0, t1, t2 /* Switch to the interrupt stack */ + USE_INTSTACK t0, t1, t2, t3 /* Switch to the interrupt stack */ la t0, pic32mz_decodeirq /* Call pic32mz_decodeirq(regs) */ jalr ra, t0 nop @@ -620,7 +620,7 @@ _int_handler: _nmi_handler: EXCPT_PROLOGUE t0 /* Save registers on stack, enable nested interrupts */ move a0, sp /* Pass register save structure as the parameter 1 */ - USE_INTSTACK t0, t1, t2 /* Switch to the interrupt stack */ + USE_INTSTACK t0, t1, t2, t3 /* Switch to the interrupt stack */ la t0, pic32mz_donmi /* Call up_donmi(regs) */ jalr ra, t0 nop From 951c40215a6005e5254a3382f8d88cef8ca89a33 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 6 Jan 2016 09:50:15 -0600 Subject: [PATCH 2/3] Atmega: Eliminate some warnings --- arch/avr/src/atmega/Kconfig | 2 +- arch/avr/src/atmega/atmega_lowconsole.c | 148 ++++++++++++------------ 2 files changed, 77 insertions(+), 73 deletions(-) diff --git a/arch/avr/src/atmega/Kconfig b/arch/avr/src/atmega/Kconfig index 26bd15e4231..8c3d6c01456 100644 --- a/arch/avr/src/atmega/Kconfig +++ b/arch/avr/src/atmega/Kconfig @@ -39,7 +39,7 @@ config AVR_USART1 endmenu # ATMega Peripheral Selections -menu "Low level UART driver options" +menu "Low level USART driver options" depends on AVR_USART0 || AVR_USART1 config SERIAL_TERMIOS diff --git a/arch/avr/src/atmega/atmega_lowconsole.c b/arch/avr/src/atmega/atmega_lowconsole.c index ab4b70ec3cf..28fb17d8400 100644 --- a/arch/avr/src/atmega/atmega_lowconsole.c +++ b/arch/avr/src/atmega/atmega_lowconsole.c @@ -77,41 +77,43 @@ * AVR_DBLSPEED_UBRR1 = 104 (rounded), actual baud = 9615 */ -#undef UART0_DOUBLE_SPEED -#if BOARD_CPU_CLOCK <= 4000000 -# if CONFIG_USART0_BAUD <= 9600 -# define AVR_UBRR0 AVR_NORMAL_UBRR0 +#undef USART0_DOUBLE_SPEED +#ifdef CONFIG_AVR_USART0 +# if BOARD_CPU_CLOCK <= 4000000 +# if CONFIG_USART0_BAUD <= 9600 +# define AVR_UBRR0 AVR_NORMAL_UBRR0 +# else +# define AVR_UBRR0 AVR_DBLSPEED_UBRR0 +# define USART0_DOUBLE_SPEED 1 +# endif +# elif BOARD_CPU_CLOCK <= 8000000 +# if CONFIG_USART0_BAUD <= 19200 +# define AVR_UBRR0 AVR_NORMAL_UBRR0 +# else +# define AVR_UBRR0 AVR_DBLSPEED_UBRR0 +# define USART0_DOUBLE_SPEED 1 +# endif +# elif BOARD_CPU_CLOCK <= 12000000 +# if CONFIG_USART0_BAUD <= 28800 +# define AVR_UBRR0 AVR_NORMAL_UBRR0 +# else +# define AVR_UBRR0 AVR_DBLSPEED_UBRR0 +# define USART0_DOUBLE_SPEED 1 +# endif +# elif BOARD_CPU_CLOCK <= 16000000 +# if CONFIG_USART0_BAUD <= 38400 +# define AVR_UBRR0 AVR_NORMAL_UBRR0 +# else +# define AVR_UBRR0 AVR_DBLSPEED_UBRR0 +# define USART0_DOUBLE_SPEED 1 +# endif # else -# define AVR_UBRR0 AVR_DBLSPEED_UBRR0 -# define UART0_DOUBLE_SPEED 1 -# endif -#elif BOARD_CPU_CLOCK <= 8000000 -# if CONFIG_USART0_BAUD <= 19200 -# define AVR_UBRR0 AVR_NORMAL_UBRR0 -# else -# define AVR_UBRR0 AVR_DBLSPEED_UBRR0 -# define UART0_DOUBLE_SPEED 1 -# endif -#elif BOARD_CPU_CLOCK <= 12000000 -# if CONFIG_USART0_BAUD <= 28800 -# define AVR_UBRR0 AVR_NORMAL_UBRR0 -# else -# define AVR_UBRR0 AVR_DBLSPEED_UBRR0 -# define UART0_DOUBLE_SPEED 1 -# endif -#elif BOARD_CPU_CLOCK <= 16000000 -# if CONFIG_USART0_BAUD <= 38400 -# define AVR_UBRR0 AVR_NORMAL_UBRR0 -# else -# define AVR_UBRR0 AVR_DBLSPEED_UBRR0 -# define UART0_DOUBLE_SPEED 1 -# endif -#else -# if CONFIG_USART0_BAUD <= 57600 -# define AVR_UBRR0 AVR_NORMAL_UBRR0 -# else -# define AVR_UBRR0 AVR_DBLSPEED_UBRR0 -# define UART0_DOUBLE_SPEED 1 +# if CONFIG_USART0_BAUD <= 57600 +# define AVR_UBRR0 AVR_NORMAL_UBRR0 +# else +# define AVR_UBRR0 AVR_DBLSPEED_UBRR0 +# define USART0_DOUBLE_SPEED 1 +# endif # endif #endif @@ -137,41 +139,43 @@ * AVR_DBLSPEED_UBRR1 = 104 (rounded), actual baud = 9615 */ -#undef UART1_DOUBLE_SPEED -#if BOARD_CPU_CLOCK <= 4000000 -# if CONFIG_USART1_BAUD <= 9600 -# define AVR_UBRR1 AVR_NORMAL_UBRR1 +#undef USART1_DOUBLE_SPEED +#ifdef CONFIG_AVR_USART1 +# if BOARD_CPU_CLOCK <= 4000000 +# if CONFIG_USART1_BAUD <= 9600 +# define AVR_UBRR1 AVR_NORMAL_UBRR1 +# else +# define AVR_UBRR1 AVR_DBLSPEED_UBRR1 +# define USART1_DOUBLE_SPEED 1 +# endif +# elif BOARD_CPU_CLOCK <= 8000000 +# if CONFIG_USART1_BAUD <= 19200 +# define AVR_UBRR1 AVR_NORMAL_UBRR1 +# else +# define AVR_UBRR1 AVR_DBLSPEED_UBRR1 +# define USART1_DOUBLE_SPEED 1 +# endif +# elif BOARD_CPU_CLOCK <= 12000000 +# if CONFIG_USART1_BAUD <= 28800 +# define AVR_UBRR1 AVR_NORMAL_UBRR1 +# else +# define AVR_UBRR1 AVR_DBLSPEED_UBRR1 +# define USART1_DOUBLE_SPEED 1 +# endif +# elif BOARD_CPU_CLOCK <= 16000000 +# if CONFIG_USART1_BAUD <= 38400 +# define AVR_UBRR1 AVR_NORMAL_UBRR1 +# else +# define AVR_UBRR1 AVR_DBLSPEED_UBRR1 +# define USART1_DOUBLE_SPEED 1 +# endif # else -# define AVR_UBRR1 AVR_DBLSPEED_UBRR1 -# define UART1_DOUBLE_SPEED 1 -# endif -#elif BOARD_CPU_CLOCK <= 8000000 -# if CONFIG_USART1_BAUD <= 19200 -# define AVR_UBRR1 AVR_NORMAL_UBRR1 -# else -# define AVR_UBRR1 AVR_DBLSPEED_UBRR1 -# define UART1_DOUBLE_SPEED 1 -# endif -#elif BOARD_CPU_CLOCK <= 12000000 -# if CONFIG_USART1_BAUD <= 28800 -# define AVR_UBRR1 AVR_NORMAL_UBRR1 -# else -# define AVR_UBRR1 AVR_DBLSPEED_UBRR1 -# define UART1_DOUBLE_SPEED 1 -# endif -#elif BOARD_CPU_CLOCK <= 16000000 -# if CONFIG_USART1_BAUD <= 38400 -# define AVR_UBRR1 AVR_NORMAL_UBRR1 -# else -# define AVR_UBRR1 AVR_DBLSPEED_UBRR1 -# define UART1_DOUBLE_SPEED 1 -# endif -#else -# if CONFIG_USART1_BAUD <= 57600 -# define AVR_UBRR1 AVR_NORMAL_UBRR1 -# else -# define AVR_UBRR1 AVR_DBLSPEED_UBRR1 -# define UART1_DOUBLE_SPEED 1 +# if CONFIG_USART1_BAUD <= 57600 +# define AVR_UBRR1 AVR_NORMAL_UBRR1 +# else +# define AVR_UBRR1 AVR_DBLSPEED_UBRR1 +# define USART1_DOUBLE_SPEED 1 +# endif # endif #endif @@ -270,7 +274,7 @@ void usart0_configure(void) /* Select normal or double speed. */ -#ifdef UART0_DOUBLE_SPEED +#ifdef USART0_DOUBLE_SPEED UCSR0A = (1 << U2X0); #else UCSR0A = 0; @@ -324,7 +328,7 @@ void usart0_configure(void) * USART0 forces this pin to be an input, a logical one in PORTD0 will * turn on the internal pull-up. * - * Port D, Bit 1: TXD0, UART0 Transmit pin. + * Port D, Bit 1: TXD0, USART0 Transmit pin. */ DDRD |= (1 << 1); /* Force Port D pin 1 to be an output -- should not be necessary */ @@ -340,7 +344,7 @@ void usart0_configure(void) * USART0 forces this pin to be an input, a logical one in PORTE0 will * turn on the internal pull-up. * - * Port E, Bit 1: TXD0, UART0 Transmit pin. + * Port E, Bit 1: TXD0, USART0 Transmit pin. * * REVISIT: According to table 41, TXD0 is also automatically configured. * However, this is not explicitly stated in the text. @@ -365,7 +369,7 @@ void usart1_configure(void) /* Select normal or double speed. */ -#ifdef UART1_DOUBLE_SPEED +#ifdef USART1_DOUBLE_SPEED UCSR1A = (1 << U2X1); #else UCSR1A = 0; From dfe3240973c365f37866d44503628ec73bd14d95 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 7 Jan 2016 08:14:09 -0600 Subject: [PATCH 3/3] AVR: Rename ATMEGA_PC_SIZE to AVR_PC_SIZE since it must be used in common AVR logic. Add definitions for other AVR architectures as necessary for compilation --- arch/avr/include/at90usb/irq.h | 1 + arch/avr/include/atmega/irq.h | 154 ++++++++++++++-------------- arch/avr/include/avr/irq.h | 4 +- arch/avr/include/xmega/xmegac_irq.h | 1 + arch/avr/src/avr/excptmacros.h | 12 +-- 5 files changed, 87 insertions(+), 85 deletions(-) diff --git a/arch/avr/include/at90usb/irq.h b/arch/avr/include/at90usb/irq.h index 9bc59e156f2..b9322896322 100644 --- a/arch/avr/include/at90usb/irq.h +++ b/arch/avr/include/at90usb/irq.h @@ -94,6 +94,7 @@ #define AT90USB_IRQ_SPMRDY 36 /* 0x004a Store Program Memory Ready */ #define NR_IRQS 37 +#define AVR_PC_SIZE 16 #define XCPTCONTEXT_REGS 37 /* Size of the register state save array (in bytes) */ /**************************************************************************** diff --git a/arch/avr/include/atmega/irq.h b/arch/avr/include/atmega/irq.h index adc0288ddf5..0f0a6995a5c 100644 --- a/arch/avr/include/atmega/irq.h +++ b/arch/avr/include/atmega/irq.h @@ -57,85 +57,85 @@ #if defined(CONFIG_ARCH_CHIP_ATMEGA128) -# define ATMEGA_IRQ_INT0 0 /* 0x0002 External Interrupt Request 0 */ -# define ATMEGA_IRQ_INT1 1 /* 0x0004 External Interrupt Request 1 */ -# define ATMEGA_IRQ_INT2 2 /* 0x0006 External Interrupt Request 2 */ -# define ATMEGA_IRQ_INT3 3 /* 0x0008 External Interrupt Request 3 */ -# define ATMEGA_IRQ_INT4 4 /* 0x000a External Interrupt Request 4 */ -# define ATMEGA_IRQ_INT5 5 /* 0x000c External Interrupt Request 5 */ -# define ATMEGA_IRQ_INT6 6 /* 0x000e External Interrupt Request 6 */ -# define ATMEGA_IRQ_INT7 7 /* 0x0010 External Interrupt Request 7 */ -# define ATMEGA_IRQ_T2COMP 8 /* 0x0012 TIMER2 COMP Timer/Counter2 Compare Match */ -# define ATMEGA_IRQ_T2OVF 9 /* 0x0014 TIMER2 OVF Timer/Counter2 Overflow */ -# define ATMEGA_IRQ_T1CAPT 10 /* 0x0016 TIMER1 CAPT Timer/Counter1 Capture Event */ -# define ATMEGA_IRQ_T1COMPA 11 /* 0x0018 TIMER1 COMPA Timer/Counter1 Compare Match A */ -# define ATMEGA_IRQ_T1COMPB 12 /* 0x001a TIMER1 COMPB Timer/Counter1 Compare Match B */ -# define ATMEGA_IRQ_T1OVF 13 /* 0x001c TIMER1 OVF Timer/Counter1 Overflow */ -# define ATMEGA_IRQ_T0COMP 14 /* 0x001e TIMER0 COMP Timer/Counter0 Compare Match */ -# define ATMEGA_IRQ_T0OVF 15 /* 0x0020 TIMER0 OVF Timer/Counter0 Overflow */ -# define ATMEGA_IRQ_SPI 16 /* 0x0022 STC SPI Serial Transfer Complete */ -# define ATMEGA_IRQ_U0RX 17 /* 0x0024 USART0 Rx Complete */ -# define ATMEGA_IRQ_U0DRE 18 /* 0x0026 USART0 Data Register Empty */ -# define ATMEGA_IRQ_U0TX 19 /* 0x0028 USART0 Tx Complete */ -# define ATMEGA_IRQ_ADC 20 /* 0x002a ADC Conversion Complete */ -# define ATMEGA_IRQ_EE 21 /* 0x002c EEPROM Ready */ -# define ATMEGA_IRQ_ANACOMP 22 /* 0x002e ANALOG COMP Analog Comparator */ -# define ATMEGA_IRQ_T1COMPC 23 /* 0x0030 TIMER1 COMPC Timer/Countre1 Compare Match C */ -# define ATMEGA_IRQ_T3CAPT 24 /* 0x0032 TIMER3 CAPT Timer/Counter3 Capture Event */ -# define ATMEGA_IRQ_T3COMPA 25 /* 0x0034 TIMER3 COMPA Timer/Counter3 Compare Match A */ -# define ATMEGA_IRQ_T3COMPB 26 /* 0x0036 TIMER3 COMPB Timer/Counter3 Compare Match B */ -# define ATMEGA_IRQ_T3COMPC 27 /* 0x0038 TIMER3 COMPC Timer/Counter3 Compare Match C */ -# define ATMEGA_IRQ_T3OVF 28 /* 0x003a TIMER3 OVF Timer/Counter3 Overflow */ -# define ATMEGA_IRQ_U1RX 29 /* 0x003c USART1 Rx Complete */ -# define ATMEGA_IRQ_U1DRE 30 /* 0x003e USART1 Data Register Empty */ -# define ATMEGA_IRQ_U1TX 31 /* 0x0040 USART1 Tx Complete */ -# define ATMEGA_IRQ_TWI 32 /* 0x0042 TWI Two-wire Serial Interface */ -# define ATMEGA_IRQ_SPMRDY 33 /* 0x0044 Store Program Memory Ready */ +# define ATMEGA_IRQ_INT0 0 /* 0x0002 External Interrupt Request 0 */ +# define ATMEGA_IRQ_INT1 1 /* 0x0004 External Interrupt Request 1 */ +# define ATMEGA_IRQ_INT2 2 /* 0x0006 External Interrupt Request 2 */ +# define ATMEGA_IRQ_INT3 3 /* 0x0008 External Interrupt Request 3 */ +# define ATMEGA_IRQ_INT4 4 /* 0x000a External Interrupt Request 4 */ +# define ATMEGA_IRQ_INT5 5 /* 0x000c External Interrupt Request 5 */ +# define ATMEGA_IRQ_INT6 6 /* 0x000e External Interrupt Request 6 */ +# define ATMEGA_IRQ_INT7 7 /* 0x0010 External Interrupt Request 7 */ +# define ATMEGA_IRQ_T2COMP 8 /* 0x0012 TIMER2 COMP Timer/Counter2 Compare Match */ +# define ATMEGA_IRQ_T2OVF 9 /* 0x0014 TIMER2 OVF Timer/Counter2 Overflow */ +# define ATMEGA_IRQ_T1CAPT 10 /* 0x0016 TIMER1 CAPT Timer/Counter1 Capture Event */ +# define ATMEGA_IRQ_T1COMPA 11 /* 0x0018 TIMER1 COMPA Timer/Counter1 Compare Match A */ +# define ATMEGA_IRQ_T1COMPB 12 /* 0x001a TIMER1 COMPB Timer/Counter1 Compare Match B */ +# define ATMEGA_IRQ_T1OVF 13 /* 0x001c TIMER1 OVF Timer/Counter1 Overflow */ +# define ATMEGA_IRQ_T0COMP 14 /* 0x001e TIMER0 COMP Timer/Counter0 Compare Match */ +# define ATMEGA_IRQ_T0OVF 15 /* 0x0020 TIMER0 OVF Timer/Counter0 Overflow */ +# define ATMEGA_IRQ_SPI 16 /* 0x0022 STC SPI Serial Transfer Complete */ +# define ATMEGA_IRQ_U0RX 17 /* 0x0024 USART0 Rx Complete */ +# define ATMEGA_IRQ_U0DRE 18 /* 0x0026 USART0 Data Register Empty */ +# define ATMEGA_IRQ_U0TX 19 /* 0x0028 USART0 Tx Complete */ +# define ATMEGA_IRQ_ADC 20 /* 0x002a ADC Conversion Complete */ +# define ATMEGA_IRQ_EE 21 /* 0x002c EEPROM Ready */ +# define ATMEGA_IRQ_ANACOMP 22 /* 0x002e ANALOG COMP Analog Comparator */ +# define ATMEGA_IRQ_T1COMPC 23 /* 0x0030 TIMER1 COMPC Timer/Countre1 Compare Match C */ +# define ATMEGA_IRQ_T3CAPT 24 /* 0x0032 TIMER3 CAPT Timer/Counter3 Capture Event */ +# define ATMEGA_IRQ_T3COMPA 25 /* 0x0034 TIMER3 COMPA Timer/Counter3 Compare Match A */ +# define ATMEGA_IRQ_T3COMPB 26 /* 0x0036 TIMER3 COMPB Timer/Counter3 Compare Match B */ +# define ATMEGA_IRQ_T3COMPC 27 /* 0x0038 TIMER3 COMPC Timer/Counter3 Compare Match C */ +# define ATMEGA_IRQ_T3OVF 28 /* 0x003a TIMER3 OVF Timer/Counter3 Overflow */ +# define ATMEGA_IRQ_U1RX 29 /* 0x003c USART1 Rx Complete */ +# define ATMEGA_IRQ_U1DRE 30 /* 0x003e USART1 Data Register Empty */ +# define ATMEGA_IRQ_U1TX 31 /* 0x0040 USART1 Tx Complete */ +# define ATMEGA_IRQ_TWI 32 /* 0x0042 TWI Two-wire Serial Interface */ +# define ATMEGA_IRQ_SPMRDY 33 /* 0x0044 Store Program Memory Ready */ -# define NR_IRQS 34 -# define ATMEGA_PC_SIZE 16 -# define XCPTCONTEXT_REGS 37 /* Size of the register state save array (in bytes) */ +# define NR_IRQS 34 +# define AVR_PC_SIZE 16 +# define XCPTCONTEXT_REGS 37 /* Size of the register state save array (in bytes) */ #elif defined(CONFIG_ARCH_CHIP_ATMEGA1284P) -# define ATMEGA_IRQ_INT0 0 /* 0x0002 External Interrupt Request 0 */ -# define ATMEGA_IRQ_INT1 1 /* 0x0004 External Interrupt Request 1 */ -# define ATMEGA_IRQ_INT2 2 /* 0x0006 External Interrupt Request 2 */ -# define ATMEGA_IRQ_PCINT0 3 /* 0x0008 Pin Change Interrupt Request 0 */ -# define ATMEGA_IRQ_PCINT1 4 /* 0x000a Pin Change Interrupt Request 1 */ -# define ATMEGA_IRQ_PCINT2 5 /* 0x000c Pin Change Interrupt Request 2 */ -# define ATMEGA_IRQ_PCINT3 6 /* 0x000e Pin Change Interrupt Request 3 */ -# define ATMEGA_IRQ_WDT 7 /* 0x0010 Watchdog Time-Out Interrupt */ -# define ATMEGA_IRQ_T2COMPA 8 /* 0x0012 TIMER2 COMPA Timer/Counter2 Compare Match */ -# define ATMEGA_IRQ_T2COMPB 9 /* 0x0014 TIMER2 COMPB Timer/Counter2 Compare Match */ -# define ATMEGA_IRQ_T2OVF 10 /* 0x0016 TIMER2 OVF Timer/Counter2 Overflow */ -# define ATMEGA_IRQ_T1CAPT 11 /* 0x0018 TIMER1 CAPT Timer/Counter1 Capture Event */ -# define ATMEGA_IRQ_T1COMPA 12 /* 0x001a TIMER1 COMPA Timer/Counter1 Compare Match A */ -# define ATMEGA_IRQ_T1COMPB 13 /* 0x001c TIMER1 COMPB Timer/Counter1 Compare Match B */ -# define ATMEGA_IRQ_T1OVF 14 /* 0x001e TIMER1 OVF Timer/Counter1 Overflow */ -# define ATMEGA_IRQ_T0COMPA 15 /* 0x0020 TIMER0 COMP Timer/Counter0 Compare Match */ -# define ATMEGA_IRQ_T0COMPB 16 /* 0x0022 TIMER0 COMP Timer/Counter0 Compare Match */ -# define ATMEGA_IRQ_T0OVF 17 /* 0x0024 TIMER0 OVF Timer/Counter0 Overflow */ -# define ATMEGA_IRQ_SPI 18 /* 0x0026 STC SPI Serial Transfer Complete */ -# define ATMEGA_IRQ_U0RX 19 /* 0x0028 USART0 Rx Complete */ -# define ATMEGA_IRQ_U0DRE 20 /* 0x002a USART0 Data Register Empty */ -# define ATMEGA_IRQ_U0TX 21 /* 0x002c USART0 Tx Complete */ -# define ATMEGA_IRQ_ANACOMP 22 /* 0x002e ANALOG COMP Analog Comparator */ -# define ATMEGA_IRQ_ADC 23 /* 0x0030 ADC Conversion Complete */ -# define ATMEGA_IRQ_EE 24 /* 0x0032 EEPROM Ready */ -# define ATMEGA_IRQ_TWI 25 /* 0x0034 TWI Two-wire Serial Interface */ -# define ATMEGA_IRQ_SPMRDY 26 /* 0x0036 Store Program Memory Ready */ -# define ATMEGA_IRQ_U1RX 27 /* 0x0038 USART1 Rx Complete */ -# define ATMEGA_IRQ_U1DRE 28 /* 0x003a USART1 Data Register Empty */ -# define ATMEGA_IRQ_U1TX 29 /* 0x003c USART1 Tx Complete */ -# define ATMEGA_IRQ_T3CAPT 30 /* 0x003e TIMER3 CAPT Timer/Counter3 Capture Event */ -# define ATMEGA_IRQ_T3COMPA 31 /* 0x0040 TIMER3 COMPA Timer/Counter3 Compare Match A */ -# define ATMEGA_IRQ_T3COMPB 32 /* 0x0042 TIMER3 COMPB Timer/Counter3 Compare Match B */ -# define ATMEGA_IRQ_T3OVF 33 /* 0x0044 TIMER3 OVF Timer/Counter3 Overflow */ +# define ATMEGA_IRQ_INT0 0 /* 0x0002 External Interrupt Request 0 */ +# define ATMEGA_IRQ_INT1 1 /* 0x0004 External Interrupt Request 1 */ +# define ATMEGA_IRQ_INT2 2 /* 0x0006 External Interrupt Request 2 */ +# define ATMEGA_IRQ_PCINT0 3 /* 0x0008 Pin Change Interrupt Request 0 */ +# define ATMEGA_IRQ_PCINT1 4 /* 0x000a Pin Change Interrupt Request 1 */ +# define ATMEGA_IRQ_PCINT2 5 /* 0x000c Pin Change Interrupt Request 2 */ +# define ATMEGA_IRQ_PCINT3 6 /* 0x000e Pin Change Interrupt Request 3 */ +# define ATMEGA_IRQ_WDT 7 /* 0x0010 Watchdog Time-Out Interrupt */ +# define ATMEGA_IRQ_T2COMPA 8 /* 0x0012 TIMER2 COMPA Timer/Counter2 Compare Match */ +# define ATMEGA_IRQ_T2COMPB 9 /* 0x0014 TIMER2 COMPB Timer/Counter2 Compare Match */ +# define ATMEGA_IRQ_T2OVF 10 /* 0x0016 TIMER2 OVF Timer/Counter2 Overflow */ +# define ATMEGA_IRQ_T1CAPT 11 /* 0x0018 TIMER1 CAPT Timer/Counter1 Capture Event */ +# define ATMEGA_IRQ_T1COMPA 12 /* 0x001a TIMER1 COMPA Timer/Counter1 Compare Match A */ +# define ATMEGA_IRQ_T1COMPB 13 /* 0x001c TIMER1 COMPB Timer/Counter1 Compare Match B */ +# define ATMEGA_IRQ_T1OVF 14 /* 0x001e TIMER1 OVF Timer/Counter1 Overflow */ +# define ATMEGA_IRQ_T0COMPA 15 /* 0x0020 TIMER0 COMP Timer/Counter0 Compare Match */ +# define ATMEGA_IRQ_T0COMPB 16 /* 0x0022 TIMER0 COMP Timer/Counter0 Compare Match */ +# define ATMEGA_IRQ_T0OVF 17 /* 0x0024 TIMER0 OVF Timer/Counter0 Overflow */ +# define ATMEGA_IRQ_SPI 18 /* 0x0026 STC SPI Serial Transfer Complete */ +# define ATMEGA_IRQ_U0RX 19 /* 0x0028 USART0 Rx Complete */ +# define ATMEGA_IRQ_U0DRE 20 /* 0x002a USART0 Data Register Empty */ +# define ATMEGA_IRQ_U0TX 21 /* 0x002c USART0 Tx Complete */ +# define ATMEGA_IRQ_ANACOMP 22 /* 0x002e ANALOG COMP Analog Comparator */ +# define ATMEGA_IRQ_ADC 23 /* 0x0030 ADC Conversion Complete */ +# define ATMEGA_IRQ_EE 24 /* 0x0032 EEPROM Ready */ +# define ATMEGA_IRQ_TWI 25 /* 0x0034 TWI Two-wire Serial Interface */ +# define ATMEGA_IRQ_SPMRDY 26 /* 0x0036 Store Program Memory Ready */ +# define ATMEGA_IRQ_U1RX 27 /* 0x0038 USART1 Rx Complete */ +# define ATMEGA_IRQ_U1DRE 28 /* 0x003a USART1 Data Register Empty */ +# define ATMEGA_IRQ_U1TX 29 /* 0x003c USART1 Tx Complete */ +# define ATMEGA_IRQ_T3CAPT 30 /* 0x003e TIMER3 CAPT Timer/Counter3 Capture Event */ +# define ATMEGA_IRQ_T3COMPA 31 /* 0x0040 TIMER3 COMPA Timer/Counter3 Compare Match A */ +# define ATMEGA_IRQ_T3COMPB 32 /* 0x0042 TIMER3 COMPB Timer/Counter3 Compare Match B */ +# define ATMEGA_IRQ_T3OVF 33 /* 0x0044 TIMER3 OVF Timer/Counter3 Overflow */ -# define NR_IRQS 34 -# define ATMEGA_PC_SIZE 16 -# define XCPTCONTEXT_REGS 37 /* Size of the register state save array (in bytes) */ +# define NR_IRQS 34 +# define AVR_PC_SIZE 16 +# define XCPTCONTEXT_REGS 37 /* Size of the register state save array (in bytes) */ #elif defined(CONFIG_ARCH_CHIP_ATMEGA2560) @@ -167,7 +167,7 @@ # define ATMEGA_IRQ_USART0_UDRE 27 /* 0x0034 USART0 UDRE USART0 Data Register Empty */ # define ATMEGA_IRQ_USART0_TXC 28 /* 0x0036 USART0 TX USART0 Tx Complete */ # define ATMEGA_IRQ_ANA_COMP 29 /* 0x0038 ANALOG COMP Analog Comparator */ -# define ATMEGA_IRQ_ADC 30 /* 0x003A ADC ADC Conversion Complete */ +# define ATMEGA_IRQ_ADC 30 /* 0x003A ADC ADC Conversion Complete */ # define ATMEGA_IRQ_EE_RDY 31 /* 0x003C EE READY EEPROM Ready */ # define ATMEGA_IRQ_TIM3_CAPT 32 /* 0x003E TIMER3 CAPT Timer/Counter3 Capture Event */ # define ATMEGA_IRQ_TIM3_COMPA 33 /* 0x0040 TIMER3 COMPA Timer/Counter3 Compare Match A */ @@ -177,7 +177,7 @@ # define ATMEGA_IRQ_USART1_RXC 37 /* 0x0048 USART1 RX USART1 Rx Complete */ # define ATMEGA_IRQ_USART1_UDRE 38 /* 0x004A USART1 UDRE USART1 Data Register Empty */ # define ATMEGA_IRQ_USART1_TXC 39 /* 0x004C USART1 TX USART1 Tx Complete */ -# define ATMEGA_IRQ_TWI 40 /* 0x004E TWI 2-wire Serial Interface */ +# define ATMEGA_IRQ_TWI 40 /* 0x004E TWI 2-wire Serial Interface */ # define ATMEGA_IRQ_SPM_RDY 41 /* 0x0050 SPM READY Store Program Memory Ready */ # define ATMEGA_IRQ_TIM4_CAPT 42 /* 0x0052 TIMER4 CAPT Timer/Counter4 Capture Event */ # define ATMEGA_IRQ_TIM4_COMPA 43 /* 0x0054 TIMER4 COMPA Timer/Counter4 Compare Match A */ @@ -197,7 +197,7 @@ # define ATMEGA_IRQ_USART3_TXC 57 /* 0x0070 USART3 TX USART3 Tx Complete */ # define NR_IRQS 58 -# define ATMEGA_PC_SIZE 24 +# define AVR_PC_SIZE 24 # define XCPTCONTEXT_REGS 38 /* Size of the register state save array (in bytes) */ #else diff --git a/arch/avr/include/avr/irq.h b/arch/avr/include/avr/irq.h index 9c8ec670afc..9868e03fb55 100644 --- a/arch/avr/include/avr/irq.h +++ b/arch/avr/include/avr/irq.h @@ -34,7 +34,7 @@ ****************************************************************************/ /* This file should never be included directed but, rather, only indirectly - * through nuttx/irq.h + * through nuttx/irq.h. */ #ifndef __ARCH_AVR_INCLUDE_AVR_IRQ_H @@ -93,7 +93,7 @@ #define REG_PC0 35 /* PC */ #define REG_PC1 36 -#if ATMEGA_PC_SIZE > 16 +#if AVR_PC_SIZE > 16 # define REG_PC2 37 #endif diff --git a/arch/avr/include/xmega/xmegac_irq.h b/arch/avr/include/xmega/xmegac_irq.h index 150826319ee..77813e04d66 100644 --- a/arch/avr/include/xmega/xmegac_irq.h +++ b/arch/avr/include/xmega/xmegac_irq.h @@ -86,6 +86,7 @@ #define XMEGA_IRQ_USB xx /* 0x00fa USB on port D Interrupt base */ #define NR_IRQS xx +#define AVR_PC_SIZE xx /**************************************************************************** * Public Types diff --git a/arch/avr/src/avr/excptmacros.h b/arch/avr/src/avr/excptmacros.h index 8458255fc93..2af838560dc 100644 --- a/arch/avr/src/avr/excptmacros.h +++ b/arch/avr/src/avr/excptmacros.h @@ -335,9 +335,9 @@ /* Pop the return address from the stack (PC0 then PC1). R18:19 are Call-used */ -#if ATMEGA_PC_SIZE > 16 +#if AVR_PC_SIZE > 16 pop r20 -#endif /* ATMEGA_PC_SIZE */ +#endif /* AVR_PC_SIZE */ pop r19 pop r18 @@ -402,9 +402,9 @@ /* Save the return address that we have saved in r18:19*/ -#if ATMEGA_PC_SIZE > 16 +#if AVR_PC_SIZE > 16 st x+, r20 -#endif /* ATMEGA_PC_SIZE */ +#endif /* AVR_PC_SIZE */ st x+, r19 st x+, r18 .endm @@ -435,7 +435,7 @@ */ movw r28, r26 /* Get a pointer to the PC0/PC1 storage location */ -#if ATMEGA_PC_SIZE <= 16 +#if AVR_PC_SIZE <= 16 adiw r28, REG_PC0 #else adiw r28, REG_PC2 @@ -457,7 +457,7 @@ * --- <- SP */ -#if ATMEGA_PC_SIZE <= 16 +#if AVR_PC_SIZE <= 16 ld r25, y+ /* Load PC0 (r25) then PC1 (r24) */ ld r24, y+ push r24 /* Push PC0 and PC1 on the stack (PC1 then PC0) */