Merge remote-tracking branch 'origin/master' into ieee802154

2026-06-06 00:14:22 +08:00 · 2017-03-22 14:26:20 -06:00
parent b03d46d36d 4c6646ad5d
commit 0be851d339
147 changed files with 26628 additions and 334 deletions
@@ -8,7 +8,7 @@
  <tr align="center" bgcolor="#e4e4e4">
    <td>
      <h1><big><font color="#3c34ec"><i>NuttX README Files</i></font></big></h1>
-      <p>Last Updated: February 19, 2017</p>
+      <p>Last Updated: March 21, 2017</p>
    </td>
  </tr>
 </table>
@@ -297,6 +297,8 @@ nuttx/
 |   |   `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/us7032evb1/README.txt" target="_blank"><b><i>README.txt</i></b></a>
 |   |- viewtool-stm32f107/
 |   |   `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/viewtool-stm32f107/README.txt" target="_blank"><b><i>README.txt</i></b></a>
 |   |- xmc4500-relax/
 |   |   `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/xmc4500-relax/README.txt" target="_blank"><b><i>README.txt</i></b></a>
 |   |- xtrs/
 |   |   `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/xtrs/README.txt" target="_blank"><b><i>README.txt</i></b></a>
 |   |- z16f2800100zcog/
@@ -1681,6 +1681,8 @@ nuttx/
 |   |   `- README.txt
 |   |- viewtool-stm32f107/
 |   |   `- README.txt
 |   |- xmc5400-relax/
 |   |   `- README.txt
 |   |- xtrs/
 |   |   `- README.txt
 |   |- z16f2800100zcog/
@@ -151,12 +151,20 @@ config ARCH_CHIP_LPC43XX
 	---help---
 		NPX LPC43XX architectures (ARM Cortex-M4).
 config ARCH_CHIP_MOXART
 	bool "MoxART"
 	select ARCH_ARM7TDMI
 	select ARCH_HAVE_RESET
 	select ARCH_HAVE_SERIAL_TERMIOS
 	---help---
 		MoxART family
 config ARCH_CHIP_NUC1XX
 	bool "Nuvoton NUC100/120"
 	select ARCH_CORTEXM0
 	select ARCH_HAVE_CMNVECTOR
 	---help---
-		NPX LPC43XX architectures (ARM Cortex-M4).
+		Nuvoton NUC100/120 architectures (ARM Cortex-M0).
 config ARCH_CHIP_SAMA5
 	bool "Atmel SAMA5"
@@ -270,13 +278,18 @@ config ARCH_CHIP_TMS570
 	---help---
 		TI TMS570 family
-config ARCH_CHIP_MOXART
+config ARCH_CHIP_XMC4
-	bool "MoxART"
+	bool "Infineon XMC4xxx"
-	select ARCH_ARM7TDMI
+	select ARCH_HAVE_CMNVECTOR
-	select ARCH_HAVE_RESET
+	select ARCH_CORTEXM4
-	select ARCH_HAVE_SERIAL_TERMIOS
+	select ARCH_HAVE_MPU
 	select ARCH_HAVE_RAMFUNCS
 	select ARCH_HAVE_I2CRESET
 	select ARM_HAVE_MPU_UNIFIED
 	select ARMV7M_CMNVECTOR
 	select ARMV7M_HAVE_STACKCHECK
 	---help---
-		MoxART family
+		Infineon XMC4xxx(ARM Cortex-M4) architectures
 endchoice
@@ -421,6 +434,7 @@ config ARCH_CHIP
 	default "lpc2378"	if ARCH_CHIP_LPC2378
 	default "lpc31xx"	if ARCH_CHIP_LPC31XX
 	default "lpc43xx"	if ARCH_CHIP_LPC43XX
 	default "moxart"	if ARCH_CHIP_MOXART
 	default "nuc1xx"	if ARCH_CHIP_NUC1XX
 	default "sama5"		if ARCH_CHIP_SAMA5
 	default "samdl"		if ARCH_CHIP_SAMD || ARCH_CHIP_SAML
@@ -431,7 +445,7 @@ config ARCH_CHIP
 	default "stm32l4"	if ARCH_CHIP_STM32L4
 	default "str71x"	if ARCH_CHIP_STR71X
 	default "tms570"	if ARCH_CHIP_TMS570
-	default "moxart"	if ARCH_CHIP_MOXART
+	default "xmc4"		if ARCH_CHIP_XMC4
 config ARM_TOOLCHAIN_IAR
 	bool
@@ -662,6 +676,9 @@ endif
 if ARCH_CHIP_LPC43XX
 source arch/arm/src/lpc43xx/Kconfig
 endif
 if ARCH_CHIP_MOXART
 source arch/arm/src/moxart/Kconfig
 endif
 if ARCH_CHIP_NUC1XX
 source arch/arm/src/nuc1xx/Kconfig
 endif
@@ -692,8 +709,8 @@ endif
 if ARCH_CHIP_TMS570
 source arch/arm/src/tms570/Kconfig
 endif
-if ARCH_CHIP_MOXART
+if ARCH_CHIP_XMC4
-source arch/arm/src/moxart/Kconfig
+source arch/arm/src/xmc4/Kconfig
 endif
 endif # ARCH_ARM
@@ -0,0 +1,139 @@
 /************************************************************************************
 * arch/arm/include/xmc4/chip.h
 *
 *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
 *   Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 * 3. Neither the name NuttX nor the names of its contributors may be
 *    used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 *
 ************************************************************************************/
 #ifndef __ARCH_ARM_INCLUDE_XMC4_CHIP_H
 #define __ARCH_ARM_INCLUDE_XMC4_CHIP_H
 /************************************************************************************
 * Included Files
 ************************************************************************************/
 #include <nuttx/config.h>
 /************************************************************************************
 * Pre-processor Definitions
 ************************************************************************************/
 /* Get customizations for each supported chip */
 #if defined(CONFIG_ARCH_CHIP_XMC4500)
 #  define XMC4_NUSIC          3          /* Three USIC modules: USCI0-2 */
 #  undef  XMC4_SCU_GATING                /* No clock gating registers */
 #  define XMC4_NECAT          0          /* No EtherCAT support */
 #elif defined(CONFIG_ARCH_CHIP_XMC4700)
 #  define XMC4_NUSIC          3          /* Three USIC modules: USCI0-2 */
 #  define XMC4_SCU_GATING     1          /* Has clock gating registers */
 #  define XMC4_NECAT          0          /* No EtherCAT support */
 #elif defined(CONFIG_ARCH_CHIP_XMC4800)
 #  define XMC4_NUSIC          3          /* Three USIC modules: USCI0-2 */
 #  define XMC4_SCU_GATING     1          /* Has clock gating registers */
 #  define XMC4_NECAT          1          /* One EtherCAT module */
 #else
 #  error "Unsupported XMC4xxx chip"
 #endif
 /* NVIC priority levels *************************************************************/
 /* Each priority field holds a priority value.  The lower the value, the greater the
 * priority of the corresponding interrupt.  The XMC4500 implements only bits[7:2]
 * of this field, bits[1:0] read as zero and ignore writes.
 */
 #define NVIC_SYSH_PRIORITY_MIN     0xfc /* All bits[7:2] set is minimum priority */
 #define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
 #define NVIC_SYSH_PRIORITY_MAX     0x00 /* Zero is maximum priority */
 #define NVIC_SYSH_PRIORITY_STEP    0x04 /* Steps between supported priority values */
 /* If CONFIG_ARMV7M_USEBASEPRI is selected, then interrupts will be disabled
 * by setting the BASEPRI register to NVIC_SYSH_DISABLE_PRIORITY so that most
 * interrupts will not have execution priority.  SVCall must have execution
 * priority in all cases.
 *
 * In the normal cases, interrupts are not nest-able and all interrupts run
 * at an execution priority between NVIC_SYSH_PRIORITY_MIN and
 * NVIC_SYSH_PRIORITY_MAX (with NVIC_SYSH_PRIORITY_MAX reserved for SVCall).
 *
 * If, in addition, CONFIG_ARCH_HIPRI_INTERRUPT is defined, then special
 * high priority interrupts are supported.  These are not "nested" in the
 * normal sense of the word.  These high priority interrupts can interrupt
 * normal processing but execute outside of OS (although they can "get back
 * into the game" via a PendSV interrupt).
 *
 * In the normal course of things, interrupts must occasionally be disabled
 * using the up_irq_save() inline function to prevent contention in use of
 * resources that may be shared between interrupt level and non-interrupt
 * level logic.  Now the question arises, if CONFIG_ARCH_HIPRI_INTERRUPT,
 * do we disable all interrupts (except SVCall), or do we only disable the
 * "normal" interrupts.  Since the high priority interrupts cannot interact
 * with the OS, you may want to permit the high priority interrupts even if
 * interrupts are disabled.  The setting CONFIG_ARCH_INT_DISABLEALL can be
 * used to select either behavior:
 *
 *   ----------------------------+--------------+----------------------------
 *   CONFIG_ARCH_HIPRI_INTERRUPT |      NO      |             YES
 *   ----------------------------+--------------+--------------+-------------
 *   CONFIG_ARCH_INT_DISABLEALL  |     N/A      |     YES      |      NO
 *   ----------------------------+--------------+--------------+-------------
 *                               |              |              |    SVCall
 *                               |    SVCall    |    SVCall    |    HIGH
 *   Disable here and below --------> MAXNORMAL ---> HIGH --------> MAXNORMAL
 *                               |              |    MAXNORMAL |
 *   ----------------------------+--------------+--------------+-------------
 */
 #if defined(CONFIG_ARCH_HIPRI_INTERRUPT) && defined(CONFIG_ARCH_INT_DISABLEALL)
 #  define NVIC_SYSH_MAXNORMAL_PRIORITY  (NVIC_SYSH_PRIORITY_MAX + 2*NVIC_SYSH_PRIORITY_STEP)
 #  define NVIC_SYSH_HIGH_PRIORITY       (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP)
 #  define NVIC_SYSH_DISABLE_PRIORITY    NVIC_SYSH_HIGH_PRIORITY
 #  define NVIC_SYSH_SVCALL_PRIORITY     NVIC_SYSH_PRIORITY_MAX
 #else
 #  define NVIC_SYSH_MAXNORMAL_PRIORITY  (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP)
 #  define NVIC_SYSH_HIGH_PRIORITY       NVIC_SYSH_PRIORITY_MAX
 #  define NVIC_SYSH_DISABLE_PRIORITY    NVIC_SYSH_MAXNORMAL_PRIORITY
 #  define NVIC_SYSH_SVCALL_PRIORITY     NVIC_SYSH_PRIORITY_MAX
 #endif
 /************************************************************************************
 * Public Types
 ************************************************************************************/
 /************************************************************************************
 * Public Data
 ************************************************************************************/
 /************************************************************************************
 * Public Functions
 ************************************************************************************/
 #endif /* __ARCH_ARM_INCLUDE_XMC4_CHIP_H */
@@ -0,0 +1,120 @@
 /****************************************************************************
 * arch/arm/include/xmc4/irq.h
 *
 *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
 *   Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 * 3. Neither the name NuttX nor the names of its contributors may be
 *    used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 *
 ****************************************************************************/
 /* This file should never be included directed but, rather, only indirectly
 * through nuttx/irq.h
 */
 #ifndef __ARCH_ARM_INCLUDE_XMC4_IRQ_H
 #define __ARCH_ARM_INCLUDE_XMC4_IRQ_H
 /************************************************************************************
 * Included Files
 ************************************************************************************/
 #include <nuttx/config.h>
 #include <nuttx/irq.h>
 /************************************************************************************
 * Pre-processor Definitions
 ************************************************************************************/
 /* IRQ numbers.  The IRQ number corresponds vector number and hence map directly to
 * bits in the NVIC.  This does, however, waste several words of memory in the IRQ
 * to handle mapping tables.
 */
 /* Processor Exceptions (vectors 0-15) */
 #define XMC4_IRQ_RESERVED      (0)   /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
                                     /* Vector  0: Reset stack pointer value */
                                     /* Vector  1: Reset (not handler as an IRQ) */
 #define XMC4_IRQ_NMI           (2)   /* Vector  2: Non-Maskable Interrupt (NMI) */
 #define XMC4_IRQ_HARDFAULT     (3)   /* Vector  3: Hard fault */
 #define XMC4_IRQ_MEMFAULT      (4)   /* Vector  4: Memory management (MPU) */
 #define XMC4_IRQ_BUSFAULT      (5)   /* Vector  5: Bus fault */
 #define XMC4_IRQ_USAGEFAULT    (6)   /* Vector  6: Usage fault */
                                     /* Vectors 7-10: Reserved */
 #define XMC4_IRQ_SVCALL        (11)  /* Vector 11: SVC call */
 #define XMC4_IRQ_DBGMONITOR    (12)  /* Vector 12: Debug Monitor */
                                     /* Vector 13: Reserved */
 #define XMC4_IRQ_PENDSV        (14)  /* Vector 14: Pendable system service request */
 #define XMC4_IRQ_SYSTICK       (15)  /* Vector 15: System tick */
 /* External interrupts (vectors >= 16).  These definitions are chip-specific */
 #define XMC4_IRQ_FIRST         (16)  /* Vector number of the first external interrupt */
 #if defined(CONFIG_ARCH_CHIP_XMC4500)
 #  include <arch/xmc4/xmc4500_irq.h>
 #else
  /* The interrupt vectors for other parts are defined in other documents and may or
   * may not be the same as above (the family members are all very similar)  This
   * error just means that you have to look at the document and determine for yourself
   * if the vectors are the same.
   */
 #  error "No IRQ numbers for this XMC4xxx part"
 #endif
 /************************************************************************************
 * Public Types
 ************************************************************************************/
 /************************************************************************************
 * Public Data
 ************************************************************************************/
 #ifndef __ASSEMBLY__
 #ifdef __cplusplus
 #define EXTERN extern "C"
 extern "C"
 {
 #else
 #define EXTERN extern
 #endif
 /************************************************************************************
 * Public Functions
 ************************************************************************************/
 #undef EXTERN
 #ifdef __cplusplus
 }
 #endif
 #endif
 #endif /* __ARCH_ARM_INCLUDE_XMC4_IRQ_H */
@@ -0,0 +1,225 @@
 /*****************************************************************************
 * arch/arm/include/xmc4/xmc4500_.h
 *
 *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
 *   Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 * 3. Neither the name NuttX nor the names of its contributors may be
 *    used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 *
 ****************************************************************************/
 /* This file should never be included directed but, rather, only indirectly
 * through nuttx/irq.h
 */
 #ifndef xmc4__ARCH_ARM_INCLUDE_XMC4_XM4500_IRQ_H
 #define xmc4__ARCH_ARM_INCLUDE_XMC4_XM4500_IRQ_H
 /*****************************************************************************
 * Included Files
 ****************************************************************************/
 #include <nuttx/config.h>
 /*****************************************************************************
 * Pre-processor Definitions
 ****************************************************************************/
 /* IRQ numbers.  The IRQ number corresponds vector number and hence map
 * directly to bits in the NVIC.  This does, however, waste several words of
 * memory in the IRQ to handle mapping tables.
 *
 * Processor Exceptions (vectors 0-15).  These common definitions can be found
 * in the file nuttx/arch/arm/include/kinets/irq.h which includes this file
 *
 * External interrupts (vectors >= 16)
 *
 * Acronyms:
 *  ADC   - Analog to Digital Converter
 *  CCU   - Capture Compare Unit
 *  DAC   - Digital to Analog Converter
 *  DSD   - Delta Sigmoid Demodulator
 *  ERU   - External Request Unit
 *  FCE   - Flexible CRC Engine
 *  GPDMA - General Purpose DMA
 *  LEDTS - LED and Touch Sense Control Unit
 *  PMU   - Program Management Unit
 *  POSIF - Position Interface
 *  SDMMC - Multi Media Card Interface
 *  USB   - Universal Serial Bus
 *  USCI  - Universal Serial Interface
 */
 #define XMC4_IRQ_SCU        (XMC4_IRQ_FIRST+0)   /*   0: System Control */
 #define XMC4_IRQ_ERU0_SR0   (XMC4_IRQ_FIRST+1)   /*   1: ERU0, SR0 */
 #define XMC4_IRQ_ERU0_SR1   (XMC4_IRQ_FIRST+2)   /*   2: ERU0, SR1 */
 #define XMC4_IRQ_ERU0_SR2   (XMC4_IRQ_FIRST+3)   /*   3: ERU0, SR2 */
 #define XMC4_IRQ_ERU0_SR3   (XMC4_IRQ_FIRST+4)   /*   4: ERU0, SR3 */
 #define XMC4_IRQ_ERU1_SR0   (XMC4_IRQ_FIRST+5)   /*   5: ERU1, SR0 */
 #define XMC4_IRQ_ERU1_SR1   (XMC4_IRQ_FIRST+6)   /*   6: ERU1, SR1 */
 #define XMC4_IRQ_ERU1_SR2   (XMC4_IRQ_FIRST+7)   /*   7: ERU1, SR2 */
 #define XMC4_IRQ_ERU1_SR3   (XMC4_IRQ_FIRST+8)   /*   8: ERU1, SR3 */
 #define XMC4_IRQ_RESVD009   (XMC4_IRQ_FIRST+9)   /*   9: Reserved */
 #define XMC4_IRQ_RESVD010   (XMC4_IRQ_FIRST+10)  /*  10: Reserved */
 #define XMC4_IRQ_RESVD011   (XMC4_IRQ_FIRST+11)  /*  11: Reserved */
 #define XMC4_IRQ_PMU1_SR0   (XMC4_IRQ_FIRST+12)  /*  12: PMU, SR0 */
 #define XMC4_IRQ_RESVD011   (XMC4_IRQ_FIRST+13)  /*  13: Reserved */
 #define XMC4_IRQ_VADC_COSR0 (XMC4_IRQ_FIRST+14)  /*  14: ADC Common Block 0 */
 #define XMC4_IRQ_VADC_COSR1 (XMC4_IRQ_FIRST+15)  /*  15: ADC Common Block 1 */
 #define XMC4_IRQ_VADC_COSR2 (XMC4_IRQ_FIRST+16)  /*  16: ADC Common Block 2 */
 #define XMC4_IRQ_VADC_COSR3 (XMC4_IRQ_FIRST+17)  /*  17: ADC Common Block 3 */
 #define XMC4_IRQ_VADC_GOSR0 (XMC4_IRQ_FIRST+18)  /*  18: ADC Group 0, SR0 */
 #define XMC4_IRQ_VADC_GOSR1 (XMC4_IRQ_FIRST+19)  /*  19: ADC Group 0, SR1 */
 #define XMC4_IRQ_VADC_GOSR2 (XMC4_IRQ_FIRST+20)  /*  20: ADC Group 0, SR2 */
 #define XMC4_IRQ_VADC_GOSR3 (XMC4_IRQ_FIRST+21)  /*  21: ADC Group 0, SR3 */
 #define XMC4_IRQ_VADC_G1SR0 (XMC4_IRQ_FIRST+22)  /*  22: ADC Group 1, SR0 */
 #define XMC4_IRQ_VADC_G1SR1 (XMC4_IRQ_FIRST+23)  /*  23: ADC Group 1, SR1 */
 #define XMC4_IRQ_VADC_G1SR2 (XMC4_IRQ_FIRST+24)  /*  24: ADC Group 1, SR2 */
 #define XMC4_IRQ_VADC_G1SR3 (XMC4_IRQ_FIRST+25)  /*  25: ADC Group 1, SR3 */
 #define XMC4_IRQ_VADC_G2SR0 (XMC4_IRQ_FIRST+26)  /*  26: ADC Group 2, SR0 */
 #define XMC4_IRQ_VADC_G2SR1 (XMC4_IRQ_FIRST+27)  /*  27: ADC Group 2, SR1 */
 #define XMC4_IRQ_VADC_G2SR2 (XMC4_IRQ_FIRST+28)  /*  28: ADC Group 2, SR2 */
 #define XMC4_IRQ_VADC_G2SR3 (XMC4_IRQ_FIRST+29)  /*  29: ADC Group 2, SR3 */
 #define XMC4_IRQ_VADC_G3SR0 (XMC4_IRQ_FIRST+30)  /*  30: ADC Group 3, SR0 */
 #define XMC4_IRQ_VADC_G3SR1 (XMC4_IRQ_FIRST+31)  /*  31: ADC Group 3, SR1 */
 #define XMC4_IRQ_VADC_G3SR2 (XMC4_IRQ_FIRST+32)  /*  32: ADC Group 3, SR2 */
 #define XMC4_IRQ_VADC_G3SR3 (XMC4_IRQ_FIRST+33)  /*  33: ADC Group 3, SR3 */
 #define XMC4_IRQ_DSD_SRM0   (XMC4_IRQ_FIRST+34)  /*  34: DSD Main, SRM0 */
 #define XMC4_IRQ_DSD_SRM1   (XMC4_IRQ_FIRST+35)  /*  35: DSD Main, SRM1 */
 #define XMC4_IRQ_DSD_SRM2   (XMC4_IRQ_FIRST+36)  /*  36: DSD Main, SRM2 */
 #define XMC4_IRQ_DSD_SRM3   (XMC4_IRQ_FIRST+37)  /*  37: DSD Main, SRM3 */
 #define XMC4_IRQ_DSD_SRA0   (XMC4_IRQ_FIRST+38)  /*  38: DSD Auxiliary, SRA0 */
 #define XMC4_IRQ_DSD_SRA1   (XMC4_IRQ_FIRST+39)  /*  39: DSD Auxiliary, SRA1 */
 #define XMC4_IRQ_DSD_SRA2   (XMC4_IRQ_FIRST+40)  /*  40: DSD Auxiliary, SRA2 */
 #define XMC4_IRQ_DSD_SRA3   (XMC4_IRQ_FIRST+41)  /*  41: DSD Auxiliary, SRA3 */
 #define XMC4_IRQ_DAC_SR0    (XMC4_IRQ_FIRST+42)  /*  42: DAC, SR0 */
 #define XMC4_IRQ_DAC_SR1    (XMC4_IRQ_FIRST+43)  /*  43: DAC, SR1 */
 #define XMC4_IRQ_CCU40_SR0  (XMC4_IRQ_FIRST+44)  /*  44: CCU4 Module 0, SR0 */
 #define XMC4_IRQ_CCU40_SR1  (XMC4_IRQ_FIRST+45)  /*  45: CCU4 Module 0, SR1 */
 #define XMC4_IRQ_CCU40_SR2  (XMC4_IRQ_FIRST+46)  /*  46: CCU4 Module 0, SR2 */
 #define XMC4_IRQ_CCU40_SR3  (XMC4_IRQ_FIRST+47)  /*  47: CCU4 Module 0, SR3 */
 #define XMC4_IRQ_CCU41_SR0  (XMC4_IRQ_FIRST+48)  /*  48: CCU4 Module 1, SR0 */
 #define XMC4_IRQ_CCU41_SR1  (XMC4_IRQ_FIRST+49)  /*  49: CCU4 Module 1, SR1 */
 #define XMC4_IRQ_CCU41_SR2  (XMC4_IRQ_FIRST+50)  /*  50: CCU4 Module 1, SR2 */
 #define XMC4_IRQ_CCU41_SR3  (XMC4_IRQ_FIRST+51)  /*  51: CCU4 Module 1, SR3 */
 #define XMC4_IRQ_CCU42_SR0  (XMC4_IRQ_FIRST+52)  /*  52: CCU4 Module 2, SR0 */
 #define XMC4_IRQ_CCU42_SR1  (XMC4_IRQ_FIRST+53)  /*  53: CCU4 Module 2, SR1 */
 #define XMC4_IRQ_CCU42_SR2  (XMC4_IRQ_FIRST+54)  /*  54: CCU4 Module 2, SR2 */
 #define XMC4_IRQ_CCU42_SR3  (XMC4_IRQ_FIRST+55)  /*  55: CCU4 Module 2, SR3 */
 #define XMC4_IRQ_CCU43_SR0  (XMC4_IRQ_FIRST+56)  /*  56: CCU4 Module 3, SR0 */
 #define XMC4_IRQ_CCU43_SR1  (XMC4_IRQ_FIRST+57)  /*  57: CCU4 Module 3, SR1 */
 #define XMC4_IRQ_CCU43_SR2  (XMC4_IRQ_FIRST+58)  /*  58: CCU4 Module 3, SR2 */
 #define XMC4_IRQ_CCU43_SR3  (XMC4_IRQ_FIRST+59)  /*  59: CCU4 Module 3, SR3 */
 #define XMC4_IRQ_CCU80_SR0  (XMC4_IRQ_FIRST+60)  /*  60: CCU8 Module 0, SR0 */
 #define XMC4_IRQ_CCU80_SR1  (XMC4_IRQ_FIRST+61)  /*  61: CCU8 Module 0, SR1 */
 #define XMC4_IRQ_CCU80_SR2  (XMC4_IRQ_FIRST+62)  /*  62: CCU8 Module 0, SR2 */
 #define XMC4_IRQ_CCU80_SR3  (XMC4_IRQ_FIRST+63)  /*  63: CCU8 Module 0, SR3 */
 #define XMC4_IRQ_CCU81_SR0  (XMC4_IRQ_FIRST+64)  /*  64: CCU8 Module 1, SR0 */
 #define XMC4_IRQ_CCU81_SR1  (XMC4_IRQ_FIRST+65)  /*  65: CCU8 Module 1, SR1 */
 #define XMC4_IRQ_CCU81_SR2  (XMC4_IRQ_FIRST+66)  /*  66: CCU8 Module 1, SR2 */
 #define XMC4_IRQ_CCU81_SR3  (XMC4_IRQ_FIRST+67)  /*  67: CCU8 Module 1, SR3 */
 #define XMC4_IRQ_POSIF0_SR0 (XMC4_IRQ_FIRST+68)  /*  68: POSIF Module 0, SR0 */
 #define XMC4_IRQ_POSIF0_SR1 (XMC4_IRQ_FIRST+69)  /*  69: POSIF Module 0, SR1 */
 #define XMC4_IRQ_POSIF1_SR0 (XMC4_IRQ_FIRST+70)  /*  70: POSIF Module 1, SR0 */
 #define XMC4_IRQ_POSIF1_SR1 (XMC4_IRQ_FIRST+71)  /*  71: POSIF Module 1, SR1 */
 #define XMC4_IRQ_RESVD072   (XMC4_IRQ_FIRST+72)  /*  72: Reserved */
 #define XMC4_IRQ_RESVD073   (XMC4_IRQ_FIRST+73)  /*  73: Reserved */
 #define XMC4_IRQ_RESVD074   (XMC4_IRQ_FIRST+74)  /*  74: Reserved */
 #define XMC4_IRQ_RESVD075   (XMC4_IRQ_FIRST+75)  /*  75: Reserved */
 #define XMC4_IRQ_CAN_SR0    (XMC4_IRQ_FIRST+76)  /*  76: MultiCAN, SR0 */
 #define XMC4_IRQ_CAN_SR1    (XMC4_IRQ_FIRST+77)  /*  77: MultiCAN, SR1 */
 #define XMC4_IRQ_CAN_SR2    (XMC4_IRQ_FIRST+78)  /*  78: MultiCAN, SR2 */
 #define XMC4_IRQ_CAN_SR3    (XMC4_IRQ_FIRST+79)  /*  79: MultiCAN, SR3 */
 #define XMC4_IRQ_CAN_SR4    (XMC4_IRQ_FIRST+80)  /*  80: MultiCAN, SR4 */
 #define XMC4_IRQ_CAN_SR5    (XMC4_IRQ_FIRST+81)  /*  81: MultiCAN, SR5 */
 #define XMC4_IRQ_CAN_SR6    (XMC4_IRQ_FIRST+82)  /*  82: MultiCAN, SR6 */
 #define XMC4_IRQ_CAN_SR7    (XMC4_IRQ_FIRST+83)  /*  83: MultiCAN, SR7 */
 #define XMC4_IRQ_USIC0_SR0  (XMC4_IRQ_FIRST+84)  /*  84: USIC0 Channel, SR0 */
 #define XMC4_IRQ_USIC0_SR1  (XMC4_IRQ_FIRST+85)  /*  85: USIC0 Channel, SR1 */
 #define XMC4_IRQ_USIC0_SR2  (XMC4_IRQ_FIRST+86)  /*  86: USIC0 Channel, SR2 */
 #define XMC4_IRQ_USIC0_SR3  (XMC4_IRQ_FIRST+87)  /*  87: USIC0 Channel, SR3 */
 #define XMC4_IRQ_USIC0_SR4  (XMC4_IRQ_FIRST+88)  /*  88: USIC0 Channel, SR4 */
 #define XMC4_IRQ_USIC0_SR5  (XMC4_IRQ_FIRST+89)  /*  89: USIC0 Channel, SR5 */
 #define XMC4_IRQ_USIC1_SR0  (XMC4_IRQ_FIRST+90)  /*  90: USIC1 Channel, SR0 */
 #define XMC4_IRQ_USIC1_SR1  (XMC4_IRQ_FIRST+91)  /*  91: USIC1 Channel, SR1 */
 #define XMC4_IRQ_USIC1_SR2  (XMC4_IRQ_FIRST+92)  /*  92: USIC1 Channel, SR2 */
 #define XMC4_IRQ_USIC1_SR3  (XMC4_IRQ_FIRST+93)  /*  93: USIC1 Channel, SR3 */
 #define XMC4_IRQ_USIC1_SR4  (XMC4_IRQ_FIRST+94)  /*  94: USIC1 Channel, SR4 */
 #define XMC4_IRQ_USIC1_SR5  (XMC4_IRQ_FIRST+95)  /*  95: USIC1 Channel, SR5 */
 #define XMC4_IRQ_USIC2_SR0  (XMC4_IRQ_FIRST+96)  /*  96: USIC1 Channel, SR0 */
 #define XMC4_IRQ_USIC2_SR1  (XMC4_IRQ_FIRST+97)  /*  97: USIC1 Channel, SR1 */
 #define XMC4_IRQ_USIC2_SR2  (XMC4_IRQ_FIRST+98)  /*  98: USIC1 Channel, SR2 */
 #define XMC4_IRQ_USIC2_SR3  (XMC4_IRQ_FIRST+99)  /*  99: USIC1 Channel, SR3 */
 #define XMC4_IRQ_USIC2_SR4  (XMC4_IRQ_FIRST+100) /* 100: USIC1 Channel, SR4 */
 #define XMC4_IRQ_USIC2_SR5  (XMC4_IRQ_FIRST+101) /* 101: USIC1 Channel, SR5 */
 #define XMC4_IRQ_LEDTS0_SR0 (XMC4_IRQ_FIRST+102) /* 102: LEDTS0, SR0 */
 #define XMC4_IRQ_RESVD103   (XMC4_IRQ_FIRST+103) /* 103: Reserved */
 #define XMC4_IRQ_FCR_SR0    (XMC4_IRQ_FIRST+104) /* 102: FCE, SR0 */
 #define XMC4_IRQ_GPCMA0_SR0 (XMC4_IRQ_FIRST+105) /* 105: GPDMA0, SR0 */
 #define XMC4_IRQ_SDMMC_SR0  (XMC4_IRQ_FIRST+106) /* 106: SDMMC, SR0 */
 #define XMC4_IRQ_USB0_SR0   (XMC4_IRQ_FIRST+107) /* 107: USB, SR0 */
 #define XMC4_IRQ_ETH0_SR0   (XMC4_IRQ_FIRST+108) /* 108: Ethernet, module 0, SR0 */
 #define XMC4_IRQ_ECAT0_SR0  (XMC4_IRQ_FIRST+109) /* 109: EtherCAT, module 0, SR0 */
 #define XMC4_IRQ_GPCMA1_SR0 (XMC4_IRQ_FIRST+110) /* 110: GPDMA1, SR0 */
 #define XMC4_IRQ_RESVD111   (XMC4_IRQ_FIRST+111) /* 111: Reserved */
 #define NR_INTERRUPTS       112                  /* 112 Non core IRQs*/
 #define NR_VECTORS          (XMC4_IRQ_FIRST+NR_INTERRUPTS) /* 118 vectors */
 /* GPIO IRQ interrupts -- To be provided */
 #define NR_IRQS             NR_VECTORS
 /*****************************************************************************
 * Public Types
 ****************************************************************************/
 /*****************************************************************************
 * Public Data
 ****************************************************************************/
 #ifndef __ASSEMBLY__
 #ifdef __cplusplus
 #define EXTERN extern "C"
 extern "C"
 {
 #else
 #define EXTERN extern
 #endif
 /*****************************************************************************
 * Public Functions
 ****************************************************************************/
 #undef EXTERN
 #ifdef __cplusplus
 }
 #endif
 #endif
 #endif /* xmc4__ARCH_ARM_INCLUDE_XMC4_XM4500_IRQ_H */
@@ -159,16 +159,6 @@ void up_irqinitialize(void)
      (void)getreg32(A1X_INTC_IRQ_PEND(i));   /* Reading status clears pending interrupts */
    }
  /* Colorize the interrupt stack for debug purposes */
 #if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3
  {
    size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~3);
    up_stack_color((FAR void *)((uintptr_t)&g_intstackbase - intstack_size),
                   intstack_size);
  }
 #endif
  /* Set the interrupt base address to zero.  We do not use the vectored
   * interrupts.
   */
@@ -66,22 +66,11 @@
 #  define HAVE_KERNEL_HEAP 1
 #endif
-/* ARM requires at least a 4-byte stack alignment.  For use with EABI and
+/* For use with EABI and floating point, the stack must be aligned to 8-byte
- * floating point, the stack must be aligned to 8-byte addresses.
+ * addresses.
 */
-#ifndef CONFIG_STACK_ALIGNMENT
+#define CONFIG_STACK_ALIGNMENT 8
 /* The symbol  __ARM_EABI__ is defined by GCC if EABI is being used.  If you
 * are not using GCC, make sure that CONFIG_STACK_ALIGNMENT is set correctly!
 */
 #  ifdef __ARM_EABI__
 #    define CONFIG_STACK_ALIGNMENT 8
 #  else
 #    define CONFIG_STACK_ALIGNMENT 4
 #  endif
 #endif
 /* Stack alignment macros */
@@ -233,9 +222,9 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype)
      top_of_stack = (uint32_t)tcb->stack_alloc_ptr + stack_size - 4;
-      /* The ARM stack must be aligned; 4 byte alignment for OABI and
+      /* The ARM stack must be aligned to 8-byte alignment for EABI.
-       * 8-byte alignment for EABI. If necessary top_of_stack must be
+       * If necessary top_of_stack must be rounded down to the next 
-       * rounded down to the next boundary
+       * boundary
       */
      top_of_stack = STACK_ALIGN_DOWN(top_of_stack);
@@ -100,7 +100,7 @@ static void up_calibratedelay(void)
 *
 ****************************************************************************/
-#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 7
+#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3
 static inline void up_color_intstack(void)
 {
  uint32_t *ptr = (uint32_t *)&g_intstackalloc;
@@ -53,22 +53,11 @@
 * Pre-processor Macros
 ****************************************************************************/
-/* ARM requires at least a 4-byte stack alignment.  For use with EABI and
+/* For use with EABI and floating point, the stack must be aligned to 8-byte
- * floating point, the stack must be aligned to 8-byte addresses.
+ * addresses.
 */
-#ifndef CONFIG_STACK_ALIGNMENT
+#define CONFIG_STACK_ALIGNMENT 8
 /* The symbol  __ARM_EABI__ is defined by GCC if EABI is being used.  If you
 * are not using GCC, make sure that CONFIG_STACK_ALIGNMENT is set correctly!
 */
 #  ifdef __ARM_EABI__
 #    define CONFIG_STACK_ALIGNMENT 8
 #  else
 #    define CONFIG_STACK_ALIGNMENT 4
 #  endif
 #endif
 /* Stack alignment macros */
@@ -56,22 +56,11 @@
 * Pre-processor Macros
 ****************************************************************************/
-/* ARM requires at least a 4-byte stack alignment.  For use with EABI and
+/* For use with EABI and floating point, the stack must be aligned to 8-byte
- * floating point, the stack must be aligned to 8-byte addresses.
+ * addresses.
 */
-#ifndef CONFIG_STACK_ALIGNMENT
+#define CONFIG_STACK_ALIGNMENT 8
 /* The symbol  __ARM_EABI__ is defined by GCC if EABI is being used.  If you
 * are not using GCC, make sure that CONFIG_STACK_ALIGNMENT is set correctly!
 */
 #  ifdef __ARM_EABI__
 #    define CONFIG_STACK_ALIGNMENT 8
 #  else
 #    define CONFIG_STACK_ALIGNMENT 4
 #  endif
 #endif
 /* Stack alignment macros */
@@ -143,9 +132,9 @@ int up_use_stack(struct tcb_s *tcb, void *stack, size_t stack_size)
  top_of_stack = (uint32_t)tcb->stack_alloc_ptr + stack_size - 4;
-  /* The ARM stack must be aligned; 4 byte alignment for OABI and 8-byte
+  /* The ARM stack must be aligned to 8-byte alignment for EABI.
-   * alignment for EABI. If necessary top_of_stack must be rounded down
+   * If necessary top_of_stack must be rounded down to the next 
-   * to the next boundary
+   * boundary
   */
  top_of_stack = STACK_ALIGN_DOWN(top_of_stack);
@@ -56,22 +56,11 @@
 * Pre-processor Definitions
 ****************************************************************************/
-/* ARM requires at least a 4-byte stack alignment.  For use with EABI and
+/* For use with EABI and floating point, the stack must be aligned to 8-byte
- * floating point, the stack must be aligned to 8-byte addresses.
+ * addresses.
 */
-#ifndef CONFIG_STACK_ALIGNMENT
+#define CONFIG_STACK_ALIGNMENT 8
 /* The symbol  __ARM_EABI__ is defined by GCC if EABI is being used.  If you
 * are not using GCC, make sure that CONFIG_STACK_ALIGNMENT is set correctly!
 */
 #  ifdef __ARM_EABI__
 #    define CONFIG_STACK_ALIGNMENT 8
 #  else
 #    define CONFIG_STACK_ALIGNMENT 4
 #  endif
 #endif
 /****************************************************************************
 * Public Functions
@@ -319,16 +319,6 @@ void up_irqinitialize(void)
      putreg32(0xffffffff, NVIC_IRQ_CLEAR(i));
    }
 #if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3
  /* Colorize the interrupt stack for debug purposes */
  {
    size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~3);
    up_stack_color((FAR void *)((uintptr_t)&g_intstackbase - intstack_size),
                   intstack_size);
  }
 #endif
  /* Make sure that we are using the correct vector table.  The default
   * vector address is 0x0000:0000 but if we are executing code that is
   * positioned in SRAM or in external FLASH, then we may need to reset
@@ -93,16 +93,6 @@ void up_irqinitialize(void)
   * access to the GIC.
   */
  /* Colorize the interrupt stack for debug purposes */
 #if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3
  {
    size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~3);
    up_stack_color((FAR void *)((uintptr_t)&g_intstackbase - intstack_size),
                   intstack_size);
  }
 #endif
  /* Initialize the Generic Interrupt Controller (GIC) for CPU0 */
  arm_gic0_initialize();  /* Initialization unique to CPU0 */
@@ -385,16 +385,6 @@ void up_irqinitialize(void)
      putreg32(0, regaddr);
    }
  /* Colorize the interrupt stack for debug purposes */
 #if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3
  {
    size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~3);
    up_stack_color((FAR void *)((uintptr_t)&g_intstackbase - intstack_size),
                   intstack_size);
  }
 #endif
  /* Make sure that we are using the correct vector table.  The default
   * vector address is 0x0000:0000 but if we are executing code that is
   * positioned in SRAM or in external FLASH, then we may need to reset
@@ -431,16 +431,6 @@ void up_irqinitialize(void)
   * access to the AIC.
   */
  /* Colorize the interrupt stack for debug purposes */
 #if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3
  {
    size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~3);
    up_stack_color((FAR void *)((uintptr_t)&g_intstackbase - intstack_size),
                   intstack_size);
  }
 #endif
  /* Redirect all interrupts to the AIC if so configured */
  sam_aic_redirection();
@@ -381,16 +381,6 @@ void up_irqinitialize(void)
      putreg32(0, regaddr);
    }
  /* Colorize the interrupt stack for debug purposes */
 #if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3
  {
    size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~3);
    up_stack_color((FAR void *)((uintptr_t)&g_intstackbase - intstack_size),
                   intstack_size);
  }
 #endif
  /* Make sure that we are using the correct vector table.  The default
   * vector address is 0x0000:0000 but if we are executing code that is
   * positioned in SRAM or in external FLASH, then we may need to reset
@@ -6190,6 +6190,16 @@ config STM32_I2C_DUTY16_9
 	default n
 	depends on STM32_I2C
 config STM32_I2C_DMA
 	bool "I2C DMA Support"
 	default n
 	depends on STM32_I2C && STM32_STM32F40XX && STM32_DMA1
 	---help---
 		This option enables the DMA for I2C transfers.
 		Note: The user can define CONFIG_I2C_DMAPRIO: a custom priority value for the
 		I2C dma streams, else the default priority level is set to medium.
 		Note: This option is compatible with CONFIG_I2C_POLLED.
 endmenu
 menu "SDIO Configuration"
@@ -217,6 +217,10 @@ ifeq ($(CONFIG_DAC),y)
 CHIP_CSRCS += stm32_dac.c
 endif
 ifeq ($(CONFIG_COMP),y)
 CHIP_CSRCS += stm32_comp.c
 endif
 ifeq ($(CONFIG_STM32_1WIREDRIVER),y)
 CHIP_CSRCS += stm32_1wire.c
 endif
@@ -72,7 +72,8 @@
 #  define COMP_CSR_INMSEL_1P2VREF   (1 << COMP_CSR_INMSEL_SHIFT)  /* 0001: 1/2 of Vrefint */
 #  define COMP_CSR_INMSEL_3P4VREF   (2 << COMP_CSR_INMSEL_SHIFT)  /* 0010: 3/4 of Vrefint */
 #  define COMP_CSR_INMSEL_VREF      (3 << COMP_CSR_INMSEL_SHIFT)  /* 0011: Vrefint */
-#  define COMP_CSR_INMSEL_PA4       (4 << COMP_CSR_INMSEL_SHIFT)  /* 0100: PA4 or DAC1_CH output if enabled */
+#  define COMP_CSR_INMSEL_PA4       (4 << COMP_CSR_INMSEL_SHIFT)  /* 0100: PA4 or */
 #  define COMP_CSR_INMSEL_DAC1CH1   (4 << COMP_CSR_INMSEL_SHIFT)  /* 0100: DAC1_CH1 output if enabled */
 #  define COMP_CSR_INMSEL_DAC1CH2   (5 << COMP_CSR_INMSEL_SHIFT)  /* 0101: DAC1_CH2 output */
 #  define COMP_CSR_INMSEL_PA2       (6 << COMP_CSR_INMSEL_SHIFT)  /* 0110: PA2 (COMP2 only) */
 #  define COMP_CSR_INMSEL_PB2       (7 << COMP4_CSR_INMSEL_SHIFT) /* 0111: PB2 (COMP4 only) */
@@ -87,32 +88,32 @@
                                                                  /* 0011: Reserved */
                                                                  /* 0100: Reserved */
 #  define COMP_CSR_OUTSEL_BRK2_     (5 << COMP_CSR_INMSEL_SHIFT)  /* 0101: Timer 1 break input2 */
-#  define COMP_CSR_OUTSEL_T1OCCC    (6 << COMP_CSR_INMSEL_SHIFT)  /* 0110: Timer 1 OCREF_CLR input (COMP2 only) */
+#  define COMP_CSR_OUTSEL_T1OCC     (6 << COMP_CSR_INMSEL_SHIFT)  /* 0110: Timer 1 OCREF_CLR input (COMP2 only) */
 #  define COMP_CSR_OUTSEL_T3CAP3    (6 << COMP_CSR_INMSEL_SHIFT)  /* 0110: Timer 3 input apture 3 (COMP4 only) */
 #  define COMP_CSR_OUTSEL_T2CAP2    (6 << COMP_CSR_INMSEL_SHIFT)  /* 0110: Timer 2 input apture 2 (COMP6 only) */
 #  define COMP_CSR_OUTSEL_T1CAP1    (7 << COMP_CSR_INMSEL_SHIFT)  /* 0111: Timer 1 input capture 1 (COMP2 only) */
 #  define COMP_CSR_OUTSEL_T2CAP4    (8 << COMP_CSR_INMSEL_SHIFT)  /* 1000: Timer 2 input capture 4 (COMP2 only) */
 #  define COMP_CSR_OUTSEL_T15CAP2   (8 << COMP_CSR_INMSEL_SHIFT)  /* 1000: Timer 15 input capture 2 (COMP4 only) */
-#  define COMP_CSR_OUTSEL_T2OCC     (8 << COMP_CSR_INMSEL_SHIFT)  /* 1000: Timer 2 OCREF CLR input (COMP6 only) */
+#  define COMP6_CSR_OUTSEL_T2OCC    (8 << COMP_CSR_INMSEL_SHIFT)  /* 1000: Timer 2 OCREF CLR input (COMP6 only) */
-#  define COMP_CSR_OUTSEL_T2OCC     (9 << COMP_CSR_INMSEL_SHIFT)  /* 1001: Timer 2 OCREF_CLR input (COMP2 only) */
+#  define COMP2_CSR_OUTSEL_T2OCC    (9 << COMP_CSR_INMSEL_SHIFT)  /* 1001: Timer 2 OCREF_CLR input (COMP2 only) */
 #  define COMP_CSR_OUTSEL_T16OCC    (9 << COMP_CSR_INMSEL_SHIFT)  /* 1001: Timer 16 OCREF_CLR input (COMP6 only) */
 #  define COMP_CSR_OUTSEL_T3CAP1    (10 << COMP_CSR_INMSEL_SHIFT) /* 1010: Timer 3 input capture 1 (COMP2 only) */
-#  define COMP_CSR_OUTSEL_T3CAP1    (10 << COMP_CSR_INMSEL_SHIFT) /* 1010: Timer 15 OCREF_CLR input (COMP4 only) */
+#  define COMP_CSR_OUTSEL_T15OCC    (10 << COMP_CSR_INMSEL_SHIFT) /* 1010: Timer 15 OCREF_CLR input (COMP4 only) */
-#  define COMP_CSR_OUTSEL_T3CAP1    (10 << COMP_CSR_INMSEL_SHIFT) /* 1010: Timer 16 input capture 1 (COMP6 only) */
+#  define COMP_CSR_OUTSEL_T16CAP1   (10 << COMP_CSR_INMSEL_SHIFT) /* 1010: Timer 16 input capture 1 (COMP6 only) */
 #  define COMP_CSR_OUTSEL_T3OCC     (11 << COMP_CSR_INMSEL_SHIFT) /* 1011: Timer 3 OCREF_CLR input (COMP2,COMP4 only) */
                                                /* Bit 14: Reserved */
 #define COMP_CSR_POL                (1 << 15)   /* Bit 15: comparator output polarity */
                                                /* Bits 16-17: Reserved */
-#define COMP_CSR_BLANCKING_SHIFT    (18)        /* Bit 18-20: comparator output blanking source */
+#define COMP_CSR_BLANKING_SHIFT    (18)        /* Bit 18-20: comparator output blanking source */
-#define COMP_CSR_BLANCKING_MASK     (7 << COMP_CSR_BLANCKING_SHIFT)
+#define COMP_CSR_BLANKING_MASK     (7 << COMP_CSR_BLANKING_SHIFT)
-#  define COMP_CSR_BLANCKING_DIS    (0 << COMP_CSR_BLANCKING_SHIFT)  /* 000: No blanking */
+#  define COMP_CSR_BLANKING_DIS    (0 << COMP_CSR_BLANKING_SHIFT)  /* 000: No blanking */
-#  define COMP_CSR_BLANCKING_T1OC5  (1 << COMP_CSR_BLANCKING_SHIFT)  /* 001: TIM1 OC5 as blanking source (COMP2 only) */
+#  define COMP_CSR_BLANKING_T1OC5  (1 << COMP_CSR_BLANKING_SHIFT)  /* 001: TIM1 OC5 as blanking source (COMP2 only) */
-#  define COMP_CSR_BLANCKING_T3OC4  (1 << COMP_CSR_BLANCKING_SHIFT)  /* 001: TIM3 OC4 as blanking source (COMP4 only) */
+#  define COMP_CSR_BLANKING_T3OC4  (1 << COMP_CSR_BLANKING_SHIFT)  /* 001: TIM3 OC4 as blanking source (COMP4 only) */
-#  define COMP_CSR_BLANCKING_T2OC3  (2 << COMP_CSR_BLANCKING_SHIFT)  /* 010: TIM2 OC3 as blanking source (COMP2 only) */
+#  define COMP_CSR_BLANKING_T2OC3  (2 << COMP_CSR_BLANKING_SHIFT)  /* 010: TIM2 OC3 as blanking source (COMP2 only) */
-#  define COMP_CSR_BLANCKING_T3OC3  (3 << COMP_CSR_BLANCKING_SHIFT)  /* 011: TIM3 OC3 as blanking source (COMP2 only) */
+#  define COMP_CSR_BLANKING_T3OC3  (3 << COMP_CSR_BLANKING_SHIFT)  /* 011: TIM3 OC3 as blanking source (COMP2 only) */
-#  define COMP_CSR_BLANCKING_T15OC1 (3 << COMP_CSR_BLANCKING_SHIFT)  /* 011: TIM15 OC1 as blanking source (COMP4 only) */
+#  define COMP_CSR_BLANKING_T15OC1 (3 << COMP_CSR_BLANKING_SHIFT)  /* 011: TIM15 OC1 as blanking source (COMP4 only) */
-#  define COMP_CSR_BLANCKING_T2OC4  (3 << COMP_CSR_BLANCKING_SHIFT)  /* 011: TIM2 OC4 as blanking source (COMP6 only) */
+#  define COMP_CSR_BLANKING_T2OC4  (3 << COMP_CSR_BLANKING_SHIFT)  /* 011: TIM2 OC4 as blanking source (COMP6 only) */
-#  define COMP_CSR_BLANCKING_T15OC2 (4 << COMP_CSR_BLANCKING_SHIFT)  /* 011: TIM15 OC2 as blanking source (COMP6 only) */
+#  define COMP_CSR_BLANKING_T15OC2 (4 << COMP_CSR_BLANKING_SHIFT)  /* 011: TIM15 OC2 as blanking source (COMP6 only) */
                                                /* Bit 21: Reserved  */
 #define COMP_CSR_INMSEL_DAC2CH1     (1 << 22)   /* Bit 22: used with bits 4-6, DAC2_CH1 output */
                                                /* Bits 23-29: Reserved */
@@ -0,0 +1,366 @@
 /************************************************************************************
 * arch/arm/src/stm32/chip/stm32f33xxx_dma.h
 *
 *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
 *   Authors: Gregory Nutt <gnutt@nuttx.org>
 *            Mateusz Szafoni <raiden00@railab.me>
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 * 3. Neither the name NuttX nor the names of its contributors may be
 *    used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 *
 ************************************************************************************/
 #ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F33XXX_DMA_H
 #define __ARCH_ARM_SRC_STM32_CHIP_STM32F33XXX_DMA_H
 /************************************************************************************
 * Pre-processor Definitions
 ************************************************************************************/
 /* 12 Channels Total: 7 DMA1 Channels(1-7) and 5 DMA2 channels (1-5) */
 #define DMA1 0
 #define DMA2 1
 #define DMA3 2
 #define DMA4 3
 #define DMA5 4
 #define DMA6 5
 #define DMA7 6
 /* Register Offsets *****************************************************************/
 #define STM32_DMA_ISR_OFFSET       0x0000 /* DMA interrupt status register */
 #define STM32_DMA_IFCR_OFFSET      0x0004 /* DMA interrupt flag clear register */
 #define STM32_DMACHAN_OFFSET(n)    (0x0014*(n))
 #define STM32_DMACHAN1_OFFSET      0x0000
 #define STM32_DMACHAN2_OFFSET      0x0014
 #define STM32_DMACHAN3_OFFSET      0x0028
 #define STM32_DMACHAN4_OFFSET      0x003c
 #define STM32_DMACHAN5_OFFSET      0x0050
 #define STM32_DMACHAN6_OFFSET      0x0064
 #define STM32_DMACHAN7_OFFSET      0x0078
 #define STM32_DMACHAN_CCR_OFFSET   0x0008 /* DMA channel configuration register */
 #define STM32_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */
 #define STM32_DMACHAN_CPAR_OFFSET  0x0010 /* DMA channel peripheral address register */
 #define STM32_DMACHAN_CMAR_OFFSET  0x0014 /* DMA channel 1 memory address register */
 #define STM32_DMA_CCR_OFFSET(n)   (STM32_DMACHAN_CCR_OFFSET+STM32_DMACHAN_OFFSET(n))
 #define STM32_DMA_CNDTR_OFFSET(n) (STM32_DMACHAN_CNDTR_OFFSET+STM32_DMACHAN_OFFSET(n))
 #define STM32_DMA_CPAR_OFFSET(n)  (STM32_DMACHAN_CPAR_OFFSET+STM32_DMACHAN_OFFSET(n))
 #define STM32_DMA_CMAR_OFFSET(n)  (STM32_DMACHAN_CMAR_OFFSET+STM32_DMACHAN_OFFSET(n))
 #define STM32_DMA_CCR1_OFFSET     0x0008 /* DMA channel 1 configuration register */
 #define STM32_DMA_CCR2_OFFSET     0x001c /* DMA channel 2 configuration register */
 #define STM32_DMA_CCR3_OFFSET     0x0030 /* DMA channel 3 configuration register */
 #define STM32_DMA_CCR4_OFFSET     0x0044 /* DMA channel 4 configuration register */
 #define STM32_DMA_CCR5_OFFSET     0x0058 /* DMA channel 5 configuration register */
 #define STM32_DMA_CCR6_OFFSET     0x006c /* DMA channel 6 configuration register */
 #define STM32_DMA_CCR7_OFFSET     0x0080 /* DMA channel 7 configuration register */
 #define STM32_DMA_CNDTR1_OFFSET   0x000c /* DMA channel 1 number of data register */
 #define STM32_DMA_CNDTR2_OFFSET   0x0020 /* DMA channel 2 number of data register */
 #define STM32_DMA_CNDTR3_OFFSET   0x0034 /* DMA channel 3 number of data register */
 #define STM32_DMA_CNDTR4_OFFSET   0x0048 /* DMA channel 4 number of data register */
 #define STM32_DMA_CNDTR5_OFFSET   0x005c /* DMA channel 5 number of data register */
 #define STM32_DMA_CNDTR6_OFFSET   0x0070 /* DMA channel 6 number of data register */
 #define STM32_DMA_CNDTR7_OFFSET   0x0084 /* DMA channel 7 number of data register */
 #define STM32_DMA_CPAR1_OFFSET    0x0010 /* DMA channel 1 peripheral address register */
 #define STM32_DMA_CPAR2_OFFSET    0x0024 /* DMA channel 2 peripheral address register */
 #define STM32_DMA_CPAR3_OFFSET    0x0038 /* DMA channel 3 peripheral address register */
 #define STM32_DMA_CPAR4_OFFSET    0x004c /* DMA channel 4 peripheral address register */
 #define STM32_DMA_CPAR5_OFFSET    0x0060 /* DMA channel 5 peripheral address register */
 #define STM32_DMA_CPAR6_OFFSET    0x0074 /* DMA channel 6 peripheral address register */
 #define STM32_DMA_CPAR7_OFFSET    0x0088 /* DMA channel 7 peripheral address register */
 #define STM32_DMA_CMAR1_OFFSET    0x0014 /* DMA channel 1 memory address register */
 #define STM32_DMA_CMAR2_OFFSET    0x0028 /* DMA channel 2 memory address register */
 #define STM32_DMA_CMAR3_OFFSET    0x003c /* DMA channel 3 memory address register */
 #define STM32_DMA_CMAR4_OFFSET    0x0050 /* DMA channel 4 memory address register */
 #define STM32_DMA_CMAR5_OFFSET    0x0064 /* DMA channel 5 memory address register */
 #define STM32_DMA_CMAR6_OFFSET    0x0078 /* DMA channel 6 memory address register */
 #define STM32_DMA_CMAR7_OFFSET    0x008c /* DMA channel 7 memory address register */
 /* Register Addresses ***************************************************************/
 #define STM32_DMA1_ISRC           (STM32_DMA1_BASE+STM32_DMA_ISR_OFFSET)
 #define STM32_DMA1_IFCR           (STM32_DMA1_BASE+STM32_DMA_IFCR_OFFSET)
 #define STM32_DMA1_CCR(n)         (STM32_DMA1_BASE+STM32_DMA_CCR_OFFSET(n))
 #define STM32_DMA1_CCR1           (STM32_DMA1_BASE+STM32_DMA_CCR1_OFFSET)
 #define STM32_DMA1_CCR2           (STM32_DMA1_BASE+STM32_DMA_CCR2_OFFSET)
 #define STM32_DMA1_CCR3           (STM32_DMA1_BASE+STM32_DMA_CCR3_OFFSET)
 #define STM32_DMA1_CCR4           (STM32_DMA1_BASE+STM32_DMA_CCR4_OFFSET)
 #define STM32_DMA1_CCR5           (STM32_DMA1_BASE+STM32_DMA_CCR5_OFFSET)
 #define STM32_DMA1_CCR6           (STM32_DMA1_BASE+STM32_DMA_CCR6_OFFSET)
 #define STM32_DMA1_CCR7           (STM32_DMA1_BASE+STM32_DMA_CCR7_OFFSET)
 #define STM32_DMA1_CNDTR(n)       (STM32_DMA1_BASE+STM32_DMA_CNDTR_OFFSET(n))
 #define STM32_DMA1_CNDTR1         (STM32_DMA1_BASE+STM32_DMA_CNDTR1_OFFSET)
 #define STM32_DMA1_CNDTR2         (STM32_DMA1_BASE+STM32_DMA_CNDTR2_OFFSET)
 #define STM32_DMA1_CNDTR3         (STM32_DMA1_BASE+STM32_DMA_CNDTR3_OFFSET)
 #define STM32_DMA1_CNDTR4         (STM32_DMA1_BASE+STM32_DMA_CNDTR4_OFFSET)
 #define STM32_DMA1_CNDTR5         (STM32_DMA1_BASE+STM32_DMA_CNDTR5_OFFSET)
 #define STM32_DMA1_CNDTR6         (STM32_DMA1_BASE+STM32_DMA_CNDTR6_OFFSET)
 #define STM32_DMA1_CNDTR7         (STM32_DMA1_BASE+STM32_DMA_CNDTR7_OFFSET)
 #define STM32_DMA1_CPAR(n)        (STM32_DMA1_BASE+STM32_DMA_CPAR_OFFSET(n))
 #define STM32_DMA1_CPAR1          (STM32_DMA1_BASE+STM32_DMA_CPAR1_OFFSET)
 #define STM32_DMA1_CPAR2          (STM32_DMA1_BASE+STM32_DMA_CPAR2_OFFSET)
 #define STM32_DMA1_CPAR3          (STM32_DMA1_BASE+STM32_DMA_CPAR3_OFFSET)
 #define STM32_DMA1_CPAR4          (STM32_DMA1_BASE+STM32_DMA_CPAR4_OFFSET)
 #define STM32_DMA1_CPAR5          (STM32_DMA1_BASE+STM32_DMA_CPAR5_OFFSET)
 #define STM32_DMA1_CPAR6          (STM32_DMA1_BASE+STM32_DMA_CPAR6_OFFSET)
 #define STM32_DMA1_CPAR7          (STM32_DMA1_BASE+STM32_DMA_CPAR7_OFFSET)
 #define STM32_DMA1_CMAR(n)        (STM32_DMA1_BASE+STM32_DMA_CMAR_OFFSET(n))
 #define STM32_DMA1_CMAR1          (STM32_DMA1_BASE+STM32_DMA_CMAR1_OFFSET)
 #define STM32_DMA1_CMAR2          (STM32_DMA1_BASE+STM32_DMA_CMAR2_OFFSET)
 #define STM32_DMA1_CMAR3          (STM32_DMA1_BASE+STM32_DMA_CMAR3_OFFSET)
 #define STM32_DMA1_CMAR4          (STM32_DMA1_BASE+STM32_DMA_CMAR4_OFFSET)
 #define STM32_DMA1_CMAR5          (STM32_DMA1_BASE+STM32_DMA_CMAR5_OFFSET)
 #define STM32_DMA1_CMAR6          (STM32_DMA1_BASE+STM32_DMA_CMAR6_OFFSET)
 #define STM32_DMA1_CMAR7          (STM32_DMA1_BASE+STM32_DMA_CMAR7_OFFSET)
 #define STM32_DMA2_ISRC           (STM32_DMA2_BASE+STM32_DMA_ISR_OFFSET)
 #define STM32_DMA2_IFCR           (STM32_DMA2_BASE+STM32_DMA_IFCR_OFFSET)
 #define STM32_DMA2_CCR(n)         (STM32_DMA2_BASE+STM32_DMA_CCR_OFFSET(n))
 #define STM32_DMA2_CCR1           (STM32_DMA2_BASE+STM32_DMA_CCR1_OFFSET)
 #define STM32_DMA2_CCR2           (STM32_DMA2_BASE+STM32_DMA_CCR2_OFFSET)
 #define STM32_DMA2_CCR3           (STM32_DMA2_BASE+STM32_DMA_CCR3_OFFSET)
 #define STM32_DMA2_CCR4           (STM32_DMA2_BASE+STM32_DMA_CCR4_OFFSET)
 #define STM32_DMA2_CCR5           (STM32_DMA2_BASE+STM32_DMA_CCR5_OFFSET)
 #define STM32_DMA2_CNDTR(n)       (STM32_DMA2_BASE+STM32_DMA_CNDTR_OFFSET(n))
 #define STM32_DMA2_CNDTR1         (STM32_DMA2_BASE+STM32_DMA_CNDTR1_OFFSET)
 #define STM32_DMA2_CNDTR2         (STM32_DMA2_BASE+STM32_DMA_CNDTR2_OFFSET)
 #define STM32_DMA2_CNDTR3         (STM32_DMA2_BASE+STM32_DMA_CNDTR3_OFFSET)
 #define STM32_DMA2_CNDTR4         (STM32_DMA2_BASE+STM32_DMA_CNDTR4_OFFSET)
 #define STM32_DMA2_CNDTR5         (STM32_DMA2_BASE+STM32_DMA_CNDTR5_OFFSET)
 #define STM32_DMA2_CPAR(n)        (STM32_DMA2_BASE+STM32_DMA_CPAR_OFFSET(n))
 #define STM32_DMA2_CPAR1          (STM32_DMA2_BASE+STM32_DMA_CPAR1_OFFSET)
 #define STM32_DMA2_CPAR2          (STM32_DMA2_BASE+STM32_DMA_CPAR2_OFFSET)
 #define STM32_DMA2_CPAR3          (STM32_DMA2_BASE+STM32_DMA_CPAR3_OFFSET)
 #define STM32_DMA2_CPAR4          (STM32_DMA2_BASE+STM32_DMA_CPAR4_OFFSET)
 #define STM32_DMA2_CPAR5          (STM32_DMA2_BASE+STM32_DMA_CPAR5_OFFSET)
 #define STM32_DMA2_CMAR(n)        (STM32_DMA2_BASE+STM32_DMA_CMAR_OFFSET(n))
 #define STM32_DMA2_CMAR1          (STM32_DMA2_BASE+STM32_DMA_CMAR1_OFFSET)
 #define STM32_DMA2_CMAR2          (STM32_DMA2_BASE+STM32_DMA_CMAR2_OFFSET)
 #define STM32_DMA2_CMAR3          (STM32_DMA2_BASE+STM32_DMA_CMAR3_OFFSET)
 #define STM32_DMA2_CMAR4          (STM32_DMA2_BASE+STM32_DMA_CMAR4_OFFSET)
 #define STM32_DMA2_CMAR5          (STM32_DMA2_BASE+STM32_DMA_CMAR5_OFFSET)
 /* Register Bitfield Definitions ****************************************************/
 #define DMA_CHAN_SHIFT(n)         ((n) << 2)
 #define DMA_CHAN_MASK             0x0f
 #define DMA_CHAN_GIF_BIT          (1 << 0)  /* Bit 0: Channel Global interrupt flag */
 #define DMA_CHAN_TCIF_BIT         (1 << 1)  /* Bit 1: Channel Transfer Complete flag */
 #define DMA_CHAN_HTIF_BIT         (1 << 2)  /* Bit 2: Channel Half Transfer flag */
 #define DMA_CHAN_TEIF_BIT         (1 << 3)  /* Bit 3: Channel Transfer Error flag */
 /* DMA interrupt status register */
 #define DMA_ISR_CHAN_SHIFT(n)     DMA_CHAN_SHIFT(n)
 #define DMA_ISR_CHAN_MASK(n)      (DMA_CHAN_MASK <<  DMA_ISR_CHAN_SHIFT(n))
 #define DMA_ISR_CHAN1_SHIFT       (0)       /* Bits 3-0:  DMA Channel 1 interrupt status */
 #define DMA_ISR_CHAN1_MASK        (DMA_CHAN_MASK <<  DMA_ISR_CHAN1_SHIFT)
 #define DMA_ISR_CHAN2_SHIFT       (4)       /* Bits 7-4:  DMA Channel 2 interrupt status */
 #define DMA_ISR_CHAN2_MASK        (DMA_CHAN_MASK <<  DMA_ISR_CHAN2_SHIFT)
 #define DMA_ISR_CHAN3_SHIFT       (8)       /* Bits 11-8:  DMA Channel 3 interrupt status */
 #define DMA_ISR_CHAN3_MASK        (DMA_CHAN_MASK <<  DMA_ISR_CHAN3_SHIFT)
 #define DMA_ISR_CHAN4_SHIFT       (12)      /* Bits 15-12:  DMA Channel 4 interrupt status */
 #define DMA_ISR_CHAN4_MASK        (DMA_CHAN_MASK <<  DMA_ISR_CHAN4_SHIFT)
 #define DMA_ISR_CHAN5_SHIFT       (16)      /* Bits 19-16:  DMA Channel 5 interrupt status */
 #define DMA_ISR_CHAN5_MASK        (DMA_CHAN_MASK <<  DMA_ISR_CHAN5_SHIFT)
 #define DMA_ISR_CHAN6_SHIFT       (20)      /* Bits 23-20:  DMA Channel 6 interrupt status */
 #define DMA_ISR_CHAN6_MASK        (DMA_CHAN_MASK <<  DMA_ISR_CHAN6_SHIFT)
 #define DMA_ISR_CHAN7_SHIFT       (24)      /* Bits 27-24:  DMA Channel 7 interrupt status */
 #define DMA_ISR_CHAN7_MASK        (DMA_CHAN_MASK <<  DMA_ISR_CHAN7_SHIFT)
 #define DMA_ISR_GIF(n)            (DMA_CHAN_GIF_BIT << DMA_ISR_CHAN_SHIFT(n))
 #define DMA_ISR_TCIF(n)           (DMA_CHAN_TCIF_BIT << DMA_ISR_CHAN_SHIFT(n))
 #define DMA_ISR_HTIF(n)           (DMA_CHAN_HTIF_BIT << DMA_ISR_CHAN_SHIFT(n))
 #define DMA_ISR_TEIF(n)           (DMA_CHAN_TEIF_BIT << DMA_ISR_CHAN_SHIFT(n))
 /* DMA interrupt flag clear register */
 #define DMA_IFCR_CHAN_SHIFT(n)    DMA_CHAN_SHIFT(n)
 #define DMA_IFCR_CHAN_MASK(n)     (DMA_CHAN_MASK <<  DMA_IFCR_CHAN_SHIFT(n))
 #define DMA_IFCR_CHAN1_SHIFT      (0)       /* Bits 3-0:  DMA Channel 1 interrupt flag clear */
 #define DMA_IFCR_CHAN1_MASK       (DMA_CHAN_MASK <<  DMA_IFCR_CHAN1_SHIFT)
 #define DMA_IFCR_CHAN2_SHIFT      (4)       /* Bits 7-4:  DMA Channel 2 interrupt flag clear */
 #define DMA_IFCR_CHAN2_MASK       (DMA_CHAN_MASK <<  DMA_IFCR_CHAN2_SHIFT)
 #define DMA_IFCR_CHAN3_SHIFT      (8)       /* Bits 11-8:  DMA Channel 3 interrupt flag clear */
 #define DMA_IFCR_CHAN3_MASK       (DMA_CHAN_MASK <<  DMA_IFCR_CHAN3_SHIFT)
 #define DMA_IFCR_CHAN4_SHIFT      (12)      /* Bits 15-12:  DMA Channel 4 interrupt flag clear */
 #define DMA_IFCR_CHAN4_MASK       (DMA_CHAN_MASK <<  DMA_IFCR_CHAN4_SHIFT)
 #define DMA_IFCR_CHAN5_SHIFT      (16)      /* Bits 19-16:  DMA Channel 5 interrupt flag clear */
 #define DMA_IFCR_CHAN5_MASK       (DMA_CHAN_MASK <<  DMA_IFCR_CHAN5_SHIFT)
 #define DMA_IFCR_CHAN6_SHIFT      (20)      /* Bits 23-20:  DMA Channel 6 interrupt flag clear */
 #define DMA_IFCR_CHAN6_MASK       (DMA_CHAN_MASK <<  DMA_IFCR_CHAN6_SHIFT)
 #define DMA_IFCR_CHAN7_SHIFT      (24)      /* Bits 27-24:  DMA Channel 7 interrupt flag clear */
 #define DMA_IFCR_CHAN7_MASK       (DMA_CHAN_MASK <<  DMA_IFCR_CHAN7_SHIFT)
 #define DMA_IFCR_ALLCHANNELS      (0x0fffffff)
 #define DMA_IFCR_CGIF(n)          (DMA_CHAN_GIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
 #define DMA_IFCR_CTCIF(n)         (DMA_CHAN_TCIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
 #define DMA_IFCR_CHTIF(n)         (DMA_CHAN_HTIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
 #define DMA_IFCR_CTEIF(n)         (DMA_CHAN_TEIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
 /* DMA channel configuration register */
 #define DMA_CCR_EN                (1 << 0)  /* Bit 0: Channel enable */
 #define DMA_CCR_TCIE              (1 << 1)  /* Bit 1: Transfer complete interrupt enable */
 #define DMA_CCR_HTIE              (1 << 2)  /* Bit 2: Half Transfer interrupt enable */
 #define DMA_CCR_TEIE              (1 << 3)  /* Bit 3: Transfer error interrupt enable */
 #define DMA_CCR_DIR               (1 << 4)  /* Bit 4: Data transfer direction */
 #define DMA_CCR_CIRC              (1 << 5)  /* Bit 5: Circular mode */
 #define DMA_CCR_PINC              (1 << 6)  /* Bit 6: Peripheral increment mode */
 #define DMA_CCR_MINC              (1 << 7)  /* Bit 7: Memory increment mode */
 #define DMA_CCR_PSIZE_SHIFT       (8)       /* Bits 8-9: Peripheral size */
 #define DMA_CCR_PSIZE_MASK        (3 << DMA_CCR_PSIZE_SHIFT)
 #  define DMA_CCR_PSIZE_8BITS     (0 << DMA_CCR_PSIZE_SHIFT) /* 00: 8-bits */
 #  define DMA_CCR_PSIZE_16BITS    (1 << DMA_CCR_PSIZE_SHIFT) /* 01: 16-bits */
 #  define DMA_CCR_PSIZE_32BITS    (2 << DMA_CCR_PSIZE_SHIFT) /* 10: 32-bits */
 #define DMA_CCR_MSIZE_SHIFT       (10)      /* Bits 10-11: Memory size */
 #define DMA_CCR_MSIZE_MASK        (3 << DMA_CCR_MSIZE_SHIFT)
 #  define DMA_CCR_MSIZE_8BITS     (0 << DMA_CCR_MSIZE_SHIFT) /* 00: 8-bits */
 #  define DMA_CCR_MSIZE_16BITS    (1 << DMA_CCR_MSIZE_SHIFT) /* 01: 16-bits */
 #  define DMA_CCR_MSIZE_32BITS    (2 << DMA_CCR_MSIZE_SHIFT) /* 10: 32-bits */
 #define DMA_CCR_PL_SHIFT          (12)      /* Bits 12-13: Channel Priority level */
 #define DMA_CCR_PL_MASK           (3 << DMA_CCR_PL_SHIFT)
 #  define DMA_CCR_PRILO           (0 << DMA_CCR_PL_SHIFT) /* 00: Low */
 #  define DMA_CCR_PRIMED          (1 << DMA_CCR_PL_SHIFT) /* 01: Medium */
 #  define DMA_CCR_PRIHI           (2 << DMA_CCR_PL_SHIFT) /* 10: High */
 #  define DMA_CCR_PRIVERYHI       (3 << DMA_CCR_PL_SHIFT) /* 11: Very high */
 #define DMA_CCR_MEM2MEM           (1 << 14) /* Bit 14: Memory to memory mode */
 #define DMA_CCR_ALLINTS           (DMA_CCR_TEIE|DMA_CCR_HTIE|DMA_CCR_TCIE)
 /* DMA channel number of data register */
 #define DMA_CNDTR_NDT_SHIFT       (0)       /* Bits 15-0: Number of data to Transfer */
 #define DMA_CNDTR_NDT_MASK        (0xffff << DMA_CNDTR_NDT_SHIFT)
 /* DMA Channel mapping.  Each DMA channel has a mapping to several possible
 * sources/sinks of data.  The requests from peripherals assigned to a channel
 * are simply OR'ed together before entering the DMA block.  This means that only
 * one request on a given channel can be enabled at once.
 *
 * Alternative DMA channel selections are provided with a numeric suffix like _1,
 * _2, etc.  Drivers, however, will use the pin selection without the numeric suffix.
 * Additional definitions are required in the board.h file.
 */
 #define STM32_DMA1_CHAN1          (0)
 #define STM32_DMA1_CHAN2          (1)
 #define STM32_DMA1_CHAN3          (2)
 #define STM32_DMA1_CHAN4          (3)
 #define STM32_DMA1_CHAN5          (4)
 #define STM32_DMA1_CHAN6          (5)
 #define STM32_DMA1_CHAN7          (6)
 #define STM32_DMA2_CHAN1          (7)
 #define STM32_DMA2_CHAN2          (8)
 #define STM32_DMA2_CHAN3          (9)
 #define STM32_DMA2_CHAN4          (10)
 #define STM32_DMA2_CHAN5          (11)
 #define DMACHAN_ADC1            STM32_DMA1_CHAN1
 #define DMACHAN_TIM2_CH3        STM32_DMA1_CHAN1
 #define DMACHAN_TIM17_CH1_1     STM32_DMA1_CHAN1
 #define DMACHAN_TIM17_UP_1      STM32_DMA1_CHAN1
 #define DMACHAN_ADC2_1          STM32_DMA1_CHAN2
 #define DMACHAN_SPI1_RX_1       STM32_DMA1_CHAN2
 #define DMACHAN_USART3_TX       STM32_DMA1_CHAN2
 #define DMACHAN_I2C1_TX_3       STM32_DMA1_CHAN4
 #define DMACHAN_TIM1_CH1        STM32_DMA1_CHAN2
 #define DMACHAN_TIM2_UP         STM32_DMA1_CHAN2
 #define DMACHAN_TIM3_CH3        STM32_DMA1_CHAN2
 #define DMACHAN_HRTIM1_M        STM32_DMA1_CHAN2
 #define DMACHAN_SPI1_TX_1       STM32_DMA1_CHAN3
 #define DMACHAN_USART3_RX       STM32_DMA1_CHAN3
 #define DMACHAN_I2C1_RX_2       STM32_DMA1_CHAN3
 #define DMACHAN_TIM3_CH4        STM32_DMA1_CHAN3
 #define DMACHAN_TIM3_UP         STM32_DMA1_CHAN3
 #define DMACHAN_TIM6_UP         STM32_DMA1_CHAN3
 #define DMACHAN_DAC1_CH1        STM32_DMA1_CHAN3
 #define DMACHAN_DAC16_CH1_1     STM32_DMA1_CHAN3
 #define DMACHAN_DAC16_UP_1      STM32_DMA1_CHAN3
 #define DMACHAN_HRTIM1_A        STM32_DMA1_CHAN3
 #define DMACHAN_ADC2_2          STM32_DMA1_CHAN4
 #define DMACHAN_SPI1_RX_2       STM32_DMA1_CHAN4
 #define DMACHAN_USART1_TX       STM32_DMA1_CHAN4
 #define DMACHAN_I2C1_TX_3       STM32_DMA1_CHAN4
 #define DMACHAN_TIM1_CH4        STM32_DMA1_CHAN4
 #define DMACHAN_TIM1_TRIG       STM32_DMA1_CHAN4
 #define DMACHAN_TIM1_COM        STM32_DMA1_CHAN4
 #define DMACHAN_TIM7_UP         STM32_DMA1_CHAN4
 #define DMACHAN_DAC2_CH2        STM32_DMA1_CHAN4
 #define DMACHAN_HRTIM1_B        STM32_DMA1_CHAN4
 #define DMACHAN_SPI1_TX_2       STM32_DMA1_CHAN5
 #define DMACHAN_USART1_RX       STM32_DMA1_CHAN5
 #define DMACHAN_I2C1_RX_3       STM32_DMA1_CHAN5
 #define DMACHAN_TIM1_UP         STM32_DMA1_CHAN5
 #define DMACHAN_TIM2_CH1        STM32_DMA1_CHAN5
 #define DMACHAN_DAC2_CH1        STM32_DMA1_CHAN5
 #define DMACHAN_TIM15_CH1       STM32_DMA1_CHAN5
 #define DMACHAN_TIM15_UP        STM32_DMA1_CHAN5
 #define DMACHAN_TIM15_TRIG      STM32_DMA1_CHAN5
 #define DMACHAN_TIM15_COM       STM32_DMA1_CHAN5
 #define DMACHAN_HRTIM1_C        STM32_DMA1_CHAN5
 #define DMACHAN_SPI1_RX_3       STM32_DMA1_CHAN6
 #define DMACHAN_USART2_RX       STM32_DMA1_CHAN6
 #define DMACHAN_I2C1_TX_1       STM32_DMA1_CHAN6
 #define DMACHAN_TIM1_CH3        STM32_DMA1_CHAN6
 #define DMACHAN_TIM3_CH1        STM32_DMA1_CHAN6
 #define DMACHAN_TIM3_TRIG       STM32_DMA1_CHAN6
 #define DMACHAN_TIM16_CH1_2     STM32_DMA1_CHAN6
 #define DMACHAN_TIM16_UP_2      STM32_DMA1_CHAN6
 #define DMACHAN_HRTIM1_D        STM32_DMA1_CHAN6
 #define DMACHAN_SPI1_TX_3       STM32_DMA1_CHAN7
 #define DMACHAN_USART2_TX       STM32_DMA1_CHAN7
 #define DMACHAN_I2C1_RX_1       STM32_DMA1_CHAN7
 #define DMACHAN_TIM2_CH2        STM32_DMA1_CHAN7
 #define DMACHAN_TIM2_CH4        STM32_DMA1_CHAN7
 #define DMACHAN_TIM17_CH1_2     STM32_DMA1_CHAN7
 #define DMACHAN_TIM17_UP_2      STM32_DMA1_CHAN7
 #define DMACHAN_HRTIM1_E        STM32_DMA1_CHAN7
 #endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F33XXX_DMA_H */
@@ -59,6 +59,7 @@
 #include "stm32_adc.h"
 //#include "stm32_bkp.h"
 #include "stm32_can.h"
 #include "stm32_comp.h"
 #include "stm32_dbgmcu.h"
 #include "stm32_dma.h"
 #include "stm32_dac.h"
@@ -6,6 +6,7 @@
 *   Authors: Gregory Nutt <gnutt@nuttx.org>
 *            Diego Sanchez <dsanchez@nx-engineering.com>
 *            Paul Alexander Patience <paul-a.patience@polymtl.ca>
 *            Mateusz Szafoni <raiden00@railab.me>
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
@@ -77,11 +78,12 @@
 #if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \
    defined(CONFIG_STM32_ADC3) || defined(CONFIG_STM32_ADC4)
-/* This implementation is for the STM32 F1, F2, F4 and STM32L15XX only */
+/* This implementation is for the STM32 F1, F2, F3, F4 and STM32L15XX only */
 #if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F20XX) || \
-    defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) || \
+    defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
-    defined(CONFIG_STM32_STM32F40XX) || defined(CONFIG_STM32_STM32L15XX)
+    defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F40XX) || \
    defined(CONFIG_STM32_STM32L15XX)
 /* At the moment there is no proper implementation for timers external
 * trigger in STM32L15XX May be added latter
@@ -91,6 +93,14 @@
 #  warning "There is no proper implementation for TIMER TRIGGERS at the moment"
 #endif
 /* At the moment there is no proper implementation for HRTIMER external
 * trigger in STM32F33XX
 */
 #if defined(ADC_HAVE_HRTIMER) && defined(CONFIG_STM32_STM32F33XX)
 #  warning "There is no proper implementation for HRTIMER TRIGGERS at the moment"
 #endif
 /****************************************************************************
 * Pre-processor Definitions
 ****************************************************************************/
@@ -108,6 +118,10 @@
 #  define RCC_RSTR_ADC2RST RCC_AHBRSTR_ADC12RST
 #  define RCC_RSTR_ADC3RST RCC_AHBRSTR_ADC34RST
 #  define RCC_RSTR_ADC4RST RCC_AHBRSTR_ADC34RST
 #elif defined(CONFIG_STM32_STM32F33XX)
 #  define STM32_RCC_RSTR   STM32_RCC_AHBRSTR
 #  define RCC_RSTR_ADC1RST RCC_AHBRSTR_ADC12RST
 #  define RCC_RSTR_ADC2RST RCC_AHBRSTR_ADC12RST
 #elif defined(CONFIG_STM32_STM32F37XX)
 #  define STM32_RCC_RSTR   STM32_RCC_APB2RSTR
 #  define RCC_RSTR_ADC1RST RCC_APB2RSTR_ADCRST
@@ -124,7 +138,7 @@
 /* ADC interrupts ***********************************************************/
-#ifdef CONFIG_STM32_STM32F30XX
+#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX)
 #  define STM32_ADC_DMAREG_OFFSET    STM32_ADC_CFGR_OFFSET
 #  define ADC_DMAREG_DMA             ADC_CFGR_DMAEN
 #  define STM32_ADC_EXTREG_OFFSET    STM32_ADC_CFGR_OFFSET
@@ -226,7 +240,7 @@
                               (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP7_SHIFT) | \
                               (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP8_SHIFT) | \
                               (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP9_SHIFT))
-#elif defined(CONFIG_STM32_STM32F30XX)
+#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX)
 #  if defined(ADC_HAVE_DMA) || (ADC_MAX_SAMPLES == 1)
 #    define ADC_SMPR_DEFAULT    ADC_SMPR_61p5
 #  else /* Slow down sampling frequency */
@@ -338,8 +352,8 @@ struct stm32_dev_s
 /* ADC Register access */
 #if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \
-    defined(CONFIG_STM32_STM32F37XX) ||defined(CONFIG_STM32_STM32F40XX) || \
+    defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F37XX) || \
-    defined(CONFIG_STM32_STM32L15XX)
+    defined(CONFIG_STM32_STM32F40XX) || defined(CONFIG_STM32_STM32L15XX)
 static void stm32_modifyreg32(unsigned int addr, uint32_t clrbits,
                              uint32_t setbits);
 #endif
@@ -606,8 +620,8 @@ static struct adc_dev_s g_adcdev4 =
 ****************************************************************************/
 #if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \
-    defined(CONFIG_STM32_STM32F37XX) ||defined(CONFIG_STM32_STM32F40XX) || \
+    defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F37XX) || \
-    defined(CONFIG_STM32_STM32L15XX)
+    defined(CONFIG_STM32_STM32F40XX) || defined(CONFIG_STM32_STM32L15XX)
 static void stm32_modifyreg32(unsigned int addr, uint32_t clrbits,
                              uint32_t setbits)
 {
@@ -1242,7 +1256,7 @@ static void adc_startconv(FAR struct stm32_dev_s *priv, bool enable)
  adc_enable(priv, true);
 }
-#elif defined(CONFIG_STM32_STM32F30XX)
+#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX)
 static void adc_startconv(FAR struct stm32_dev_s *priv, bool enable)
 {
  uint32_t regval;
@@ -1520,7 +1534,7 @@ static void adc_select_ch_bank(FAR struct stm32_dev_s *priv,
 *
 ****************************************************************************/
-#ifdef CONFIG_STM32_STM32F30XX
+#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX)
 static void adc_enable(FAR struct stm32_dev_s *priv, bool enable)
 {
  uint32_t regval;
@@ -1699,8 +1713,8 @@ static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, FAR void *arg)
 * Name: adc_bind
 *
 * Description:
- *   Bind the upper-half driver callbacks to the lower-half implementation.  This
+ *   Bind the upper-half driver callbacks to the lower-half implementation.
- *   must be called early in order to receive ADC event notifications.
+ *   This must be called early in order to receive ADC event notifications.
 *
 ****************************************************************************/
@@ -1718,8 +1732,8 @@ static int adc_bind(FAR struct adc_dev_s *dev,
 * Name: adc_reset
 *
 * Description:
- *   Reset the ADC device.  Called early to initialize the hardware. This
+ *   Reset the ADC device.  Called early to initialize the hardware.
- *   is called, before adc_setup() and on error conditions.
+ *   This is called, before adc_setup() and on error conditions.
 *
 * Input Parameters:
 *
@@ -1751,7 +1765,7 @@ static void adc_reset(FAR struct adc_dev_s *dev)
 #endif
-#ifdef CONFIG_STM32_STM32F30XX
+#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX)
  /* Turn off the ADC so we can write the RCC bits */
@@ -1767,7 +1781,7 @@ static void adc_reset(FAR struct adc_dev_s *dev)
  adc_rccreset(priv, false);
-#ifdef CONFIG_STM32_STM32F30XX
+#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX)
  /* Set voltage regular enable to intermediate state */
@@ -1822,7 +1836,7 @@ static void adc_reset(FAR struct adc_dev_s *dev)
  adc_putreg(priv, STM32_ADC_SMPR2_OFFSET, ADC_SMPR2_DEFAULT);
 #endif
-#ifdef CONFIG_STM32_STM32F30XX
+#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX)
  /* Enable the analog watchdog */
@@ -1870,7 +1884,7 @@ static void adc_reset(FAR struct adc_dev_s *dev)
  adc_modifyreg(priv, STM32_ADC_IER_OFFSET, clrbits, setbits);
-#else /* ifdef CONFIG_STM32_STM32F30XX */
+#else /* CONFIG_STM32_STM32F30XX || CONFIG_STM32_STM33XX */
  /* Enable the analog watchdog */
@@ -1968,7 +1982,7 @@ static void adc_reset(FAR struct adc_dev_s *dev)
  /* ADC CCR configuration */
-#if defined(CONFIG_STM32_STM32F30XX)
+#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX)
  clrbits = ADC_CCR_DUAL_MASK | ADC_CCR_DELAY_MASK | ADC_CCR_DMACFG |
            ADC_CCR_MDMA_MASK | ADC_CCR_CKMODE_MASK | ADC_CCR_VREFEN |
            ADC_CCR_TSEN | ADC_CCR_VBATEN;
@@ -1979,10 +1993,12 @@ static void adc_reset(FAR struct adc_dev_s *dev)
    {
      stm32_modifyreg32(STM32_ADC12_CCR, clrbits, setbits);
    }
 #ifndef CONFIG_STM32_STM32F33XX
  else
    {
      stm32_modifyreg32(STM32_ADC34_CCR, clrbits, setbits);
    }
 #endif
 #elif defined(CONFIG_STM32_STM32F20XX) || \
      defined(CONFIG_STM32_STM32F40XX) || \
      defined(CONFIG_STM32_STM32L15XX)
@@ -2050,7 +2066,7 @@ static void adc_reset(FAR struct adc_dev_s *dev)
  leave_critical_section(flags);
-#ifdef CONFIG_STM32_STM32F30XX
+#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX)
  ainfo("ISR:  0x%08x CR:   0x%08x CFGR: 0x%08x\n",
        adc_getreg(priv, STM32_ADC_ISR_OFFSET),
        adc_getreg(priv, STM32_ADC_CR_OFFSET),
@@ -2067,7 +2083,7 @@ static void adc_reset(FAR struct adc_dev_s *dev)
        adc_getreg(priv, STM32_ADC_SQR2_OFFSET),
        adc_getreg(priv, STM32_ADC_SQR3_OFFSET));
-#if defined(CONFIG_STM32_STM32F30XX)
+#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX)
  ainfo("SQR4: 0x%08x\n", adc_getreg(priv, STM32_ADC_SQR4_OFFSET));
 #elif defined(CONFIG_STM32_STM32L15XX)
  ainfo("SQR4: 0x%08x SQR5: 0x%08x\n",
@@ -2075,15 +2091,17 @@ static void adc_reset(FAR struct adc_dev_s *dev)
        adc_getreg(priv, STM32_ADC_SQR5_OFFSET));
 #endif
-#if defined(CONFIG_STM32_STM32F30XX)
+#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX)
  if (priv->base == STM32_ADC1_BASE || priv->base == STM32_ADC2_BASE)
    {
      ainfo("CCR:  0x%08x\n", getreg32(STM32_ADC12_CCR));
    }
 #ifndef CONFIG_STM32_STM32F33XX
  else
    {
      ainfo("CCR:  0x%08x\n", getreg32(STM32_ADC34_CCR));
    }
 #endif
 #elif defined(CONFIG_STM32_STM32F20XX) || \
      defined(CONFIG_STM32_STM32F40XX) || \
      defined(CONFIG_STM32_STM32L15XX)
@@ -3085,8 +3103,9 @@ struct adc_dev_s *stm32_adcinitialize(int intf, FAR const uint8_t *chanlist,
 }
 #endif /* CONFIG_STM32_STM32F10XX || CONFIG_STM32_STM32F20XX ||
-        * CONFIG_STM32_STM32F30XX || CONFIG_STM32_STM32F47XX ||
+        * CONFIG_STM32_STM32F30XX || CONFIG_STM32_STM32F33XX ||
-        * CONFIG_STM32_STM32F40XX || CONFIG_STM32_STM32L15XX
+        * CONFIG_STM32_STM32F47XX || CONFIG_STM32_STM32F40XX ||
        * CONFIG_STM32_STM32L15XX
        */
 #endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 ||
        * CONFIG_STM32_ADC3 || CONFIG_STM32_ADC4
@@ -0,0 +1,281 @@
 /************************************************************************************
 * arch/arm/src/stm32/stm32_comp.h
 *
 *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
 *   Author: Mateusz Szafoni <raiden00@railab.me>
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 * 3. Neither the name NuttX nor the names of its contributors may be
 *    used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 *
 ************************************************************************************/
 #ifndef __ARCH_ARM_SRC_STM32_STM32_COMP_H
 #define __ARCH_ARM_SRC_STM32_STM32_COMP_H
 /************************************************************************************
 * Included Files
 ************************************************************************************/
 #include <nuttx/config.h>
 #include "chip.h"
 #if defined(CONFIG_STM32_STM32F30XX)
 #  error "COMP support for STM32F30XX not implemented yet"
 #elif defined(CONFIG_STM32_STM32F33XX)
 #  include "chip/stm32f33xxx_comp.h"
 #elif defined(CONFIG_STM32_STM32F37XX)
 #  error "COMP support for STM32F37XX ot implemented yet"
 #endif
 /************************************************************************************
 * Pre-processor definitions
 ************************************************************************************/
 #define COMP_BLANKING_DEFAULT COMP_BLANKING_DIS   /* No blanking */
 #define COMP_POL_DEFAULT      COMP_POL_NONINVERT  /* Output is not inverted */
 #define COMP_INM_DEFAULT      COMP_INMSEL_1P4VREF /* 1/4 of Vrefint as INM */
 #define COMP_OUTSEL_DEFAULT   COMP_OUTSEL_NOSEL   /* Output not selected */
 #define COMP_LOCK_DEFAULT     COMP_LOCK_RO        /* Do not lock CSR register */
 #ifndef CONFIG_STM32_STM32F33XX
 #define COMP_MODE_DEFAULT
 #define COMP_HYST_DEFAULT
 #define COMP_WINMODE_DEFAULT
 #endif
 /************************************************************************************
 * Public Types
 ************************************************************************************/
 /* Blanking source */
 enum stm32_comp_blanking_e
 {
  COMP_BLANKING_DIS,
 #if defined(CONFIG_STM32_STM32F33XX)
  COMP_BLANKING_T1OC5,
  COMP_BLANKING_T3OC4,
  COMP_BLANKING_T2OC3,
  COMP_BLANKING_T3OC3,
  COMP_BLANKING_T15OC1,
  COMP_BLANKING_T2OC4,
  COMP_BLANKING_T15OC2,
 #endif
 };
 /* Output polarisation */
 enum stm32_comp_pol_e
 {
  COMP_POL_NONINVERT,
  COMP_POL_INVERTED
 };
 /* Inverting input */
 enum stm32_comp_inm_e
 {
  COMP_INMSEL_1P4VREF,
  COMP_INMSEL_1P2VREF,
  COMP_INMSEL_3P4VREF,
  COMP_INMSEL_VREF,
  COMP_INMSEL_DAC1CH1,
  COMP_INMSEL_DAC1CH2,
  COMP_INMSEL_PIN
 };
 /* Output selection */
 enum stm32_comp_outsel_e
 {
  COMP_OUTSEL_NOSEL,
 #if defined(CONFIG_STM32_STM32F33XX)
  COMP_OUTSEL_BRKACTH,
  COMP_OUTSEL_BRK2,
  COMP_OUTSEL_T1OCC,          /* COMP2 only */
  COMP_OUTSEL_T3CAP3,         /* COMP4 only */
  COMP_OUTSEL_T2CAP2,         /* COMP6 only */
  COMP_OUTSEL_T1CAP1,         /* COMP2 only */
  COMP_OUTSEL_T2CAP4,         /* COMP2 only */
  COMP_OUTSEL_T15CAP2,        /* COMP4 only */
  COMP_OUTSEL_T2OCC,          /* COMP6 only */
  COMP_OUTSEL_T16OCC,         /* COMP2 only */
  COMP_OUTSEL_T3CAP1,         /* COMP2 only */
  COMP_OUTSEL_T15OCC,         /* COMP4 only */
  COMP_OUTSEL_T16CAP1,        /* COMP6 only */
  COMP_OUTSEL_T3OCC,          /* COMP2 and COMP4 only */
 #endif
 };
 /* CSR register lock state */
 enum stm32_comp_lock_e
 {
  COMP_LOCK_RW,
  COMP_LOCK_RO
 };
 #ifndef CONFIG_STM32_STM32F33XX
 /* Hysteresis  */
 enum stm32_comp_hyst_e
 {
  COMP_HYST_DIS,
  COMP_HYST_LOW,
  COMP_HYST_MEDIUM,
  COMP_HYST_HIGH
 };
 /* Power/Speed Modes */
 enum stm32_comp_mode_e
 {
  COMP_MODE_HIGHSPEED,
  COMP_MODE_MEDIUMSPEED,
  COMP_MODE_LOWPOWER,
  COMP_MODE_ULTRALOWPOWER
 };
 /* Window mode */
 enum stm32_comp_winmode_e
 {
  COMP_WINMODE_DIS,
  COMP_WINMODE_EN
 };
 #endif
 /* Comparator configuration ***********************************************************/
 struct stm32_comp_s
 {
  uint8_t blanking;             /* Blanking source */
  uint8_t pol;                  /* Output polarity */
  uint8_t inm;                  /* Inverting input selection */
  uint8_t out;                  /* Comparator output */
  uint8_t lock;                 /* Comparator Lock */
  uint32_t csr;                 /* Control and status register */
 #ifndef CONFIG_STM32_STM32F33XX
  uint8_t mode;                 /* Comparator mode */
  uint8_t hyst;                 /* Comparator hysteresis */
                                /* @TODO: Window mode + INP selection */
 #endif
 };
 /************************************************************************************
 * Public Function Prototypes
 ************************************************************************************/
 #ifndef __ASSEMBLY__
 #ifdef __cplusplus
 #define EXTERN extern "C"
 extern "C"
 {
 #else
 #define EXTERN extern
 #endif
 /****************************************************************************
 * Name: stm32_compconfig
 *
 * Description:
 *   Configure comparator and used I/Os
 *
 * Input Parameters:
 *   priv   - A reference to the COMP structure
 *
 * Returned Value:
 *  0 on success, a negated errno value on failure
 *
 ****************************************************************************/
 int stm32_compconfig(FAR struct stm32_comp_s *priv);
 /****************************************************************************
 * Name: stm32_compinitialize
 *
 * Description:
 *   Initialize the COMP.
 *
 * Input Parameters:
 *   intf - The COMP interface number.
 *
 * Returned Value:
 *   Valid COMP device structure reference on succcess; a NULL on failure.
 *
 * Assumptions:
 *   1. Clock to the COMP block has enabled,
 *   2. Board-specific logic has already configured
 *
 ****************************************************************************/
 FAR struct stm32_comp_s* stm32_compinitialize(int intf);
 /****************************************************************************
 * Name: stm32_compenable
 *
 * Description:
 *   Enable/disable comparator
 *
 * Input Parameters:
 *   priv   - A reference to the COMP structure
 *   enable - enable/disable flag
 *
 * Returned Value:
 *  0 on success, a negated errno value on failure
 *
 ****************************************************************************/
 int stm32_compenable(FAR struct stm32_comp_s *priv, bool enable);
 /****************************************************************************
 * Name: stm32_complock
 *
 * Description:
 *   Lock comparator CSR register
 *
 * Input Parameters:
 *   priv   - A reference to the COMP structure
 *   enable - lock flag
 *
 * Returned Value:
 *  0 on success, a negated errno value on failure
 *
 ****************************************************************************/
 int stm32_complock(FAR struct stm32_comp_s *priv, bool lock);
 #undef EXTERN
 #ifdef __cplusplus
 }
 #endif
 #endif /* __ASSEMBLY__ */
 #endif /* __ARCH_ARM_SRC_STM32_STM32_COMP_H */
@@ -56,9 +56,10 @@
 */
 #if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \
-    defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
+    defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)
    defined(CONFIG_STM32_STM32F37XX)
 #  include "stm32f10xxx_dma.c"
 #elif defined(CONFIG_STM32_STM32F33XX)
 #  include "stm32f33xxx_dma.c"
 #elif defined(CONFIG_STM32_STM32F20XX)
 #  include "stm32f20xxx_dma.c"
 #elif defined(CONFIG_STM32_STM32F40XX)
@@ -48,9 +48,10 @@
 /* Include the correct DMA register definitions for this STM32 family */
 #if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \
-    defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
+    defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)
    defined(CONFIG_STM32_STM32F37XX)
 #  include "chip/stm32f10xxx_dma.h"
 #elif defined(CONFIG_STM32_STM32F33XX)
 #  include "chip/stm32f33xxx_dma.h"
 #elif defined(CONFIG_STM32_STM32F20XX)
 #  include "chip/stm32f20xxx_dma.h"
 #elif defined(CONFIG_STM32_STM32F40XX)
@@ -310,16 +310,6 @@ void up_irqinitialize(void)
      putreg32(0xffffffff, NVIC_IRQ_CLEAR(i));
    }
  /* Colorize the interrupt stack for debug purposes */
 #if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3
  {
    size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~3);
    up_stack_color((FAR void *)((uintptr_t)&g_intstackbase - intstack_size),
                   intstack_size);
  }
 #endif
  /* The standard location for the vector table is at the beginning of FLASH
   * at address 0x0800:0000.  If we are using the STMicro DFU bootloader, then
   * the vector table will be offset to a different location in FLASH and we
@@ -57,7 +57,8 @@
 #if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || \
-    defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32L15XX)
+    defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F37XX) || \
    defined(CONFIG_STM32_STM32L15XX)
 /****************************************************************************
 * Pre-processor Definitions
@@ -415,16 +415,6 @@ void up_irqinitialize(void)
      putreg32(0, regaddr);
    }
  /* Colorize the interrupt stack for debug purposes */
 #if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3
  {
    size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~3);
    up_stack_color((FAR void *)((uintptr_t)&g_intstackbase - intstack_size),
                   intstack_size);
  }
 #endif
  /* Make sure that we are using the correct vector table.  The default
   * vector address is 0x0000:0000 but if we are executing code that is
   * positioned in SRAM or in external FLASH, then we may need to reset
@@ -304,16 +304,6 @@ void up_irqinitialize(void)
      putreg32(0xffffffff, NVIC_IRQ_CLEAR(i));
    }
  /* Colorize the interrupt stack for debug purposes */
 #if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3
  {
    size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~3);
    up_stack_color((FAR void *)((uintptr_t)&g_intstackbase - intstack_size),
                   intstack_size);
  }
 #endif
  /* The standard location for the vector table is at the beginning of FLASH
   * at address 0x0800:0000.  If we are using the STMicro DFU bootloader, then
   * the vector table will be offset to a different location in FLASH and we
@@ -115,14 +115,6 @@ void up_irqinitialize(void)
  FAR uintptr_t *vimram;
  int i;
  /* Colorize the interrupt stack for debug purposes */
 #if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3
  size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~3);
  up_stack_color((FAR void *)((uintptr_t)&g_intstackbase - intstack_size),
                 intstack_size);
 #endif
  /* Initialize VIM RAM vectors.  These vectors are not used in the current
   * interrupt handler logic.
   */
@@ -0,0 +1,346 @@
 #
 # For a description of the syntax of this configuration file,
 # see the file kconfig-language.txt in the NuttX tools repository.
 #
 comment "XMC4xxx Configuration Options"
 choice
 	prompt "XMC4xxx Chip Selection"
 	default ARCH_CHIP_XMC4500
 	depends on ARCH_CHIP_XMC4
 config ARCH_CHIP_XMC4500
 	bool "XMC4500"
 	select ARCH_HAVE_FPU
 config ARCH_CHIP_XMC4700
 	bool "XMC4700"
 	select ARCH_HAVE_FPU
 config ARCH_CHIP_XMC4800
 	bool "XMC4800"
 	select ARCH_HAVE_FPU
 endchoice
 # These "hidden" settings determine is a peripheral option is available for
 # the selection MCU
 # When there are multiple instances of a device, these "hidden" settings
 # will automatically be selected and will represent the 'OR' of the
 # instances selected.
 config XMC4_USIC
 	bool
 	default n
 config XMC4_USCI_UART
 	bool
 	default n
 	select MCU_SERIAL
 config XMC4_USCI_LIN
 	bool
 	default n
 config XMC4_USCI_SPI
 	bool
 	default n
 config XMC4_USCI_I2C
 	bool
 	default n
 config XMC4_USCI_I2S
 	bool
 	default n
 # Chip families
 menu "XMC4xxx Peripheral Support"
 config XMC4_USIC0
 	bool "USIC0"
 	default n
 	select XMC4_USIC
 	---help---
 		Support USIC0
 config XMC4_USIC1
 	bool "USIC1"
 	default n
 	---help---
 		Support USIC1
 config XMC4_USIC2
 	bool "USIC2"
 	default n
 	select XMC4_USIC
 	---help---
 		Support USIC2
 endmenu
 menu "XMC4xxx USIC Configuration"
 	depends on XMC4_USIC
 choice
 	prompt "USIC0 Channel 0 Configuration"
 	default XMC4_USIC0_CHAN0_ISUART
 	depends on XMC4_USIC0
 config XMC4_USIC0_CHAN0_NONE
 	bool "Not used"
 	---help---
 		USIC0 Channel 0 will not be enabled
 config XMC4_USIC0_CHAN0_ISUART
 	bool "UART0"
 	select UART0_SERIALDRIVER
 	select XMC4_USCI_UART
 	---help---
 		Configure USIC0 Channel 0 as a UART
 config XMC4_USIC0_CHAN0_ISLIN
 	bool "LIN"
 	select XMC4_USCI_LIN
 	---help---
 		Configure USIC0 Channel 0 as a LIN UART
 config XMC4_USIC0_CHAN0_ISSPI
 	bool "SPI"
 	select XMC4_USCI_SPI
 	---help---
 		Configure USIC0 Channel 0 for SPI communications
 config XMC4_USIC0_CHAN0_ISI2C
 	bool "I2C"
 	select XMC4_USCI_I2C
 	---help---
 		Configure USIC0 Channel 0 for I2C communications
 config XMC4_USIC0_CHAN0_ISI2S
 	bool "I2S"
 	select XMC4_USCI_I2S
 	---help---
 		Configure USIC0 Channel 0 for I2S audio
 endchoice # USIC0 Channel 0 Configuration
 choice
 	prompt "USIC0 Channel 1 Configuration"
 	default XMC4_USIC0_CHAN1_ISUART
 	depends on XMC4_USIC0
 config XMC4_USIC0_CHAN1_NONE
 	bool "Not used"
 	---help---
 		USIC0 Channel 1 will not be enabled
 config XMC4_USIC0_CHAN1_ISUART
 	bool "UART1"
 	select UART1_SERIALDRIVER
 	select XMC4_USCI_UART
 	---help---
 		Configure USIC0 Channel 1 as a UART
 config XMC4_USIC0_CHAN1_ISLIN
 	bool "LIN"
 	select XMC4_USCI_LIN
 	---help---
 		Configure USIC0 Channel 1 as a LIN UART
 config XMC4_USIC0_CHAN1_ISSPI
 	bool "SPI"
 	select XMC4_USCI_SPI
 	---help---
 		Configure USIC0 Channel 1 for SPI communications
 config XMC4_USIC0_CHAN1_ISI2C
 	bool "I2C"
 	select XMC4_USCI_I2C
 	---help---
 		Configure USIC0 Channel 1 for I2C communications
 config XMC4_USIC0_CHAN1_ISI2S
 	bool "I2S"
 	select XMC4_USCI_I2S
 	---help---
 		Configure USIC0 Channel 1 for I2S audio
 endchoice # USIC0 Channel 1 Configuration
 choice
 	prompt "USIC1 Channel 0 Configuration"
 	default XMC4_USIC1_CHAN0_ISUART
 	depends on XMC4_USIC1
 config XMC4_USIC1_CHAN0_NONE
 	bool "Not used"
 	---help---
 		USIC0 Channel 0 will not be enabled
 config XMC4_USIC1_CHAN0_ISUART
 	bool "UART2"
 	select UART2_SERIALDRIVER
 	select XMC4_USCI_UART
 	---help---
 		Configure USIC1 Channel 0 as a UART
 config XMC4_USIC1_CHAN0_ISLIN
 	bool "LIN"
 	select XMC4_USCI_LIN
 	---help---
 		Configure USIC1 Channel 0 as a LIN UART
 config XMC4_USIC1_CHAN0_ISSPI
 	bool "SPI"
 	select XMC4_USCI_SPI
 	---help---
 		Configure USIC1 Channel 0 for SPI communications
 config XMC4_USIC1_CHAN0_ISI2C
 	bool "I2C"
 	select XMC4_USCI_I2C
 	---help---
 		Configure USIC1 Channel 0 for I2C communications
 config XMC4_USIC1_CHAN0_ISI2S
 	bool "I2S"
 	select XMC4_USCI_I2S
 	---help---
 		Configure USIC1 Channel 0 for I2S audio
 endchoice # USIC1 Channel 0 Configuration
 choice
 	prompt "USIC1 Channel 1 Configuration"
 	default XMC4_USIC1_CHAN1_ISUART
 	depends on XMC4_USIC1
 config XMC4_USIC1_CHAN1_NONE
 	bool "Not used"
 	---help---
 		USIC0 Channel 1 will not be enabled
 config XMC4_USIC1_CHAN1_ISUART
 	bool "UART3"
 	select UART3_SERIALDRIVER
 	select XMC4_USCI_UART
 	---help---
 		Configure USIC1 Channel 1 as a UART
 config XMC4_USIC1_CHAN1_ISLIN
 	bool "LIN"
 	select XMC4_USCI_LIN
 	---help---
 		Configure USIC1 Channel 1 as a LIN UART
 config XMC4_USIC1_CHAN1_ISSPI
 	bool "SPI"
 	select XMC4_USCI_SPI
 	---help---
 		Configure USIC1 Channel 1 for SPI communications
 config XMC4_USIC1_CHAN1_ISI2C
 	bool "I2C"
 	select XMC4_USCI_I2C
 	---help---
 		Configure USIC1 Channel 1 for I2C communications
 config XMC4_USIC1_CHAN1_ISI2S
 	bool "I2S"
 	select XMC4_USCI_I2S
 	---help---
 		Configure USIC1 Channel 1 for I2S audio
 endchoice # USIC1 Channel 1 Configuration
 choice
 	prompt "USIC2 Channel 0 Configuration"
 	default XMC4_USIC2_CHAN0_ISUART
 	depends on XMC4_USIC2
 config XMC4_USIC2_CHAN0_NONE
 	bool "Not used"
 	---help---
 		USIC0 Channel 0 will not be enabled
 config XMC4_USIC2_CHAN0_ISUART
 	bool "UART4"
 	select UART4_SERIALDRIVER
 	select XMC4_USCI_UART
 	---help---
 		Configure USIC2 Channel 0 as a UART
 config XMC4_USIC2_CHAN0_ISLIN
 	bool "LIN"
 	select XMC4_USCI_LIN
 	---help---
 		Configure USIC2 Channel 0 as a LIN UART
 config XMC4_USIC2_CHAN0_ISSPI
 	bool "SPI"
 	select XMC4_USCI_SPI
 	---help---
 		Configure USIC2 Channel 0 for SPI communications
 config XMC4_USIC2_CHAN0_ISI2C
 	bool "I2C"
 	select XMC4_USCI_I2C
 	---help---
 		Configure USIC2 Channel 0 for I2C communications
 config XMC4_USIC2_CHAN0_ISI2S
 	bool "I2S"
 	select XMC4_USCI_I2S
 	---help---
 		Configure USIC2 Channel 0 for I2S audio
 endchoice # USIC2 Channel 0 Configuration
 choice
 	prompt "USIC2 Channel 1 Configuration"
 	default XMC4_USIC2_CHAN1_ISUART
 	depends on XMC4_USIC2
 config XMC4_USIC2_CHAN1_NONE
 	bool "Not used"
 	---help---
 		USIC0 Channel 1 will not be enabled
 config XMC4_USIC2_CHAN1_ISUART
 	bool "UART5"
 	select UART5_SERIALDRIVER
 	select XMC4_USCI_UART
 	---help---
 		Configure USIC2 Channel 1 as a UART
 config XMC4_USIC2_CHAN1_ISLIN
 	bool "LIN"
 	select XMC4_USCI_LIN
 	---help---
 		Configure USIC2 Channel 1 as a LIN UART
 config XMC4_USIC2_CHAN1_ISSPI
 	bool "SPI"
 	select XMC4_USCI_SPI
 	---help---
 		Configure USIC2 Channel 1 for SPI communications
 config XMC4_USIC2_CHAN1_ISI2C
 	bool "I2C"
 	select XMC4_USCI_I2C
 	---help---
 		Configure USIC2 Channel 1 for I2C communications
 config XMC4_USIC2_CHAN1_ISI2S
 	bool "I2S"
 	select XMC4_USCI_I2S
 	---help---
 		Configure USIC2 Channel 1 for I2S audio
 endchoice # USIC2 Channel 1 Configuration
 endmenu # XMC4xxx USIC Configuration
@@ -0,0 +1,141 @@
 ############################################################################
 # arch/arm/src/kinetis/Make.defs
 #
 #   Copyright (C) 2017 Gregory Nutt. All rights reserved.
 #   Author: Gregory Nutt <gnutt@nuttx.org>
 #
 # Redistribution and use in source and binary forms, with or without
 # modification, are permitted provided that the following conditions
 # are met:
 #
 # 1. Redistributions of source code must retain the above copyright
 #    notice, this list of conditions and the following disclaimer.
 # 2. Redistributions in binary form must reproduce the above copyright
 #    notice, this list of conditions and the following disclaimer in
 #    the documentation and/or other materials provided with the
 #    distribution.
 # 3. Neither the name NuttX nor the names of its contributors may be
 #    used to endorse or promote products derived from this software
 #    without specific prior written permission.
 #
 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 # FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
 # COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 # BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
 # OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
 # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 # LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
 # ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 # POSSIBILITY OF SUCH DAMAGE.
 #
 ############################################################################
 ifeq ($(CONFIG_ARMV7M_CMNVECTOR),y)
 HEAD_ASRC =
 else
 HEAD_ASRC = xmc4_vectors.S
 endif
 CMN_UASRCS =
 CMN_UCSRCS =
 CMN_ASRCS  = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S
 CMN_ASRCS += up_testset.S vfork.S
 CMN_CSRCS  = up_assert.c up_blocktask.c up_copyfullstate.c up_createstack.c
 CMN_CSRCS += up_mdelay.c up_udelay.c up_exit.c up_initialize.c up_memfault.c
 CMN_CSRCS += up_initialstate.c up_interruptcontext.c up_modifyreg8.c
 CMN_CSRCS += up_modifyreg16.c up_modifyreg32.c up_releasestack.c
 CMN_CSRCS += up_reprioritizertr.c up_schedulesigaction.c up_releasepending.c
 CMN_CSRCS += up_sigdeliver.c up_stackframe.c up_unblocktask.c up_usestack.c
 CMN_CSRCS += up_doirq.c up_hardfault.c up_svcall.c up_vfork.c
 CMN_CSRCS += up_systemreset.c
 ifeq ($(CONFIG_ARMV7M_STACKCHECK),y)
 CMN_CSRCS += up_stackcheck.c
 endif
 ifeq ($(CONFIG_ARMV7M_CMNVECTOR),y)
 ifeq ($(CONFIG_ARMV7M_LAZYFPU),y)
 CMN_ASRCS += up_lazyexception.S
 else
 CMN_ASRCS += up_exception.S
 endif
 CMN_CSRCS += up_vectors.c
 endif
 ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
 CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c
 endif
 ifeq ($(CONFIG_BUILD_PROTECTED),y)
 CMN_CSRCS += up_mpu.c up_task_start.c up_pthread_start.c
 ifneq ($(CONFIG_DISABLE_SIGNALS),y)
 CMN_CSRCS += up_signal_dispatch.c
 CMN_UASRCS += up_signal_handler.S
 endif
 endif
 ifeq ($(CONFIG_STACK_COLORATION),y)
 CMN_CSRCS += up_checkstack.c
 endif
 # Use of common/up_etherstub.c is deprecated.  The preferred mechanism is to
 # use CONFIG_NETDEV_LATEINIT=y to suppress the call to up_netinitialize() in
 # up_initialize().  Then this stub would not be needed.
 ifeq ($(CONFIG_NET),y)
 ifneq ($(CONFIG_XMC4_ENET),y)
 CMN_CSRCS += up_etherstub.c
 endif
 endif
 ifeq ($(CONFIG_ARCH_FPU),y)
 CMN_ASRCS += up_fpu.S
 ifneq ($(CONFIG_ARMV7M_CMNVECTOR),y)
 CMN_CSRCS += up_copyarmstate.c
 else ifeq ($(CONFIG_ARMV7M_LAZYFPU),y)
 CMN_CSRCS += up_copyarmstate.c
 endif
 endif
 ifeq ($(CONFIG_ARMV7M_ITMSYSLOG),y)
 CMN_CSRCS += up_itm_syslog.c
 endif
 # Required XMC4xxx files
 CHIP_ASRCS  =
 CHIP_CSRCS  = xmc4_allocateheap.c xmc4_clockconfig.c xmc4_clockutils.c
 CHIP_CSRCS += xmc4_clrpend.c xmc4_idle.c xmc4_irq.c xmc4_lowputc.c
 CHIP_CSRCS += xmc4_gpio.c xmc4_serial.c xmc4_start.c xmc4_usic.c
 # Configuration-dependent Kinetis files
 ifneq ($(CONFIG_SCHED_TICKLESS),y)
 CHIP_CSRCS += xmc4_timerisr.c
 endif
 ifeq ($(CONFIG_BUILD_PROTECTED),y)
 CHIP_CSRCS += xmc4_userspace.c xmc4_mpuinit.c
 endif
 ifeq ($(CONFIG_DEBUG_GPIO_INFO),y)
 CHIP_CSRCS += xmc4_pindump.c
 endif
 ifeq ($(CONFIG_XMC4_DMA),y)
 CHIP_CSRCS += xmc4_dma.c
 endif
 ifeq ($(CONFIG_PWM),y)
 CHIP_CSRCS += xmc4_pwm.c
 endif
 ifeq ($(CONFIG_I2C),y)
 CHIP_CSRCS += xmc4_i2c.c
 endif
@@ -0,0 +1,77 @@
 /************************************************************************************
 * arch/arm/src/xmc4/chip.h
 *
 *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
 *   Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 * 3. Neither the name NuttX nor the names of its contributors may be
 *    used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 *
 ************************************************************************************/
 #ifndef __ARCH_ARM_SRC_XMC4_CHIP_H
 #define __ARCH_ARM_SRC_XMC4_CHIP_H
 /************************************************************************************
 * Included Files
 ************************************************************************************/
 #include <nuttx/config.h>
 /* Include the memory map and the chip definitions file.  Other chip hardware files
 * should then include this file for the proper setup.
 */
 #include <arch/irq.h>
 #include <arch/xmc4/chip.h>
 #include "chip/xmc4_memorymap.h"
 /* If the common ARMv7-M vector handling logic is used, then it expects the
 * following definition in this file that provides the number of supported external
 * interrupts which, for this architecture, is provided in the arch/xmc4/chip.h
 * header file.
 */
 #define ARMV7M_PERIPHERAL_INTERRUPTS NR_INTERRUPTS
 /************************************************************************************
 * Pre-processor Definitions
 ************************************************************************************/
 /************************************************************************************
 * Public Types
 ************************************************************************************/
 /************************************************************************************
 * Public Data
 ************************************************************************************/
 /************************************************************************************
 * Public Functions
 ************************************************************************************/
 #endif /* __ARCH_ARM_SRC_XMC4_CHIP_H */
@@ -0,0 +1,205 @@
 /************************************************************************************
 * arch/arm/src/xmc4/chip/xmc4_flash.h
 *
 *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
 *   Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Reference: XMC4500 Reference Manual V1.5 2014-07 Microcontrollers.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 * 3. Neither the name NuttX nor the names of its contributors may be
 *    used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 *
 * May include some logic from sample code provided by Infineon:
 *
 *   Copyright (C) 2011-2015 Infineon Technologies AG. All rights reserved.
 *
 * Infineon Technologies AG (Infineon) is supplying this software for use with
 * Infineon's microcontrollers.  This file can be freely distributed within
 * development tools that are supporting such microcontrollers.
 *
 * THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
 * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
 * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
 *
 ************************************************************************************/
 #ifndef __ARCH_ARM_SRC_XMC4_CHIP_XMC4_FLASH_H
 #define __ARCH_ARM_SRC_XMC4_CHIP_XMC4_FLASH_H
 /************************************************************************************
 * Included Files
 ************************************************************************************/
 #include <nuttx/config.h>
 #include "chip/xmc4_memorymap.h"
 /************************************************************************************
 * Pre-processor Definitions
 ************************************************************************************/
 /* Register Offsets *****************************************************************/
 /* PMU Registers -- See ID register */
 /* Prefetch Registers -- See PCON register */
 /* FLASH Registers */
 #define XMC4_FLASH_ID_OFFSET       0x1008    /* Flash Module Identification Register */
 #define XMC4_FLASH_FSR_OFFSET      0x1010    /* Flash Status Register */
 #define XMC4_FLASH_FCON_OFFSET     0x1014    /* Flash Configuration Register */
 #define XMC4_FLASH_MARP_OFFSET     0x1018    /* Flash Margin Control Register PFLASH */
 #define XMC4_FLASH_PROCON0_OFFSET  0x1020    /* Flash Protection Configuration User 0 */
 #define XMC4_FLASH_PROCON1_OFFSET  0x1024    /* Flash Protection Configuration User 1 */
 #define XMC4_FLASH_PROCON2_OFFSET  0x1028    /* Flash Protection Configuration User 2 */
 /* Register Addresses ****************************************************************/
 /* FLASH Registers */
 #define XMC4_FLASH_ID               (XMC4_FLASH0_BASE+XMC4_FLASH_ID_OFFSET)
 #define XMC4_FLASH_FSR              (XMC4_FLASH0_BASE+XMC4_FLASH_FSR_OFFSET)
 #define XMC4_FLASH_FCON             (XMC4_FLASH0_BASE+XMC4_FLASH_FCON_OFFSET)
 #define XMC4_FLASH_MARP             (XMC4_FLASH0_BASE+XMC4_FLASH_MARP_OFFSET)
 #define XMC4_FLASH_PROCON0          (XMC4_FLASH0_BASE+XMC4_FLASH_PROCON0_OFFSET)
 #define XMC4_FLASH_PROCON1          (XMC4_FLASH0_BASE+XMC4_FLASH_PROCON1_OFFSET)
 #define XMC4_FLASH_PROCON2          (XMC4_FLASH0_BASE+XMC4_FLASH_PROCON2_OFFSET)
 /* Register Bit-Field Definitions **************************************************/
 /* FLASH Registers */
 /* Flash Module Identification Register */
 #define FLASH_ID_MOD_REV_SHIFT      (0)       /* Bits 0-7: Module Revision Number */
 #define FLASH_ID_MOD_REV_MASK       (0xff << FLASH_ID_MOD_REV_SHIFT)
 #define FLASH_ID_MOD_TYPE_SHIFT     (8)       /* Bits 8-15: Module Type */
 #define FLASH_ID_MOD_TYPE_MASK      (0xff << FLASH_ID_MOD_REV_SHIFT)
 #define FLASH_ID_MOD_NUMBER_SHIFT   (16)      /* Bits 16-31: Module Number Value */
 #define FLASH_ID_MOD_NUMBER_MASK    (0xffff << FLASH_ID_MOD_NUMBER_SHIFT)
 /* Flash Status Register */
 #define FLASH_FSR_PBUSY             (1 << 0)  /* Bit 0:  Program Flash Busy */
 #define FLASH_FSR_FABUSY            (1 << 1)  /* Bit 1:  Flash Array Busy */
 #define FLASH_FSR_PROG              (1 << 4)  /* Bit 4:  Programming State */
 #define FLASH_FSR_ERASE             (1 << 5)  /* Bit 5:  Erase State */
 #define FLASH_FSR_PFPAGE            (1 << 6)  /* Bit 6:  Program Flash in Page Mode */
 #define FLASH_FSR_PFOPER            (1 << 8)  /* Bit 8:  Program Flash Operation Error */
 #define FLASH_FSR_SQER              (1 << 10) /* Bit 10: Command Sequence Error */
 #define FLASH_FSR_PROER             (1 << 11) /* Bit 11: Protection Error */
 #define FLASH_FSR_PFSBER            (1 << 12) /* Bit 12: PFLASH Single-Bit Error and Correction */
 #define FLASH_FSR_PFDBER            (1 << 14) /* Bit 14: PFLASH Double-Bit Error */
 #define FLASH_FSR_PROIN             (1 << 16) /* Bit 16: Protection Installed */
 #define FLASH_FSR_RPROIN            (1 << 18) /* Bit 18: Read Protection Installed */
 #define FLASH_FSR_RPRODIS           (1 << 19) /* Bit 19: Read Protection Disable State */
 #define FLASH_FSR_WPROIN0           (1 << 21) /* Bit 21: Sector Write Protection Installed for User 0 */
 #define FLASH_FSR_WPROIN1           (1 << 22) /* Bit 22: Sector Write Protection Installed for User 1 */
 #define FLASH_FSR_WPROIN2           (1 << 23) /* Bit 23: Sector Write Protection Installed for User 2 */
 #define FLASH_FSR_WPRODIS0          (1 << 25) /* Bit 25: Sector Write Protection Disabled for User 0 */
 #define FLASH_FSR_WPRODIS1          (1 << 26) /* Bit 26: Sector Write Protection Disabled for User 1 */
 #define FLASH_FSR_SLM               (1 << 28) /* Bit 28: Flash Sleep Mode */
 #define FLASH_FSR_VER               (1 << 31) /* Bit 31: Verify Error */
 /* Flash Configuration Register */
 #define FLASH_FCON_WSPFLASH_SHIFT   (0)       /* Bits 0-3: Wait States for read access to PFLASH */
 #define FLASH_FCON_WSPFLASH_MASK    (15 << FLASH_FCON_WSPFLASH_SHIFT)
 #  define FLASH_FCON_WSPFLASH(n)    ((uint32_t)((n)-1) << FLASH_FCON_WSPFLASH_SHIFT)
 #define FLASH_FCON_WSECPF           (1 << 4)  /* Bit 4:  Wait State for Error Correction of PFLASH */
 #define FLASH_FCON_IDLE             (1 << 13) /* Bit 13: Dynamic Flash Idle */
 #define FLASH_FCON_ESLDIS           (1 << 14) /* Bit 14: External Sleep Request Disable */
 #define FLASH_FCON_SLEEP            (1 << 15) /* Bit 15: Flash SLEEP */
 #define FLASH_FCON_RPA              (1 << 16) /* Bit 16: Read Protection Activated */
 #define FLASH_FCON_DCF              (1 << 17) /* Bit 17: Disable Code Fetch from Flash Memory */
 #define FLASH_FCON_DDF              (1 << 18) /* Bit 18: Disable Any Data Fetch from Flash */
 #define FLASH_FCON_VOPERM           (1 << 24) /* Bit 24: Verify and Operation Error Interrupt Mask */
 #define FLASH_FCON_SQERM            (1 << 25) /* Bit 25: Command Sequence Error Interrupt Mask */
 #define FLASH_FCON_PROERM           (1 << 26) /* Bit 26: Protection Error Interrupt Mask */
 #define FLASH_FCON_PFSBERM          (1 << 27) /* Bit 27: PFLASH Single-Bit Error Interrupt Mask */
 #define FLASH_FCON_PFDBERM          (1 << 29) /* Bit 29: PFLASH Double-Bit Error Interrupt Mask */
 #define FLASH_FCON_EOBM             (1 << 31) /* Bit 31: End of Busy Interrupt Mask */
 /* Flash Margin Control Register PFLASH */
 #define FLASH_MARP_MARGIN_SHIFT     (0)       /* Bits 0-3: PFLASH Margin Selection */
 #define FLASH_MARP_MARGIN_MASK      (15 << FLASH_MARP_MARGIN_SHIFT)
 #define FLASH_MARP_TRAPDIS          (1 << 15) /* Bit 15: PFLASH Double-Bit Error Trap Disable */
 /* Flash Protection Configuration User 0 */
 #define FLASH_PROCON0_S0L           (1 << 0)  /* Bit 0:  Sector 0 Locked for Write Protection by User 0 */
 #define FLASH_PROCON0_S1L           (1 << 1)  /* Bit 1:  Sector 1 Locked for Write Protection by User 0 */
 #define FLASH_PROCON0_S2L           (1 << 2)  /* Bit 2:  Sector 2 Locked for Write Protection by User 0 */
 #define FLASH_PROCON0_S3L           (1 << 3)  /* Bit 3:  Sector 3 Locked for Write Protection by User 0 */
 #define FLASH_PROCON0_S4L           (1 << 4)  /* Bit 4:  Sector 4 Locked for Write Protection by User 0 */
 #define FLASH_PROCON0_S5L           (1 << 5)  /* Bit 5:  Sector 5 Locked for Write Protection by User 0 */
 #define FLASH_PROCON0_S6L           (1 << 6)  /* Bit 6:  Sector 6 Locked for Write Protection by User 0 */
 #define FLASH_PROCON0_S7L           (1 << 7)  /* Bit 7:  Sector 7 Locked for Write Protection by User 0 */
 #define FLASH_PROCON0_S8L           (1 << 8)  /* Bit 8:  Sector 8 Locked for Write Protection by User 0 */
 #define FLASH_PROCON0_S9L           (1 << 9)  /* Bit 9:  Sector 9 Locked for Write Protection by User 0 */
 #define FLASH_PROCON0_S10_S11L      (1 << 10) /* Bit 10: Sectors 10 and 11 Locked for Write Protection by User 0 */
 #define FLASH_PROCON0_S12_S13L      (1 << 11) /* Bit 11: Sectors 12 and 13 Locked for Write Protection by User 0 */
 #define FLASH_PROCON0_S14_S15L      (1 << 12) /* Bit 12: Sectors 14 and 15 Locked for Write Protection by User 0 */
 #define FLASH_PROCON0_RPRO          (1 << 15) /* Bit 15: Read Protection Configuration */
 /* Flash Protection Configuration User 1 */
 #define FLASH_PROCON1_S0L           (1 << 0)  /* Bit 0:  Sector 0 Locked for Write Protection by User 1 */
 #define FLASH_PROCON1_S1L           (1 << 1)  /* Bit 1:  Sector 1 Locked for Write Protection by User 1 */
 #define FLASH_PROCON1_S2L           (1 << 2)  /* Bit 2:  Sector 2 Locked for Write Protection by User 1 */
 #define FLASH_PROCON1_S3L           (1 << 3)  /* Bit 3:  Sector 3 Locked for Write Protection by User 1 */
 #define FLASH_PROCON1_S4L           (1 << 4)  /* Bit 4:  Sector 4 Locked for Write Protection by User 1 */
 #define FLASH_PROCON1_S5L           (1 << 5)  /* Bit 5:  Sector 5 Locked for Write Protection by User 1 */
 #define FLASH_PROCON1_S6L           (1 << 6)  /* Bit 6:  Sector 6 Locked for Write Protection by User 1 */
 #define FLASH_PROCON1_S7L           (1 << 7)  /* Bit 7:  Sector 7 Locked for Write Protection by User 1 */
 #define FLASH_PROCON1_S8L           (1 << 8)  /* Bit 8:  Sector 8 Locked for Write Protection by User 1 */
 #define FLASH_PROCON1_S9L           (1 << 9)  /* Bit 9:  Sector 9 Locked for Write Protection by User 1 */
 #define FLASH_PROCON1_S10_S11L      (1 << 10) /* Bit 10: Sectors 10 and 11 Locked for Write Protection by User 1 */
 #define FLASH_PROCON1_S12_S13L      (1 << 11) /* Bit 11: Sectors 12 and 13 Locked for Write Protection by User 1 */
 #define FLASH_PROCON1_S14_S15L      (1 << 12) /* Bit 12: Sectors 14 and 15 Locked for Write Protection by User 1 */
 #define FLASH_PROCON1_PSR           (1 << 16) /* Bit 16:  */
 /* Flash Protection Configuration User 2 */
 #define FLASH_PROCON2_S0ROM         (1 << 0)  /* Bit 0:  Sector 0 Locked Forever by User 2 */
 #define FLASH_PROCON2_S1ROM         (1 << 1)  /* Bit 1:  Sector 1 Locked Forever by User 2 */
 #define FLASH_PROCON2_S2ROM         (1 << 2)  /* Bit 2:  Sector 2 Locked Forever by User 2 */
 #define FLASH_PROCON2_S3ROM         (1 << 3)  /* Bit 3:  Sector 3 Locked Forever by User 2 */
 #define FLASH_PROCON2_S4ROM         (1 << 4)  /* Bit 4:  Sector 4 Locked Forever by User 2 */
 #define FLASH_PROCON2_S5ROM         (1 << 5)  /* Bit 5:  Sector 5 Locked Forever by User 2 */
 #define FLASH_PROCON2_S6ROM         (1 << 6)  /* Bit 6:  Sector 6 Locked Forever by User 2 */
 #define FLASH_PROCON2_S7ROM         (1 << 7)  /* Bit 7:  Sector 7 Locked Forever by User 2 */
 #define FLASH_PROCON2_S8ROM         (1 << 8)  /* Bit 8:  Sector 8 Locked Forever by User 2 */
 #define FLASH_PROCON2_S9ROM         (1 << 9)  /* Bit 9:  Sector 9 Locked Forever by User 2 */
 #define FLASH_PROCON2_S10_S11ROM    (1 << 10) /* Bit 10: Sectors 10 and 11 Locked Forever by User 2 */
 #define FLASH_PROCON2_S12_S13ROM    (1 << 11) /* Bit 11: Sectors 12 and 13 Locked Forever by User 2 */
 #define FLASH_PROCON2_S14_S15ROM    (1 << 12) /* Bit 12: Sectors 14 and 15 Locked Forever by User 2 */
 #endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_FLASH_H */
@@ -0,0 +1,243 @@
 /************************************************************************************
 * arch/arm/src/xmc4/chip/xmc4_memorymap.h
 *
 *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
 *   Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Reference: XMC4500 Reference Manual V1.5 2014-07 Microcontrollers.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 * 3. Neither the name NuttX nor the names of its contributors may be
 *    used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 *
 * May include some logic from sample code provided by Infineon:
 *
 *   Copyright (C) 2011-2015 Infineon Technologies AG. All rights reserved.
 *
 * Infineon Technologies AG (Infineon) is supplying this software for use with
 * Infineon's microcontrollers.  This file can be freely distributed within
 * development tools that are supporting such microcontrollers.
 *
 * THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
 * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
 * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
 *
 ************************************************************************************/
 #ifndef __ARCH_ARM_SRC_XMC4_CHIP_XMC4_MEMORYMAP_H
 #define __ARCH_ARM_SRC_XMC4_CHIP_XMC4_MEMORYMAP_H
 /************************************************************************************
 * Included Files
 ************************************************************************************/
 #include <nuttx/config.h>
 /************************************************************************************
 * Pre-processor Definitions
 ************************************************************************************/
 /* Peripheral Memory Map ************************************************************/
 /* Acronyms:
 *  ADC   - Analog to Digital Converter
 *  CCU   - Capture Compare Unit
 *  DAC   - Digital to Analog Converter
 *  DSD   - Delta Sigmoid Demodulator
 *  ERU   - External Request Unit
 *  FCE   - Flexible CRC Engine
 *  GPDMA - General Purpose DMA
 *  LEDTS - LED and Touch Sense Control Unit
 *  PMU   - Program Management Unit
 *  POSIF - Position Interface
 *  SDMMC - Multi Media Card Interface
 *  USB   - Universal Serial Bus
 *  USCI  - Universal Serial Interface
 */
 #define XMC4_PBA0_BASE              0x40000000 /* PBA0 */
 #define XMC4_VADC_BASE              0x40004000 /* VADC */
 #define XMC4_VADC_G0_BASE           0x40004400
 #define XMC4_VADC_G1_BASE           0x40004800
 #define XMC4_VADC_G2_BASE           0x40004c00
 #define XMC4_VADC_G3_BASE           0x40005000
 #define XMC4_DSD_BASE               0x40008000 /* DSD */
 #define XMC4_DSD_CH0_BASE           0x40008100
 #define XMC4_DSD_CH1_BASE           0x40008200
 #define XMC4_DSD_CH2_BASE           0x40008300
 #define XMC4_DSD_CH3_BASE           0x40008400
 #define XMC4_CCU40_BASE             0x4000c000 /* CCU40 */
 #define XMC4_CCU40_CC40_BASE        0x4000c100
 #define XMC4_CCU40_CC41_BASE        0x4000c200
 #define XMC4_CCU40_CC42_BASE        0x4000c300
 #define XMC4_CCU40_CC43_BASE        0x4000c400
 #define XMC4_CCU41_BASE             0x40010000 /* CCU41 */
 #define XMC4_CCU41_CC40_BASE        0x40010100
 #define XMC4_CCU41_CC41_BASE        0x40010200
 #define XMC4_CCU41_CC42_BASE        0x40010300
 #define XMC4_CCU41_CC43_BASE        0x40010400
 #define XMC4_CCU42_BASE             0x40014000 /* CCU42 */
 #define XMC4_CCU42_CC40_BASE        0x40014100
 #define XMC4_CCU42_CC41_BASE        0x40014200
 #define XMC4_CCU42_CC42_BASE        0x40014300
 #define XMC4_CCU42_CC43_BASE        0x40014400
 #define XMC4_CCU80_BASE             0x40020000 /* CCU80 */
 #define XMC4_CCU80_CC80_BASE        0x40020100
 #define XMC4_CCU80_CC81_BASE        0x40020200
 #define XMC4_CCU80_CC82_BASE        0x40020300
 #define XMC4_CCU80_CC83_BASE        0x40020400
 #define XMC4_CCU81_BASE             0x40024000 /* CCU81 */
 #define XMC4_CCU81_CC80_BASE        0x40024100
 #define XMC4_CCU81_CC81_BASE        0x40024200
 #define XMC4_CCU81_CC82_BASE        0x40024300
 #define XMC4_CCU81_CC83_BASE        0x40024400
 #define XMC4_POSIF0_BASE            0x40028000 /* POSIF0 */
 #define XMC4_POSIF1_BASE            0x4002c000 /* POSIF1 */
 #define XMC4_USIC0_BASE             0x40030000 /* USIC0 */
 #define XMC4_USIC0_CH0_BASE         0x40030000
 #define XMC4_USIC0_CH1_BASE         0x40030200
 #define XMC4_USIC0_RAM_BASE         0x40030400
 #define XMC4_ERU1_BASE              0x40044000 /* ERU1 */
 #define XMC4_PBA1_BASE              0x48000000 /* PBA1 */
 #define XMC4_CCU43_BASE             0x48004000 /* CCU43 */
 #define XMC4_CCU43_CC40_BASE        0x48004100
 #define XMC4_CCU43_CC41_BASE        0x48004200
 #define XMC4_CCU43_CC42_BASE        0x48004300
 #define XMC4_CCU43_CC43_BASE        0x48004400
 #define XMC4_LEDTS0_BASE            0x48010000 /* LEDTS0 */
 #define XMC4_CAN_BASE               0x48014000 /* MultiCAN */
 #define XMC4_CAN_NODE0_BASE         0x48014200
 #define XMC4_CAN_NODE1_BASE         0x48014300
 #define XMC4_CAN_NODE2_BASE         0x48014400
 #define XMC4_CAN_NODE3_BASE         0x48014500
 #define XMC4_CAN_NODE4_BASE         0x48014600
 #define XMC4_CAN_NODE5_BASE         0x48014700
 #define XMC4_CAN_MO_BASE            0x48015000
 #define XMC4_DAC_BASE               0x48018000 /* DAC */
 #define XMC4_SDMMC_BASE             0x4801c000 /* SDMMC */
 #define XMC4_USIC1_BASE             0x48020000 /* USIC1 */
 #define XMC4_USIC1_CH0_BASE         0x48020000
 #define XMC4_USIC1_CH1_BASE         0x48020200
 #define XMC4_USIC1_RAM_BASE         0x48020400
 #define XMC4_USIC2_BASE             0x48024000 /* USIC2 */
 #define XMC4_USIC2_CH0_BASE         0x48024000
 #define XMC4_USIC2_CH1_BASE         0x48024200
 #define XMC4_USIC2_RAM_BASE         0x48024400
 #define XMC4_PORT_BASE(n)           (0x48028000 + ((n) << 8))
 #define XMC4_PORT0_BASE             0x48028000 /* PORTS */
 #define XMC4_PORT1_BASE             0x48028100
 #define XMC4_PORT2_BASE             0x48028200
 #define XMC4_PORT3_BASE             0x48028300
 #define XMC4_PORT4_BASE             0x48028400
 #define XMC4_PORT5_BASE             0x48028500
 #define XMC4_PORT6_BASE             0x48028600
 #define XMC4_PORT7_BASE             0x48028700
 #define XMC4_PORT8_BASE             0x48028800
 #define XMC4_PORT9_BASE             0x48028900
 #define XMC4_PORT14_BASE            0x48028e00
 #define XMC4_PORT15_BASE            0x48028f00
 #define XMC4_PBA2_BASE              0x50000000 /* PBA2 */
 #define XMC4_SCU_GENERAL_BASE       0x50004000 /* SCU & RTC */
 #define XMC4_ETH0_CON_BASE          0x50004040
 #define XMC4_SCU_INTERRUPT_BASE     0x50004074
 #define XMC4_SDMMC_CON_BASE         0x500040b4
 #define XMC4_SCU_PARITY_BASE        0x5000413c
 #define XMC4_SCU_TRAP_BASE          0x50004160
 #define XMC4_SCU_POWER_BASE         0x50004200
 #define XMC4_SCU_HIBERNATE_BASE     0x50004300
 #define XMC4_SCU_RESET_BASE         0x50004400
 #define XMC4_SCU_CLK_BASE           0x50004600
 #define XMC4_SCU_OSC_BASE           0x50004700
 #define XMC4_SCU_PLL_BASE           0x50004710
 #define XMC4_ERU0_BASE              0x50004800
 #define XMC4_DLR_BASE               0x50004900
 #define XMC4_RTC_BASE               0x50004a00
 #define XMC4_WDT_BASE               0x50008000 /* WDT */
 #define XMC4_ETH0_BASE              0x5000c000 /* ETH */
 #define XMC4_GPDMA0_CH0_BASE        0x50014000 /* GPDMA0 */
 #define XMC4_GPDMA0_CH1_BASE        0x50014058
 #define XMC4_GPDMA0_CH2_BASE        0x500140b0
 #define XMC4_GPDMA0_CH3_BASE        0x50014108
 #define XMC4_GPDMA0_CH4_BASE        0x50014160
 #define XMC4_GPDMA0_CH5_BASE        0x500141b8
 #define XMC4_GPDMA0_CH6_BASE        0x50014210
 #define XMC4_GPDMA0_CH7_BASE        0x50014268
 #define XMC4_GPDMA0_BASE            0x500142c0
 #define XMC4_GPDMA1_CH0_BASE        0x50018000 /* GPDMA1 */
 #define XMC4_GPDMA1_CH1_BASE        0x50018058
 #define XMC4_GPDMA1_CH2_BASE        0x500180b0
 #define XMC4_GPDMA1_CH3_BASE        0x50018108
 #define XMC4_GPDMA1_BASE            0x500182c0
 #define XMC4_FCE_BASE               0x50020000 /* FCE */
 #define XMC4_FCE_KE0_BASE           0x50020020
 #define XMC4_FCE_KE1_BASE           0x50020040
 #define XMC4_FCE_KE2_BASE           0x50020060
 #define XMC4_FCE_KE3_BASE           0x50020080
 #define XMC4_USB0_BASE              0x50040000 /* USB0 */
 #define XMC4_USB0_CH0_BASE          0x50040500
 #define XMC4_USB0_CH1_BASE          0x50040520
 #define XMC4_USB0_CH2_BASE          0x50040540
 #define XMC4_USB0_CH3_BASE          0x50040560
 #define XMC4_USB0_CH4_BASE          0x50040580
 #define XMC4_USB0_CH5_BASE          0x500405a0
 #define XMC4_USB0_CH6_BASE          0x500405c0
 #define XMC4_USB0_CH7_BASE          0x500405e0
 #define XMC4_USB0_CH8_BASE          0x50040600
 #define XMC4_USB0_CH9_BASE          0x50040620
 #define XMC4_USB0_CH10_BASE         0x50040640
 #define XMC4_USB0_CH11_BASE         0x50040660
 #define XMC4_USB0_CH12_BASE         0x50040680
 #define XMC4_USB0_CH13_BASE         0x500406a0
 #define XMC4_USB_EP_BASE            0x50040900
 #define XMC4_USB0_EP1_BASE          0x50040920
 #define XMC4_USB0_EP2_BASE          0x50040940
 #define XMC4_USB0_EP3_BASE          0x50040960
 #define XMC4_USB0_EP4_BASE          0x50040980
 #define XMC4_USB0_EP5_BASE          0x500409a0
 #define XMC4_USB0_EP6_BASE          0x500409c0
 #define XMC4_ECAT0_BASE             0x50100000 /* ECAT0 */
 #define XMC4_PMU0_BASE              0x58000000 /* PMU0 registers */
 #define XMC4_FLASH0_BASE            0x58001000
 #define XMC4_PREF_BASE              0x58004000 /* PMU0 prefetch */
 #define XMC4_EBU_BASE               0x58008000 /* EBU registers */
 #define XMC4_EBUMEM_CS0             0x60000000 /* EBU memory CS0 */
 #define XMC4_EBUMEM_CS1             0x64000000 /* EBU memory CS1 */
 #define XMC4_EBUMEM_CS2             0x68000000 /* EBU memory CS2 */
 #define XMC4_EBUMEM_CS3             0x6c000000 /* EBU memory CS3 */
 #define XMC4_EBUDEV_CS0             0xa0000000 /* EBU devices CS0 */
 #define XMC4_EBUDEV_CS1             0xa4000000 /* EBU devices CS1 */
 #define XMC4_EBUDEV_CS2             0xa8000000 /* EBU devices CS2 */
 #define XMC4_EBUDEV_CS3             0xac000000 /* EBU devices CS3 */
 #define XMC4_PPB_BASE               0xe000e000
 #endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_MEMORYMAP_H */
@@ -0,0 +1,181 @@
 /****************************************************************************
 * arch/arm/src/xmc4/xmc4_allocateheap.c
 *
 *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
 *   Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 * 3. Neither the name NuttX nor the names of its contributors may be
 *    used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 *
 ****************************************************************************/
 /****************************************************************************
 * Included Files
 ****************************************************************************/
 #include <nuttx/config.h>
 #include <sys/types.h>
 #include <stdint.h>
 #include <assert.h>
 #include <debug.h>
 #include <nuttx/arch.h>
 #include <nuttx/board.h>
 #include <nuttx/userspace.h>
 #include <arch/board/board.h>
 #include "mpu.h"
 #include "up_arch.h"
 #include "up_internal.h"
 #include "xmc4_mpuinit.h"
 /****************************************************************************
 * Public Functions
 ****************************************************************************/
 /****************************************************************************
 * Name: up_allocate_heap
 *
 * Description:
 *   This function will be called to dynamically set aside the heap region.
 *
 *   For the kernel build (CONFIG_BUILD_PROTECTED=y) with both kernel- and
 *   user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function provides the
 *   size of the unprotected, user-space heap.
 *
 *   If a protected kernel-space heap is provided, the kernel heap must be
 *   allocated (and protected) by an analogous up_allocate_kheap().
 *
 *   The following memory map is assumed for the flat build:
 *
 *     .data region.  Size determined at link time.
 *     .bss  region  Size determined at link time.
 *     IDLE thread stack.  Size determined by CONFIG_IDLETHREAD_STACKSIZE.
 *     Heap.  Extends to the end of SRAM.
 *
 *   The following memory map is assumed for the kernel build:
 *
 *     Kernel .data region.  Size determined at link time.
 *     Kernel .bss  region  Size determined at link time.
 *     Kernel IDLE thread stack.  Size determined by CONFIG_IDLETHREAD_STACKSIZE.
 *     Padding for alignment
 *     User .data region.  Size determined at link time.
 *     User .bss region  Size determined at link time.
 *     Kernel heap.  Size determined by CONFIG_MM_KERNEL_HEAPSIZE.
 *     User heap.  Extends to the end of SRAM.
 *
 ****************************************************************************/
 void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
 {
 #if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
  /* Get the unaligned size and position of the user-space heap.
   * This heap begins after the user-space .bss section at an offset
   * of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment).
   */
  uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE;
  size_t    usize = CONFIG_RAM_END - ubase;
  int       log2;
  DEBUGASSERT(ubase < (uintptr_t)CONFIG_RAM_END);
  /* Adjust that size to account for MPU alignment requirements.
   * NOTE that there is an implicit assumption that the CONFIG_RAM_END
   * is aligned to the MPU requirement.
   */
  log2  = (int)mpu_log2regionfloor(usize);
  DEBUGASSERT((CONFIG_RAM_END & ((1 << log2) - 1)) == 0);
  usize = (1 << log2);
  ubase = CONFIG_RAM_END - usize;
  /* Return the user-space heap settings */
  board_autoled_on(LED_HEAPALLOCATE);
  *heap_start = (FAR void *)ubase;
  *heap_size  = usize;
  /* Allow user-mode access to the user heap memory */
   xmc4_mpu_uheap((uintptr_t)ubase, usize);
 #else
  /* Return the heap settings */
  board_autoled_on(LED_HEAPALLOCATE);
  *heap_start = (FAR void *)g_idle_topstack;
  *heap_size  = CONFIG_RAM_END - g_idle_topstack;
 #endif
 }
 /****************************************************************************
 * Name: up_allocate_kheap
 *
 * Description:
 *   For the kernel build (CONFIG_BUILD_PROTECTED=y) with both kernel- and
 *   user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function allocates
 *   (and protects) the kernel-space heap.
 *
 ****************************************************************************/
 #if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
 void up_allocate_kheap(FAR void **heap_start, size_t *heap_size)
 {
  /* Get the unaligned size and position of the user-space heap.
   * This heap begins after the user-space .bss section at an offset
   * of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment).
   */
  uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE;
  size_t    usize = CONFIG_RAM_END - ubase;
  int       log2;
  DEBUGASSERT(ubase < (uintptr_t)CONFIG_RAM_END);
  /* Adjust that size to account for MPU alignment requirements.
   * NOTE that there is an implicit assumption that the CONFIG_RAM_END
   * is aligned to the MPU requirement.
   */
  log2  = (int)mpu_log2regionfloor(usize);
  DEBUGASSERT((CONFIG_RAM_END & ((1 << log2) - 1)) == 0);
  usize = (1 << log2);
  ubase = CONFIG_RAM_END - usize;
  /* Return the kernel heap settings (i.e., the part of the heap region
   * that was not dedicated to the user heap).
   */
  *heap_start = (FAR void *)USERSPACE->us_bssend;
  *heap_size  = ubase - (uintptr_t)USERSPACE->us_bssend;
 }
 #endif
@@ -0,0 +1,90 @@
 /************************************************************************************
 * arch/arm/src/xmc4/xmc4_clockconfig.h
 *
 *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
 *   Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 * 3. Neither the name NuttX nor the names of its contributors may be
 *    used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 *
 ************************************************************************************/
 #ifndef __ARCH_ARM_SRC_XMC4_XMC4_CLOCKCONFIG_H
 #define __ARCH_ARM_SRC_XMC4_XMC4_CLOCKCONFIG_H
 /************************************************************************************
 * Included Files
 ************************************************************************************/
 #include <nuttx/config.h>
 #include <stdint.h>
 /************************************************************************************
 * Preprocessor Definitions
 ************************************************************************************/
 #define OFI_FREQUENCY 24000000 /* Frequency of internal Backup Clock Source */
 #define OSI_FREQUENCY 32768    /* Frequency of internal Slow Clock Source */
 /************************************************************************************
 * Public Functions
 ************************************************************************************/
 /****************************************************************************
 * Name: xmc4_clock_configure
 *
 * Description:
 *   Called to initialize the XMC4xxx chip.  This does whatever setup is
 *   needed to put the  MCU in a usable state.  This includes the
 *   initialization of clocking using the settings in board.h.
 *
 ****************************************************************************/
 void xmc4_clock_configure(void);
 /****************************************************************************
 * Name: xmc4_get_coreclock
 *
 * Description:
 *   Return the current core clock frequency, fCPU.
 *
 ****************************************************************************/
 uint32_t xmc4_get_coreclock(void);
 /****************************************************************************
 * Name: xmc4_get_periphclock
 *
 * Description:
 *   The peripheral clock is either fCPU or fCPU/2, depending on the state
 *   of the peripheral divider.
 *
 ****************************************************************************/
 uint32_t xmc4_get_periphclock(void);
 #endif /* __ARCH_ARM_SRC_XMC4_XMC4_CLOCKCONFIG_H */
@@ -0,0 +1,183 @@
 /****************************************************************************
 * arch/arm/src/xmc4/xmc4_clockutils.c
 *
 *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
 *   Authors: Gregory Nutt <gnutt@nuttx.org>
 *
 * Reference: XMC4500 Reference Manual V1.5 2014-07 Microcontrollers.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 * 3. Neither the name NuttX nor the names of its contributors may be
 *    used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 *
 * May include some logic from sample code provided by Infineon:
 *
 *   Copyright (C) 2011-2015 Infineon Technologies AG. All rights reserved.
 *
 * Infineon Technologies AG (Infineon) is supplying this software for use with
 * Infineon's microcontrollers.  This file can be freely distributed within
 * development tools that are supporting such microcontrollers.
 *
 * THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
 * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
 * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
 *
 ****************************************************************************/
 /****************************************************************************
 * Included Files
 ****************************************************************************/
 #include <nuttx/config.h>
 #include "up_arch.h"
 #include "chip/xmc4_scu.h"
 #include "xmc4_clockconfig.h"
 #include <arch/board/board.h>
 /****************************************************************************
 * Public Functions
 ****************************************************************************/
 /****************************************************************************
 * Name: xmc4_get_coreclock
 *
 * Description:
 *   Return the current core clock frequency (fCPU).
 *
 ****************************************************************************/
 uint32_t xmc4_get_coreclock(void)
 {
  uint32_t pdiv;
  uint32_t ndiv;
  uint32_t kdiv;
  uint32_t sysdiv;
  uint32_t regval;
  uint32_t temp;
  if ((getreg32(XMC4_SCU_SYSCLKCR) & SCU_SYSCLKCR_SYSSEL) != 0)
    {
      /* fPLL is clock source for fSYS */
      if ((getreg32(XMC4_SCU_PLLCON2) & SCU_PLLCON2_PINSEL) != 0)
        {
          /* PLL input clock is the backup clock (fOFI) */
          temp = OFI_FREQUENCY;
        }
      else
        {
          /* PLL input clock is the high performance oscillator (fOSCHP);
           * Only board specific logic knows this value.
           */
          temp = BOARD_XTAL_FREQUENCY;
        }
      /* Check if PLL is locked */
      regval = getreg32(XMC4_SCU_PLLSTAT);
      if ((regval & SCU_PLLSTAT_VCOLOCK) != 0)
        {
          /* PLL normal mode */
          regval = getreg32(XMC4_SCU_PLLCON1);
          pdiv   = ((regval & SCU_PLLCON1_PDIV_MASK) >> SCU_PLLCON1_PDIV_SHIFT) + 1;
          ndiv   = ((regval & SCU_PLLCON1_NDIV_MASK) >> SCU_PLLCON1_NDIV_SHIFT) + 1;
          kdiv   = ((regval & SCU_PLLCON1_K2DIV_MASK) >> SCU_PLLCON1_K2DIV_SHIFT) + 1;
          temp   = (temp / (pdiv * kdiv)) * ndiv;
        }
      else
        {
          /* PLL prescalar mode */
          regval = getreg32(XMC4_SCU_PLLCON1);
          kdiv   = ((regval & SCU_PLLCON1_K1DIV_MASK) >> SCU_PLLCON1_K1DIV_SHIFT) + 1;
          temp   = (temp / kdiv);
        }
    }
  else
    {
      /* fOFI is clock source for fSYS */
      temp = OFI_FREQUENCY;
    }
  /* Divide by SYSDIV to get fSYS */
  regval = getreg32(XMC4_SCU_SYSCLKCR);
  sysdiv = ((regval & SCU_SYSCLKCR_SYSDIV_MASK) >> SCU_SYSCLKCR_SYSDIV_SHIFT) + 1;
  temp   = temp / sysdiv;
  /* Check if the fSYS clock is divided by two to produce fCPU clock. */
  regval = getreg32(XMC4_SCU_CPUCLKCR);
  if ((regval & SCU_CPUCLKCR_CPUDIV) != 0)
    {
      temp = temp >> 1;
    }
  return temp;
 }
 /****************************************************************************
 * Name: xmc4_get_periphclock
 *
 * Description:
 *   The peripheral clock is either fCPU or fCPU/2, depending on the state
 *   of the peripheral divider.
 *
 ****************************************************************************/
 uint32_t xmc4_get_periphclock(void)
 {
  uint32_t periphclock;
  uint32_t regval;
  /* Get the CPU clock frequency.  Unless it is divided down, this also the
   * peripheral clock frequency.
   */
  periphclock = xmc4_get_coreclock();
  /* Get the peripheral clock divider */
  regval = getreg32(XMC4_SCU_PBCLKCR);
  if ((regval & SCU_PBCLKCR_PBDIV) != 0)
    {
      /* The peripheral clock is fCPU/2 */
      periphclock >>= 1;
    }
  return periphclock;
 }
@@ -0,0 +1,86 @@
 /****************************************************************************
 * arch/arm/src/xmc4/xmc4_clrpend.c
 *
 *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
 *   Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 * 3. Neither the name NuttX nor the names of its contributors may be
 *    used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 *
 ****************************************************************************/
 /****************************************************************************
 * Included Files
 ****************************************************************************/
 #include <nuttx/config.h>
 #include <arch/irq.h>
 #include "nvic.h"
 #include "up_arch.h"
 /****************************************************************************
 * Public Functions
 ****************************************************************************/
 /****************************************************************************
 * Name: xmc4_clrpend
 *
 * Description:
 *   Clear a pending interrupt at the NVIC.  This does not seem to be required
 *   for most interrupts.  Don't know why...
 *
 *   I keep it in a separate file so that it will not increase the footprint
 *   on Kinetis platforms that do not need this function.
 *
 ****************************************************************************/
 void xmc4_clrpend(int irq)
 {
  /* Check for external interrupt */
  if (irq >= XMC4_IRQ_FIRST)
    {
      if (irq < (XMC4_IRQ_FIRST+32))
        {
          putreg32(1 << (irq - XMC4_IRQ_FIRST), NVIC_IRQ0_31_CLRPEND);
        }
      else if (irq < (XMC4_IRQ_FIRST+64))
        {
          putreg32(1 << (irq - XMC4_IRQ_FIRST - 32), NVIC_IRQ32_63_CLRPEND);
        }
      else if (irq < (XMC4_IRQ_FIRST+96))
        {
          putreg32(1 << (irq - XMC4_IRQ_FIRST - 64), NVIC_IRQ64_95_CLRPEND);
        }
      else if (irq < NR_IRQS)
        {
          putreg32(1 << (irq - XMC4_IRQ_FIRST - 96), NVIC_IRQ96_127_CLRPEND);
        }
    }
 }
@@ -0,0 +1,219 @@
 /************************************************************************************
 * arch/arm/src/xmc4/xmc4_config.h
 *
 *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
 *   Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 * 3. Neither the name NuttX nor the names of its contributors may be
 *    used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 *
 ************************************************************************************/
 #ifndef __ARCH_ARM_SRC_XMC4_XMC4_CONFIG_H
 #define __ARCH_ARM_SRC_XMC4_XMC4_CONFIG_H
 /************************************************************************************
 * Included Files
 ************************************************************************************/
 #include <nuttx/config.h>
 #include <arch/board/board.h>
 #include "chip.h"
 /************************************************************************************
 * Pre-processor Definitions
 ************************************************************************************/
 /* Configuration *********************************************************************/
 /* Make sure that no unsupported UARTs are enabled */
 #ifndef CONFIG_XMC4_USIC0
 #  undef CONFIG_XMC4_USIC0_CHAN0_ISUART
 #  undef CONFIG_XMC4_USIC0_CHAN1_ISUART
 #endif
 #ifndef CONFIG_XMC4_USIC1
 #  undef CONFIG_XMC4_USIC1_CHAN0_ISUART
 #  undef CONFIG_XMC4_USIC1_CHAN1_ISUART
 #endif
 #ifndef CONFIG_XMC4_USIC2
 #  undef CONFIG_XMC4_USIC2_CHAN0_ISUART
 #  undef CONFIG_XMC4_USIC2_CHAN1_ISUART
 #endif
 /* Map logical UART names (Just for simplicity of naming) */
 #undef HAVE_UART0
 #undef HAVE_UART1
 #undef HAVE_UART2
 #undef HAVE_UART3
 #undef HAVE_UART4
 #undef HAVE_UART5
 #ifdef CONFIG_XMC4_USIC0_CHAN0_ISUART
 #  define HAVE_UART0
 #endif
 #ifdef CONFIG_XMC4_USIC0_CHAN1_ISUART
 #  define HAVE_UART1
 #endif
 #ifdef CONFIG_XMC4_USIC1_CHAN0_ISUART
 #  define HAVE_UART2
 #endif
 #ifdef CONFIG_XMC4_USIC1_CHAN1_ISUART
 #  define HAVE_UART3
 #endif
 #ifdef CONFIG_XMC4_USIC2_CHAN0_ISUART
 #  define HAVE_UART4
 #endif
 #ifdef CONFIG_XMC4_USIC2_CHAN1_ISUART
 #  define HAVE_UART5
 #endif
 /* Are any UARTs enabled? */
 #undef HAVE_UART_DEVICE
 #if defined(HAVE_UART0) || defined(HAVE_UART1) || defined(HAVE_UART2) || \
    defined(HAVE_UART3) || defined(HAVE_UART4) || defined(HAVE_UART5)
 #  define HAVE_UART_DEVICE 1
 #endif
 /* Is there a serial console? There should be at most one defined.  It could be on
 * any UARTn, n=0,1,2,3,4,5
 */
 #undef HAVE_UART_CONSOLE
 #if defined(CONFIG_CONSOLE_SYSLOG)
 #    undef CONFIG_UART0_SERIAL_CONSOLE
 #    undef CONFIG_UART1_SERIAL_CONSOLE
 #    undef CONFIG_UART2_SERIAL_CONSOLE
 #    undef CONFIG_UART3_SERIAL_CONSOLE
 #    undef CONFIG_UART4_SERIAL_CONSOLE
 #    undef CONFIG_UART5_SERIAL_CONSOLE
 #else
 #  if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(HAVE_UART0)
 #    undef CONFIG_UART1_SERIAL_CONSOLE
 #    undef CONFIG_UART2_SERIAL_CONSOLE
 #    undef CONFIG_UART3_SERIAL_CONSOLE
 #    undef CONFIG_UART4_SERIAL_CONSOLE
 #    undef CONFIG_UART5_SERIAL_CONSOLE
 #    define HAVE_UART_CONSOLE 1
 #  elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(HAVE_UART1)
 #    undef CONFIG_UART0_SERIAL_CONSOLE
 #    undef CONFIG_UART2_SERIAL_CONSOLE
 #    undef CONFIG_UART3_SERIAL_CONSOLE
 #    undef CONFIG_UART4_SERIAL_CONSOLE
 #    undef CONFIG_UART5_SERIAL_CONSOLE
 #    define HAVE_UART_CONSOLE 1
 #  elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(HAVE_UART2)
 #    undef CONFIG_UART0_SERIAL_CONSOLE
 #    undef CONFIG_UART1_SERIAL_CONSOLE
 #    undef CONFIG_UART3_SERIAL_CONSOLE
 #    undef CONFIG_UART4_SERIAL_CONSOLE
 #    undef CONFIG_UART5_SERIAL_CONSOLE
 #    define HAVE_UART_CONSOLE 1
 #  elif defined(CONFIG_UART3_SERIAL_CONSOLE) && defined(HAVE_UART3)
 #    undef CONFIG_UART0_SERIAL_CONSOLE
 #    undef CONFIG_UART1_SERIAL_CONSOLE
 #    undef CONFIG_UART2_SERIAL_CONSOLE
 #    undef CONFIG_UART4_SERIAL_CONSOLE
 #    undef CONFIG_UART5_SERIAL_CONSOLE
 #    define HAVE_UART_CONSOLE 1
 #  elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(HAVE_UART4)
 #    undef CONFIG_UART0_SERIAL_CONSOLE
 #    undef CONFIG_UART1_SERIAL_CONSOLE
 #    undef CONFIG_UART2_SERIAL_CONSOLE
 #    undef CONFIG_UART3_SERIAL_CONSOLE
 #    undef CONFIG_UART5_SERIAL_CONSOLE
 #    define HAVE_UART_CONSOLE 1
 #  elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(HAVE_UART5)
 #    undef CONFIG_UART0_SERIAL_CONSOLE
 #    undef CONFIG_UART1_SERIAL_CONSOLE
 #    undef CONFIG_UART2_SERIAL_CONSOLE
 #    undef CONFIG_UART3_SERIAL_CONSOLE
 #    undef CONFIG_UART4_SERIAL_CONSOLE
 #    define HAVE_UART_CONSOLE 1
 #  else
 #    ifdef CONFIG_DEV_CONSOLE
 #      warning "No valid CONFIG_[LP]UART[n]_SERIAL_CONSOLE Setting"
 #    endif
 #    undef CONFIG_UART0_SERIAL_CONSOLE
 #    undef CONFIG_UART1_SERIAL_CONSOLE
 #    undef CONFIG_UART2_SERIAL_CONSOLE
 #    undef CONFIG_UART3_SERIAL_CONSOLE
 #    undef CONFIG_UART4_SERIAL_CONSOLE
 #    undef CONFIG_UART5_SERIAL_CONSOLE
 #  endif
 #endif
 /* Check UART flow control (Not yet supported) */
 # undef CONFIG_UART0_FLOWCONTROL
 # undef CONFIG_UART1_FLOWCONTROL
 # undef CONFIG_UART2_FLOWCONTROL
 # undef CONFIG_UART3_FLOWCONTROL
 # undef CONFIG_UART4_FLOWCONTROL
 # undef CONFIG_UART5_FLOWCONTROL
 /* UART Default Interrupt Priorities */
 #ifndef CONFIG_XMC4_UART0PRIO
 #  define CONFIG_XMC4_UART0PRIO NVIC_SYSH_PRIORITY_DEFAULT
 #endif
 #ifndef CONFIG_XMC4_UART1PRIO
 #  define CONFIG_XMC4_UART1PRIO NVIC_SYSH_PRIORITY_DEFAULT
 #endif
 #ifndef CONFIG_XMC4_UART2PRIO
 #  define CONFIG_XMC4_UART2PRIO NVIC_SYSH_PRIORITY_DEFAULT
 #endif
 #ifndef CONFIG_XMC4_UART3PRIO
 #  define CONFIG_XMC4_UART3PRIO NVIC_SYSH_PRIORITY_DEFAULT
 #endif
 #ifndef CONFIG_XMC4_UART4PRIO
 #  define CONFIG_XMC4_UART4PRIO NVIC_SYSH_PRIORITY_DEFAULT
 #endif
 #ifndef CONFIG_XMC4_UART5PRIO
 #  define CONFIG_XMC4_UART5PRIO NVIC_SYSH_PRIORITY_DEFAULT
 #endif
 /************************************************************************************
 * Public Types
 ************************************************************************************/
 /************************************************************************************
 * Public Data
 ************************************************************************************/
 /************************************************************************************
 * Inline Functions
 ************************************************************************************/
 /************************************************************************************
 * Public Functions
 ************************************************************************************/
 #endif /* __ARCH_ARM_SRC_XMC4_XMC4_CONFIG_H */
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