From 0b17b1feb340d6f1547e55b020e483ad1739020d Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 28 May 2016 17:42:29 -0600 Subject: [PATCH] i.MX6: Add ECSPI configuration logic. Updated ECSPI header files --- arch/arm/src/imx6/Kconfig | 29 +++++++++++++++ arch/arm/src/imx6/chip/imx_ecspi.h | 60 +++++++++++++++--------------- arch/arm/src/imx6/imx_ecspi.h | 40 ++++++++++++++++++-- 3 files changed, 96 insertions(+), 33 deletions(-) diff --git a/arch/arm/src/imx6/Kconfig b/arch/arm/src/imx6/Kconfig index 8296c1a2ae3..f49dde32bf6 100644 --- a/arch/arm/src/imx6/Kconfig +++ b/arch/arm/src/imx6/Kconfig @@ -54,8 +54,37 @@ config IMX6_HAVE_HDCP endmenu # "iMX.6 Chip Selection" +config IMX6_ECSPI + bool + default n + menu "iMX.6 Peripheral Selection" +config IMX6_ECSPI1 + bool "ECSPI1" + default n + select IMX6_ECSPI + +config IMX6_ECSPI2 + bool "ECSPI2" + default n + select IMX6_ECSPI + +config IMX6_ECSPI3 + bool "ECSPI3" + default n + select IMX6_ECSPI + +config IMX6_ECSPI4 + bool "ECSPI4" + default n + select IMX6_ECSPI + +config IMX6_ECSPI5 + bool "ECSPI5" + default n + select IMX6_ECSPI + config IMX6_UART1 bool "UART1" default n diff --git a/arch/arm/src/imx6/chip/imx_ecspi.h b/arch/arm/src/imx6/chip/imx_ecspi.h index 21ed32186df..e034ef737c0 100644 --- a/arch/arm/src/imx6/chip/imx_ecspi.h +++ b/arch/arm/src/imx6/chip/imx_ecspi.h @@ -131,36 +131,36 @@ /* Control Register */ -#define ECSPI_CONREG_EN (1 << 0) /* Bit 0: SPI Block enable control */ -#define ECSPI_CONREG_HT (1 << 1) /* Bit 1: Hardware trigger enable */ -#define ECSPI_CONREG_XCH (1 << 2) /* Bit 2: SPI Exchange bit */ -#define ECSPI_CONREG_SMC (1 << 3) /* Bit 3: Start mode control */ -#define ECSPI_CONREG_CHMODE_SHIFT (4) /* Bits 4-7: SPI Channel mode */ -#define ECSPI_CONREG_CHMODE_MASK (15 << ECSPI_CONREG_CHMODE_SHIFT) -# define ECSPI_CONREG_CH0MASTER (1 << ECSPI_CONREG_CHMODE_SHIFT) /* Channel 0 master mode */ -# define ECSPI_CONREG_CH1MASTER (2 << ECSPI_CONREG_CHMODE_SHIFT) /* Channel 1 master mode */ -# define ECSPI_CONREG_CH2MASTER (4 << ECSPI_CONREG_CHMODE_SHIFT) /* Channel 2 master mode */ -# define ECSPI_CONREG_CH3MASTER (8 << ECSPI_CONREG_CHMODE_SHIFT) /* Channel 3 master mode */ -#define ECSPI_CONREG_POSTDIV_SHIFT (8) /* Bits 8-11: SPI Post divider */ -#define ECSPI_CONREG_POSTDIV_MASK (15 << ECSPI_CONREG_POSTDIV_SHIFT) -# define ECSPI_CONREG_POSTDIV(n) ((uint32_t)(n) << ECSPI_CONREG_POSTDIV_SHIFT) -#define ECSPI_CONREG_PREDIV_SHIFT (12) /* Bits 12-15: SPI Pre divider */ -#define ECSPI_CONREG_PREDIV_MASK (15 << ECSPI_CONREG_PREDIV_SHIFT) -# define ECSPI_CONREG_PREDIV(n) ((uint32_t)(n) << ECSPI_CONREG_PREDIV_SHIFT) -#define ECSPI_CONREG_DRCTL_SHIFT 16 /* Bits 16-17: SPI Data ready control */ -#define ECSPI_CONREG_DRCTL_MASK (3 << ECSPI_CONREG_DRCTL_SHIFT) -# define ECSPI_CONREG_DRCTL_IGNRDY (0 << ECSPI_CONREG_DRCTL_SHIFT) -# define ECSPI_CONREG_DRCTL_FALLING (1 << ECSPI_CONREG_DRCTL_SHIFT) -# define ECSPI_CONREG_DRCTL_ACTVLOW (2 << ECSPI_CONREG_DRCTL_SHIFT) -#define ECSPI_CONREG_CHSEL_SHIFT (18) /* Bits 18-19: SPI Channel select bits */ -#define ECSPI_CONREG_CHSEL_MASK (3 << ECSPI_CONREG_CHSEL_SHIFT) -# define ECSPI_CONREG_CHSEL_SS0 (0 << ECSPI_CONREG_CHSEL_SHIFT) /* Channel 0 select (SS0) */ -# define ECSPI_CONREG_CHSEL_SS1 (1 << ECSPI_CONREG_CHSEL_SHIFT) /* Channel 1 select (SS1) */ -# define ECSPI_CONREG_CHSEL_SS2 (2 << ECSPI_CONREG_CHSEL_SHIFT) /* Channel 2 select (SS2) */ -# define ECSPI_CONREG_CHSEL_SS3 (3 << ECSPI_CONREG_CHSEL_SHIFT) /* Channel 3 select (SS3) */ -#define ECSPI_CONREG_BURSTLEN_SHIFT (20) /* Bits 20-31: Burst length */ -#define ECSPI_CONREG_BURSTLEN_MASK (0xfff << ECSPI_CONREG_BURSTLEN_SHIFT) -# define ECSPI_CONREG_BURSTLEN(n) ((uint32_t)(n) << ECSPI_CONREG_BURSTLEN_SHIFT) +#define ECSPI_CONREG_EN (1 << 0) /* Bit 0: SPI Block enable control */ +#define ECSPI_CONREG_HT (1 << 1) /* Bit 1: Hardware trigger enable */ +#define ECSPI_CONREG_XCH (1 << 2) /* Bit 2: SPI Exchange bit */ +#define ECSPI_CONREG_SMC (1 << 3) /* Bit 3: Start mode control */ +#define ECSPI_CONREG_CHMODE_SHIFT (4) /* Bits 4-7: SPI Channel mode */ +#define ECSPI_CONREG_CHMODE_MASK (15 << ECSPI_CONREG_CHMODE_SHIFT) +# define ECSPI_CONREG_CH0MASTER (1 << ECSPI_CONREG_CHMODE_SHIFT) /* Channel 0 master mode */ +# define ECSPI_CONREG_CH1MASTER (2 << ECSPI_CONREG_CHMODE_SHIFT) /* Channel 1 master mode */ +# define ECSPI_CONREG_CH2MASTER (4 << ECSPI_CONREG_CHMODE_SHIFT) /* Channel 2 master mode */ +# define ECSPI_CONREG_CH3MASTER (8 << ECSPI_CONREG_CHMODE_SHIFT) /* Channel 3 master mode */ +#define ECSPI_CONREG_POSTDIV_SHIFT (8) /* Bits 8-11: SPI Post divider */ +#define ECSPI_CONREG_POSTDIV_MASK (15 << ECSPI_CONREG_POSTDIV_SHIFT) +# define ECSPI_CONREG_POSTDIV(n) ((uint32_t)(n) << ECSPI_CONREG_POSTDIV_SHIFT) +#define ECSPI_CONREG_PREDIV_SHIFT (12) /* Bits 12-15: SPI Pre divider */ +#define ECSPI_CONREG_PREDIV_MASK (15 << ECSPI_CONREG_PREDIV_SHIFT) +# define ECSPI_CONREG_PREDIV(n) ((uint32_t)(n) << ECSPI_CONREG_PREDIV_SHIFT) +#define ECSPI_CONREG_DRCTL_SHIFT 16 /* Bits 16-17: SPI Data ready control */ +#define ECSPI_CONREG_DRCTL_MASK (3 << ECSPI_CONREG_DRCTL_SHIFT) +# define ECSPI_CONREG_DRCTL_IGNRDY (0 << ECSPI_CONREG_DRCTL_SHIFT) +# define ECSPI_CONREG_DRCTL_FALLING (1 << ECSPI_CONREG_DRCTL_SHIFT) +# define ECSPI_CONREG_DRCTL_ACTVLOW (2 << ECSPI_CONREG_DRCTL_SHIFT) +#define ECSPI_CONREG_CHSEL_SHIFT (18) /* Bits 18-19: SPI Channel select bits */ +#define ECSPI_CONREG_CHSEL_MASK (3 << ECSPI_CONREG_CHSEL_SHIFT) +# define ECSPI_CONREG_CHSEL_SS0 (0 << ECSPI_CONREG_CHSEL_SHIFT) /* Channel 0 select (SS0) */ +# define ECSPI_CONREG_CHSEL_SS1 (1 << ECSPI_CONREG_CHSEL_SHIFT) /* Channel 1 select (SS1) */ +# define ECSPI_CONREG_CHSEL_SS2 (2 << ECSPI_CONREG_CHSEL_SHIFT) /* Channel 2 select (SS2) */ +# define ECSPI_CONREG_CHSEL_SS3 (3 << ECSPI_CONREG_CHSEL_SHIFT) /* Channel 3 select (SS3) */ +#define ECSPI_CONREG_BURSTLEN_SHIFT (20) /* Bits 20-31: Burst length */ +#define ECSPI_CONREG_BURSTLEN_MASK (0xfff << ECSPI_CONREG_BURSTLEN_SHIFT) +# define ECSPI_CONREG_BURSTLEN(n) ((uint32_t)(n) << ECSPI_CONREG_BURSTLEN_SHIFT) /* Configuration Register */ diff --git a/arch/arm/src/imx6/imx_ecspi.h b/arch/arm/src/imx6/imx_ecspi.h index b0166e28a9e..40ca57c465c 100644 --- a/arch/arm/src/imx6/imx_ecspi.h +++ b/arch/arm/src/imx6/imx_ecspi.h @@ -117,10 +117,44 @@ FAR struct spi_dev_s *imx_spibus_initialize(int port); * ************************************************************************************/ -void imx_spiselect(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected); -uint8_t imx_spistatus(FAR struct spi_dev_s *dev, enum spi_dev_e devid); +#ifdef CONFIG_IMX6_ECSPI1 +void imx_spi1select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected); +uint8_t imx_spi1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid); #ifdef CONFIG_SPI_CMDDATA -int imx_spicmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd); +int imx_spi1cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd); +#endif +#endif + +#ifdef CONFIG_IMX6_ECSPI2 +void imx_spi2select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected); +uint8_t imx_spi2status(FAR struct spi_dev_s *dev, enum spi_dev_e devid); +#ifdef CONFIG_SPI_CMDDATA +int imx_spi2cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd); +#endif +#endif + +#ifdef CONFIG_IMX6_ECSPI3 +void imx_spi3select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected); +uint8_t imx_spi3status(FAR struct spi_dev_s *dev, enum spi_dev_e devid); +#ifdef CONFIG_SPI_CMDDATA +int imx_spi3cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd); +#endif +#endif + +#ifdef CONFIG_IMX6_ECSPI4 +void imx_spi4select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected); +uint8_t imx_spi4status(FAR struct spi_dev_s *dev, enum spi_dev_e devid); +#ifdef CONFIG_SPI_CMDDATA +int imx_spi4cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd); +#endif +#endif + +#ifdef CONFIG_IMX6_ECSPI5 +void imx_spi5select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected); +uint8_t imx_spi5status(FAR struct spi_dev_s *dev, enum spi_dev_e devid); +#ifdef CONFIG_SPI_CMDDATA +int imx_spi5cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd); +#endif #endif #undef EXTERN