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Merged nuttx/nuttx into master

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This commit is contained in:
Aleksandr Vyhovanec
2017-03-17 11:47:31 +03:00
parent add351ea39 c3ccfab720
commit 0ac4e2e7a4
112 changed files with 6705 additions and 581 deletions
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FlatLibs.mk
+6
View File
@@ -118,6 +118,12 @@ ifeq ($(CONFIG_WIRELESS),y)
NUTTXLIBS += lib$(DELIM)libwireless$(LIBEXT)
endif
# Add C++ library
ifeq ($(CONFIG_HAVE_CXX),y)
NUTTXLIBS += lib$(DELIM)libcxx$(LIBEXT)
endif
# Export all libraries
EXPORTLIBS = $(NUTTXLIBS)
Kconfig
+32
View File
@@ -732,6 +732,38 @@ config DEBUG_NET_INFO
endif # DEBUG_NET
config DEBUG_WIRELESS
bool "Wireless Debug Features"
default n
depends on WIRELESS || DRIVERS_WIRELESS
---help---
Enable DEBUG_WIRELESS debug features.
if DEBUG_WIRELESS
config DEBUG_WIRELESS_ERROR
bool "Wireless Error Output"
default n
depends on DEBUG_ERROR
---help---
Enable wireless error output to SYSLOG.
config DEBUG_WIRELESS_WARN
bool "Wireless Warnings Output"
default n
depends on DEBUG_WARN
---help---
Enable wireless warning output to SYSLOG.
config DEBUG_WIRELESS_INFO
bool "Wireless Informational Output"
default n
depends on DEBUG_INFO
---help---
Enable wireless informational output to SYSLOG.
endif # DEBUG_WIRELESS
config DEBUG_SCHED
bool "Scheduler Debug Features"
default n
KernelLibs.mk
+6
View File
@@ -113,6 +113,12 @@ ifeq ($(CONFIG_WIRELESS),y)
NUTTXLIBS += lib$(DELIM)libwireless$(LIBEXT)
endif
# Add C++ library
ifeq ($(CONFIG_HAVE_CXX),y)
NUTTXLIBS += lib$(DELIM)libcxx$(LIBEXT)
endif
# Export only the user libraries
EXPORTLIBS = $(USERLIBS)
ProtectedLibs.mk
+6
View File
@@ -123,6 +123,12 @@ ifeq ($(CONFIG_WIRELESS),y)
NUTTXLIBS += lib$(DELIM)libwireless$(LIBEXT)
endif
# Add C++ library
ifeq ($(CONFIG_HAVE_CXX),y)
NUTTXLIBS += lib$(DELIM)libcxx$(LIBEXT)
endif
# Export only the user libraries
EXPORTLIBS = $(USERLIBS)
TODO
+17 -3
View File
@@ -1,4 +1,4 @@
NuttX TODO List (Last updated March 7, 2017)
NuttX TODO List (Last updated March 14, 2017)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
This file summarizes known NuttX bugs, limitations, inconsistencies with
@@ -19,7 +19,7 @@ nuttx/:
(8) Kernel/Protected Build
(3) C++ Support
(6) Binary loaders (binfmt/)
(13) Network (net/, drivers/net)
(14) Network (net/, drivers/net)
(4) USB (drivers/usbdev, drivers/usbhost)
(0) Other drivers (drivers/)
(12) Libraries (libc/, libm/)
@@ -507,7 +507,7 @@ o Kernel/Protected Build
in the nuttx/ directory. However, the user interfaces must be
moved into a NuttX library or into apps/. Currently
applications calls to the NxTerm user interfaces are
undefined.
undefined in the Kernel/Protected builds.
Status: Open
Priority: Medium
@@ -1065,6 +1065,20 @@ o Network (net/, drivers/net)
Status: Open
Priority: High if you happen to be using Ethernet in this configuration.
Title: REPARTITION DRIVER FUNCTIONALITY
Description: Every network driver performs the first level of packet decoding.
It examines the packet header and calls ipv4_input(), ipv6_input().
icmp_input(), etc. as appropriate. This is a maintenance problem
because it means that any changes to the network input interfaces
affects all drivers.
A better, more maintainable solution would use a single net_input()
function that would receive all incoming packets. This function
would then perform that common packet decoding logic that is
currently implemented in every network driver.
Status: Open
Priority: Low. Really just as aesthetic maintainability issue.
o USB (drivers/usbdev, drivers/usbhost)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
arch/arm/Kconfig
+1 -1
View File
@@ -156,7 +156,7 @@ config ARCH_CHIP_NUC1XX
select ARCH_CORTEXM0
select ARCH_HAVE_CMNVECTOR
---help---
NPX LPC43XX architectures (ARM Cortex-M4).
Nuvoton NUC100/120 architectures (ARM Cortex-M0).
config ARCH_CHIP_SAMA5
bool "Atmel SAMA5"
arch/arm/src/a1x/a1x_irq.c
-10
View File
@@ -159,16 +159,6 @@ void up_irqinitialize(void)
(void)getreg32(A1X_INTC_IRQ_PEND(i)); /* Reading status clears pending interrupts */
}
/* Colorize the interrupt stack for debug purposes */
#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3
{
size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~3);
up_stack_color((FAR void *)((uintptr_t)&g_intstackbase - intstack_size),
intstack_size);
}
#endif
/* Set the interrupt base address to zero. We do not use the vectored
* interrupts.
*/
arch/arm/src/armv7-m/gnu/up_exception.S
+1 -1
View File
@@ -323,7 +323,7 @@ exception_common:
.global g_intstackbase
.align 8
g_intstackalloc:
.skip (CONFIG_ARCH_INTERRUPTSTACK & ~7)
.skip ((CONFIG_ARCH_INTERRUPTSTACK + 4) & ~7)
g_intstackbase:
.size g_intstackalloc, .-g_intstackalloc
#endif
arch/arm/src/armv7-m/gnu/up_lazyexception.S
+2 -2
View File
@@ -235,7 +235,7 @@ exception_common:
*
* Here:
* r0 = Address of the register save area
*
* NOTE: It is a requirement that up_restorefpu() preserve the value of
* r0!
*/
@@ -355,7 +355,7 @@ exception_common:
.global g_intstackbase
.align 8
g_intstackalloc:
.skip (CONFIG_ARCH_INTERRUPTSTACK & ~7)
.skip ((CONFIG_ARCH_INTERRUPTSTACK + 4) & ~7)
g_intstackbase:
.size g_intstackalloc, .-g_intstackalloc
#endif
arch/arm/src/common/up_createstack.c
+6 -17
View File
@@ -66,22 +66,11 @@
# define HAVE_KERNEL_HEAP 1
#endif
/* ARM requires at least a 4-byte stack alignment. For use with EABI and
* floating point, the stack must be aligned to 8-byte addresses.
/* For use with EABI and floating point, the stack must be aligned to 8-byte
* addresses.
*/
#ifndef CONFIG_STACK_ALIGNMENT
/* The symbol __ARM_EABI__ is defined by GCC if EABI is being used. If you
* are not using GCC, make sure that CONFIG_STACK_ALIGNMENT is set correctly!
*/
# ifdef __ARM_EABI__
# define CONFIG_STACK_ALIGNMENT 8
# else
# define CONFIG_STACK_ALIGNMENT 4
# endif
#endif
#define CONFIG_STACK_ALIGNMENT 8
/* Stack alignment macros */
@@ -233,9 +222,9 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype)
top_of_stack = (uint32_t)tcb->stack_alloc_ptr + stack_size - 4;
/* The ARM stack must be aligned; 4 byte alignment for OABI and
* 8-byte alignment for EABI. If necessary top_of_stack must be
* rounded down to the next boundary
/* The ARM stack must be aligned to 8-byte alignment for EABI.
* If necessary top_of_stack must be rounded down to the next
* boundary
*/
top_of_stack = STACK_ALIGN_DOWN(top_of_stack);
arch/arm/src/common/up_initialize.c
+1 -1
View File
@@ -100,7 +100,7 @@ static void up_calibratedelay(void)
*
****************************************************************************/
#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3
#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 7
static inline void up_color_intstack(void)
{
uint32_t *ptr = (uint32_t *)&g_intstackalloc;
arch/arm/src/common/up_stackframe.c
+3 -14
View File
@@ -53,22 +53,11 @@
* Pre-processor Macros
****************************************************************************/
/* ARM requires at least a 4-byte stack alignment. For use with EABI and
* floating point, the stack must be aligned to 8-byte addresses.
/* For use with EABI and floating point, the stack must be aligned to 8-byte
* addresses.
*/
#ifndef CONFIG_STACK_ALIGNMENT
/* The symbol __ARM_EABI__ is defined by GCC if EABI is being used. If you
* are not using GCC, make sure that CONFIG_STACK_ALIGNMENT is set correctly!
*/
# ifdef __ARM_EABI__
# define CONFIG_STACK_ALIGNMENT 8
# else
# define CONFIG_STACK_ALIGNMENT 4
# endif
#endif
#define CONFIG_STACK_ALIGNMENT 8
/* Stack alignment macros */
arch/arm/src/common/up_usestack.c
+6 -17
View File
@@ -56,22 +56,11 @@
* Pre-processor Macros
****************************************************************************/
/* ARM requires at least a 4-byte stack alignment. For use with EABI and
* floating point, the stack must be aligned to 8-byte addresses.
/* For use with EABI and floating point, the stack must be aligned to 8-byte
* addresses.
*/
#ifndef CONFIG_STACK_ALIGNMENT
/* The symbol __ARM_EABI__ is defined by GCC if EABI is being used. If you
* are not using GCC, make sure that CONFIG_STACK_ALIGNMENT is set correctly!
*/
# ifdef __ARM_EABI__
# define CONFIG_STACK_ALIGNMENT 8
# else
# define CONFIG_STACK_ALIGNMENT 4
# endif
#endif
#define CONFIG_STACK_ALIGNMENT 8
/* Stack alignment macros */
@@ -143,9 +132,9 @@ int up_use_stack(struct tcb_s *tcb, void *stack, size_t stack_size)
top_of_stack = (uint32_t)tcb->stack_alloc_ptr + stack_size - 4;
/* The ARM stack must be aligned; 4 byte alignment for OABI and 8-byte
* alignment for EABI. If necessary top_of_stack must be rounded down
* to the next boundary
/* The ARM stack must be aligned to 8-byte alignment for EABI.
* If necessary top_of_stack must be rounded down to the next
* boundary
*/
top_of_stack = STACK_ALIGN_DOWN(top_of_stack);
arch/arm/src/common/up_vfork.c
+3 -14
View File
@@ -56,22 +56,11 @@
* Pre-processor Definitions
****************************************************************************/
/* ARM requires at least a 4-byte stack alignment. For use with EABI and
* floating point, the stack must be aligned to 8-byte addresses.
/* For use with EABI and floating point, the stack must be aligned to 8-byte
* addresses.
*/
#ifndef CONFIG_STACK_ALIGNMENT
/* The symbol __ARM_EABI__ is defined by GCC if EABI is being used. If you
* are not using GCC, make sure that CONFIG_STACK_ALIGNMENT is set correctly!
*/
# ifdef __ARM_EABI__
# define CONFIG_STACK_ALIGNMENT 8
# else
# define CONFIG_STACK_ALIGNMENT 4
# endif
#endif
#define CONFIG_STACK_ALIGNMENT 8
/****************************************************************************
* Public Functions
arch/arm/src/efm32/efm32_irq.c
-10
View File
@@ -319,16 +319,6 @@ void up_irqinitialize(void)
putreg32(0xffffffff, NVIC_IRQ_CLEAR(i));
}
#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3
/* Colorize the interrupt stack for debug purposes */
{
size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~3);
up_stack_color((FAR void *)((uintptr_t)&g_intstackbase - intstack_size),
intstack_size);
}
#endif
/* Make sure that we are using the correct vector table. The default
* vector address is 0x0000:0000 but if we are executing code that is
* positioned in SRAM or in external FLASH, then we may need to reset
arch/arm/src/imx6/imx_irq.c
-10
View File
@@ -93,16 +93,6 @@ void up_irqinitialize(void)
* access to the GIC.
*/
/* Colorize the interrupt stack for debug purposes */
#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3
{
size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~3);
up_stack_color((FAR void *)((uintptr_t)&g_intstackbase - intstack_size),
intstack_size);
}
#endif
/* Initialize the Generic Interrupt Controller (GIC) for CPU0 */
arm_gic0_initialize(); /* Initialization unique to CPU0 */
arch/arm/src/kinetis/chip.h
+1 -1
View File
@@ -52,7 +52,7 @@
/* If the common ARMv7-M vector handling logic is used, then it expects the
* following definition in this file that provides the number of supported external
* interrupts which, for this architecture, is provided in the arch/stm32f7/chip.h
* interrupts which, for this architecture, is provided in the arch/kinetis/chip.h
* header file.
*/
arch/arm/src/kinetis/kinetis_clrpend.c
-1
View File
@@ -1,6 +1,5 @@
/****************************************************************************
* arch/arm/src/kinetis/kinetis_clrpend.c
* arch/arm/src/chip/kinetis_clrpend.c
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
arch/arm/src/kinetis/kinetis_start.c
+1 -1
View File
@@ -1,6 +1,5 @@
/****************************************************************************
* arch/arm/src/kinetis/kinetis_start.c
* arch/arm/src/chip/kinetis_start.c
*
* Copyright (C) 2011-2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@@ -327,6 +326,7 @@ void __start(void)
* can get debug output as soon as possible (This depends on clock
* configuration).
*/
kinetis_fpuconfig();
kinetis_lowsetup();
#ifdef USE_EARLYSERIALINIT
arch/arm/src/kinetis/kinetis_vectors.S
+1 -1
View File
@@ -484,7 +484,7 @@ exception_common:
.global g_intstackbase
.align 8
g_intstackalloc:
.skip (CONFIG_ARCH_INTERRUPTSTACK & ~7)
.skip ((CONFIG_ARCH_INTERRUPTSTACK + 4) & ~7)
g_intstackbase:
.size g_intstackalloc, .-g_intstackalloc
#endif
arch/arm/src/lpc17xx/lpc17_vectors.S
+2 -2
View File
@@ -348,7 +348,7 @@ exception_common:
*
* Here:
* r0 = Address of the register save area
*
* NOTE: It is a requirement that up_restorefpu() preserve the value of
* r0!
*/
@@ -468,7 +468,7 @@ exception_common:
.global g_intstackbase
.align 8
g_intstackalloc:
.skip (CONFIG_ARCH_INTERRUPTSTACK & ~7)
.skip ((CONFIG_ARCH_INTERRUPTSTACK + 4) & ~7)
g_intstackbase:
.size g_intstackalloc, .-g_intstackalloc
#endif
arch/arm/src/sam34/sam_irq.c
-10
View File
@@ -385,16 +385,6 @@ void up_irqinitialize(void)
putreg32(0, regaddr);
}
/* Colorize the interrupt stack for debug purposes */
#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3
{
size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~3);
up_stack_color((FAR void *)((uintptr_t)&g_intstackbase - intstack_size),
intstack_size);
}
#endif
/* Make sure that we are using the correct vector table. The default
* vector address is 0x0000:0000 but if we are executing code that is
* positioned in SRAM or in external FLASH, then we may need to reset
arch/arm/src/sam34/sam_vectors.S
+2 -2
View File
@@ -362,7 +362,7 @@ exception_common:
*
* Here:
* r0 = Address of the register save area
*
* NOTE: It is a requirement that up_restorefpu() preserve the value of
* r0!
*/
@@ -482,7 +482,7 @@ exception_common:
.global g_intstackbase
.align 8
g_intstackalloc:
.skip (CONFIG_ARCH_INTERRUPTSTACK & ~7)
.skip ((CONFIG_ARCH_INTERRUPTSTACK + 4) & ~7)
g_intstackbase:
.size g_intstackalloc, .-g_intstackalloc
#endif
arch/arm/src/sama5/sam_irq.c
-10
View File
@@ -431,16 +431,6 @@ void up_irqinitialize(void)
* access to the AIC.
*/
/* Colorize the interrupt stack for debug purposes */
#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3
{
size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~3);
up_stack_color((FAR void *)((uintptr_t)&g_intstackbase - intstack_size),
intstack_size);
}
#endif
/* Redirect all interrupts to the AIC if so configured */
sam_aic_redirection();
arch/arm/src/samv7/sam_irq.c
-10
View File
@@ -381,16 +381,6 @@ void up_irqinitialize(void)
putreg32(0, regaddr);
}
/* Colorize the interrupt stack for debug purposes */
#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3
{
size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~3);
up_stack_color((FAR void *)((uintptr_t)&g_intstackbase - intstack_size),
intstack_size);
}
#endif
/* Make sure that we are using the correct vector table. The default
* vector address is 0x0000:0000 but if we are executing code that is
* positioned in SRAM or in external FLASH, then we may need to reset
arch/arm/src/stm32/chip/stm32f33xxx_adc.h
+9 -9
View File
@@ -49,13 +49,13 @@
* Pre-processor Definitions
****************************************************************************************************/
#define STM32_ADC1_BASE_OFFSET 0x0000
#define STM32_ADC2_BASE_OFFSET 0x0100
#define STM32_ADC12_BASE_OFFSET 0x0300
#define STM32_ADC1_OFFSET 0x0000
#define STM32_ADC2_OFFSET 0x0100
#define STM32_ADC12_CMN_OFFSET 0x0300
#define STM32_ADC1_BASE (STM32_ADC1_BASE_OFFSET+STM32_ADC12_BASE) /* ADC1 Master ADC */
#define STM32_ADC2_BASE (STM32_ADC1_BASE_OFFSET+STM32_ADC12_BASE) /* ADC2 Slave ADC */
#define STM32_ADC12_BASE (STM32_ADC1_BASE_OFFSET+STM32_ADC12_BASE) /* ADC1, ADC2 common */
#define STM32_ADC1_BASE (STM32_ADC1_OFFSET+STM32_ADC12_BASE) /* ADC1 Master ADC */
#define STM32_ADC2_BASE (STM32_ADC2_OFFSET+STM32_ADC12_BASE) /* ADC2 Slave ADC */
#define STM32_ADC12_CMN_BASE (STM32_ADC12_CMN_OFFSET+STM32_ADC12_BASE) /* ADC1, ADC2 common */
/* Register Offsets *********************************************************************************/
@@ -151,9 +151,9 @@
#define STM32_ADC2_DIFSEL (STM32_ADC2_BASE+STM32_ADC_DIFSEL_OFFSET)
#define STM32_ADC2_CALFACT (STM32_ADC2_BASE+STM32_ADC_CALFACT_OFFSET)
#define STM32_ADC12_CSR (STM32_ADC12_BASE+STM32_ADC_CSR_OFFSET)
#define STM32_ADC12_CCR (STM32_ADC12_BASE+STM32_ADC_CCR_OFFSET)
#define STM32_ADC12_CDR (STM32_ADC12_BASE+STM32_ADC_CDR_OFFSET)
#define STM32_ADC12_CSR (STM32_ADC12_CMN_BASE+STM32_ADC_CSR_OFFSET)
#define STM32_ADC12_CCR (STM32_ADC12_CMN_BASE+STM32_ADC_CCR_OFFSET)
#define STM32_ADC12_CDR (STM32_ADC12_CMN_BASE+STM32_ADC_CDR_OFFSET)
/* Register Bitfield Definitions ********************************************************************/
/* ADC interrupt and status register (ISR) and ADC interrupt enable register (IER) */
arch/arm/src/stm32/gnu/stm32_vectors.S
+1 -1
View File
@@ -497,7 +497,7 @@ exception_common:
.global g_intstackbase
.align 8
g_intstackalloc:
.skip (CONFIG_ARCH_INTERRUPTSTACK & ~7)
.skip ((CONFIG_ARCH_INTERRUPTSTACK + 4) & ~7)
g_intstackbase:
.size g_intstackalloc, .-g_intstackalloc
#endif
arch/arm/src/stm32/iar/stm32_vectors.S
+1 -1
View File
@@ -1055,7 +1055,7 @@ l5:
.global g_intstackbase
.align 8
g_intstackalloc:
.skip (CONFIG_ARCH_INTERRUPTSTACK & ~7)
.skip ((CONFIG_ARCH_INTERRUPTSTACK + 4) & ~7)
g_intstackbase:
.size g_intstackalloc, .-g_intstackalloc
#endif
arch/arm/src/stm32/stm32_i2c.c
+4 -4
View File
@@ -729,6 +729,10 @@ static inline void stm32_i2c_sem_waitstop(FAR struct stm32_i2c_priv_s *priv)
start = clock_systimer();
do
{
/* Calculate the elapsed time */
elapsed = clock_systimer() - start;
/* Check for STOP condition */
cr1 = stm32_i2c_getreg(priv, STM32_I2C_CR1_OFFSET);
@@ -744,10 +748,6 @@ static inline void stm32_i2c_sem_waitstop(FAR struct stm32_i2c_priv_s *priv)
{
return;
}
/* Calculate the elapsed time */
elapsed = clock_systimer() - start;
}
/* Loop until the stop is complete or a timeout occurs. */
arch/arm/src/stm32/stm32_i2c_alt.c
+4 -4
View File
@@ -737,6 +737,10 @@ static inline void stm32_i2c_sem_waitstop(FAR struct stm32_i2c_priv_s *priv)
start = clock_systimer();
do
{
/* Calculate the elapsed time */
elapsed = clock_systimer() - start;
/* Check for STOP condition */
cr1 = stm32_i2c_getreg(priv, STM32_I2C_CR1_OFFSET);
@@ -752,10 +756,6 @@ static inline void stm32_i2c_sem_waitstop(FAR struct stm32_i2c_priv_s *priv)
{
return;
}
/* Calculate the elapsed time */
elapsed = clock_systimer() - start;
}
/* Loop until the stop is complete or a timeout occurs. */
arch/arm/src/stm32/stm32_irq.c
-10
View File
@@ -310,16 +310,6 @@ void up_irqinitialize(void)
putreg32(0xffffffff, NVIC_IRQ_CLEAR(i));
}
/* Colorize the interrupt stack for debug purposes */
#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3
{
size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~3);
up_stack_color((FAR void *)((uintptr_t)&g_intstackbase - intstack_size),
intstack_size);
}
#endif
/* The standard location for the vector table is at the beginning of FLASH
* at address 0x0800:0000. If we are using the STMicro DFU bootloader, then
* the vector table will be offset to a different location in FLASH and we
arch/arm/src/stm32/stm32_otgfshost.c
+54
View File
@@ -212,6 +212,7 @@ struct stm32_chan_s
uint8_t eptype; /* See OTGFS_EPTYPE_* definitions */
uint8_t funcaddr; /* Device function address */
uint8_t speed; /* Device speed */
uint8_t interval; /* Interrupt/isochronous EP polling interval */
uint8_t pid; /* Data PID */
uint8_t npackets; /* Number of packets (for data toggle) */
bool inuse; /* True: This channel is "in use" */
@@ -1210,6 +1211,7 @@ static int stm32_ctrlchan_alloc(FAR struct stm32_usbhost_s *priv,
chan->eptype = OTGFS_EPTYPE_CTRL;
chan->funcaddr = funcaddr;
chan->speed = speed;
chan->interval = 0;
chan->maxpacket = STM32_EP0_DEF_PACKET_SIZE;
chan->indata1 = false;
chan->outdata1 = false;
@@ -1234,6 +1236,7 @@ static int stm32_ctrlchan_alloc(FAR struct stm32_usbhost_s *priv,
chan->eptype = OTGFS_EPTYPE_CTRL;
chan->funcaddr = funcaddr;
chan->speed = speed;
chan->interval = 0;
chan->maxpacket = STM32_EP0_DEF_PACKET_SIZE;
chan->indata1 = false;
chan->outdata1 = false;
@@ -1363,6 +1366,7 @@ static int stm32_xfrep_alloc(FAR struct stm32_usbhost_s *priv,
chan->eptype = epdesc->xfrtype;
chan->funcaddr = hport->funcaddr;
chan->speed = hport->speed;
chan->interval = epdesc->interval;
chan->maxpacket = epdesc->mxpacketsize;
chan->indata1 = false;
chan->outdata1 = false;
@@ -1893,6 +1897,8 @@ static ssize_t stm32_in_transfer(FAR struct stm32_usbhost_s *priv, int chidx,
}
else
{
useconds_t delay;
/* Get the elapsed time. Has the timeout elapsed?
* if not then try again.
*/
@@ -1906,6 +1912,54 @@ static ssize_t stm32_in_transfer(FAR struct stm32_usbhost_s *priv, int chidx,
return (ssize_t)ret;
}
/* Wait a bit before retrying after a NAK. */
if (chan->eptype == OTGFS_HCCHAR_EPTYP_INTR)
{
/* For interrupt (and isochronous) endpoints, the
* polling rate is determined by the bInterval field
* of the endpoint descriptor (in units of frames
* which we treat as milliseconds here).
*/
if (chan->interval > 0)
{
/* Convert the delay to units of microseconds */
delay = (useconds_t)chan->interval * 1000;
}
else
{
/* Out of range! For interrupt endpoints, the valid
* range is 1-255 frames. Assume one frame.
*/
delay = 1000;
}
}
else
{
/* For Isochronous endpoints, bInterval must be 1. Bulk
* endpoints do not have a polling interval. Rather,
* the should wait until data is received.
*
* REVISIT: For bulk endpoints this 1 msec delay is only
* intended to give the CPU a break from the bulk EP tight
* polling loop. But are there performance issues?
*/
delay = 1000;
}
/* Wait for the next polling interval.
*
* REVISIT: This delay could require more resolution than
* is provided by the system timer. In that case, the
* delay could be significantly longer than required.
*/
usleep(delay);
}
}
else
arch/arm/src/stm32/stm32_otghsdev.c
+5 -3
View File
@@ -5319,20 +5319,22 @@ static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv)
stm32_putreg(0xbfffffff, STM32_OTGHS_GINTSTS);
#ifndef BOARD_ENABLE_USBOTG_HSULPI
/* Disable the ULPI Clock enable in RCC AHB1 Register. This must
* be done because if both the ULPI and the FS PHY clock enable bits
* are set at the same time, the ARM never awakens from WFI due to
* some bug / errata in the chip.
*/
regval = stm32_getreg(STM32_RCC_AHB1LPENR);
regval = stm32_getreg(STM32_RCC_AHB1LPENR);
regval &= ~RCC_AHB1ENR_OTGHSULPIEN;
stm32_putreg(regval, STM32_RCC_AHB1LPENR);
#endif
/* Enable the interrupts in the INTMSK */
regval = (OTGHS_GINT_RXFLVL | OTGHS_GINT_USBSUSP | OTGHS_GINT_ENUMDNE |
OTGHS_GINT_IEP | OTGHS_GINT_OEP | OTGHS_GINT_USBRST);
regval = (OTGHS_GINT_RXFLVL | OTGHS_GINT_USBSUSP | OTGHS_GINT_ENUMDNE |
OTGHS_GINT_IEP | OTGHS_GINT_OEP | OTGHS_GINT_USBRST);
#ifdef CONFIG_USBDEV_ISOCHRONOUS
regval |= (OTGHS_GINT_IISOIXFR | OTGHS_GINT_IISOOXFR);
arch/arm/src/stm32/stm32_otghshost.c
+54
View File
@@ -217,6 +217,7 @@ struct stm32_chan_s
uint8_t eptype; /* See OTGHS_EPTYPE_* definitions */
uint8_t funcaddr; /* Device function address */
uint8_t speed; /* Device speed */
uint8_t interval; /* Interrupt/isochronous EP polling interval */
uint8_t pid; /* Data PID */
uint8_t npackets; /* Number of packets (for data toggle) */
bool inuse; /* True: This channel is "in use" */
@@ -1215,6 +1216,7 @@ static int stm32_ctrlchan_alloc(FAR struct stm32_usbhost_s *priv,
chan->eptype = OTGHS_EPTYPE_CTRL;
chan->funcaddr = funcaddr;
chan->speed = speed;
chan->interval = 0;
chan->maxpacket = STM32_EP0_DEF_PACKET_SIZE;
chan->indata1 = false;
chan->outdata1 = false;
@@ -1239,6 +1241,7 @@ static int stm32_ctrlchan_alloc(FAR struct stm32_usbhost_s *priv,
chan->eptype = OTGHS_EPTYPE_CTRL;
chan->funcaddr = funcaddr;
chan->speed = speed;
chan->interval = 0;
chan->maxpacket = STM32_EP0_DEF_PACKET_SIZE;
chan->indata1 = false;
chan->outdata1 = false;
@@ -1368,6 +1371,7 @@ static int stm32_xfrep_alloc(FAR struct stm32_usbhost_s *priv,
chan->eptype = epdesc->xfrtype;
chan->funcaddr = hport->funcaddr;
chan->speed = hport->speed;
chan->interval = epdesc->interval;
chan->maxpacket = epdesc->mxpacketsize;
chan->indata1 = false;
chan->outdata1 = false;
@@ -1898,6 +1902,8 @@ static ssize_t stm32_in_transfer(FAR struct stm32_usbhost_s *priv, int chidx,
}
else
{
useconds_t delay;
/* Get the elapsed time. Has the timeout elapsed?
* if not then try again.
*/
@@ -1911,6 +1917,54 @@ static ssize_t stm32_in_transfer(FAR struct stm32_usbhost_s *priv, int chidx,
return (ssize_t)ret;
}
/* Wait a bit before retrying after a NAK. */
if (chan->eptype == OTGFS_HCCHAR_EPTYP_INTR)
{
/* For interrupt (and isochronous) endpoints, the
* polling rate is determined by the bInterval field
* of the endpoint descriptor (in units of frames
* which we treat as milliseconds here).
*/
if (chan->interval > 0)
{
/* Convert the delay to units of microseconds */
delay = (useconds_t)chan->interval * 1000;
}
else
{
/* Out of range! For interrupt endpoints, the valid
* range is 1-255 frames. Assume one frame.
*/
delay = 1000;
}
}
else
{
/* For Isochronous endpoints, bInterval must be 1. Bulk
* endpoints do not have a polling interval. Rather,
* the should wait until data is received.
*
* REVISIT: For bulk endpoints this 1 msec delay is only
* intended to give the CPU a break from the bulk EP tight
* polling loop. But are there performance issues?
*/
delay = 1000;
}
/* Wait for the next polling interval.
*
* REVISIT: This delay could require more resolution than
* is provided by the system timer. In that case, the
* delay could be significantly longer than required.
*/
usleep(delay);
}
}
else
arch/arm/src/stm32/stm32f20xxx_rcc.c
+7 -1
View File
@@ -193,10 +193,16 @@ static inline void rcc_enableahb1(void)
#endif
#ifdef CONFIG_STM32_OTGHS
/* USB OTG HS */
#ifdef BOARD_ENABLE_USBOTG_HSULPI
/* Enable clocking for USB OTG HS and external PHY */
regval |= (RCC_AHB1ENR_OTGHSEN | RCC_AHB1ENR_OTGHSULPIEN);
#else
/* Enable only clocking for USB OTG HS */
regval |= (RCC_AHB1ENR_OTGHSEN);
#endif
#endif /* CONFIG_STM32_OTGHS */
putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */
}
arch/arm/src/stm32/stm32f30xxx_i2c.c
+4 -3
View File
@@ -844,6 +844,10 @@ static inline void stm32_i2c_sem_waitstop(FAR struct stm32_i2c_priv_s *priv)
start = clock_systimer();
do
{
/* Calculate the elapsed time */
elapsed = clock_systimer() - start;
/* Check for STOP condition */
cr = stm32_i2c_getreg32(priv, STM32_I2C_CR2_OFFSET);
@@ -860,9 +864,6 @@ static inline void stm32_i2c_sem_waitstop(FAR struct stm32_i2c_priv_s *priv)
return;
}
/* Calculate the elapsed time */
elapsed = clock_systimer() - start;
}
/* Loop until the stop is complete or a timeout occurs. */
arch/arm/src/stm32/stm32f40xxx_i2c.c
+4 -3
View File
@@ -731,6 +731,10 @@ static inline void stm32_i2c_sem_waitstop(FAR struct stm32_i2c_priv_s *priv)
start = clock_systimer();
do
{
/* Calculate the elapsed time */
elapsed = clock_systimer() - start;
/* Check for STOP condition */
cr1 = stm32_i2c_getreg(priv, STM32_I2C_CR1_OFFSET);
@@ -747,9 +751,6 @@ static inline void stm32_i2c_sem_waitstop(FAR struct stm32_i2c_priv_s *priv)
return;
}
/* Calculate the elapsed time */
elapsed = clock_systimer() - start;
}
/* Loop until the stop is complete or a timeout occurs. */
arch/arm/src/stm32/stm32f40xxx_rcc.c
+7 -2
View File
@@ -215,10 +215,15 @@ static inline void rcc_enableahb1(void)
#endif
#ifdef CONFIG_STM32_OTGHS
/* USB OTG HS */
#ifdef BOARD_ENABLE_USBOTG_HSULPI
/* Enable clocking for USB OTG HS and external PHY */
regval |= (RCC_AHB1ENR_OTGHSEN | RCC_AHB1ENR_OTGHSULPIEN);
#else
/* Enable only clocking for USB OTG HS */
regval |= RCC_AHB1ENR_OTGHSEN;
#endif
#endif /* CONFIG_STM32_OTGHS */
#ifdef CONFIG_STM32_DMA2D
arch/arm/src/stm32f7/stm32_i2c.c
+5 -4
View File
@@ -7,7 +7,7 @@
*
* With extensions and modifications for the F1, F2, and F4 by:
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Copyright (C) 2016-2017 Gregory Nutt. All rights reserved.
* Authors: Gregroy Nutt <gnutt@nuttx.org>
* John Wharington
* David Sidrane <david_s5@nscdg.com>
@@ -1034,6 +1034,10 @@ static inline void stm32_i2c_sem_waitstop(FAR struct stm32_i2c_priv_s *priv)
start = clock_systimer();
do
{
/* Calculate the elapsed time */
elapsed = clock_systimer() - start;
/* Check for STOP condition */
cr = stm32_i2c_getreg32(priv, STM32_I2C_CR2_OFFSET);
@@ -1050,9 +1054,6 @@ static inline void stm32_i2c_sem_waitstop(FAR struct stm32_i2c_priv_s *priv)
return;
}
/* Calculate the elapsed time */
elapsed = clock_systimer() - start;
}
/* Loop until the stop is complete or a timeout occurs. */
arch/arm/src/stm32f7/stm32_irq.c
-10
View File
@@ -415,16 +415,6 @@ void up_irqinitialize(void)
putreg32(0, regaddr);
}
/* Colorize the interrupt stack for debug purposes */
#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3
{
size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~3);
up_stack_color((FAR void *)((uintptr_t)&g_intstackbase - intstack_size),
intstack_size);
}
#endif
/* Make sure that we are using the correct vector table. The default
* vector address is 0x0000:0000 but if we are executing code that is
* positioned in SRAM or in external FLASH, then we may need to reset
arch/arm/src/stm32f7/stm32_otgdev.c
+1 -1
View File
@@ -5446,7 +5446,7 @@ static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv)
regval &= OTG_GINT_RESERVED;
stm32_putreg(regval | OTG_GINT_RC_W1, STM32_OTG_GINTSTS);
#if defined(CONFIG_STM32F7_OTGHS)
#if defined(CONFIG_STM32F7_OTGHS) && !defined(BOARD_ENABLE_USBOTG_HSULPI)
/* Disable the ULPI Clock enable in RCC AHB1 Register. This must
* be done because if both the ULPI and the FS PHY clock enable bits
* are set at the same time, the ARM never awakens from WFI due to
arch/arm/src/stm32f7/stm32_otghost.c
+54
View File
@@ -214,6 +214,7 @@ struct stm32_chan_s
uint8_t eptype; /* See OTG_EPTYPE_* definitions */
uint8_t funcaddr; /* Device function address */
uint8_t speed; /* Device speed */
uint8_t interval; /* Interrupt/isochronous EP polling interval */
uint8_t pid; /* Data PID */
uint8_t npackets; /* Number of packets (for data toggle) */
bool inuse; /* True: This channel is "in use" */
@@ -1209,6 +1210,7 @@ static int stm32_ctrlchan_alloc(FAR struct stm32_usbhost_s *priv,
chan->eptype = OTG_EPTYPE_CTRL;
chan->funcaddr = funcaddr;
chan->speed = speed;
chan->interval = 0;
chan->maxpacket = STM32_EP0_DEF_PACKET_SIZE;
chan->indata1 = false;
chan->outdata1 = false;
@@ -1233,6 +1235,7 @@ static int stm32_ctrlchan_alloc(FAR struct stm32_usbhost_s *priv,
chan->eptype = OTG_EPTYPE_CTRL;
chan->funcaddr = funcaddr;
chan->speed = speed;
chan->interval = 0;
chan->maxpacket = STM32_EP0_DEF_PACKET_SIZE;
chan->indata1 = false;
chan->outdata1 = false;
@@ -1362,6 +1365,7 @@ static int stm32_xfrep_alloc(FAR struct stm32_usbhost_s *priv,
chan->eptype = epdesc->xfrtype;
chan->funcaddr = hport->funcaddr;
chan->speed = hport->speed;
chan->interval = epdesc->interval;
chan->maxpacket = epdesc->mxpacketsize;
chan->indata1 = false;
chan->outdata1 = false;
@@ -1892,6 +1896,8 @@ static ssize_t stm32_in_transfer(FAR struct stm32_usbhost_s *priv, int chidx,
}
else
{
useconds_t delay;
/* Get the elapsed time. Has the timeout elapsed?
* if not then try again.
*/
@@ -1905,6 +1911,54 @@ static ssize_t stm32_in_transfer(FAR struct stm32_usbhost_s *priv, int chidx,
return (ssize_t)ret;
}
/* Wait a bit before retrying after a NAK. */
if (chan->eptype == OTGFS_HCCHAR_EPTYP_INTR)
{
/* For interrupt (and isochronous) endpoints, the
* polling rate is determined by the bInterval field
* of the endpoint descriptor (in units of frames
* which we treat as milliseconds here).
*/
if (chan->interval > 0)
{
/* Convert the delay to units of microseconds */
delay = (useconds_t)chan->interval * 1000;
}
else
{
/* Out of range! For interrupt endpoints, the valid
* range is 1-255 frames. Assume one frame.
*/
delay = 1000;
}
}
else
{
/* For Isochronous endpoints, bInterval must be 1. Bulk
* endpoints do not have a polling interval. Rather,
* the should wait until data is received.
*
* REVISIT: For bulk endpoints this 1 msec delay is only
* intended to give the CPU a break from the bulk EP tight
* polling loop. But are there performance issues?
*/
delay = 1000;
}
/* Wait for the next polling interval.
*
* REVISIT: This delay could require more resolution than
* is provided by the system timer. In that case, the
* delay could be significantly longer than required.
*/
usleep(delay);
}
}
else
arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c
+7 -2
View File
@@ -225,10 +225,15 @@ static inline void rcc_enableahb1(void)
#endif
#ifdef CONFIG_STM32F7_OTGHS
/* USB OTG HS */
#ifdef BOARD_ENABLE_USBOTG_HSULPI
/* Enable clocking for USB OTG HS and external PHY */
regval |= (RCC_AHB1ENR_OTGHSEN | RCC_AHB1ENR_OTGHSULPIEN);
#else
/* Enable only clocking for USB OTG HS */
regval |= RCC_AHB1ENR_OTGHSEN;
#endif
#endif /* CONFIG_STM32F7_OTGHS */
putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */
arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c
+7 -2
View File
@@ -221,10 +221,15 @@ static inline void rcc_enableahb1(void)
#endif
#ifdef CONFIG_STM32F7_OTGHS
/* USB OTG HS */
#ifdef BOARD_ENABLE_USBOTG_HSULPI
/* Enable clocking for USB OTG HS and external PHY */
regval |= (RCC_AHB1ENR_OTGHSEN | RCC_AHB1ENR_OTGHSULPIEN);
#else
/* Enable only clocking for USB OTG HS */
regval |= RCC_AHB1ENR_OTGHSEN;
#endif
#endif /* CONFIG_STM32F7_OTGHS */
putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */
arch/arm/src/stm32l4/stm32l4_i2c.c
+4 -3
View File
@@ -788,6 +788,10 @@ static inline void stm32l4_i2c_sem_waitstop(FAR struct stm32l4_i2c_priv_s *priv)
start = clock_systimer();
do
{
/* Calculate the elapsed time */
elapsed = clock_systimer() - start;
/* Check for STOP condition */
cr = stm32l4_i2c_getreg32(priv, STM32L4_I2C_CR2_OFFSET);
@@ -804,9 +808,6 @@ static inline void stm32l4_i2c_sem_waitstop(FAR struct stm32l4_i2c_priv_s *priv)
return;
}
/* Calculate the elapsed time */
elapsed = clock_systimer() - start;
}
/* Loop until the stop is complete or a timeout occurs. */
arch/arm/src/stm32l4/stm32l4_irq.c
-10
View File
@@ -304,16 +304,6 @@ void up_irqinitialize(void)
putreg32(0xffffffff, NVIC_IRQ_CLEAR(i));
}
/* Colorize the interrupt stack for debug purposes */
#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3
{
size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~3);
up_stack_color((FAR void *)((uintptr_t)&g_intstackbase - intstack_size),
intstack_size);
}
#endif
/* The standard location for the vector table is at the beginning of FLASH
* at address 0x0800:0000. If we are using the STMicro DFU bootloader, then
* the vector table will be offset to a different location in FLASH and we
arch/arm/src/stm32l4/stm32l4_otgfshost.c
+54
View File
@@ -213,6 +213,7 @@ struct stm32l4_chan_s
uint8_t eptype; /* See OTGFS_EPTYPE_* definitions */
uint8_t funcaddr; /* Device function address */
uint8_t speed; /* Device speed */
uint8_t interval; /* Interrupt/isochronous EP polling interval */
uint8_t pid; /* Data PID */
uint8_t npackets; /* Number of packets (for data toggle) */
bool inuse; /* True: This channel is "in use" */
@@ -1212,6 +1213,7 @@ static int stm32l4_ctrlchan_alloc(FAR struct stm32l4_usbhost_s *priv,
chan->eptype = OTGFS_EPTYPE_CTRL;
chan->funcaddr = funcaddr;
chan->speed = speed;
chan->interval = 0;
chan->maxpacket = STM32L4_EP0_DEF_PACKET_SIZE;
chan->indata1 = false;
chan->outdata1 = false;
@@ -1236,6 +1238,7 @@ static int stm32l4_ctrlchan_alloc(FAR struct stm32l4_usbhost_s *priv,
chan->eptype = OTGFS_EPTYPE_CTRL;
chan->funcaddr = funcaddr;
chan->speed = speed;
chan->interval = 0;
chan->maxpacket = STM32L4_EP0_DEF_PACKET_SIZE;
chan->indata1 = false;
chan->outdata1 = false;
@@ -1365,6 +1368,7 @@ static int stm32l4_xfrep_alloc(FAR struct stm32l4_usbhost_s *priv,
chan->eptype = epdesc->xfrtype;
chan->funcaddr = hport->funcaddr;
chan->speed = hport->speed;
chan->interval = epdesc->interval;
chan->maxpacket = epdesc->mxpacketsize;
chan->indata1 = false;
chan->outdata1 = false;
@@ -1897,6 +1901,8 @@ static ssize_t stm32l4_in_transfer(FAR struct stm32l4_usbhost_s *priv,
}
else
{
useconds_t delay;
/* Get the elapsed time. Has the timeout elapsed?
* if not then try again.
*/
@@ -1910,6 +1916,54 @@ static ssize_t stm32l4_in_transfer(FAR struct stm32l4_usbhost_s *priv,
return (ssize_t)ret;
}
/* Wait a bit before retrying after a NAK. */
if (chan->eptype == OTGFS_HCCHAR_EPTYP_INTR)
{
/* For interrupt (and isochronous) endpoints, the
* polling rate is determined by the bInterval field
* of the endpoint descriptor (in units of frames
* which we treat as milliseconds here).
*/
if (chan->interval > 0)
{
/* Convert the delay to units of microseconds */
delay = (useconds_t)chan->interval * 1000;
}
else
{
/* Out of range! For interrupt endpoints, the valid
* range is 1-255 frames. Assume one frame.
*/
delay = 1000;
}
}
else
{
/* For Isochronous endpoints, bInterval must be 1. Bulk
* endpoints do not have a polling interval. Rather,
* the should wait until data is received.
*
* REVISIT: For bulk endpoints this 1 msec delay is only
* intended to give the CPU a break from the bulk EP tight
* polling loop. But are there performance issues?
*/
delay = 1000;
}
/* Wait for the next polling interval.
*
* REVISIT: This delay could require more resolution than
* is provided by the system timer. In that case, the
* delay could be significantly longer than required.
*/
usleep(delay);
}
}
else
arch/arm/src/tiva/tiva_vectors.S
+2 -2
View File
@@ -339,7 +339,7 @@ exception_common:
*
* Here:
* r0 = Address of the register save area
*
* NOTE: It is a requirement that up_restorefpu() preserve the value of
* r0!
*/
@@ -459,7 +459,7 @@ exception_common:
.global g_intstackbase
.align 8
g_intstackalloc:
.skip (CONFIG_ARCH_INTERRUPTSTACK & ~7)
.skip ((CONFIG_ARCH_INTERRUPTSTACK + 4) & ~7)
g_intstackbase:
.size g_intstackalloc, .-g_intstackalloc
#endif
arch/arm/src/tms570/tms570_irq.c
-8
View File
@@ -115,14 +115,6 @@ void up_irqinitialize(void)
FAR uintptr_t *vimram;
int i;
/* Colorize the interrupt stack for debug purposes */
#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3
size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~3);
up_stack_color((FAR void *)((uintptr_t)&g_intstackbase - intstack_size),
intstack_size);
#endif
/* Initialize VIM RAM vectors. These vectors are not used in the current
* interrupt handler logic.
*/
configs/Kconfig
+15
View File
@@ -956,6 +956,17 @@ config ARCH_BOARD_SPARK
(http://www.spark.io). This board features the STM32103CBT6
MCU from STMicro.
config ARCH_BOARD_PHOTON
bool "Photon wifi board"
depends on ARCH_CHIP_STM32F205RG
select ARCH_HAVE_LEDS
select ARCH_HAVE_BUTTONS
select ARCH_HAVE_IRQBUTTONS
---help---
A configuration for the Photon from Particle Devices
(https://www.particle.io). This board features the STM32F205RGY6
MCU from STMicro.
config ARCH_BOARD_STM32_BUTTERFLY2
bool "Kamami STM32Butterfly2 development board"
depends on ARCH_CHIP_STM32F107VC
@@ -1489,6 +1500,7 @@ config ARCH_BOARD
default "shenzhou" if ARCH_BOARD_SHENZHOU
default "skp16c26" if ARCH_BOARD_SKP16C26
default "spark" if ARCH_BOARD_SPARK
default "photon" if ARCH_BOARD_PHOTON
default "stm32butterfly2" if ARCH_BOARD_STM32_BUTTERFLY2
default "stm32_tiny" if ARCH_BOARD_STM32_TINY
default "stm32f103-minimum" if ARCH_BOARD_STM32F103_MINIMUM
@@ -1837,6 +1849,9 @@ endif
if ARCH_BOARD_SPARK
source "configs/spark/Kconfig"
endif
if ARCH_BOARD_PHOTON
source "configs/photon/Kconfig"
endif
if ARCH_BOARD_STM32_BUTTERFLY2
source "configs/stm32butterfly2/Kconfig"
endif

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