SAM4E: Add vector definition header files

ChangeLog

@@ -6641,4 +6641,6 @@
 	  fs/Kconfig and in apps/.  It turns out this this is not very useful
 	  if you are modifying existing configurations because then the
 	  defaults do not apply (2014-2-20).
+	* arch/arm/src/sam34/chip/sam4e_vectors.h:  Add vector definitions
+	  for the SAM4E (2014-2-21).
 

arch/arm/include/sam34/sam4e_irq.h

@@ -1,7 +1,7 @@
 /****************************************************************************************
  * arch/arm/include/sam34/sam4e_irq.h
  *
- *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -90,9 +90,11 @@
 #define SAM_PID_CAN0          (37)  /* CAN0 */
 #define SAM_PID_CAN1          (38)  /* CAN1 */
 #define SAM_PID_AES           (39)  /* AES */
+                                    /* 40-43: Reserved
 #define SAM_PID_EMAC          (44)  /* EMAC */
 #define SAM_PID_UART1         (45)  /* UART */
-#define NR_PIDS               (46)   /* Number of peripheral identifiers */
+                                    /* 46: Reserved */
+#define NR_PIDS               (47)  /* Number of peripheral identifiers */
 
 /* External interrupts (priority levels >= 256*/
 
@@ -106,6 +108,7 @@
 #define SAM_IRQ_UART0         (SAM_IRQ_EXTINT+SAM_PID_UART0)  /* Universal Asynchronous Receiver Transmitter 0 */
 #define SAM_IRQ_PIOA          (SAM_IRQ_EXTINT+SAM_PID_PIOA)   /* Parallel I/O Controller A */
 #define SAM_IRQ_PIOB          (SAM_IRQ_EXTINT+SAM_PID_PIOB)   /* Parallel I/O Controller B */
+
 #define SAM_IRQ_PIOC          (SAM_IRQ_EXTINT+SAM_PID_PIOC)   /* Parallel I/O Controller C */
 #define SAM_IRQ_PIOD          (SAM_IRQ_EXTINT+SAM_PID_PIOD)   /* Parallel I/O Controller D */
 #define SAM_IRQ_PIOE          (SAM_IRQ_EXTINT+SAM_PID_PIOE)   /* Parallel I/O Controller E */
@@ -136,7 +139,8 @@
 #define SAM_IRQ_CAN1          (SAM_IRQ_EXTINT+SAM_PID_CAN1)   /* CAN1 */
 #define SAM_IRQ_AES           (SAM_IRQ_EXTINT+SAM_PID_AES)    /* AES */
 #define SAM_IRQ_EMAC          (SAM_IRQ_EXTINT+SAM_PID_EMAC)   /* EMAC */
-#define SAM_IRQ_UART1         (SAM_IRQ_EXTINT+SAM_PID_UART1)  /* UART */
+#define SAM_IRQ_UART1         (SAM_IRQ_EXTINT+SAM_PID_UART1)  /* UART1 */
+
 #define SAM_IRQ_NEXTINT       NR_PIDS                         /* Total number of external interrupt numbers */
 #define SAM_IRQ_NIRQS         (SAM_IRQ_EXTINT+NR_PIDS)        /* The number of real IRQs */
 

arch/arm/src/sam34/Make.defs

@@ -85,7 +85,7 @@ CHIP_CSRCS += sam_serial.c sam_start.c sam_timerisr.c
 ifeq ($(CONFIG_ARCH_CHIP_SAM4L),y)
 CHIP_CSRCS += sam4l_clockconfig.c sam4l_periphclks.c sam4l_gpio.c
 else
-CHIP_CSRCS += sam3u_clockconfig.c sam3u_gpio.c
+CHIP_CSRCS += sam_clockconfig.c sam_gpio.c
 endif
 
 ifeq ($(CONFIG_NUTTX_KERNEL),y)

arch/arm/src/sam34/chip.h

@@ -1,7 +1,7 @@
 /************************************************************************************
  * arch/arm/src/sam34/chip.h
  *
- *   Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2009-2010, 2013-2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -58,6 +58,8 @@
 #    include "chip/sam3u_vectors.h"
 #  elif defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
 #    include "chip/sam3x_vectors.h"
+#  elif defined(CONFIG_ARCH_CHIP_SAM4E)
+#    include "chip/sam4e_vectors.h"
 #  elif defined(CONFIG_ARCH_CHIP_SAM4L)
 #    include "chip/sam4l_vectors.h"
 #  elif defined(CONFIG_ARCH_CHIP_SAM4S)

arch/arm/src/sam34/chip/sam4e_vectors.h

@@ -0,0 +1,103 @@
+/************************************************************************************************
+ * arch/arm/src/sam34/chip/sam4e_vectors.h
+ *
+ *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************************/
+
+/************************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************************/
+/* This file is included by sam_vectors.S.  It provides the macro VECTOR that supplies each SAM4E
+ * vector in terms of a (lower-case) ISR label and an (upper-case) IRQ number as defined in
+ * arch/arm/include/sam/sam3u_irq.h.  sam_vectors.S will defined the VECTOR in different ways in
+ * order to generate the interrupt vectors and handlers in their final form.
+ */
+
+/* If the common ARMv7-M vector handling is used, then all it needs is the following
+ * definition that provides the number of supported vectors.
+ */
+
+#ifdef CONFIG_ARMV7M_CMNVECTOR
+
+/* Reserve 35 interrupt table entries for I/O interrupts. */
+
+# define ARMV7M_PERIPHERAL_INTERRUPTS 47
+
+#else
+  VECTOR(sam_supc, SAM_IRQ_SUPC)      /* Vector 16+0:  Supply Controller */
+  VECTOR(sam_rstc, SAM_IRQ_RSTC)      /* Vector 16+1:  Reset Controller */
+  VECTOR(sam_rtc, SAM_IRQ_RTC)        /* Vector 16+2:  Real Time Clock */
+  VECTOR(sam_rtt, SAM_IRQ_RTT)        /* Vector 16+3:  Real Time Timer */
+  VECTOR(sam_wdt, SAM_IRQ_WDT)        /* Vector 16+4:  Watchdog Timer */
+  VECTOR(sam_pmc, SAM_IRQ_PMC)        /* Vector 16+5:  Power Management Controller */
+  VECTOR(sam_eefc, SAM_IRQ_EEFC)      /* Vector 16+6:  Enhanced Embedded Flash Controller */
+  VECTOR(sam_uart0, SAM_IRQ_UART0)    /* Vector 16+7:  Universal Asynchronous Receiver Transmitter 0 */
+  UNUSED(SAM_IRQ_RESERVED_8)          /* Vector 16+8:  Static Memory Controller (no vector) */
+  VECTOR(sam_pioa, SAM_IRQ_PIOA)      /* Vector 16+9:  Parallel I/O Controller A */
+  VECTOR(sam_piob, SAM_IRQ_PIOB)      /* Vector 16+10: Parallel I/O Controller B */
+  VECTOR(sam_pioc, SAM_IRQ_PIOC)      /* Vector 16+11: Parallel I/O Controller C */
+  VECTOR(sam_piod, SAM_IRQ_PIOD)      /* Vector 16+12: Parallel I/O Controller C */
+  VECTOR(sam_pioe, SAM_IRQ_PIOE)      /* Vector 16+13: Parallel I/O Controller C */
+  VECTOR(sam_usart0, SAM_IRQ_USART0)  /* Vector 16+14: USART 0 */
+  VECTOR(sam_usart1, SAM_IRQ_USART1)  /* Vector 16+15: USART 1 */
+  VECTOR(sam_hsmci, SAM_IRQ_HSMCI)    /* Vector 16+16: High Speed Multimedia Card Interface */
+  VECTOR(sam_twi0, SAM_IRQ_TWI0)      /* Vector 16+17: Two-Wire Interface 0 */
+  VECTOR(sam_twi1, SAM_IRQ_TWI1)      /* Vector 16+18: Two-Wire Interface 1 */
+  VECTOR(sam_spi0, SAM_IRQ_SPI0)      /* Vector 16+19: Serial Peripheral Interface */
+  VECTOR(sam_dmac, SAM_IRQ_DMAC)      /* Vector 16+20: DMA controller */
+  VECTOR(sam_tc0, SAM_IRQ_TC0)        /* Vector 16+21: Timer Counter 0 */
+  VECTOR(sam_tc1, SAM_IRQ_TC1)        /* Vector 16+22: Timer Counter 1 */
+  VECTOR(sam_tc2, SAM_IRQ_TC2)        /* Vector 16+23: Timer Counter 2 */
+  VECTOR(sam_tc3, SAM_IRQ_TC3)        /* Vector 16+24: Timer Counter 3 */
+  VECTOR(sam_tc4, SAM_IRQ_TC4)        /* Vector 16+25: Timer Counter 4 */
+  VECTOR(sam_tc5, SAM_IRQ_TC5)        /* Vector 16+26: Timer Counter 5 */
+  VECTOR(sam_tc5, SAM_IRQ_TC6)        /* Vector 16+27: Timer Counter 6 */
+  VECTOR(sam_tc5, SAM_IRQ_TC7)        /* Vector 16+28: Timer Counter 7 */
+  VECTOR(sam_tc5, SAM_IRQ_TC8)        /* Vector 16+29: Timer Counter 8 */
+  VECTOR(sam_afec0, SAM_IRQ_AFEC0)    /* Vector 16+30: Analog Front End 0 */
+  VECTOR(sam_afec1, SAM_IRQ_AFEC1)    /* Vector 16+31: Analog Front End 1 */
+  VECTOR(sam_dacc, SAM_IRQ_DACC)      /* Vector 16+32: Digital To Analog Converter */
+  VECTOR(sam_acc, SAM_IRQ_ACC)        /* Vector 16+33: Analog Comparator */
+  VECTOR(sam_arm, SAM_IRQ_ARM)        /* Vector 16+34: FPU signals: FPIXC, FPOFC, FPUFC, FPIOC, FPDZC,FPIDC, FPIXC */
+  VECTOR(sam_udp, SAM_IRQ_UDP)        /* Vector 16+35: USB Device Port */
+  VECTOR(sam_pwm, SAM_IRQ_PWM)        /* Vector 16+36: Pulse Width Modulation */
+  VECTOR(sam_can0, SAM_IRQ_CAN0)      /* Vector 16+37: CAN0 */
+  VECTOR(sam_can1, SAM_IRQ_CAN1)      /* Vector 16+38: CAN1 */
+  VECTOR(sam_aes, SAM_IRQ_AES)        /* Vector 16+39: AES */
+  UNUSED(SAM_IRQ_RESERVED_40)         /* Vector 16+40: Reserved */
+  UNUSED(SAM_IRQ_RESERVED_41)         /* Vector 16+41: Reserved */
+  UNUSED(SAM_IRQ_RESERVED_42)         /* Vector 16+42: Reserved */
+  UNUSED(SAM_IRQ_RESERVED_43)         /* Vector 16+43: Reserved */
+  VECTOR(sam_emac, SAM_IRQ_EMAC)      /* Vector 16+44: EMAC */
+  VECTOR(sam_uart1, SAM_IRQ_UART1)    /* Vector 16+45: UART1 */
+  UNUSED(SAM_IRQ_RESERVED_46)         /* Vector 16+46: Reserved */
+#endif

arch/arm/src/sam34/chip/sam4s_vectors.h

@@ -1,5 +1,5 @@
 /************************************************************************************************
- * arch/arm/src/sam34/chip/sam42_vectors.h
+ * arch/arm/src/sam34/chip/sam4s_vectors.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
@@ -37,7 +37,7 @@
  * Pre-processor Definitions
  ************************************************************************************************/
 /* This file is included by sam_vectors.S.  It provides the macro VECTOR that
- * supplies ach SAM3U vector in terms of a (lower-case) ISR label and an
+ * supplies ach SAM4S vector in terms of a (lower-case) ISR label and an
  * (upper-case) IRQ number as defined in arch/arm/include/sam/sam3u_irq.h.
  * sam_vectors.S will defined the VECTOR in different ways in order to generate
  * the interrupt vectors and handlers in their final form.

arch/arm/src/sam34/sam_clockconfig.c

@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/chip/sam3u_clockconfig.c
+ * arch/arm/src/chip/sam_clockconfig.c
  *
  *   Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>

arch/arm/src/sam34/sam_gpio.c

@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/sam34/sam3u_gpio.c
+ * arch/arm/src/sam34/sam_gpio.c
  * General Purpose Input/Output (GPIO) logic for the SAM3U and SAM4S
  *
  *   Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved.
@@ -502,11 +502,11 @@ int sam_dumpgpio(uint32_t pinset, const char *msg)
   lldbg("   PDSR: %08x    IMR: %08x    ISR: %08x   MDSR: %08x\n",
         getreg32(base + SAM_PIO_PDSR_OFFSET), getreg32(base + SAM_PIO_IMR_OFFSET),
         getreg32(base + SAM_PIO_ISR_OFFSET), getreg32(base + SAM_PIO_MDSR_OFFSET));
-#if defined(CONFIG_ARCH_CHIP_ATSAM3U)
+#if defined(CONFIG_ARCH_CHIP_SAM3U)
   lldbg("   ABSR: %08x SCIFSR: %08x  DIFSR: %08x IFDGSR: %08x\n",
         getreg32(base + SAM_PIO_ABSR_OFFSET), getreg32(base + SAM_PIO_SCIFSR_OFFSET),
         getreg32(base + SAM_PIO_DIFSR_OFFSET), getreg32(base + SAM_PIO_IFDGSR_OFFSET));
-#elif defined(CONFIG_ARCH_CHIP_ATSAM4S)
+#elif defined(CONFIG_ARCH_CHIP_SAM4S)
   lldbg(" ABCDSR: %08x %08x         IFSCSR: %08x  PPDSR: %08x\n",
         getreg32(base + SAM_PIO_ABCDSR1_OFFSET), getreg32(base + SAM_PIO_ABCDSR2_OFFSET),
         getreg32(base + SAM_PIO_IFSCSR_OFFSET), getreg32(base + SAM_PIOC_PPDSR));
@@ -520,7 +520,7 @@ int sam_dumpgpio(uint32_t pinset, const char *msg)
   lldbg(" FRLHSR: %08x LOCKSR: %08x   WPMR: %08x   WPSR: %08x\n",
         getreg32(base + SAM_PIO_FRLHSR_OFFSET), getreg32(base + SAM_PIO_LOCKSR_OFFSET),
         getreg32(base + SAM_PIO_WPMR_OFFSET), getreg32(base + SAM_PIO_WPSR_OFFSET));
-#if defined(CONFIG_ARCH_CHIP_ATSAM4S)
+#if defined(CONFIG_ARCH_CHIP_SAM4S)
   lldbg("   PCMR: %08x PCIMR: %08x   PCISR: %08x   PCRHR: %08x\n",
         getreg32(base + SAM_PIO_PCMR_OFFSET), getreg32(base + SAM_PIO_PCIMR_OFFSET),
         getreg32(base + SAM_PIO_PCISR_OFFSET), getreg32(base + SAM_PIO_PCRHR_OFFSET));

arch/arm/src/sam34/sam_vectors.S

@@ -1,7 +1,7 @@
 /************************************************************************************************
  * arch/arm/src/sam34/sam_vectors.S
  *
- *   Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2009-2010, 2013-2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -166,6 +166,8 @@ _vectors:
 #  include "chip/sam3u_vectors.h"
 #elif defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
 #  include "chip/sam3x_vectors.h"
+#elif defined(CONFIG_ARCH_CHIP_SAM4E)
+#  include "chip/sam4e_vectors.h"
 #elif defined(CONFIG_ARCH_CHIP_SAM4L)
 #  include "chip/sam4l_vectors.h"
 #elif defined(CONFIG_ARCH_CHIP_SAM4S)
@@ -205,6 +207,8 @@ handlers:
 #  include "chip/sam3u_vectors.h"
 #elif defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
 #  include "chip/sam3x_vectors.h"
+#elif defined(CONFIG_ARCH_CHIP_SAM4E)
+#  include "chip/sam4e_vectors.h"
 #elif defined(CONFIG_ARCH_CHIP_SAM4L)
 #  include "chip/sam4l_vectors.h"
 #elif defined(CONFIG_ARCH_CHIP_SAM4S)

configs/samd20-xplained/README.txt

@@ -883,8 +883,14 @@ Configuration sub-directories
          be clock related???
        - The program seems to be running normally, just producing bad output.
 
-    3. SPI current hangs so no much progress has been made tested the I/O1
+    3. SPI current hangs so not much progress has been made testing the I/O1
-       module.
+       module.  The hang occurs because the SPI is waiting for SYNCBUSY to
+       be cleared after enabling the SPI.  This even does not happen and so
+       causes the hang.
+
+       Another note:  Enabling the SPI on SERCOM0 also seems to interfere
+       with the USART output on SERCOM4.  Both symptoms imply some clock-
+       related issue.
 
        The configuration suggests CONFIG_MMCSD_HAVECARDDETECT=y, but as of
        this writing, there is no support for EIC pin interrupts.